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Anyone have ideal to Double CLK freq,in the FPGA design.Article: 10826
Buy a FPGA with an internal PLL. Don't try to make a combinitorial freq. doubler via sliver generator. Matt jaleco wrote in message <6mpq75$ln6$1@news.seed.net.tw>... > Anyone have ideal to Double CLK freq,in the FPGA design. > > >Article: 10827
>Buy a FPGA with an internal PLL. > >Don't try to make a combinitorial freq. doubler via sliver generator. > I don't need exactly,double freq,a appromix freq is OK.Article: 10828
Hello reader,
i would announce two development boards of Alcatel Telecom.
The two boards are useful for ASIC prototyping and simulation.
We already used the boards to verify DSP algorithms written in
VHDL, to test the behaviour of PLL circuits, to built test
equippment (complex signal generators written in VHDL) for our
fab and for other applications.
Short description of the boards:
HW_SIM
* 200.000 gates logical resources (4*Altera EPF10K50)
(300.000 gates if equpipped with 1EPF10K70)
* 2 Slots for SIMM memory modules (30 pin types)
* 2 on board oscillators (48,640 MHz, 16,384MHz)
* PBA size 233mm*210mm
* breadboard area
* reset circuit
* ...
DEV_KIT
* 20.000 gates logical resource (2*Altera EPF81188)
* on board oscillator (16,384 MHz)
* PBA size 233mm*160mm (possible splitting 2 times 100mm*160mm)
* breadboard area
* reset circuit
* ...
For more information about the development boards contact
one of the persons listed below.
Financial Questions: R.Prestin@alcatel.de
Technical Questions: brod@lts.sel.alcatel.de
Best regards Lothar Brodbeck
p.s.
An user wrote: ... We successfully used the HW_SIM development
board to verify our complex signal processing
algorithm. ... The programming and the handling
of the evaluation board stands out. ...
You can find a description and pictures of the boards using the
following address:
http://www.dev.alcatel.de/telecom/asd/test_hw/topdevboard.htm
--
Best regards Lothar Brodbeck
MFG Lothar Brodbeck
\////
(o/o)
+----------------+-------------UUUU----U----UUUU--+-------------------+
|Lothar Brodbeck | Email: brod@lts.sel.alcatel.de | Alcatel Telecom |
|Dept.: AS/EC1 | Phone: +49-711-821-47334 | Lorenzstrasse 10 |
|Room: 58/2/4 | Fax: +49-711-821-45068 | D-70435 Stuttgart |
+----------------+--------------------------------+-------------------+
Article: 10829anyone know where i can get a vhdl model (for synthesis or sim) of the Motorola MC68681 DUART? - its really just the data transmission part that i need. thanks, mark harveyArticle: 10830
Has anybody tried to implement an I squared C interface on an FPGA? I am trying to implement it in an HDL, say VHDL, but find that my logic is excessive for such a simple serial interface. I figure I'm missing some key insight into making the logic much simpler. If anybody has attempted this or knows where I might look for information on this subject, please help. -- Bryn Wolfe - Robotics Engineer Metrica TRAC LabsArticle: 10831
On Wed, 24 Jun 1998 08:27:52 -0500, Aliens from the 3rd dimension made Bryn Wolfe <bwolfe@hypercon.com> write: >Has anybody tried to implement an I squared C interface on an FPGA? I am >trying to implement it in an HDL, say VHDL, but find that my logic is >excessive for such a simple serial interface. There are some example I2C 8 bit port expander macros on the Philips CoolRunner Website (www.coolpld.com). These are in Philips PHD source, which is similar to ABEL/PALASM, and therefore pretty easy to understand and port to the HDL of your choosing. - Mark (formerly a Philips CoolRunner960 guy...) Mark Aaldering mma"at"netwiz"dot"net...Article: 10832
MEMEC Design Services (http://www.memecdesign.com) offers an FPGA-based core for I squared C that they call "Two-Wire Serial Interface". There's more information available at http://www.memecdesign.com/xf-twsi.htm. It supports both master and slave transactions. ----------------------------------------------------------- Steven K. Knapp OptiMagic, Inc. -- "Great Designs Happen 'OptiMagic'-ally" E-mail: sknapp@optimagic.com Web: http://www.optimagic.com ----------------------------------------------------------- Bryn Wolfe wrote in message <3590FED8.B6AFA96@hypercon.com>... >Has anybody tried to implement an I squared C interface on an FPGA? I am >trying to implement it in an HDL, say VHDL, but find that my logic is >excessive for such a simple serial interface. I figure I'm missing some >key insight into making the logic much simpler. > >If anybody has attempted this or knows where I might look for >information on this subject, please help. > >-- >Bryn Wolfe - Robotics Engineer >Metrica TRAC LabsArticle: 10833
Bryn Wolfe wrote: > > Has anybody tried to implement an I squared C interface on an FPGA? I am > trying to implement it in an HDL, say VHDL, but find that my logic is > excessive for such a simple serial interface. I figure I'm missing some > key insight into making the logic much simpler. > > If anybody has attempted this or knows where I might look for > information on this subject, please help. > > -- > Bryn Wolfe - Robotics Engineer > Metrica TRAC Labs Yes! We've build a slave receiver/transmitter model in vhdl for xilixn fpga. It's working fine, standalone receiver is about 14 clbs. HagenArticle: 10834
here is a *terrible* way to uprate in an fpga clk module up_clk(clk_in, clk_out, _reset); input clk_in; output clk_out; wire clk_out ; wire clk_in_delayed // This will work for sample of one, as long as the temperature doesn't change or the voltage. // otherwise buy a $2 pll and have piece of mind. assign clk_in_delayed = #CLK_IN_PERIOD_DIV_4 clk_in; // delay is via *precision* delay elements in FPGA // aka lotsa inverters.. assign clk_out = clk_in ^ clk_in_delayed; // ^ is xor end module; jaleco wrote in message <6mqabm$13g$1@news.seed.net.tw>... > > >>Buy a FPGA with an internal PLL. >> >>Don't try to make a combinitorial freq. doubler via sliver generator. >> >I don't need exactly,double freq,a appromix freq is OK. > > >Article: 10835
Here is not a best solution but work
Of course better to by PLL chip
Example in AHDL of ALTERA MAX+PLUS II
subdesign doubler
(
clk :input;
clk2 :output;
)
variable
doubler :node:
flipflop :dff;
begin
doubler=clk $ flipflop;
flipflop.d=!flipflop;
flipflop.clk=doubler;
clk2=doubler;
end;
Incoming clock should be as close as posible to 50% duty cycle
Output clock, of course, is not 50% duty cycle
Best regards
Lev Razamat
lrazamat@netvision.net.il
ICQ# 3347700
Matthew Morris wrote in message <359074d6.0@news3.uswest.net>...
>Buy a FPGA with an internal PLL.
>
>Don't try to make a combinitorial freq. doubler via sliver generator.
>
>Matt
>
>jaleco wrote in message <6mpq75$ln6$1@news.seed.net.tw>...
>> Anyone have ideal to Double CLK freq,in the FPGA design.
>>
>>
>>
>
>
Article: 10836How can I transfert a binary file from a PC (printer port) to a Xilinx XC3030 in Slave Serial Mode? Which software can I use? Regards, Laurent.Article: 10837
I woudn't have thought this would work as the # operator is not a synthesized construct. It is used in behavioural modelling. I think the only way to really get a clock double is by drawing the exact schematic you want and getting the FPGA tools to implement it. You will probably have to put constraints on the nets so that the logic fitter doesn't minimise the logic out for you. Matthew Morris wrote: > here is a *terrible* way to uprate in an fpga clk > > module up_clk(clk_in, clk_out, _reset); > > input clk_in; > output clk_out; > > wire clk_out ; > wire clk_in_delayed > > // This will work for sample of one, as long as the temperature doesn't > change or the voltage. > // otherwise buy a $2 pll and have piece of mind. > assign clk_in_delayed = #CLK_IN_PERIOD_DIV_4 clk_in; // delay is via > *precision* delay elements in FPGA > > // aka lotsa inverters.. > assign clk_out = clk_in ^ clk_in_delayed; > // ^ is xor > > end module; > > jaleco wrote in message <6mqabm$13g$1@news.seed.net.tw>... > > > > > >>Buy a FPGA with an internal PLL. > >> > >>Don't try to make a combinitorial freq. doubler via sliver generator. > >> > >I don't need exactly,double freq,a appromix freq is OK. > > > > > > -- ------------ Gareth BaronArticle: 10838
This is a multi-part message in MIME format. --------------00F0BF5B67F8A161CFFE1A05 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit If you are interested in converting your AHDL designs to VHDL please see your local Xilinx FAE. There is a tool that can do this very nicely. Best Regards Terry -- ___ ___ / ^/ /\ /___/ \ / Terry L. Zumwalt Xilinx Inc. \ \ v 4100 McEwen Field Applications Engineer \ \ Suite 237 Phone: (972) 960-1043 / / Dallas, TX Fax: (972) 960-0927 /___/ ^ 75244 E-Mail: terry.zumwalt@xilinx.com \ \ / \ USA Applications Hotline: 800-255-7778 \___v\__\/ Xilinx Home Page - http://www.xilinx.com --------------00F0BF5B67F8A161CFFE1A05 Content-Type: text/x-vcard; charset=us-ascii; name="vcard.vcf" Content-Transfer-Encoding: 7bit Content-Description: Card for Terry L. Zumwalt Content-Disposition: attachment; filename="vcard.vcf" begin: vcard fn: Terry L. Zumwalt n: Zumwalt;Terry L. org: Xilinx Inc. adr: 4100 McEwen Suite #237;;;Dallas;Texas;75244;USA email;internet: terry.zumwalt@xilinx.com title: Field Applications Engineer tel;work: (972) 960-1043 tel;fax: (972) 960-0927 x-mozilla-cpt: ;0 x-mozilla-html: FALSE version: 2.1 end: vcard --------------00F0BF5B67F8A161CFFE1A05--Article: 10839
... > is there > book or means to determine how much logic a particular > statement in vhdl will take ... A statement can take quite a different amount of logic depending on previous definitions. The statement: C <= D OR E; could be a single "OR" gate or thirty-two of them if C, D, and E are 32 bit buses. If the thirty-two bit version of the statement is in this process: process begin wait until clk='1'; C <= D OR E; end process; It creates 32 flip-flops in addition to 32 "OR" gates. Rich HatcherArticle: 10840
jaleco wrote: > I don't need exactly,double freq,a appromix freq is OK. In the digital world, that is really impossible. I will defend the internal "sliver generator" ( using an XOR ) as described in previous issues of the Xilinx data book. It is adaptive, creating a long pulse in a slow part, a short one in a fast part. Obviously, some common sense is required. Don't generate a 2 ns pulse and then run it all over the chip.... Peter AlfkeArticle: 10841
Okay, the reason the FFS weren't in IOB's was because I had logic after the FFS. I have since redesigned the system, accepting a performace hit, but registering the outputs again, so that the last FFS are in the IOBS, thus getting no skew problems. thanks for all the replies, Richard.Article: 10842
Patrick: One element limiting the speed of your "Memory Element" is the required address decoding needed to address one of N CLB-based memories. The other side of the coin is the muxing/(Inverse addressing) of the correct "Memory Element" to get output data. Without sounding too forward, perhaps we could take this further for you if you're interested. -- Ed McCauley Bottom Line Technologies Inc. Specializing Exclusively in Xilinx Design, Development and Training Voice: (500) 447-FPGA, (908) 996-0817 FAX: (908) 996-0817 Patrick Müller wrote: > > Hi, > I am evaluating Xilinx FPGAs (Spartan XCS40XL-4 and XC4020XL-2). > In this devices I need a 128x17Bit dualport fifo that runs at 62.5MHz. > Xilinx says, that this would not run with this speedgrades.... > Is it possible, that a interleaved dualport-fifo, implemented with > single port Memorys could reach that speed? And how many CLBs would be > used? > > Thanks Patrick > > ============================================================ > Supercomputing Systems AG email: mueller@scs.ch > Patrick Müller www: http://www.scs.ch > Technoparkstrasse 1 phone: ++41 (0)1 445 16 09 > CH-8005 Zurich fax: ++41 (0)1 445 16 10 > ============================================================Article: 10843
Dies ist eine mehrteilige Nachricht im MIME-Format. --------------D1452C5CF172EF372608F74C Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Hi, I'd like to program a XC9536 CPLD for hobby purpose without big investments. Can anyone give me a hint where I can get shareware or evalauation software to generate the necessary bitstream for is-programming and a hardware solution to program via the parallel port for example? Thanks, Andreas PS: Please send a copy to me at andreas.kemper@post.rwth-aachen.de --------------D1452C5CF172EF372608F74C Content-Type: text/x-vcard; charset=us-ascii; name="vcard.vcf" Content-Transfer-Encoding: 7bit Content-Description: Visitenkarte für Andreas Kemper Content-Disposition: attachment; filename="vcard.vcf" begin: vcard fn: Andreas Kemper n: Kemper;Andreas adr: Templergraben 32;;;Aachen;NRW;52062;Germany email;internet: andreas.kemper@post.rwth-aachen.de tel;home: 0241-23594 x-mozilla-cpt: ;0 x-mozilla-html: FALSE end: vcard --------------D1452C5CF172EF372608F74C--Article: 10844
Bryn Wolfe wrote: > > Has anybody tried to implement an I squared C interface on an FPGA? I am > trying to implement it in an HDL, say VHDL, but find that my logic is > excessive for such a simple serial interface. I figure I'm missing some > key insight into making the logic much simpler. > > If anybody has attempted this or knows where I might look for > information on this subject, please help. > > -- > Bryn Wolfe - Robotics Engineer > Metrica TRAC Labs We have done i2c Slave on CPLD. You do not explain 'excessive', but i2c is more complex than SPI, or our SPL variant. You need a State engine to take care of Start, Address Bit Compares, and ACK generation, plus a branch for READ or WRITE blocks, and then Stop. Besides the data storage elements, I think this took 5 registers. ( Tho in a FPGA, the more-registers, fewer-terms blocks may use more registers ) - jg -- ======= Manufacturers of Serious Design Tools for uC and PLD ========= = Specialists in Development tools for C51 cored controllers = Leaders in Rapid Application Development SW for C51 uC = Ask for our Controller & Tools selector Guides = mailto:DesignTools@xtra.co.nz Subject : Selc51ToolsArticle: 10845
Hi All
I am looking for any documentation for VHDL and EDIF
conversion. (Paper, Technical reports, Thesis)
Thanks in advance
Khalid
Article: 10846ARM Ltd has developed a PCI board comprising of an ARM based Micro-controller and two Xilinx FPGAs which are available for user applications. It is possible that there might be a spare place on the beta trial which will take place over the next three months. If you are interested please read the extra information below and email me as soon as possible. Thanks Dominic Plunkett OptionExist Ltd Cambridge ASPIRE Beta Trial ================== The ASPIRE beta trial aims to test and evaluate the ASPIRE board and software packages that go with the board. The trial will run for three months, at the end we will require a report. OptionExist Ltd have been appointed by ARM Ltd to run the trial. If you have a use for the board and kit beyond the 3 month trial, it will be available at a discounted price. Please could you give us an indication as to the likely applications and which software packages you would require for the trial, and your experience with similar products. The ASPIRE Board ---------------- This ASPIRE development board was jointly developed between ARM Ltd and Oxford University under the ASPIRE project. The board contains the following : MicroController ( based on the ARM7TDMI). Clocked at 16/33MHz. BOOTROM with the Angel Debug Monitor. JTAG ICE many also be used 1MB of Flash Memory for the MicroController. RS232 port DRAM SIMM (4/16Mbytes) System Controller (in an XC4013XL) which provides a DRAM controller, DMA Controller, Interrupt controller and other glue logic functions AMCC PCI chip which can directly DMA into/out of the DRAM via the system controller Selectable clock rates 4/8/16/33MHz. On board Crystal or PCI Clock. 2 x XC4013XL FPGA's for user Applications, programmed by the AT91 256K SSRAM directly connected to the FPGAs External power connector for standalone applications Many Expansion connectors Software -------- For the Trial we have arranged the following software to be available for evaluation if you need it. ARM Development Tool Version 2.11a (www.arm.com) HandelC : Oxford University Hardware Compilation Group have developed a C like language that can target the FPGA's. So it becomes very easy to develop hardware in a software environment. Oxford University now have a spin off company Embedded Solutions Ltd (www.embedded-solutions.ltd.uk). Xilinx Alliance standard needed for HandelC or possible Xilinx Foundation needed for VHDL or HandelC. This software places and route the designs for the FPGA's. (www.xilinx.com) Reports -------- We are looking for people who could make use of the board in the 3 months. We would like monthly email reports about the board and the software. At the end of the trial we will require a final report, this should cover: What the board has been used for? How easy was it to use? Was the board suitable? Do you have enough information? Any problems you have had? It is useful to develop a product or test software? Do you know of any competing product? What improvements would you like? Dominic Plunkett OptionExist -----== Posted via Deja News, The Leader in Internet Discussion ==----- http://www.dejanews.com/ Now offering spam-free web-based newsreadingArticle: 10847
Andreas Kemper wrote: > Hi, > > I'd like to program a XC9536 CPLD for hobby purpose without big > investments. > Can anyone give me a hint where I can get shareware or evalauation > software to generate the necessary bitstream for is-programming and a > hardware solution to program via the parallel port for example? > > Thanks, > Andreas > > PS: Please send a copy to me at andreas.kemper@post.rwth-aachen.de > > ------------------------------------------------------------------------ > > Name: vcard.vcf > vcard.vcf Type: VCard (text/x-vcard) > Encoding: 7bit > Description: Visitenkarte für Andreas Kemper Try http://www.optimagic.com/lowcost.html There is beginners software "xilinx student edition" with an interesting price. good luck. -- =================================================================== Sergio A. Cuenca Asensi Dept. Tecnologia Informatica y Computacion Escuela Politecnica Superior, Campus de San Vicente Universidad de Alicante Ap. Correos 99, E-03080 ALICANTE email : sergio@dtic.ua.es Phone : +34 6 590 34 00 ext. 3182 Fax : +34 6 590 36 81 ===================================================================Article: 10848
Fusion/SpeedWave (from Viewlogic) is a complete high-performance VHDL simulator and debug environment and does not require synthesis of the design. It does support VITAL acceleration if you are simulating at the gate level, but it also provides one of the fastest RTL/Behavioral simulation capabilities. There is no problem with simulating both your testbench (at any level of abstraction) and your design. Fusion/SpeedWave also supports co-simulation with a variety of other simulators so your design can be in virtually any form (digital, analog, mechanical, etc). Many customers will synthesize their VHDL to a Verilog netlist to take advantage of Verilog's optimized gate-level performance. leslie.yip@asmpt.com wrote: > Dear William White > > How can I use SpeedWave to do testbenches? In the past, I used ModelSim's > V-System to do testbenches. Yet I know SpeedWave requires synthesis before, > right? > > Leslie Yip > > In article <RePGPJAfYAg1EAfI@fpga.demon.co.uk>, > William White <will@fpga.demon.co.uk> wrote: > > > > Yes, Speedwave will run "testbenches". Indeed any VHDL simulator should have > this > > capability. There is nothing special about testbenches. The general form of a > testbench > > is an empty entity with the DUT component Instantiated in the architecture. > There will > > then be a process to provide stimulus. See template below. There are also > tools > > available to automatically generate testbenches from timing diagrams such as > QuickBench > > from Chronology. If you require any further information on this please email > me > > directly. > > > > Regards > > > > Will > > > > ------------------------------------------------------------------------------ > > -- > > -- Typical testbench skeletons > > -- > > ------------------------------------------------------------------------------ > > > > -- > > -- Top-level entity/architecture > > -- > > library ieee ; > > use ieee.std_logic_1164.all ; > > > > entity testbench is > > end testbench; > > > > architecture only of testbench is > > > > -- > > -- Paste in any necessary signals and component declarations here. > > -- Declare DUT component here. > > -- > > > > begin > > > > -- > > -- Paste in the instantiation(s) of the DUT component and any other > testbench > > -- components here. > > -- > > -- > > > > -- Stimulus thread > > -- > > > > stim : process > > > > begin > > > > -- > > -- Paste in your test sequence here > > -- > > > > wait; > > end process; > > end only; > > > > configuration testbench_config of testbench is > > for only > > > > -- > > -- Paste in your configuration statements here. > > -- > > > > end for; > > end testbench_config; > > > > In article <6l853l$cee$1@goanna.cs.rmit.edu.au>, Hamish Moffatt > <hamish@moffatt.nu> > > writes > > >In comp.arch.fpga John Huang <hungi@tpts4.seed.net.tw> wrote: > > >> I got some questions about Viewlogic/Speedwave, > > >> I have a design that use VHDL for a FPGA. > > >> 1. Can I use VHDL testbench in the speedwave, if > > >> it is YES, how will I do? > > >> 2. What simulaors support the VHDL testbench? > > > > > >Aldec's ActiveVHDL seems to run them nicely. > > > > > >> 3. Would you please give me an example for > > >> write testbench? > > > > > >Best to grab a book eg Skahill's VHDL for Programmable Logic, > > >it has a whole chapter on it. Aldec's also has a thing for generating > > >test benches for you, I haven't tried it. > > > > > > > > >Hamish > > > > -- > > William White < > > ------------------------ < < < ---------- Mailto: will@fpga.demon.co.uk > > | Direct Insight Ltd < < < < > Tel: +44 1280 700262 | > > | < < < Fax: +44 1280 700577 | > > --------------------------- < ------------------------------------------ > > > > -----== Posted via Deja News, The Leader in Internet Discussion ==----- > http://www.dejanews.com/ Now offering spam-free web-based newsreading -- *-------------------------------------------------------* * John Willoughby ƒWƒˆƒ“ ƒEƒCƒƒrƒC * * System Simulation Mktg office: 508-303-5238 * * Viewlogic Systems mobile: 508-254-9608 * * 293 Boston Post Rd West fax: 508-460-7826 * * Marlboro, MA 01752 email: jww@viewlogic.com * * * * "Well done is better than well said" - Ben Franklin * *-------------------------------------------------------*Article: 10849
Gareth Baron wrote in message <359129A5.9615DD68@eng.efi.com>... >I woudn't have thought this would work as the # operator is not a >synthesized construct. It is used in behavioural modelling. I know # is not a synthesizable construct. That is why the comment mentions implementation of delay via *precision* delay elements available within an FPGA aka lotsa inverters. I hope what the original poster figures out is that, with the exception of the PLL, there is no good solution for uprating clocks in a FPGA. Matt > >I think the only way to really get a clock double is by drawing the exact >schematic you want and getting the FPGA tools to implement it. You will >probably have to put constraints on the nets so that the logic fitter >doesn't minimise the logic out for you. > >Matthew Morris wrote: > >> here is a *terrible* way to uprate in an fpga clk >> >> module up_clk(clk_in, clk_out, _reset); >> >> input clk_in; >> output clk_out; >> >> wire clk_out ; >> wire clk_in_delayed >> >> // This will work for sample of one, as long as the temperature doesn't >> change or the voltage. >> // otherwise buy a $2 pll and have piece of mind. >> assign clk_in_delayed = #CLK_IN_PERIOD_DIV_4 clk_in; // delay is via >> *precision* delay elements in FPGA >> >> // aka lotsa inverters.. >> assign clk_out = clk_in ^ clk_in_delayed; >> // ^ is xor >> >> end module; >> >> jaleco wrote in message <6mqabm$13g$1@news.seed.net.tw>... >> > >> > >> >>Buy a FPGA with an internal PLL. >> >> >> >>Don't try to make a combinitorial freq. doubler via sliver generator. >> >> >> >I don't need exactly,double freq,a appromix freq is OK. >> > >> > >> > > > > >-- > > > >------------ >Gareth Baron > >
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