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In article 1335@univision.com, "John L. Smith" <jsmith@univision.com> () writes:
> LFSRs make good cheap address generators for FIFOs, but how about
> an address generator for a LIFO? Has anyone ever looked at an LFSR
> that can run in both directions? One bit is lost from the end of the
> shift register each clock, but perhaps there is an interesting
> combination of xor's that can produce the neccessary bits for shifting
> reversibly in either direction? Just posing the question...
Good idea!
You can get a reverse sequence in at least one situation. Given a
maximal-length LFSR, i.e. one with a sequence length of 2^n - 1 for n
flip-flops, you can form a new LFSR with the property that it counts in
the reverse sequence in the following way.
Assume the bit numbers of the LFSR start from n-1 down to 0 as shown
below. The setup has the taps as shown.
Let the tap numbers be the set of values in range 0 to n where the
number of values is n+1 and one of the values always equals n and one
of them always equals 0.
+-----+
| |<----------------+
+---| XOR | |
| | |<---+ |
| +-----+ | |
+-----+ <----+ | |
| |<-------- etc. ... | |
+--| XOR | | |
| | |<--+ | |
| +-----+ | | |
| | | |
| | n-1 | 1 | 0
| +-----------------------------------------------------+ |
| n | | |
+---->| n-bit Right Shift Register |-----+
| |
+-----------------------------------------------------+
^
|
Clock ------+
Now form a new LFSR with all taps = n - (each tap value)
Then use the bits in reverse order. The sequence of the new LFSR
will be the reverse of the original LFSR.
For example: For a three bit register start with taps = (3, 1, 0)
The sequence is 001, 100, 010, 101, 110, 111, 011
Form the new LFSR with taps = (3-3, 3-1, 3-0) = (0, 2, 3)= (3, 2, 0)
The sequence is 110, 111, 011, 101, 010, 001, 100 but reverse the bit
order and you have 011, 111, 110, 101, 010, 100, 001 which is the
reverse sequence of the original register.
For a four bit LFSR, a maximal-length set of taps is (4, 1, 0) and the
reverse LFSR would have the taps (4, 3, 0)
For a five bit LFSR a maximal-length set of taps is (5, 2, 0) and the
reverse LFSR is (5, 3, 0)
These values come from a table of primitive polynomials for the Galois
field of 2.
As Philip Freidin stated, if you use a left/right shift register and
rearrange the XORs when you change from left to right then you can use
the above taps to get the reversible counter.
Up/Down
enable +--------------------------------------------+
---+------>| |
| +----| XOR's with Up/Down enable |-----+
| | | | |
| | +--------------------------------------------+ |
| | ^ ^ |
| | | | |
| | +-----------------------------------------------+ |
| | | | |
| +-->| n-bit Right/Left Shift Register |<--+
+----->| |
+-----------------------------------------------+
^
|
Clock ------+
For the three bit example it looks like:
Up/Down +----------------------------------------+
enable | |
---+---------------------+ |
| | | |
| | v +-------+ |
| | +-----+ | | |
| | | sel | | XOR |----->+
| | | |------->| | |
| | | MUX | +-------+ |
| | +-----+ ^ |
| | ^ ^ | |
| | | 2 | 1 | 0 |
| | +---------------------------------+ |
| | | | |
| +->| 3-bit Right/Left Shift Register |<--+
+--------->| |
+---------------------------------+
^
|
Clock ---------+
This assumes "up" means with bit 1 selected and shift to right. When
shifting left, the bit numbers are reversed from the original
numbering in the taps.
Rich Hatcher
Article: 4301To any Xilinx users: We've recently derived great benefit from specifying detailed timing constraints (ie. the XACT Performance utility) for an XC4013E design. However, we found the documentation for this to be fairly limited ... the syntax is reasonably clear, but we had to learn a lot ourselves about how to use it effectively. This seems like an ideal topic for an application note. However, we've been unable to find any on the web site. I posted a question to the email hotline, and received the usual deafening silence. Has anybody (perhaps one of the Xilinx employees who work here) ever seen such an app. note? Thanks, Bruce. oakley@appliedmicro.ns.ca -- --------------------------------------------------- Bruce Oakley [ oakley@appliedmicro.ns.ca ] Hardware Design Engineer Applied Microelectronics, Inc. (AMI) Halifax, Nova Scotia, CANADA ---------------------------------------------------Article: 4302
Note that I'm with a tool vendor. But I think my answer will be helpful. Nick Gent wrote: > > I am taking (another) look at VHDL for FPGA design. I am a complete novice > at VHDL but have been doing FPGA design for years. I would be looking for a > solution which runs under HP-UX on the HP 700-series. The target will > probably be Xilinx 5k and 4k series. > > Our past attempts at synthesising Xilinx (3000) LCAs from VHDL apparently > failed because it took too much manual intervention to get a decent end > result. Have the tools improved significantly? Yes. > > Which vendors should I contact? IMHO us. www.exemplar.com. info@exemplar.com. From the UK: info@saros.co.uk. > > With VHDL entry, is it still possible to make use of the static-timing > driven routing facilities of the Xilinx PPR router? Yes. Exemplar's Leonardo writes Timespecs from the user provided timing constraints. Exemplar's Galileo has some Timespec support as well. And Xilinx provides a couple of very useful perl scripts maketnm & addtnm that help you add TNMs to the XNF if you choose to do the Timespecs from the Xilinx constraint file. They are probably on www.xilinx.com. > > Has anyone tried mixing ABEL-HDL with VHDL? What would be the issues here? While you can mix any form of design entry you like, it is best to stick with VHDL and/or Verilog. This allows you to simulate each block as you design it, then to simulate the entire design, then after place & route, to use the same testbench to simulate the routed design. Furthermore your test is then written in the same HDL as your design. The simulation phase can take far more time than the design phase, so in simulation, like design (maybe more so), it is important to use a good methodology, to maximize your productivity. There is a post further back from someone looking for macros for the primitive commands from his non-HDL gate level simulator. While it's a fine gate level simulator, it has a terrible language for developing tests. For example it has no functions or procedures that accept parameters. It's much easier to simulate in an HDL. While it is simplest (and generally best) to choose either VHDL or Verilog, Exemplar's Leonardo can synthesize a design hierarchy of mixed VHDL and Verilog, and Model Tech's VSystem Plus can simulate it. If you mix blocks from different tools you need to make sure that busses are expanded into bits in XNF using the same bit delimeters so that XNFMERGE can merge the design hierarchy. And the tools must write the same XNF version (check the LCANET record at the start of the XNF file). Solutions to the above two problems are usual very simple (tool settings, or PERL, SED or AWK scripts). You can keep legacy ABEL designs units if you like. But it can make it harder to adopt an all HDL methodology. Converting a few blocks from ABEL to VHDL should be pretty easy. Regards, David Emrich emrich@exemplar.com > > Any information will be gratefully received! > > Nick > ============================================================================ > Nick Gent > > Queensferry Telecom Operation Email: nickg@hpsqf.sqf.hp.com > Hewlett-Packard Telephone: +44 131 331 7644 > South Queensferry EH30 9TG Fax: +44 131 331 7488 > Scotland > ============================================================================Article: 4303
This is a multi-part message in MIME format.
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> Rynier van der Watt wrote:
> >
> > Hi
> >
> > Does anybody know how to instantiate the Xilinx Startup symbol in VHDL
> > for Viewlogic's Viewsynthesis?
> >
> > I am currently using the Workview Office for Windows95 tools and a
> > XC4025E device.
> >
> > Thank you very much in advance.
> >
> > Rynier van der Watt
> > CSIR South Africa
> >
> > Email: arvdwatt@csir.co.za
>
> --
>
> I give here an example how I implemented it for Examplar Galileo.
> It synthesizes Global Set Reset correctly, but there is still a
> problem with Global Three State. Maybe Viewsynthesis does it better.
There is no problem when I run it here - did you use the
-xnf_use_startup option? I ran your design (attached). The XNF is
also attached. The Galileo command line is at the top. The Startup
GSR & GTS are both fine.
If you only want GSR, and not GTS, we recommend against instantiation,
since we can handle global reset for you.
If one signal will cause all storage elements to be reset, -infer_gsr
will implement the Startup in your Xilinx design (or the GSR in your
ORCA design), and remove that GSR signal from the reset logic to
the storage elements, so it isn't routed.
In cases where the signal you want for GSR does not reset all storage
elements in your HDL design, we cannot extract the reset signal, but you
can specify it with -global_sr=<active high reset signal name>.
This will drive GSR with the specified signal and take it out of the
reset logic.
Regards,
David Emrich
Exemplar Logic
emrich@exemplar.com
>
> You have to instantiate a STARTUP component in your top level entity,
> with inputs gsr and gts. Then connect the reset and output enable
> input signals to STARTUP by PORT MAP.
>
>
> -=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-
> Hans Spaargaren (for: Philips Medical Systems Nederland B.V.)
> Origin
> Engineering Services, CAD/CAM-E
> Building QG-037 Internet:
> hspaarga@best.ms.philips.com
> P.O. Box 10.000 Voice: +31 40 2763018
> 5680 DA Best Fax: +31 40 2765641
> the Netherlands
> -=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-
>
--------------2781E494446B9B3D794BDF32
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit
Content-Disposition: inline; filename="c.vhd"
-- This VHDL file is generated by EASE/VHDL from TRANSLOGIC BV,
-- the 'Entity Architecture Schematics Editor for VHDL' tool.
--
-- EASE/VHDL Version 2.4 (Revision -8).
-- Time stamp : Thu Oct 10 07:47:40 1996.
--
-- Designed by : .
-- Company : .
-- Design info : .
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- Entity declaration of 'core'.
---------------------------------------------------------------------------
LIBRARY ieee, synergy ;
USE ieee.std_logic_1164.ALL ;
USE ieee.std_logic_1164.ALL ;
-- USE synergy.signed_arith.ALL ;
USE work.ALL ;
ENTITY core IS
PORT(
clk : IN std_ulogic ;
en_out : IN std_ulogic ;
reset : IN std_ulogic ;
a : IN std_ulogic ;
q1 : OUT std_ulogic ) ;
END core ;
---------------------------------------------------------------------------
-- Architecture 'a0' of 'core'.
---------------------------------------------------------------------------
ARCHITECTURE a0 OF core IS
signal q1_a: std_ulogic;
BEGIN
process(reset,clk,a)
begin
if reset = '1' then
q1_a <= '0';
elsif clk = '1' and clk'event then
q1_a <= a;
end if;
end process;
process(q1_a,en_out)
begin
if en_out = '1' then
q1 <= q1_a;
else
q1 <= 'Z';
end if;
end process;
END a0 ;
---------------------------------------------------------------------------
-- Entity declaration of 'xxx'.
---------------------------------------------------------------------------
LIBRARY ieee, synergy ;
USE ieee.std_logic_1164.ALL ;
USE ieee.std_logic_1164.ALL ;
-- USE synergy.signed_arith.ALL ;
USE work.ALL ;
ENTITY xxx IS
PORT(
a : IN std_ulogic ;
reset : IN std_ulogic ;
en_out : IN std_ulogic ;
q1 : OUT std_ulogic ;
clk : IN std_ulogic ) ;
END xxx ;
---------------------------------------------------------------------------
-- Architecture 'a0' of 'xxx'.
---------------------------------------------------------------------------
ARCHITECTURE a0 OF xxx IS
COMPONENT core
PORT(
clk : IN std_ulogic ;
en_out : IN std_ulogic ;
reset : IN std_ulogic ;
a : IN std_ulogic ;
q1 : OUT std_ulogic ) ;
END COMPONENT ;
COMPONENT startup -- <--------------------------
PORT(
gsr : IN std_ulogic ;
gts : IN std_ulogic ) ;
END COMPONENT ;
SIGNAL clock : std_ulogic ;
SIGNAL rst : std_ulogic ;
SIGNAL ain : std_ulogic ;
SIGNAL ena : std_ulogic ;
BEGIN
clock <= clk ;
rst <= reset ;
ain <= a ;
ena <= en_out ;
u0: core
PORT MAP(
clk => clock,
en_out => ena,
reset => rst,
a => ain,
q1 => q1 ) ;
u4: startup -- <----------------------
PORT MAP(
gsr => rst,
gts => ena ) ;
END a0 ; -- of xxx
--------------2781E494446B9B3D794BDF32
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit
Content-Disposition: inline; filename="c_xi4.xnf"
LCANET, 5
USER, FPGA, gc c.vhd c_xi4.xnf -so=xi4 -ta=xi4 -xnf_use_startup
PROG, gc, V3.2.5, "Fri Oct 11 18:45:55 1996"
USER,AREA,0
USER,PACKED_ESTIMATE,0
USER,DELAY,16.000000
USER,LEVELS,1
EXT, A, I,
EXT, RESET, I,
EXT, EN_OUT, I,
EXT, CLK, I,
EXT, Q1, T,
SYM, U4, STARTUP,LIBVER=2.0.0
PIN, GSR, I, RESET_int, ,
PIN, GTS, I, EN_OUT_int, ,
END
SYM, i90, OUTFFT,SCHNM=OFDT,LIBVER=2.0.0,INIT=R
PIN, C, I, CLK_int, ,
PIN, D, I, A_int, ,
PIN, T, I, n545, ,
PIN, O, O, Q1, 7.000000,
END
SYM, IBUF_CLK_int, IBUF,SCHNM=IBUF,LIBVER=2.0.0
PIN, I, I, CLK, ,
PIN, O, O, CLK_int, 3.000000,
END
SYM, IBUF_EN_OUT_int, IBUF,SCHNM=IBUF,LIBVER=2.0.0
PIN, I, I, EN_OUT, ,
PIN, O, O, EN_OUT_int, 3.000000,
END
SYM, IBUF_RESET_int, IBUF,SCHNM=IBUF,LIBVER=2.0.0
PIN, I, I, RESET, ,
PIN, O, O, RESET_int, 3.000000,
END
SYM, IBUF_A_int, IBUF,SCHNM=IBUF,LIBVER=2.0.0
PIN, I, I, A, ,
PIN, O, O, A_int, 3.000000,
END
SYM, i545, INV,SCHNM=INV,LIBVER=2.0.0
PIN, I, I, EN_OUT_int, ,
PIN, O, O, n545, ,
END
EOF
--------------2781E494446B9B3D794BDF32--
Article: 4304Hi, I'm looking for a way to shrink some Async circuit, has anyone done any work with implementing some Async stuff with an FPGA? I have an application which needs to respond to an input within a small time period, ~7 to 10 ns. unfortunately I can't just use a fast clock, so I was thinking of trying to design some Asyn stuff in an FPGA. any comments/ suggestions? Thanks. DavidArticle: 4305
This is dangerous, since the routing delays are likely to be different every time you run place/route. Peter. >Hi, I'm looking for a way to shrink some Async circuit, has anyone done >any work with implementing some Async stuff with an FPGA? I have an >application which needs to respond to an input within a small time period, >~7 to 10 ns. unfortunately I can't just use a fast clock, so I was >thinking of trying to design some Asyn stuff in an FPGA. any comments/ >suggestions? Thanks. > > DavidArticle: 4306
David T. Wang wrote: > > Hi, I'm looking for a way to shrink some Async circuit, has anyone done > any work with implementing some Async stuff with an FPGA? I have an > application which needs to respond to an input within a small time period, > ~7 to 10 ns. unfortunately I can't just use a fast clock, so I was > thinking of trying to design some Asyn stuff in an FPGA. any comments/ > suggestions? Thanks. Your question is too vague to enable a concise answer. That said: We've proabably all done some async logic (accidently or purposely) and often come to regret it. If you can't an async solution, at least lock the placement of your async logic blocks to minimize changes in routing delay over the course of your design effort. If you are careful, and keep the async portion of your design as simple as possible you shouldn't get into trouble. If you are doing something simple like address decode (one of the more popular uses of async logic) you will benefit from partial decode, where only the minimum necessary set of address lines are decoded. This results in aliases of the selected device but minimizes the width (and indirectly depth) of the decode logic if your device does not have wide decoder logic. Regards, ScottArticle: 4307
I have had a simular problem with MAXPLUS 6.2 and MENTOR 8.25 QUICKSIMII. Found that the edif format changed from version 5.4 (old style edif) version 6.0 (new style edit) I had to use a old version of MAXPLUS 5.4, but in your case you have to use a newer version 6.0 and above (latest is 7.0) Good luck John Edelman --- Design -> Develop -> Fab -> Assembly -> Checkout -> Test -> Sell-off -> RETIREArticle: 4308
>The trick is to ask workview to keep a log (record) of what you are doing >first, like open a single schematic, using the plot function, generate a >postscript, close the schematic. How do you get Viewlogic to keep a logfile? The only command I could find is one which "saves" a log, and the content of that is just menu commands activated by the mouse, plus keyboard input. Please remember I am using a Xilinx-only version of Viewlogic, not the $25,000 full version. Peter.Article: 4309
>How do you get Viewlogic to keep a logfile? >The only command I could find is one which "saves" a log, and the You should use "macro" at the viewdraw command line, viewdraw will create a macro file.Article: 4310
> >Hi, I'm looking for a way to shrink some Async circuit, has anyone done > >any work with implementing some Async stuff with an FPGA? I have an > >application which needs to respond to an input within a small time period, > >~7 to 10 ns. unfortunately I can't just use a fast clock, so I was > >thinking of trying to design some Asyn stuff in an FPGA. any comments/ > >suggestions? Thanks. > > David, It sounds like what you are really asking is whether it is feasible to reliably implement an async state machine in an FPGA (ie a state machine that changes state on input transitions rather than on a system clock). To answer your question, YES async state machines can be done in FPGAs. You need to be extra careful about delay paths vs placement. Lots of care is needed in the design to make sure all possible input conditions (with all possible timing combinations)result in predictable and consistent state changes. Rigorous attention to async state machine design practices should keep you out of trouble. That said, I do not recommend async design in FPGAs for the novice. There are plenty of pitfalls both for the inexperienced FPGA designer and the inexperienced async state machine designer, and it is a genuine bear to troubleshoot or even verify. -Ray Andraka, P.E. Chairman, the Andraka Consulting Group 401/884-7930 FAX 401/884-7950 mailto:randraka@ids.net http://www.ids.net/~randraka/ The Andraka Consulting Group is a digital hardware design firm specializing in high performance FPGA designs. Services include complete design, development, simulation, and integration of these devices and the surrounding circuits. We also evaluate,troubleshoot, and improve existing designs. Please call or write for a free brochure or visit our web site.Article: 4311
Make sure that the part you choose is capable of meeting the PCI spec WRT setup times and clock-to-out. I know that most Altera devices are PCI-compliant; don't know about Xilinx... In article <53lunp$fvi@mordred.gatech.edu>, dan.bartram@gtri.gatech.edu (Dan Bartram) wrote: >I'm planning on a PCI interface design and would like some first-hand >experiences and opinions on implementing this interface in an FPGA, >especially a Xilinx part. If you have done this, any comments would be >appreciated. > >thank you, > >Dan Bartram > >**************************************************************************** >Dan Bartram, Jr. >Internet: dan.bartram@.gtri.gatech.edu >****************************************************************************Article: 4312
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Article: 4313Hi. I'm looking for a small PLD (preferably with 16V8 fusemap) which will operate over this supply range. Speed could be anyhing. 35ns would be fine. Does anyone make such a device ? The power comes from a battery-backed (3.6VNiMh) supply, which is 5V when the box is powered up, and 3.6-4.3V when running off the battery. A 4.8V NiCad/NiMh battery would be rather inconvenient: e.g. need to supply 6V for charging. -- John Vickers Tel: +44 1223 560129 Hardware / Software Person Fax: +44 1223 563698 The Magic Board Company john@rhizik.demon.co.ukArticle: 4314
<richard@milliped.demon.co.uk> wrote: > Any ideas on how I can improve the placement/routing of the four address > lines? Any advice on hand placement? Of course, I've already made the nets > critical. Is there the equivalent of the Xilinx longlines? So far the The simple questions: Yes there is a long-line attribute. ORCA typically uses the exact same attributes as Xilinx. (The only one that it still doesn't have is HBLKNM which is a major problem for ORCA.) It also helps to set a minimum skew of about 3ns on a net. This will force it to try to make all delays the same which usually means using long lines. The hard question: It's near impossible to route all of your address signals on long lines. For a dual-port memory, you really have 8 address lines in addition to a write-enable. You also are probably using a common 2-bit tri-state output bus (per PFU) and a common input bus. Due to the weird twisting thing that happens on the long lines, and the fact that using a horizontal TBUF will block a vertical long-line input, it's near impossible to use all of the vertical long lines well. The half-lines work better. Here are some rules of thumb: Make sure the clock is routed in the same direction as the tristate data bus (Usually horizontally). Make sure your OE signals go in the opposite direction (vertical) and on a long-line. This allows part of the clock distribution resources to be used for routing OE. This also requires you to do some hand routing. Routing a few clock pins will set the pattern and PAR will do the rest. It's necessary to route the WE signal on a half-line. WE can only go in on A4/B4 and will get screwed up on the twisted Long Lines. If possible, put RAM only in even (or only odd) rows and/or columns to avoid some twisted-long-line conflicts. Doing both will eliminate almost all conflicts, but will make the array twice as big. Take a shot at pre-placing TBUFS. Typically, PAR wants to move the TBUF away from the PFU that drives it (Probably to avoid the twisting problem). I've had good luck pre-placing all of the TBUFs at the same site as their driving PFUs providing that you only use 2 horizontal full-length lines: using more will block your vertical inputs. The two lines should be adjacent so that at least one line will have an alternate path on the local nodes. (You pretty much have to look in EPIC to see what I'm talking about here. At any PFU, two of the TBUFs can be driven by two local nodes. The other two have only a single input). If you need 4 TBUFs (If you're using 4-bit single-port RAM) then 2 outputs should go on long-lines and 2 should go on alternate half-length lines. Again the reason for this is only explainable by pointing at an EPIC screen. I have a simple floor planning tool, XPLACE, for ORCA that allows you to place arrays of TBUFs and PFUs easily. I put this at our FTP site with a bunch of other tools: ftp://eseserver1.fnal.gov/pub/docx/xilinx/awks.zip (1 Megabyte) if you just want the documentation for these tools: ftp://eseserver1.fnal.gov/pub/docx/xilinx/mans.zip (10K byte) You might also want to look at some of the other tools which are useful for xilinx and ORCA designs.Article: 4315
David T. Wang wrote: > > Hi, I'm looking for a way to shrink some Async circuit, has anyone done > any work with implementing some Async stuff with an FPGA? I have an > application which needs to respond to an input within a small time period, > ~7 to 10 ns. unfortunately I can't just use a fast clock, so I was > thinking of trying to design some Asyn stuff in an FPGA. any comments/ > suggestions? Thanks. > > David Xilinx application note XAPP028.001 shows a phase/frequency detector for phase locked loops. This is an example of a simple async state machine, although the note does not show the derivation. So, like everyone else has said, it is possible to implement ASMs in FPGAs, but can be tricky. -- John L. Smith, Pr. Engr. | Sometimes we are inclined to class Univision Technologies, Inc. | those who are once-and-a-half witted 6 Fortune Dr. | with the half-witted, because we Billerica, MA 01821-3917 | appreciate only a third part of their wit. jsmith@univision.com | - Henry David ThoreauArticle: 4316
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Don't miss this opportunity to learn the latest in High Level Design from
the best in the industry. For course syllabi and registration information,
contact us at:
Linda Boyd, Training Registrar
Qualis Design Corporation
8705 SW Nimbus Avenue, Suite 118
Beaverton, Oregon 97008 USA
Phone: +1-503-644-9700
FAX: +1-503-644-1583
E-mail: training@qualis.com
World Wide Web: coming soon!
Brief Course Descriptions
--------------------------
High Level Design Using VHDL
Course Overview
Copyright (c) 1995, 1996 Qualis Design Corporation
"High Level Design Using VHDL" is a fast paced, 5-day hands-on,
multimedia course designed not only to teach High Level Design
techniques and the VHDL language, but to make class participants
immediately productive in a system design environment using
state-of-the-art simulation and synthesis tools.
After an introduction to VHDL, the course deviates from the
traditional bottom-up, gates-to-behavioral modeling presentation of
other VHDL courses and reverses the flow, teaching top-down
design practices, with early special emphasis on coding for synthesis,
efficient testbench generation and advanced design verification
techniques. These skills are reinforced throughout the week while
teaching VHDL from a High Level Design perspective.
The course labs are designed to accommodate the learning aptitudes of
a wide range of students with diverse design experiences. Each lab is
structured into three parts:
1. Fundamental Concepts Review and Experience
2. Recognition of Common Mistakes and Correcting Problems
3. Additional Material for Advanced Students
All students complete parts one and two of each lab. Part three is
for students who finish early and want to learn additional material.
This lab structure caters to all student skill levels and provides
excellent opportunities to expand one's knowledge of VHDL simulation
and synthesis techniques.
Each day of class is divided into multiple interactive lecture and
lab sessions. Students have access to individual Sun Sparcstations,
the VHDL simulation environment of their choice, and the Synopsys
DC Expert synthesis environment for use during the lab sessions.
The course material is presented using a projection system that allows
30% more material to be presented in a given amount of time with vivid,
interest-grabbing color slides.
Full Course Syllabus Available
------------------------------
A full course syllabus listing all topics covered in this course is available.
Contact us for more information.
------------------------------------------------------------------------------
Advanced Techniques Using VHDL
Course Overview
Copyright (c) 1996 Qualis Design Corporation
"Advanced Techniques Using VHDL" is a fast paced, 3-day hands-on,
multimedia course designed to bring Engineers with experience in
using VHDL to an unparalleled level of efficiency.
After a review of the more advanced behavioral constructs and
features of VHDL, the course immediately illustrates how these
constructs can turn an ordinary-looking environment into a design
simulation and verification powerhouse through the use of
bus-functional models, test harnesses, abstract regressionable
testbenches and behavioral models.
Each day of class includes interactive lecture sessions with
8 challenging labs. Students will have access to individual Sun
Sparcstations and the VHDL simulation environment of their
choice. The course material is presented using a projection
system that allows 30% more material to be presented in a given amount
of time with vivid, interest-grabbing color slides.
Student Questions
-----------------
Prior to the first day of the course, registered students are
encouraged to submit questions related to their current usage
of VHDL to the instructor. Questions or topics that illustrate
modeling techniques or features of the language will be included
in the course presentation.
Course Prerequisites
--------------------
Due to the fast-paced nature of this class and the caliber of the
students attending, all registrants must have prior experience with
the VHDL language, or previously attended the Qualis course
"High Level Design Using VHDL". Knowledge of a structured
programming language, such as C or Pascal, is recommended.
Full Course Syllabus Available
------------------------------
A full course syllabus listing all topics covered in this course is available.
Contact us for more information.
------------------------------------------------------------------------------
Qualis Design Corporation
8705 SW Nimbus Avenue, Suite 118
Beaverton, Oregon 97008 USA
Phone: +1-503-644-9700
FAX: +1-503-643-1583
E-mail: training@qualis.com
World Wide Web: coming soon!
"DC Expert" is a trademark of Synopsys, Inc.
"Verilog" is a registered trademark of Cadence Design Systems, Inc.
Copyright (c) 1995, 1996, Qualis Design Corporation. All Rights Reserved.
Article: 4317
A N N O U N C E
Qualis Design Corporation is offering additional sessions of our
popular courses, "High Level Design Using Verilog", and "Advanced Techniques
Using Verilog" at our Beaverton, Oregon, Training Center.
Our course "High Level Design Using Verilog" presents a comprehensive
introduction to Verilog and teaches the student how to approach complex
design tasks using High Level Design methods. The "Elite Class" course
"Advanced Techniques Using Verilog" leverages off the student's foundation
in Verilog to teach advanced design and verification methods. Both
courses provide high leverage knowledge for board, ASIC and FPGA designers.
For additional information about the material covered in these leading-edge
courses, see the course descriptions below.
These courses can also be held at your facilities in a private, one-on-one
setting -- contact us for more information.
Schedule
--------
The Portland course schedule through December follows:
Course Title Course Dates Status
-------------------------------------------------------------------
High Level Design Using Verilog: Oct 21 - Oct 25 filling fast!
Nov 18 - Nov 22 open
Advanced Techniques Using Verilog: Oct 28 - Oct 30 open
Dec 09 - Dec 11 open
For information about the material covered in these leading-edge courses,
see the course descriptions below.
The Qualis Difference
---------------------
We know what it's like to work under the pressure of aggressive schedules and
immense technical challenges. We believe that High Level Design methods
and technology, such as HDL-based verification and synthesis, are the key
to tackling those challenges and conquering today's design problems.
Our courses can really make a difference in your day-to-day work life
by showing you the high leverage points of Verilog and High Level Design.
Here's how we do it:
-- The Qualis "Best In Class" Instructor Team draws upon the absolute best
Verilog and VHDL consulting and training talent available. Our
instructors, top-notch Engineers with cutting-edge design experience,
know how to relate the course material to your real-world design problems.
-- Our courses are intense, hands-on events using the latest EDA tools
and hardware. Everything you need to learn quickly and efficiently is
provided -- you supply the brain, we'll supply everything else.
-- Our courses are like no other in the EDA industry. Engineers and
Managers who attend our courses will learn what's important and why, and
where to focus their time and resources for maximum leverage from HDLs
and design tools. And, unlike other vendor courses, our courses are
*dynamic* -- we constantly update our material with the latest in
High Level Design techniques and information, so you're assured of
learning the latest in the field.
-- Our courses are respected in the industry. We have taught our
High Level Design courses to dozens of companies and hundreds of
Engineers and Managers. Our student references attest to the
outstanding quality and real-world usefulness of our classes.
About Qualis Design Corporation
-------------------------------
Founded in 1992, Qualis Design Corporation has quickly become the
leading independent provider of High Level Design consulting and
training services. The company provides services to leading-edge
high technology firms worldwide, including Intel, Hewlett-Packard,
Tektronix, Xerox, TRW, and Northern Telecom. Qualis' corporate
headquarters are located in Beaverton, Oregon.
Don't miss this opportunity to learn the latest in High Level Design from
the best in the industry. For course syllabi and registration information,
contact us at:
Linda Boyd, Training Registrar
Qualis Design Corporation
8705 SW Nimbus Avenue, Suite 118
Beaverton, Oregon 97008 USA
Phone: +1-503-644-9700
FAX: +1-503-643-1583
E-mail: training@qualis.com
World Wide Web: coming soon!
Brief Course Descriptions
--------------------------
High Level Design Using Verilog
Course Overview
Copyright (c) 1995, 1996 Qualis Design Corporation
"High Level Design Using Verilog" is a fast paced, 5-day hands-on,
multimedia course designed not only to teach High Level Design
techniques and the Verilog language, but to make class participants
immediately productive in a system design environment using
state-of-the-art simulation and synthesis tools.
After an introduction to Verilog, the course deviates from the
traditional bottom-up, gates-to-behavioral modeling presentation of
other Verilog courses and reverses the flow, teaching top-down
design practices, with early special emphasis on coding for synthesis,
efficient testbench generation and advanced design verification
techniques. These skills are reinforced throughout the week while
teaching Verilog from a High Level Design perspective.
The course labs are designed to accommodate the learning aptitudes of
a wide range of students with diverse design experiences. Each lab is
structured into three parts:
1. Fundamental Concepts Review and Experience
2. Recognition of Common Mistakes and Correcting Problems
3. Additional Material for Advanced Students
All students complete parts one and two of each lab. Part three is
for students who finish early and want to learn additional material.
This lab structure caters to all student skill levels and provides
excellent opportunities to expand one's knowledge of Verilog simulation
and synthesis techniques.
Each day of class is divided into multiple interactive lecture and
lab sessions. Students have access to individual Sun Sparcstations,
the Verilog simulation environment of their choice, and the Synopsys
DC Expert synthesis environment for use during the lab sessions.
The course material is presented using a projection system that allows
30% more material to be presented in a given amount of time with vivid,
interest-grabbing color slides.
Full Course Syllabus Available
------------------------------
A full course syllabus listing all topics covered in this course is available.
Contact us for more information.
------------------------------------------------------------------------------
Advanced Techniques Using Verilog
Course Overview
Copyright (c) 1996 Qualis Design Corporation
"Advanced Techniques Using Verilog" is a fast paced, 3-day hands-on,
multimedia course designed to bring Engineers with experience in
using Verilog to an unparalleled level of efficiency.
After a review of the more advanced behavioral constructs and
features of Verilog, the course immediately illustrates how these
constructs can turn an ordinary-looking environment into a design
simulation and verification powerhouse through the use of
bus-functional models, test harnesses, abstract regressionable
testbenches and behavioral models.
Each day of class includes interactive lecture sessions with
8 challenging labs. Students will have access to individual Sun
Sparcstations and the Verilog simulation environment of their
choice. The course material is presented using a projection
system that allows 30% more material to be presented in a given amount
of time with vivid, interest-grabbing color slides.
Student Questions
-----------------
Prior to the first day of the course, registered students are
encouraged to submit questions related to their current usage
of Verilog to the instructor. Questions or topics that illustrate
modeling techniques or features of the language will be included
in the course presentation.
Course Prerequisites
--------------------
Due to the fast paced nature of this class and the caliber of the
students attending, all registrants must have prior experience with
the Verilog language, or previously attended the Qualis course
"High Level Design Using Verilog". Knowledge of a structured
programming language, such as C or Pascal, is recommended.
Full Course Syllabus Available
------------------------------
A full course syllabus listing all topics covered in this course is available.
Contact us for more information.
------------------------------------------------------------------------------
Qualis Design Corporation
8705 SW Nimbus Avenue, Suite 118
Beaverton, Oregon 97008 USA
Phone: +1-503-644-9700
FAX: +1-503-643-1583
E-mail: training@qualis.com
World Wide Web: coming soon!
"DC Expert" is a trademark of Synopsys, Inc.
"Verilog" is a registered trademark of Cadence Design Systems, Inc.
Copyright (c) 1995, 1996, Qualis Design Corporation. All Rights Reserved.
Article: 4318I've heard lots on LPM from Altera stuff and lately I've found on the EDIF web that LPM is indeed somekind of standard. What tool/fpga/asic vendors actually support the LPM standard? MZArticle: 4319
An older application note, XAPP043, "Improving XC4000 Design Performance," has some additional information on using XACT-Performance. However, the app note is limited to the older path-type specs and doesn't include the newer group-type specs. Xilinx plans to update the app note. The app note can be found in Acrobat format at http://www.xilinx.com/xapp/xapp043.pdf The documentation for XACT-Performance can be found at ftp://ftp.xilinx.com/pub/documentation/dsref1.pdfArticle: 4320
Mike Treseler <tres@tc.fluke.COM> wrote in article <Dz0wvA.H6p@tc.fluke.COM>... > sja@world.std.com (Stuart J Adams) writes: > > >I am considering getting Altera's MaxPlus VHDL synthesis > >add-on. Was wondering if anyone is using this and how it > >compares to other synthesis tools such as Synplicity, > >Synopsys, or Exemplar ??? > > > >Thanks, > > Stuart Adams > > sja@world.std.com > > >-- > > >Stuart Adams > >Chief Engineer > >Bright Star Engineering > > We use Exemplar, but I have spent a day on MaxPlus VHDL. > Maxplus is very easy to use and has well integrated tools. > The downside is Altera-only synthesis and no support of VHDL > testbenches. > > ---------------------------------------------------------------------- > tres@tc.fluke.com Mike Treseler > Fluke Networks Division > voice: (206) 356-5409 Fluke Corporation > fax: (206) 356-5043 P.O. Box 9090 > Everett, WA 98206-9090 > ---------------------------------------------------------------------- > > I use the Max+Plus 2 VHDL compiler for all my Altera designs. It might not be the best, but it works fine. There is a few unsupported features or deviations from the IEEE spec, but for most of them there are easy work arounds. These are more VHDL compiler issues, when you get to the VHDL synthesis issues MaxPlus2 does the job. Feel free to contact me for more info Petrus Pelser petrus@fpgatec.co.zaArticle: 4321
Hello and thanks to all who gave advice related to my AT17C128 startup problem. The problem was related to my programmer's buffer containing data from a previous data file which occupied the reset polarity bits for the Atmel device. Once I cleared the buffer (hex 0s), loaded the file, and programmed the part - it fired up properly. No more OTP serial proms will be trashed during my development phase ($$)! BTW, if anyone plans (I would recommend they do) on using the Atmel parts for prototyping they should get Atmels 17Cxxx FAQ from their local FAE or download it from their web site at www.atmel.com. Thanks for your input, Andy Embedded Systems Electronics, Inc. (630) 960-0052Article: 4322
Moshe Zalcberg wrote: > > I've heard lots on LPM from Altera stuff and lately I've found on the > EDIF web that LPM is indeed somekind of standard. > What tool/fpga/asic vendors actually support the LPM standard? > > MZ Moshe, You will find the LPM support atleast from VeriBest, for more info look at http://www.veribest.com Regards, Veli-Matti Karppinen -- ************************************************************************* ** ** ** Veli-Matti Karppinen Internet: ventti@fincitec.fi ** ** Fincitec Oy ** ** P.B. 11 tel. +358-698-21490 ** ** FIN-94601 KEMI,FINLAND fax. +358-698-21561 ** ** ** *************************************************************************Article: 4323
Hello! I would like to ask if anybody had success in using the Xilinx xchecker cable and xchecker.exe V5.1 od V5.2 under Windows NT3.51 to download a LCA? To me it keeps crashing or it ignoring the download cable almost every time. Any hints?Article: 4324
In article <32630ADD.74E8@interaccess.com>, asiska@interaccess.com wrote: >Hello and thanks to all who gave advice related to my AT17C128 startup >problem. >No more OTP serial proms >will be trashed during my development phase ($$)! I thought the AT17C128 serial proms were EEPROMS. At least the ones I used were. Perhaps I missed the original posts, but I would definitely use the EE versions during development. **************************************************************************** Dan Bartram, Jr. Internet: dan.bartram@.gtri.gatech.edu ****************************************************************************
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