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In article <01bbbbe4$05b8df00$42c220cc@drt1>, "Austin Franklin" <darkroom@ix.netcom.com> wrote: >I have used the Xilinx 4xxxE series very successfully in both target only >and target/master implementations. Xilinx has quite a lot of app notes on >PCI. I developed my own PCI design, and did not use theirs, although >theirs is not bad. My impression of the Xilinx core is that it is not very flexible. I am working on a PCI design that needs 5 functions in one device. The Xilinx core only supports a single function (1 set of configuration regs) and only two base address registers. **************************************************************************** Dan Bartram, Jr. Internet: dan.bartram@.gtri.gatech.edu ****************************************************************************Article: 4401
Dipl.-Ing. D. Lenz wrote: > I'm searching after a Demoboard for Flex8000 devices. > ... > It should have access to all I/O-Pins, configuration Port (Byteblaster) > and/or space for an EEPROM (e.g. EPC1213PC8) also Voltageregulator ... > I planned to use the EPF8636ALC84-4 (PLCC package) first. Ours has all of that and more. It is made for the EPF81500, but you can use the EPF9560 MAX-device as well. All I/O-pins are routed to 3 96p DIN connectors. The board is in eurocard format and includes a socket for a standard DIL32 (F)EPROM, Switches & LEDs, a VCO for simple PLLs, an ECL clock prescaler and a place for a TCXO. A special feature is that you can connect up to 7 boards without a backplane, yet a clock driver provides a star-type clocking network for frequencies up to 80 MHz. We used this board several times for ASIC-emulation purposes. We test the board with the FPGA's boundary-scan feature, so we can guarantee a high quality level. The board is approx. 4000 $. Alfred -- My little grey cells speak for themselves, not for my company. But have a look at http://www.siemens.at mailto:alfred.fuchs@siemens.at Phone: 43/1/1707-34113Article: 4402
Good points!! The major factor in winning design teams over to VHDL has been the portability of the HDL coding between technologies. Software re-use is a key to efficiency, and thus to use schematic entry from technology specific part libraries has to be sheer in-efficiency? Effective chip-design, FPGA or ASIC, surely has to rely upon intelligent application of design partitioning and floorplanning techniques. Whether the design is then schematically implemented, or synthesized from VHDL is irrelevant.Article: 4403
I was just wondering if anyone has benchmarked the Synplicity and/or Synopsys FPGAExpress synthesis tools. I have seen Synplicity demonstrated by our local Altera AE and it looks pretty good. It took a 3k gate equiv verilog design and spit out and edif netlist in about 10 min on his laptop. The size and speed results were quite good. I have not seen anything on FPGAExpress yet. It appears to currently support XILINX with more support to come. I have downloaded the demo software for each, but have not had time to experiment yet. Thanks DMArticle: 4404
hi i am trying to run a win3.11 program under win95 it is the FPGA design suite from Lattice the problem is that this program requires the environmet variable WDIR to point to a directory.. i have done this in my autoexec.bat and i know it is set ok by doing the set command from DOS the problem is that once i run it under win95, it fails to pick up the environment variable and comes up with an error saying 'No WDIR' what is wrong ? are there other ways to set env variables under win95? many thanks jonnyArticle: 4405
>One thing puzzled me though - xdelay and makebits uses almost 3 minutes >each to process a small 5202 design. In dos or windows 95 it only took >a few seconds(<10) to run the same design through those tools. There is some funny stuff in the Xilinx tools. For example, the xact 6 wir2xnf (or xnfmerge, I can't remember) runs about 10x faster in a wfwg3.11 DOS box than under straight DOS, where it does a huge amount of disk thrashing. And I have a 4MB smartdrv cache operative under DOS. I expect they may be doing a "reset" on the disk system, inside a tight loop, without realising it, and the 32-bit disk code in wfwg3.11 just ignores that API call. Peter.Article: 4406
>Yes you do. It is deterministic. Specially if you do know how to code in >VHDL, and the differences between each of the constructs. Knowing "how to code" is the crux of the matter. This is more than just knowing the language. One needs to know a lot of tricks to get a good result. This may be OK for some, but it means you have to use these tools very regularly to stay on top of the learning curve. Whereas schematic entry you can get into as quickly as it takes to learn the schematic editor. Peter.Article: 4407
A new PCI based reconfigurable hardware platform will soon be available from Acquisition Systems. RIOPCI consists of an Altera 81500A FPGA on the addon side of an AMCC S5933 PCI bridge, 128k x 32 bits of SRAM, and 48 bits of digital I/O available on two standard 50 pin ribbon cables. While we intend to use RIOPCI for data acquisition applications, it is clear that other researchers in reconfigurable computing, PCI bus co-processing, compiler development, teaching, etc. may have an interest in this hardware. Have a look at our web page, www.acqsys.com. Acquisition Systems staff@acqsys.comArticle: 4408
In article <54g644$prj@borg.svpal.org>, garyk@svpal.svpal.org (George Noten) wrote: >extra z to stop junk mail (zz80@digiserve.com) wrote: >: Austin, > >: I thought I would never hear anyone say this. > >: Having tried to get into VHDL myself, I feel exactly the same way >: about it. But there is so much hype in the press, and so many people >: are trying to use it for applications for which good old schematic >: entry would have been far more appropriate. > >: Peter. > > Agreed 100%. Unfortunately, it is very difficult to work with both > tools. I don't know any vendor that provides good integration between > schematic entry and an HDL ( I still prefer to write state machines > using HDL and not schematic). > > George Altera has it's own VHDL synthesis tool and also allows schematic or AHDL to mixed in as well. Many designers I know tend to do lower level VHDL (or AHDL) and a top-level schematic that also serves as a functional block diagram. I have used this method extensively and have not had any difficulties mixing entry methods in a design. WayneArticle: 4409
I have a copy of PLDShell Plus/PLDasm v3.1 (still has Intel all over it) and I'm a bit confused... I downloaded some tech. docs on the EPX880 from Altera and it states that PLDShell supports device programming with an option cable. Is that all that is needed?? I have to have a circuit up and running by December, so I can't just sit around. Is it possible to program using a simple cable, or do I have to connect some expensive hardware between that cable and the computer? Any help would be greatly appreciated, since I already turned in a project description with a FPA listed in the schematic :( --Eric ohms@vt.eduArticle: 4410
Dennis Morel (dmorel@flir.com) wrote: : I was just wondering if anyone has benchmarked the Synplicity and/or : Synopsys FPGAExpress synthesis tools. I have used both. Obviously if you need Altera support Synplicity is the way to go until Synopsys comes out with an Altera library. If you are synthesising into Xilinx, I have found FPGA Express much better, generates better data path and faster state machines. I benchmarked two circuits, one a data path and the second a state machine. In asic gates both circuits were around 11000 gates. Tool Data Path State Machine Synplicity XC4025E - 12MHz XC4020E 11MHz FPGA EXpress XC4020E - 15.6MHz XC4020E 17MHzArticle: 4411
Jonny Cochrane wrote: > > hi > > i am trying to run a win3.11 program under win95 > it is the FPGA design suite from Lattice > > the problem is that this program requires the environmet variable WDIR > to point to a directory.. i have done this in my autoexec.bat and i know > it is set ok by doing the set command from DOS > > the problem is that once i run it under win95, it fails to pick up the > environment variable and comes up with an error saying > > 'No WDIR' > > what is wrong ? > are there other ways to set env variables under win95? > > many thanks > jonny Jonny , If you are sure that the environment variable is set correctly maybe it should be WDIR section or line in system.ini or in windows.ini. w95 has this two files because of compatibility with w3.11. Have a success. MarekArticle: 4412
--
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-- /_ ()
--- ()/ JUST BIKE IT!!
Article: 4413Hi Alain, > > Tool Data Path State Machine > Synplicity XC4025E - 12MHz XC4020E 11MHz > FPGA EXpress XC4020E - 15.6MHz XC4020E 17MHz > How did the floorplan look? Do you think if you floorplanned the data path it would have timed out better? You might want to post these results (and your opinion...) in the discussions below on VHDL for Xilinx designs...it's been pretty lively... Take care, AustinArticle: 4414
In article <32702FDD.4B4@vt.edu>, Eric Holmberg <eholmber@vt.edu> wrote: >I have a copy of PLDShell Plus/PLDasm v3.1 (still >has Intel all over it) and I'm a bit confused... >I downloaded some tech. docs on the EPX880 from >Altera and it states that PLDShell supports device >programming with an option cable. Is that all >that is needed?? I have to have a circuit up and >running by December, so I can't just sit around. >Is it possible to program using a simple cable, or >do I have to connect some expensive hardware >between that cable and the computer? > >Any help would be greatly appreciated, since I >already turned in a project description with a FPA >listed in the schematic :( It is actually just a cable that goes from the parallel port to a 20-pin JTAG header on your board. It is called the Flashlogic Download Cable and can be obtained from Altera (or built, if you prefer). Get Application Note 45 (Configuring Flashlogic Devices) from the Web site (www.altera.com). WayneArticle: 4415
In article <Dzu2v6.Hu8@world.std.com>, ecla@world.std.com (alain arnaud) wrote: >Dennis Morel (dmorel@flir.com) wrote: > > >: I was just wondering if anyone has benchmarked the Synplicity and/or >: Synopsys FPGAExpress synthesis tools. > > I have used both. Obviously if you need Altera support Synplicity is > the way to go until Synopsys comes out with an Altera library. > > If you are synthesising into Xilinx, I have found FPGA Express much > better, generates better data path and faster state machines. > > I benchmarked two circuits, one a data path and the second a state > machine. In asic gates both circuits were around 11000 gates. > > Tool Data Path State Machine > Synplicity XC4025E - 12MHz XC4020E 11MHz > FPGA EXpress XC4020E - 15.6MHz XC4020E 17MHz Altera support in FPGA Express will be available in January, and since Altera and Synopsys just signed a five-year partnership to develop the Synopsys/Altera interface I think the results will be quite good.Article: 4416
waynet@goodnet.com (Wayne Turner) writes: > > In article <Dzu2v6.Hu8@world.std.com>, ecla@world.std.com (alain arnaud) wrote: > >Dennis Morel (dmorel@flir.com) wrote: > > > > > >: I was just wondering if anyone has benchmarked the Synplicity and/or > >: Synopsys FPGAExpress synthesis tools. > > > > I have used both. Obviously if you need Altera support Synplicity is > > the way to go until Synopsys comes out with an Altera library. What kind of a library? We have been using Synopsys with Altera on and off now for about 2-3 years. The results were good enough for what we did. Although there are some interfacing problems between Synopsys and Altera we never noticed a big problem. We are currently using Synopsys FPGA compiler to map some Altera 10K designs. -- Brad L. Hutchings VOICE: (801) 378-2667 Dept. of Elec. & Computer Eng. FAX: (801) 378-6586 459 Clyde Building EMAIL: hutch@ee.byu.edu Brigham Young University Provo, Utah 84602 http://www.ee.byu.edu/faculty/hutch/hutch.htmlArticle: 4417
Hi All I am just new in FPGA field (Xilinx XC6000) , has any one any advices to me for first setp in this road ? My work will be programming C++ for FPGA . Thanks in Advance Mr. Khalid Alotaibi K.Alotaibi@qub.ac.uk Queen's University of Belfast Belfast, UKArticle: 4418
alain arnaud wrote: > I benchmarked two circuits, one a data path and the second a state > machine. In asic gates both circuits were around 11000 gates. > > Tool Data Path State Machine > Synplicity XC4025E - 12MHz XC4020E 11MHz > FPGA EXpress XC4020E - 15.6MHz XC4020E 17MHz > ... Could you provide the figures for area (in terms of # of LUTs or CLBs before P&R) of these circuits? It might be possible that FPGA Express (in the way you used it) generates larger circuits than those synthesized by Synplicity. Also, I would be interested in knowing whether timing constraints (i.e. arrival dates on inputs and required dates on outputs) are accepted by both synthesis tools? Jean-Michel VuillamyArticle: 4419
Paul, How are you converting C++ to .xnf? Austin Franklin darkroom@ix.netcom.comArticle: 4420
Hi Is there any manufacturer that produced windowed serial configuration EPROMs for Altera FLEX 8000 and FLEX 10K parts ? The Altera selection guide calls their parts EPROMs but my rep says they are windowless OTP devices. Yes, I know I can use the BitBlaster cable to get the configuration straight in, but that is inconvenient for my tests. Neither do I want to use a conventional parallel EPROM, as that will use up too many of my I/Os. Many thanks. -- Steve Dewey Steve@s-dewey.demon.co.uk Too boring to have an interesting or witty .sig file.Article: 4421
C A L L F O R P A P E R S
THE FIFTH ANNUAL
IEEE SYMPOSIUM ON CUSTOM COMPUTING MACHINES
Napa, California
April 16-18,1997
PURPOSE: To bring together researchers to present recent work in the
use of Programmable Logic Devices as reconfigurable computing
elements. This symposium will focus primarily on the current
opportunities and problems in this new and evolving technology for
computing. Contributions are solicited on all aspects of custom
computing, including but not limited to:
Architecture of reconfigurable computing systems, including
coprocessors, attached processors, and hybrids;
Languages, compilation techniques, tools, and environments for
programming;
Application domains;
Prototyping for architecture emulation;
Use of custom computing in education.
SUBMISSIONS: Authors are invited to send submissions (4 copies, 10
pages maximum) by January 10, 1997, to Jeffrey Arnold. Notification
of acceptance will be sent in early March. Final papers will be due
on the first day of the symposium. After the Symposium a proceedings
will be published by the IEEE Computer Society Press.
Authors may also submit PostScript or Microsoft Word manuscripts by
FTP. For instruction on electronic submission, please contact
Jeffrey Arnold (jma@super.org).
SPONSORSHIP: The IEEE Computer Society and the Technical Committee on
Computer Architecture.
CO-CHAIRS:
Kenneth L. Pocek
Intel
Mail Stop RN6-18
2200 Mission College Boulevard
Santa Clara, California 95052
Voice: 408-765-6705 Fax: 408-765-5165
kenneth_pocek@ccm11.sc.intel.com
Jeffrey M. Arnold
10686 Mira Lago Terrace
San Diego, CA 92131
Voice: 619-547-9257 Fax: 619-547-9010
jma@super.org
PROGRAM COMMITTEE:
Peter Athanas, Virginia Tech.
Donald Bouldin, University of Tennessee, Knoxville
Duncan Buell, Center for Computing Sciences
Michael Butts, Quickturn Design Systems, Inc.
Pak Chan, Univ. California, Santa Cruz
Apostolos Dollas, Technical Univ. of Crete
Scott Hauck, Northwestern Univ.
Brad Hutchings, Brigham Young Univ.
Tom Kean, Xilinx, Inc. (U.K).
Phil Kuekes, HP Labs.
Wayne Luk, Imperial College
Mark Shand, Digital Equipment (Paris)
Satnam Singh, Univ. of Glasgow
Stephen Smith, Altera Corp.
Article: 4422
=============================================================================
Call for Papers
1997 International Symposium on Physical Design
April 14-16, 1997
Napa Valley, California
Sponsored by the ACM SIGDA in cooperation with
IEEE Circuits and Systems Society
The International Symposium on Physical Design provides a forum to
exchange ideas and promote research on critical areas related to the
physical design of VLSI systems. All aspects of physical design, from
interactions with behavior- and logic-level synthesis, to back-end
performance analysis and verification, are within the scope of the
Symposium. Target domains include semi-custom and full-custom IC, MCM
and FPGA based systems.
The Symposium is an outgrowth of the ACM/SIGDA Physical Design
Workshop. Following its five predecessors, the symposium will
highlight key new directions and leading-edge theoretical and
experimental contributions to the field. Accepted papers will be
published by ACM Press in the Symposium proceedings. Topics of
interest include but are not limited to:
1. Management of design data and constraints
2. Interactions with behavior-level synthesis flows
3. Interactions with logic-level (re-)synthesis flows
4. Analysis and management of power dissipation
5. Techniques for high-performance design
6. Floorplanning and building-block assembly
7. Estimation and point-tool modeling
8. Partitioning, placement and routing
9. Special structures for clock, power, or test
10. Compaction and layout verification
11. Performance analysis and physical verification
12. Physical design for manufacturability and yield
13. Mixed-signal and system-level issues.
IMPORTANT DATES: Submission deadline: December 20, 1996
Acceptance notification: February 1, 1997
Camera-ready (6 page limit) due: March 1, 1997
SUBMISSION OF PAPERS:
Authors should submit full-length, original, unpublished papers
(maximum 20 pages double spaced) along with an abstract of at most
200 words and contact author information (name, street/mailing address,
telephone/fax, e-mail).
Electronic submission via uuencoded e-mail is encouraged (single
postscript file, formatted for 8 1/2" x 11" paper, compressed with
Unix "compress" or "gzip''). Email to:
ispd97@ece.nwu.edu
Alternatively, send ten (10) copies of the paper to:
Prof. Majid Sarrafzadeh
Technical Program Chair, ISPD-97
Dept. of ECE, Northwestern University
2145 Sheridan Road, Evanston, IL 60208 USA
Tel 847-491-7378 / Fax 847-467-4144
SYMPOSIUM INFORMATION:
To obtain information regarding the Symposium or to be added to the
Symposium mailing list, please send e-mail to ispd97@cs.virginia.edu.
Information can also be found on the ISPD-97 web page:
http://www.cs.virginia.edu/~ispd97/
SYMPOSIUM ORGANIZATION:
General Chair: A. B. Kahng (UCLA and Cadence)
Past Chair: G. Robins (Virginia)
Steering Committee: J. Cohoon (Virginia), S. Dasgupta (Sematech),
S. M. Kang (Illinois), B. Preas (Xerox PARC)
Program Chair: M. Sarrafzadeh (Northwestern)
Keynote Address: T. C. Hu (UC San Diego) & E. S. Kuh (UC Berkeley)
Special Address: R. Camposano (Synopsys)
Publicity Chair: M. J. Alexander (Washington State)
Local Arrangements Chair: J. Lillis (UC Berkeley)
Technical Program Committee: C. K. Cheng (UC San Diego)
W. W.-M. Dai (UC Santa Cruz)
J. Frankle (Xilinx)
D. D. Hill (Synopsys)
M. A. B. Jackson (Motorola)
J. A. G. Jess (Eindhoven)
Y.-L. Lin (Tsing Hua)
C. L. Liu (Illinois)
M. Marek-Sadowska (UC Santa Barbara)
M. Sarrafzadeh (Northwestern)
C. Sechen (Washington)
K. Takamizawa (NEC)
M. Wiesel (Intel)
D. F. Wong (Texas-Austin)
E. Yoffa (IBM)
=============================================================================
Article: 4423In article <846359819snz@s-dewey.demon.co.uk> Steve@s-dewey.demon.co.uk writes: > >Hi >Is there any manufacturer that produced windowed serial configuration >EPROMs for Altera FLEX 8000 and FLEX 10K parts ? >The Altera selection guide calls their parts EPROMs but my rep says they >are windowless OTP devices. >Steve Dewey Pretty much all prom devices that are windowless are just EPROMS without an outlook on life. The older bipolar fuse/aim technology died when EPROMS caught up in speed, and were cheaper, denser, and gave higher yield at programming time. Windowless OTP (One Time Programmable) is just another way of saying EPROM in a package that does not have the expensive quartz glass window. They are more reliable than their older brother bipolar parts because they actually are usually programmed at least once during manufacturing, at wafer sort time then erased before packaging in the windowless package. Bipolar parts could only be programmed once per bit, so you get to do the final manufacturing step and test. Back to your real question, which is for windowed serial EPROMs. No manufacturer of configuration EPROMS (Altera, Atmel, ATT, Xilinx) makes a production version of their device with a window (although I have seen test devices with an outlook on life :-) Atmel manufactures an EEPROM device which for your needs is probably just as good. It is an electrically programmed/Re-programmed device, so it does not require a window or a sun-tanning lamp. Part numbers are AT17C65, AT17C128, and AT17C256. Make sure you have a device programmer that knows SPECIFICALLY about the Atmel parts !!! A programmer that knows about the xx17Cxx parts from other vendors will not be able to program the Atmel parts. Note that these parts are programmed at 5 Volts only, so building your own programmer is not too hard, and could be even done in-circuit, if enough of your system is working without your FPGA being loaded. All the best, Philip FreidinArticle: 4424
Hi, can anyone recommend me about the web site or other resources related to the following: 1, PCI-compliant VHDL module. 2, ISA, EISA, VESA and PCI bus structure. I am now doing a project. I need the information of them. But I am new in this field. Thank you. Xiangdong Li
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Compare FPGA features and resources
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