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Inbound dedicated toll-free service Now only 7.9 cents/minute * Use existing 800/888#s only rate will change! * Billing done in six second increments! * No set per month charge! no minimums * Does not effect your home or business outbound long distance service. A one time association fee is required at time of activation of $49.95 is due upon sign up Free first 30 minutes of usage if ordered by july 5,1997 Billing Information: last______________________first_______________________mi,_____ address____________________________city_______________________ state___________zip code____________________ phone:__________________fax:_______________________ Where do you wish to have this 800/888# ring?________________________ Do you have a 800/888# you wish to receive this rate on?_________________ We take: Mastercard,Visa,Amex,Discover,Money Orders or Checks Card Number_______________________________exp____/_____ signature___________________________date_______/____/____ fax completed application to: 213-650-9031 Or call for more information: 213-650-1027 Virtual Office Communications Company. 7985 santa monica bl. 109-416 West Hollywood CA. 90046-5112Article: 6851
FPGA prototype board(perri@si.deis.unical.it) Steve Martindell wrote: > > I'm looking for a board that would have a Xilinx or Altera FPGA(either > soldered or socketed) with all the FPGA I/O pins brought out to a > connector(s). A board like this would allow me to quickly protype > designs without having to send out to a board-shop. Does anyone > know of a company that makes a product like this? > > thanks, > Steve Martindell > s-martindell@ti.com We have carried out an FPGA's implementation of the SRT division algorithm. We have also carried out a prototype board to configure and to test the FPGA divisor via the ISA-bus without no additional hardware as EPROM or download cable. The board has to be used in a Digital Design Course. Thanks for the prototype board the same chip can be used to test any design of the students without no changes on the board are necessary once it is installed in the host computer. All the students have to do is constraining the pins. An FPGA SRAM-based/ISA-bus interface has been also carried out. The interface is constituted of an on board wire wrapped ACTEL chip and an on purpose written software tool. The same interface manages the configuration and the testing of the FPGA device. Stefania.Article: 6852
I figured it out...and here is what I found... wir2xnf upi xnfmerge upi hitop -f upi.xff -s -l upi.log -o upi hplusas6 -i upi -s -a -l upi.log -o temp hprep6 -i temp -r jed -l upi.jed -n upi There is a 'bug' in the last two programs that require the XACT environment variable to have the CPLD path as the first in the list, or they don't work at all. The EZTAG doesn't work well under NT (nor does XChecker...) so I had to make a DOS boot disk and run EZTAG and XChecker from this disk....real pain in the ass but it does work. Austin Austin Franklin <dark4room@ix.netcom.com> wrote in article <01bc85c7$1131e540$34c220cc@drt3>... > Has anyone used the Xilinx 95xx series parts? If so, what is the tool > flow...ie. what programs do you run to get it to make a downloadable > design.... I am using Viewlogic WVOffice as the front end.... I assume I > have to run wir2xnf...but what then? > > I am running these tools under NT 4.0.... > > Any input would be appreciated... > > Austin Franklin > darkroom@ix.netcom.com > > remove the number from the reply address to reply directly... > > >Article: 6853
Like most everyone, we just learned of Altera's Flex6000 line. It seems a bit of a departure from Altera's normal months-long hype prior to device release, so was kind of a surprise. We are planning designs in Flex10K parts, some may be candidates for the Flex6000, but with so little knowledge of the new parts, we're not sure yet if this is the right move. Were there some behind-the-scenes customers that got "pre-release" parts, if so, would any of them be willing to share their experiences? Thanks in advance, Brad Kelley Amtech Systems Corp. bkelley_nospam@alb.asctmd.com (Take out the "_nospam" from above for direct email response!)Article: 6854
Greg Brown wrote: > > Robert M. Münch wrote: > > > > [Robert M. Münch] Yes, don't use Veribest! Their programs are a > > collection of bugs! Nothing works! We tried the synthesis and their > > optimizer is real good -> you won't get any signal in the result if you > > are lucky and the program doens't crash your machine! Try Synopsis FPGA > > Express and VCS. > > > > Robert M. Muench > > SCRAP EDV-Anlagen GmbH, Karlsruhe, Germany > > > > ==> Private mail : r.m.muench@ieee.org <== > > ==> ask for PGP public-key <== > > An interesting collection of comments, especially given that you > recommend > FPGA Express which is the same synthesis tool we OEM. > Robert M. Münch was probably refering to the previous synthesis tool (from AT&T if I am correct) Veribest was selling until this recent OEM agreement with Synopsys. Jean-Michel VuillamyArticle: 6855
A free newsletter discussing EDA topics and examples is available by sending an email to eda@associatedpro.com withe SUBSCRIBE in the header. Last quarter's newsletter can be seen at http:/www.erols.com/NL_APR97.html This quarters newsletter is about to be released and will contain some new VHDL topic discussions along with an X84 Tech note on setting up an addressable IO port using the x84's on board 8255 and the XILINX 84 pin PLCC. You can also access our free on line FPGA/VHDL tutorial/labs at: http://www.erols.com/aaps/x84lab -- _____________________________________________________ Richard Schwarz, President Associated Professional Systems Inc. (APS) 3003 Latrobe Court Abingdon, Maryland 21009 USA email: aaps@erols.com web site: http://www.erols.com/aaps Phone: 410-515-3883 or 410-290-3918 Fax: 410-661-2760 or 410-290-8146Article: 6856
I don't know of a FAQ for this newsgroup but we've compiled a significant and comprehensive amount of information on programmable logic at http://www.optimagic.com. I would also be interested in what questions that you hope to find in the FAQ. -- Steven Knapp OptiMagic(tm) Logic Design Solutions E-mail: sknapp @ optimagic.com Programmable Logic Jump Station: http://www.optimagic.com Dmitry Cherniavsky <cdm@javad.ru> wrote in article <33BA1928.75B5@javad.ru>... | -- |Article: 6857
You may want to look at the X84 systems sold by APS at 'http://www.erols.com/aaps/x84.html'. While they may not have _everything_ that you ask for, they do come close. Now, the word "inexpensive" if this case means $650 but includes support for the XC3042A, most of Xilinx' lower-density devices, and all of their CPLD products. There's more on the entire system in the following Adobe Acrobat document 'http://www.xilinx.com/products/software/found_sh.pdf' -- Steven Knapp OptiMagic(tm) Logic Design Solutions E-mail: sknapp @ optimagic.com Programmable Logic Jump Station: http://www.optimagic.com D.F. Spencer <#starfire@pacbell.net> wrote in article <33B97C8D.7EDF@pacbell.net>... | Hi all - | | I know this may be a pipe dream but... | | Does anyone know of an "inexpensive" development system for the | Xilinx 3042A FPGA? It should have a socketed programmer with some | sort of interface for a serial/parallel port to a PC, schematic | capture (running on a PC), and potentially some sort of simulator | (also running on the PC). | | I'm looking for an inexpensive way to develop these chips for use | on the IP-Xilinx IP module made by Greenspring for use in an embedded | system. | | Any and all pointers to the right direction would be appreciated. | | TIA | | Dave | | | ===================================================== | NOTE : The return address in the e-mail header is bogus to reduce spam. | The correct return address is starfire@pacbell.net | (eliminate the leading # symbol). |Article: 6858
| | Could any body tell me what are at the moment the larger devices of the | 40xxE and 40xxEX series available. I now a 4025 is very much in use, | but I would like to know if the higher gate count devices like | 4036EX, 4044EX, ... are already easy to get, and if they are already | supported by tools like Synopsys-fpga compiler ?? All of the XC40xxE family is out and available. There are two of the XC40xxEX devices available and include the XC4028EX (same basic layout as the XC4025E but with twice the routing) and the XC4036EX. Beyond that, you'll need to move to the XC40xxXL family, which has the same architecture but uses a 3.3 volt VCC. The 'XL parts can accept 5 volt inputs and can send a valid TTL high to an HCT-compatible CMOS device (most 5 volt devices out there). I believe that the entire range of 'XL parts from the XC4036XL to the XC4085XL are either in sampling or production. I'd call the local Xilinx folks to find out for sure. One thing is that you will need the new M1 software to use the 'EX and 'XL devices. I don't believe that it's fully released yet but I've been able to get a copy through my local office. | | Do you know if there exists pin-compatible versions of the larger ones | to the 4025E or 4036EX ?? If my design-modules don't fit in one, I | could try to get a higher density part without making a new board ? This somewhat depends on which package that you're using. For example, the PQ208 package looks to be footprint compatible up to the XC4044XL. The PQ240 looks to be footprint compatible all the way up to the XC4062XL. | | Does any body know if prototype boards with at least 4 to 6 of these | large devices are available (with the possibility to add some glue | logic to them) ? I haven't seen such a board yet but I would recommend checking out Aptix at 'http://www.aptix.com/Products/products.html'. -- Steven Knapp OptiMagic(tm) Logic Design Solutions E-mail: sknapp @ optimagic.com Programmable Logic Jump Station: http://www.optimagic.comArticle: 6859
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Tom Burgess wrote: > > Just curious about the mental model I should use here. Is it like a > 5.5V "superZener", or something less fixed & abrupt? I'm wondering, too, > about the clamping effect on overshoots. Is a Spice model available? > The relevant patent number would also be helpful. This certainly > sounds like the way 3V input protection should work, and I congratulate Xilinx for doing the right thing on this. Power sequencing requirements would have been a total nightmare. > > regards, tom > tburgess@drao.nrc.ca The circuit is considerably more complex than you indicated. I was wrong in calling it "patented". The patent is still pending, so I cannot really tell you more about the details. Just one thing: It does not clamp at 5.5 V. The voltage can go up to 7 V without any effect, but we do not recommend to feed a constant current from a high-voltage source. I'll publish the patent number once it is granted. Thanks for the complimentary remarks. It looks like we did just the right thing. Peter Alfke, Xilinx ApplicationsArticle: 6861
hi, I am trying to place and route an edif file I generate using Exemplar's Leonardo tool with Maxplus2. The edif file has the hierarchy of my verilog design but when I write the verilog file from maxplus2, it flattens all the design and only top level module is in the .vo file. Any ideas how to fix this ? I am using maxplus2 version 7.2.2 if it makes a difference. thanks muzo WDM & NT Kernel Driver Development Consulting <muzok@pacbell.net>Article: 6862
In article <5pbcst$vh2@nntp6.u.washington.edu>, fpm@u.washington.edu (Frank Miles) says:
>
>In article <5p81b8$41k$1@wnnews.sci.kun.nl>,
>Bill Sloman <sloman@sci.kun.nl> wrote:
>>In article <ECIqFs.16J@world.std.com>, jhallen@world.std.com (Joseph H Allen) says:
<snip>
>>The oscilloscope manufacturers definitely use their own custom chips -
>>TriQuint was originally the Tektronix in-house chip source. When designing
>>such systems, there are real advantages to using balanced signals
>>and current-steering logic for interconects, so there is a preference
>>for ECL over TTL and CMOS in the vicinity of the input.
>>
>>I've done a similar sort of system, with systematically interleaved
>>sampling, for a stroboscopic electron microscope. We use a mixture
>>of Gigabit Logic GaAs and 100k ECL with a small admixture of discrete
>>components. E-mail me if you want more details.
>
>I'm not sure how Tek et al. do it these days,
So you haven't heard of TriQuint then ...?
>but remember than random
>sampling has been done for many years before GaAs or ECL ICs were
>available.
And I've done it, but ECL ics certainly make it easier.
>The usual technique is to have a fast ramp generator which starts on
>a trigger event, and is stopped by an internal clock. The amplitude
>of the fast ramp is then a measure of time offset. So long as the
>triggering events and internal clock are not in time sync, one can
>fill up a display window for repetitive waveforms after enough trigger
>events have occurred. For example, with care, you can get subnanosecond
>resolution of relative time using LS-speed logic and some discrete
>analog circuitry. Long before ICs were available, random sampling made
>it possible to view waveforms with bandwidths in the low GHz range.
>I don't know of any commercially available ICs that do all the work
>for you. There may be more direct digital approaches if your needs
>are not all that great, by running extremely fast clocks and counters,
>but to this analog guy it seems a gross way of doing things.
The GaAs and ECL logic in our system was used to let us sample,
digitize and accumulate at 40nsec intervals, to enable us to sample
repeatedly on a single trigger. The system used a 800MHz clock for
coarse timing with linear ramps digitised to 8-bits for fine timing (to
5psec in theory - closer to 60psec in practice). It was a gross system
from several points of view, but it was brilliant for sampling low
repetition rate signals. And still worked fine when your sampling probe
was reduced to a single 1kV electron....
Bill Sloman (sloman@sci.kun.nl) | Precision analog design
TZ/Electronics, Science Faculty, | Fast analog design and layout
Nijmegen University, The Netherlands | Very fast digital design/layout
| e-mail for rates and conditions.
Article: 6863The 2nd quarter APS EDA Newsletter has been released. It can be seen at: http://www.associatedpro.com/aps/NL_Q2_97.html Those who wish to subscribe to future releases need to simply send an email with EDA SUBSCRIBE in the subject header -- ---------------------------------------------------------------- Associated Professional Systems (APS) EDA and Communications Tools http://www.associatedpro.com richard@associatedpro.com 410.569.5897 fx:410.661.2760Article: 6864
muzo wrote: > > hi, > I am trying to place and route an edif file I generate using Exemplar's Leonardo > tool with Maxplus2. The edif file has the hierarchy of my verilog design but when > I write the verilog file from maxplus2, it flattens all the design and only top > level module is in the .vo file. Any ideas how to fix this ? I am using maxplus2 > version 7.2.2 if it makes a difference. > > thanks > > muzo > > WDM & NT Kernel Driver Development Consulting <muzok@pacbell.net> If you are able to generate the Verilog netlist, you must have been successful in "placing and routing" the design. The Max+Plus II place and route tool writes a flatten, structural Verilog netlist after a successful "fit" is completed. You will see this in the Compiler window as Max+Plus II compiles a design. The Verilog netlist corresponds directly to the optimized logic produced by the "place-and-route" step which itself flattens the design. The netlist contains instantiations of the Verilog primitives defined in the alt_max2.vo file which corresponds directly to the logic elements of the target Altera. device. Since the Verilog netlist of the "fitted" design is flat, it is difficult to plug the netlist back into a simulation testbench (i.e., one that you may have used to simulate the Verilog RTL code) if you specifically simulated only particular sub-blocks of the design and not the whole design at the top-level. I do not know (but someone else may) how to tell Max+Plus II to write an hierarchical netlist. Regards, ---------------------------------------------------------------- Scott Guest - MSS Nortel Technology SPM OC-3 HW Dev.(3H54) 35 Davis Drive ph (919) 991-2215 Research Triangle Park, NC 27709 ESN 6-294-2215 E-mail: cnc274@nortel.ca FAX (919) 991-7754 ----------------------------------------------------------------Article: 6865
Joseph H Allen (jhallen@world.std.com) wrote: > In some fast digital scopes they increase the vertical resolution of > repetitive signals by sampling at random different times during each period, > and "filling in" more holes on the screen as time goes on. Thus if you have > an ADC with a 2GHz bandwidth but only a 100MHz sample rate and low sample > jitter, you can still effectively sample at 2GHz. There is no requirement that the sampling be "random" in the sense that you mean. A common misunderstanding of the sampling theorem is that it says that you can only recover information at FREQUENCIES below half the sampling rate. As stated, this is not strictly correct. What Shannon & Nyquist actually tell us is that for a given sampling rate, you can sample & recover any RANGE of frequencies whose BANDWIDTH is less than half the sampling rate. The most common example given of sampling happens to be basedband signals, but there's no real reason that this would be the only case. For instance, most would accept that you can sample the 0-20 kHz range with a sampling rate of 40 kHz (actually, this gets you to just BELOW 20 kHz); but what most also fail to realize is that you can also safely sample, say, 10.000 MHz - 10.020 MHz with that same sampling rate. The trick lies in knowing, at reconstruction (aka "demodulation", if you're more comfortable with it in those terms), exactly WHICH 20 kHz band was intended. For further exercise, consider how a "direct conversion" AM receiver works. Bob Myers KC0EW Hewlett-Packard Co. |Opinions expressed here are not O- Workstations Systems Div.|those of my employer or any other myers@fc.hp.com Fort Collins, Colorado |sentient life-form on this planet.Article: 6866
In article <5pgcc1$fhh$1@wnnews.sci.kun.nl>,
Bill Sloman <sloman@sci.kun.nl> wrote:
>The GaAs and ECL logic in our system was used to let us sample,
>digitize and accumulate at 40nsec intervals, to enable us to sample
>repeatedly on a single trigger. The system used a 800MHz clock for
>coarse timing with linear ramps digitised to 8-bits for fine timing (to
>5psec in theory - closer to 60psec in practice). It was a gross system
>from several points of view, but it was brilliant for sampling low
>repetition rate signals. And still worked fine when your sampling probe
>was reduced to a single 1kV electron....
I started this thread because I'm working on a high-frequency multi-format
(10MHz - at least 140MHz dot clocks) still-video capturer and I'm exploring
the options for pixel clock (sample edge) generation. These are what I've
come up with so far:
- Capture at some fixed high frequency not syncronized to the video- with
maybe 4x oversampling for the highest video rate. You can then use a
median filter on the set of samples which you think makes up a particular
pixel. The problem with this method is that, of course, 500MHz A/Ds cost
$700 each. Also I don't look forward to dealing with a 250MHz 16 bit data
path and the ECL demultiplexer which would be required. (someone should
make a single-chip 8-bit 1:4 or 1:8 ECL-in TTL-out demultiplexer which
includes all timing circuits for just this purpose- I known Brooktree
makes the reverse: an 8:1 TTL to ECL multiplexer for feeding a DAC).
- The traditional method is to use a PLL frequency synthesizer with horz
sync used as the reference clock- you capture one sample per pixel and
hope that it's near the center of the pixel. The problems are that
vertical sync and serration edges do not necessarily occur at the same
times as horz sync edges (this can be fixed with masking), that the PLL
becomes sensitive to noise as the multiplication factor increases, and
that the loop filter has to be adjusted depending on the multiplication
factor (it really needs to be close to critical damping for all video
formats to work well). This may still be the cheapest way of doing it.
Another requirement is that there can't be any tuning, so this makes me
leery of this method.
- Use a VCXO PLL. This only has about 100ppm range, so you lock to the
leading edge of every fourth vertical sync. If you sample four successive
frames you'll get lots of precisely timed samples. The problem with this
method is the really long lock-in time and although the Q of the VCXO is
so high, the vertical sync leading edge noise and immense multiplication
factor make me think it will not work in practice.
- Use a high frequency clock (I guess 700MHz for 10E ECL), to drive a shift
register which is fed by a ram. The ram address counter and shift
register load pulse generator are reset at sync edges. The ram is
programmed with the sample clock pattern to be used. This is versatile,
doesn't require too much ECL and allows you to oversample by capturing
several frames with different sample clock patterns. It's sensitive to
horz sync edge noise (but not nearly as much as the PLL is) and gives you
a 1.4 ns resolution and jitter.
- Use the trigger vernier method which you describe above. You might use
a low fixed frequency PLL (40MHz or less) to syncronize to the video and
then use SY604 trigger vernier chips (one for each clock edge) to select
the exact sample points.
This is cool because you could capture at precise times and have a huge
amount of oversampling if you wanted. However, it would have to be
calibrated and it still requires a good PLL (but an easier one since it
could run at a fixed frequency for any video format).
Maybe instead of using the PLL, you could use a stable multivibrator
(74S124?) which is enabled after each horz. sync. This might be workable
if you calibrated before each capture.
Incidentally, does GigabitLogic still exist? If not, who is making GaAs
logic these days? A 1989 databook I have from them lists parts which are
better than ECL-lite (the best I can find today).
--
/* jhallen@world.std.com (192.74.137.5) */ /* Joseph H. Allen */
int a[1817];main(z,p,q,r){for(p=80;q+p-80;p-=2*a[p])for(z=9;z--;)q=3&(r=time(0)
+r*57)/7,q=q?q-1?q-2?1-p%79?-1:0:p%79-77?1:0:p<1659?79:0:p>158?-79:0,q?!a[p+q*2
]?a[p+=a[p+=q]=q]=q:0:0;for(;q++-1817;)printf(q%79?"%c":"%c\n"," #"[!a[q-1]]);}
Article: 6867Great Site URL:http://www.psrinc.com/metsys.htmArticle: 6868
1) No Spam 2) Respect your elders Austin.... P.S. This is just my opinion.... Dmitry Cherniavsky <cdm@javad.ru> wrote in article <33BA1928.75B5@javad.ru>... > -- >Article: 6869
Frank Gilbert wrote:
> Reetinder P. S. Sidhu wrote:
> > I'm working with simple and regular designs but require
> > complete control over place and route.
> and then wrote
> You can use "velab" to convert structural VHDL to EDIF.
The other alternative is to use the Lola HDL, which allows total control
over place and route, and is pretty quick and easy to learn. I've a web
page devoted to it, with links to the ETH site at
http://www.eee.bham.ac.uk/James-RoxbyP/lola.htm
Like velab, it is free, but the difference is you can go all the way
through to a bitstream file without having to touch the xact. Lola
often routes stuff xact falls down on, or does in a strange way, and it
is a hell of a lot quicker.
--
( ) Dr Phil James-Roxby
`--(_ _)--' Birmingham
Y-Y Mr Moose says England
/@@ \ "Lola's the one for me, +44 121 414 7506
/ \ comp.arch.rpu NOW"
`--'. \
| `.__________/) Orange : 0976 409124
Article: 6870> -----Original Message----- > From: Jean-Michel Vuillamy [SMTP:vuillamy@club-internet.fr] > Posted At: Wednesday, July 02, 1997 9:58 PM > Posted To: fpga > Conversation: Verilog Simulation and Synthesis for FPGA Devices > Subject: Re: Verilog Simulation and Synthesis for FPGA Devices > > Robert M. Münch was probably refering to the previous synthesis > tool (from AT&T if I am correct) Veribest was selling until this > recent OEM agreement with Synopsys. [Robert M. Münch] Yep, absolutly right! But Veribest had bad luck we changed our tool-vendor as they made this decision to late for us... Robert M. Muench SCRAP EDV-Anlagen GmbH, Karlsruhe, Germany ==> Private mail : r.m.muench@ieee.org <== ==> ask for PGP public-key <==Article: 6871
Hi, I need a 64 byte FIFO in my design. I'm targetting XC4000XL technology. I have independent read and write clocks. I think the data should stored in a edge-triggered dual-port RAM or in an array of four 16 byte DPRAMs. Does anybody know a simple way to describe (instantiate) this kind of FIFO system in VHDL? Or do I have to code the buffer control logic in ordinary way and to instantiate only the DPRAM? If this is the case then how is 64 x 8 bits DPRAM described in VHDL? I'm using either Exemplar Logic's Leonardo or Synopsys FPGA Compiler for synthesis. Any advice is appreciated! Best regards, Mark H. SandstromArticle: 6872
Does anybody have experience with the techniques of using several ADCs with a single input signal and sampling each in a ping-pong manner or sequence such that with say 4 ADCs, couldn't you get four times the sampling rate of a single device Each device would still require the full analog input bandwidth for its sample- hold, right? Don't people like HP use it in their v.fast 8 bit ADC sub-systems? I've seen a commercial product from Gage that does it at 100MHz with 2x12-bit converters. Main questions: What problems are there with this technique. Do you get anywhere close to doubling the sampling rate? What techniques are used to generate high accuracy sampling signals. As long as aperture jitter is good enough, can't you correct for a fixed error in the sampling times i.e. 9nS 1st to 2nd sample, 11nS 2nd to 3rd, 9ns 3rd to 4th etc. But would this work successfully for a wideband input (e.g. 40 MHz BW with 2 off 50 MHz ADCs) Thanks Paul BaxterArticle: 6873
You will need to instantiate the 16x1 RAM blocks via synthesis. I don't know of a complete FIFO that you can directly instantiate. There is more on how to instantiate the RAM blocks in Xilinx' "HDL Synthesis for FPGAs Design Guide" which is available as an Acrobat document at 'http://www.xilinx.com/apps/hdl.htm'. There is also a good application note on FIFO design at 'http://www.xilinx.com/apps/memory.htm#appnote' (See XAPP051 and XAPP053). -- Steven Knapp OptiMagic(tm) Logic Design Solutions E-mail: sknapp @ optimagic.com Programmable Logic Jump Station: http://www.optimagic.com Mark Sandstrom <Mark.Sandstrom@martis.fi> wrote in article <33BCD110.92E@martis.fi>... | Hi, | | I need a 64 byte FIFO in my design. I'm targetting XC4000XL technology. | I have independent read and write clocks. I think the data should stored | in a edge-triggered dual-port RAM or in an array of four 16 byte DPRAMs. | Does anybody know a simple way to describe (instantiate) this kind of | FIFO system in VHDL? | Or do I have to code the buffer control logic in ordinary way and to | instantiate only the DPRAM? If this is the case then how is 64 x 8 bits | DPRAM described in VHDL? | I'm using either Exemplar Logic's Leonardo or Synopsys FPGA Compiler for | synthesis. | | Any advice is appreciated! | | Best regards, | | Mark H. Sandstrom |Article: 6874
In article <01bc886b$bfea1ac0$35091ba0@paje.globalnet.co.uk>,
Paul Baxter <paje@globalnet.co.uk> wrote:
>
>Does anybody have experience with the techniques of using several ADCs with
>a single input signal and sampling each in a ping-pong manner or sequence
>such that with say 4 ADCs, couldn't you get four times the sampling rate of
>a single device
For the case of two ADC with differential inputs and a 50% duty cycle clock,
it's easy. Recent ADCs have much lower input capacitance than older ones,
which also helps. If you share the reference voltage, the ADCs should be
matched.
>As long as aperture jitter is good enough, can't you correct for a fixed
>error in the sampling times i.e. 9nS 1st to 2nd sample, 11nS 2nd to 3rd,
>9ns 3rd to 4th etc.
How do you do this? Would it require a good anti-alias filter? For
synchronous video capturing you often don't have any anti-alias filter.
>But would this work successfully for a wideband input (e.g. 40 MHz BW with
>2 off 50 MHz ADCs)
--
/* jhallen@world.std.com (192.74.137.5) */ /* Joseph H. Allen */
int a[1817];main(z,p,q,r){for(p=80;q+p-80;p-=2*a[p])for(z=9;z--;)q=3&(r=time(0)
+r*57)/7,q=q?q-1?q-2?1-p%79?-1:0:p%79-77?1:0:p<1659?79:0:p>158?-79:0,q?!a[p+q*2
]?a[p+=a[p+=q]=q]=q:0:0;for(;q++-1817;)printf(q%79?"%c":"%c\n"," #"[!a[q-1]]);}
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