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Authors (K)
K:
20133: 00/01/28: LVPECL I/O interface
k:
30651: 01/04/20: Hobbiest + LINUX
K d:
89769: 05/09/26: lwip sockets on spartan 3 microblaze? Any examples?
k e:
91534: 05/11/08: What are important factors when selecting Intellectual Property?
k flash:
73599: 04/09/24: HDL Behaviorial Model for an LCD Controller
K Goldman:
4503: 96/11/06: Re: PCB Handling of chip packages greater than 100 pins?
4629: 96/11/22: Re: Course/fine grain netlists?
5278: 97/02/03: Re: Safety Critical Apps -> Xilinx Checker.
K Mussatt:
59290: 03/08/14: Re: Yet another modelsim problem
66415: 04/02/19: Re: Dual clock FIFO with Atmel FPGA ??
K PRASAD:
41850: 02/04/09: regarding gate count of the design
41978: 02/04/11: regarding synthesis of signal and variable
42264: 02/04/19: Re: regarding synthesis of signal and variable
42319: 02/04/19: Re: ModelSim closes for unknown reason
43045: 02/05/10: timing violations in fpgas
68605: 04/04/09: regardinng static timing annalysis
K W:
55893: 03/05/22: Altera aquire a second DSP IP company
K.:
31551: 01/05/29: Re: Fun with DLLs.
k.:
38218: 02/01/09: bufg instantiation in ISE 4.1
38259: 02/01/10: Re: bufg instantiation in ISE 4.1
38260: 02/01/10: Re: bufg instantiation in ISE 4.1
39256: 02/02/05: Re: Destroying a CPLD by JTAG
K. C. Lee:
26319: 00/10/11: Re: Analogue FPGAs ?
26391: 00/10/13: Re: Analogue FPGAs ?
K. Mori:
24589: 00/08/14: Re: Virtex CLKDLL and Leonardo
25161: 00/08/29: Anyone used Spartan II XC2S200 yet?
25202: 00/08/30: Re: Anyone used Spartan II XC2S200 yet?
K. Orthner:
24213: 00/07/30: Re: OT: was: Re: Which one is good coding style?
24214: 00/07/30: Re: Which one is good coding style?
24215: 00/07/30: Free-running Oscillator.
24324: 00/08/04: Re: End of my rope.
24271: 00/08/02: Re: Desperatly needing a SpartanII
24295: 00/08/03: Re: GPIO board for Avnet Virtex Development system ?
24301: 00/08/03: Re: models of digital ICs
24325: 00/08/04: Re: Who needs all those printed ac parameters?
24400: 00/08/07: Re: FPGA selection
24401: 00/08/07: Crossing Clock Domains.
24404: 00/08/07: Re: FPGA selection
24964: 00/08/23: Re: timing simulation vs functional one
24968: 00/08/23: Re: create a RAM in a Virtex
24967: 00/08/23: Re: create a RAM in a Virtex
25061: 00/08/25: Xilinx 3.1i ISE
25062: 00/08/25: Re: Xilinx 3.1i ISE
25225: 00/08/31: Re: Latches
25238: 00/08/31: Re: Latches
25466: 00/09/12: Re: Is this practical?
25505: 00/09/13: Re: Complaint: Xilinx functional simulation libraries
25512: 00/09/13: Re: Complaint: Xilinx functional simulation libraries
25517: 00/09/13: Re: Complaint: Xilinx functional simulation libraries
25519: 00/09/13: Re: Complaint: Xilinx functional simulation libraries
25699: 00/09/18: Re: Are SpartanIIs in FG456 drop in replacements for Virtex FG456
25748: 00/09/19: Re: JTAG CPLD FPGA
25752: 00/09/19: Re: Xilinx Web Pack
25778: 00/09/20: Re: Complaint: Xilinx functional simulation libraries
25779: 00/09/20: Re: Freelance Designer Needed: Protel & FPGA
25808: 00/09/21: Re: A Question on Virtex Configuration
25885: 00/09/25: Re: 20 bit to 64 bit bus conversion
25909: 00/09/26: Re: Using the xilinx "pull-up to 5V" in VHDL
25919: 00/09/26: Re: Using the xilinx "pull-up to 5V" in VHDL
K. P. Wang:
1567: 95/07/18: benchmarks and PD program for channel routing
K. S. Venkatraman:
4188: 96/09/23: FIR filter using FPGAs??
5933: 97/03/27: Computer Architecture - IC design position wanted
6129: 97/04/14: Wallace Tree Multiplier Documentation wanted
6517: 97/05/30: FAQ's / Documentation sites wanted
6518: 97/05/30: Re: new to FPGAs
K. Sudheer Kumar:
114504: 07/01/17: Generation of Divided-by-3 clock
K. Tyler:
11568: 98/08/24: Re: professional autorouters
K. Y. Chan:
12124: 98/09/30: need fpga contract work
<k.hopkins@btinternet.com>:
85282: 05/06/07: Re: Sch & Layout Free Program
K.J. Seefried III:
25858: 00/09/23: PDP-11
26038: 00/10/01: Migrating PAL/TTL design to FPGA
<K.M.>:
364: 94/10/29: Re: fpga
K.O:
33489: 01/07/28: Re: SRL16
33982: 01/08/09: multplier
34198: 01/08/16: Re: Internal clock skew when using DLL
34280: 01/08/18: Re: Internal clock skew when using DLL
K.Orthner:
24022: 00/07/24: Virtex DLL problem.
24023: 00/07/24: Re: Real time sims with NC-Verilog
24024: 00/07/24: Re: Silicon Valley Housing Nightmare?
24027: 00/07/24: Xilinx Core Generators.
24035: 00/07/24: Re: Virtex DLL problem.
24057: 00/07/25: Xilinx "MUX_OP not inferred" error.
24068: 00/07/26: Re: Xilinx "MUX_OP not inferred" error.
24075: 00/07/26: Re: Xilinx Core Generators.
24079: 00/07/26: Re: Xilinx "MUX_OP not inferred" error.
24107: 00/07/27: Re: Xilinx "MUX_OP not inferred" error.
24106: 00/07/27: Re: Xilinx Core Generators.
24118: 00/07/27: End of my rope.
24124: 00/07/27: Re: Which one is good coding style?
24130: 00/07/27: Re: Spartan-II power consumption
24190: 00/07/29: Re: LFSR as a divider
24192: 00/07/29: Re: Question of Virtex DLL
24191: 00/07/29: Re: implementation problem of Foundation 2.1i
24194: 00/07/29: Re: Spartan-II power consumption
24195: 00/07/29: Re: Which one is good coding style?
24199: 00/07/29: Re: Question of Virtex DLL
24166: 00/07/28: Re: LFSR as a divider
32103: 01/06/13: Re: Fifo Clock in SpartanII
<K.Pisaniec@gmail.com>:
119906: 07/05/29: Re: JTAG FPGA Debugging
k.sandeep.p:
97307: 06/02/20: Any one worked with Digilent Adept(transport) feature??
k1492799:
18601: 99/11/02: logic fault simulation
K4MON:
72205: 04/08/11: FPGA/CPLD from logic diagram?
K7ITM:
97467: 06/02/22: Re: Input stage for VHF frequency counter in an FPGA?
Ka-Chung Wong:
1737: 95/08/21: Re: FPGAs with embedded RAM
1874: 95/09/13: Re: Newbie question about PLDshell
1903: 95/09/18: Re: Fast FPGA's?
kaa:
151727: 11/05/11: FPGA cards with memory bus interface
Kaalia Anthony:
86853: 05/07/07: QAM 64 implementation on a FPGA board
87650: 05/07/27: stratix gx query
kadhiem_ayob:
135477: 08/10/03: Re: Low frequency clock generation - need help
135480: 08/10/03: Re: Low frequency clock generation - need help
135485: 08/10/04: Re: Low frequency clock generation - need help
135486: 08/10/04: Re: Do two clock system blocks with one clock running half of other's need asynchronous input/output buffers?
135885: 08/10/20: Re: external differential clock inputs
136569: 08/11/22: Re: Generate sample rate ...
136572: 08/11/22: Re: Generate sample rate ...
136575: 08/11/22: Re: Generate sample rate ...
136577: 08/11/22: Re: Generate sample rate ...
136578: 08/11/22: Re: Generate sample rate ...
136579: 08/11/22: Re: Generate sample rate ...
136581: 08/11/23: Re: Generate sample rate ...
136942: 08/12/15: Re: Looking for FPGA engineer for HD camera project
137053: 08/12/21: Re: filtering decimation of a signal
137369: 09/01/12: Re: what is the difference between two process model & one process model
137385: 09/01/13: Re: Counter: natural VS std_logic_vector
137618: 09/01/23: Re: Altera 3000A: Can I make a freq. generator (1 Hz to 2 kHz) ?
138166: 09/02/08: Re: Is this phase accumulator trick well-known???
139162: 09/03/22: Re: Xilinx XAPP052 LFSR and its understanding
139166: 09/03/22: Re: Xilinx XAPP052 LFSR and its understanding
139180: 09/03/22: Re: Xilinx XAPP052 LFSR and its understanding
139192: 09/03/23: Re: Xilinx XAPP052 LFSR and its understanding
139639: 09/04/08: Two stage synchroniser,how does it work?
139641: 09/04/08: Re: Two stage synchroniser,how does it work?
139643: 09/04/08: Re: Two stage synchroniser,how does it work?
139647: 09/04/08: Re: Two stage synchroniser,how does it work?
139651: 09/04/08: Re: Two stage synchroniser,how does it work?
139664: 09/04/08: Re: Two stage synchroniser,how does it work?
139667: 09/04/08: Re: Two stage synchroniser,how does it work?
139692: 09/04/09: Re: Two stage synchroniser,how does it work?
139738: 09/04/11: Re: S3A starterkit weird behaviou (mini quiz)
139835: 09/04/15: Re: Synchronous clocking between Cyclone III and SDRAM
139836: 09/04/15: Re: Synchronous clocking between Cyclone III and SDRAM
139841: 09/04/16: Re: Synchronous clocking between Cyclone III and SDRAM
143562: 09/10/16: ModelSim fails to connect my project components
145071: 10/01/24: Re: offset constrain report confusion
145115: 10/01/28: Re: offset constrain report confusion
148243: 10/07/01: carrier tracking over zero frequency point
148262: 10/07/02: Re: carrier tracking over zero frequency point
148266: 10/07/03: Re: carrier tracking over zero frequency point
148811: 10/08/28: Re: Plotting sampled data in Matlab
148812: 10/08/28: Stratix iv PLLs ref clock
148814: 10/08/28: Re: Stratix iv PLLs ref clock
148823: 10/08/29: Re: Plotting sampled data in Matlab
149223: 10/10/09: matched filter(root raised cosine)
149247: 10/10/11: Re: matched filter(root raised cosine)
KADIONIK Patrice:
2088: 95/10/12: Re: * WARNING * $1,000,000 in 90 Days!
Kadir Solid Gold Suleyman:
77487: 05/01/07: Re: San Jose job offer - need advice
kagior:
89593: 05/09/20: SoC embedded FPGA
kahhean:
34542: 01/08/29: Gate Count Definition
<kahhean@bigfoot.com>:
30413: 01/04/07: DLL locking problem
30497: 01/04/11: Re: DLL locking problem
30499: 01/04/11: FPGA Express 3.5 One hot state machine Synthesis problem
Kai Eckert:
44784: 02/07/01: Altera Archive
Kai Harrekilde-Petersen:
9263: 98/03/05: Re: The case for Linux and EDA
43458: 02/05/21: Re: Synchronous Single Clock Designs
44885: 02/07/04: Re: Modelsim 5.6a for Linux execution problem
47898: 02/10/07: Re: .13 micron - what does it indicate
54975: 03/04/23: Re: hardware implementation of viterbi decoder
71078: 04/07/07: Re: FSM in illegal state
75287: 04/11/01: Re: max frequency with TSMC .18u std cell library
82011: 05/04/05: Re: ISA vs. patent/trademark
111044: 06/10/27: Re: Survey: simulator usage
122444: 07/07/27: Re: Best CPU platform(s) for FPGA synthesis
122458: 07/07/27: Re: Best CPU platform(s) for FPGA synthesis
122459: 07/07/27: Re: Best CPU platform(s) for FPGA synthesis
Kai Schulze:
23721: 00/07/06: XILINX configuration
23726: 00/07/06: Clock Buffer
Kai Troester:
18326: 99/10/15: Re: compiling vhdl code(help please)
18448: 99/10/25: Re: FPGA Timing Problem
19660: 00/01/07: Disable clockbuffer for only a single flip-flop
19728: 00/01/10: THANX: Disable clockbuffer for only a single flip-flop
20353: 00/02/07: Why does Virtex has no EPROM support like XC4000
20379: 00/02/08: FPGA express: No clockbuf for rst
20387: 00/02/08: Re: FPGA express: No clockbuf for rst
Kai Woska:
15284: 99/03/17: Searching binary data for configurating Xilinx XC6216
Kaj Hedin:
42481: 02/04/24: counter application
Kaj Norman Nielsen:
3166: 96/04/17: AMD-MACH-devices with PSPICE
3251: 96/05/03: Re: Simple Xilinx board
3252: 96/05/03: Re: Simple Xilinx board
3253: 96/05/03: Re: Simple Xilinx board
3254: 96/05/03: Re: Simple Xilinx board
kal:
67140: 04/03/06: Re: Release asynchrounous resets synchronously
67225: 04/03/08: Re: Can `protect-ed Verilog codes be synthesized with Xilinx XST?
67234: 04/03/09: Re: Release asynchrounous resets synchronously
68260: 04/03/31: Re: Metastablility
69488: 04/05/12: Re: One issue about free hardware
71500: 04/07/20: Re: Open Collector Circuit - How to Simulate?
72387: 04/08/17: Re: Rocket IO Deserializer
<kal@dspia.com>:
136851: 08/12/08: Re: FPGA-ASIC Migration
kaleo:
79134: 05/02/14: Recommended Single Board FPGA manufacturer
kali:
81352: 05/03/22: SystemC and OCP-IP
Kalle:
84862: 05/05/31: Timing summary
84863: 05/05/31: Re: Timing summary
kalle Henriksson:
18338: 99/10/16: Xilinx 4k and DPRAM for leonardo question
Kalle Palomäki:
16926: 99/06/17: Re: Virtex Boards
16989: 99/06/22: Re: Virtex Boards
kalogera:
55886: 03/05/22: FPGA : Partial Reconfiguration
Kalogerakis Panagiotis:
54624: 03/04/15: Re: Bus Macros:Power Supply
<kalvarajesh2003@gmail.com>:
124852: 07/10/08: code coverage in modelsim_se
124870: 07/10/09: code coverage in modesim se 6.1f
Kalyan Gokhale:
3458: 96/06/03: RS422 Connections and Pin-outs
3527: 96/06/14: FPGA Conversions
10631: 98/06/07: FPGA Conversion
13131: 98/11/16: Re: Big-Endian vs Little-Endian
15859: 99/04/16: VHDL Tutorial/Class
Kamal:
40189: 02/03/01: Re: Is ISE3.1 a good one?
40467: 02/03/07: Re: MXE 5.5e speed
41585: 02/04/02: Re: Web pack (how to) ?
41715: 02/04/05: Re: Vertex 2 DCM problem
48594: 02/10/21: Re: ISE vs. Foundation
kamal:
22779: 00/05/24: Re: 8087 in FPGA?
23868: 00/07/14: Configuration Cache
Kamal Chaudhary:
151: 94/09/01: Re: Self-Programming Devices (was Re: Proprietary Configuration Data)
20600: 00/02/15: Re: 100% slice utilization in Virtex FPGA
Kamal Patel:
13293: 98/11/24: daisy chain help!!!!
29166: 01/02/08: Re: Xilinx vs Altera
33602: 01/07/31: Re: Schematic user info
33603: 01/07/31: Re: Schematic user info
33691: 01/08/02: Re: Alliance tools going away?
33768: 01/08/03: Re: ISE 3.3 .npl files
33836: 01/08/06: Re: Bitgen persist option
33840: 01/08/06: Re: Bitgen persist option
33842: 01/08/06: Re: Bitgen persist option
33921: 01/08/08: Re: Xilinx + WebPack + Verilog + Pin designation + Help?
33994: 01/08/10: Re: Alliance tools going away?
35004: 01/09/17: Re: Virtex-E1600 unsupported?
35086: 01/09/20: Re: Xilinx equivalent gate count value in the *.mrp report
35201: 01/09/25: Re: Xilinx 4.1 software
35433: 01/10/04: Re: ISE4 - HDL Bencher
36131: 01/10/30: Re: Device support Foundation 3.1i SP8
36414: 01/11/08: Re: about ise4.1 solaris install
36700: 01/11/16: Re: CAM
36710: 01/11/16: Re: Spartan2 - 5 V tolerance question
36829: 01/11/21: Re: Foundation ISE 4.1
36975: 01/11/27: Re: Device Support in Webpack
37003: 01/11/28: Re: XST design flow for XC4010XL
38729: 02/01/23: Re: Missing IPAD, OPAD, etc. in Xilinx WebPACK Schematic Capture Library
39482: 02/02/11: Re: XILINX Webpack 4.1 beginners question
39871: 02/02/21: Re: Using a CoreGen component
41822: 02/04/08: Re: XST Synthesis tool
42458: 02/04/24: Re: ISE 4.2 Java Problem
43190: 02/05/15: Re: Exemplar in ISE
43192: 02/05/15: Re: WEBPack 4.1 - vhdl modules in schematics?
43256: 02/05/17: Re: Problem with Xilinx ISE 4.2i map
43356: 02/05/20: Re: Upgrade to ISE4.1/4.2 ?
43734: 02/05/31: Re: Nets in multiple schematics?
47142: 02/09/18: Re: Xilinx ISE5.1 and Windows NT
47163: 02/09/19: Re: ISE 5.1 Linux?
<kamath@ecn.purdue.edu>:
16176: 99/05/07: FPGA, PLD, EPLD, CPLD differences
kami:
133720: 08/07/11: Re: Fixed point number hardware implementation
133728: 08/07/11: Re: Fixed point number hardware implementation
133743: 08/07/12: Re: Fixed point number hardware implementation
133749: 08/07/12: Re: Fixed point number hardware implementation
133750: 08/07/12: Using VHDL packages
134229: 08/07/31: Re: Using VHDL packages
134231: 08/07/31: Re: Fixed point number hardware implementation
134242: 08/07/31: Re: Fixed point number hardware implementation
134243: 08/07/31: Re: Using VHDL packages
134270: 08/08/03: Re: Fixed point number hardware implementation
<kamiak@my-deja.com>:
29210: 01/02/09: Re: verilog book
KAMRAN:
34741: 01/09/05: HOW LONG WOULD LAST LONG
kams:
66317: 04/02/17: Re: sdram controller problems
66320: 04/02/17: Re: sdram controller problems
Kamtsa:
102988: 06/05/24: WebPack ISE 8 - how to avoide 'non supported language' warnings?
103049: 06/05/24: Re: WebPack ISE 8 - how to avoide 'non supported language' warnings?
Kang Liat Chuan:
19892: 00/01/17: Re: timing diagrams
21077: 00/03/06: From Xilinx Coregen 2.1 to Mentor EDDM
22349: 00/05/05: Porting design from xc40150xv to xcv300
22557: 00/05/12: Re: simulation of Xilinx Coregen modules in schematic environment
24868: 00/08/21: Re: Distributor attitude !!
25769: 00/09/20: Re: timing constraints
26655: 00/10/24: Re: Specifying pin in design file
27065: 00/11/10: Configuring Xilinx FPGA using PIC16F84
28908: 01/01/29: Re: Is it a timing constraint problem?
28927: 01/01/30: Re: Is it a timing constraint problem?
29014: 01/02/02: How different is FPGA design from IC design
44758: 02/06/30: Re: adding timing constraints
45359: 02/07/20: Re: How's the FPGA design job market near you??
53785: 03/03/23: Need Advice on using Orcad 9.2 with Xilinx ISE 4.2
54223: 03/04/05: Help: anyone has doc on Viewsim commands? Thanks!
54294: 03/04/07: Re: anyone has doc on Viewsim commands? Thanks!
54762: 03/04/18: Help with this component: ADD_BITSLICE
66077: 04/02/12: Help: Configure PCI Device in Windows 2k
66139: 04/02/13: Re: Help: Configure PCI Device in Windows 2k
66153: 04/02/13: Problem Solved! (Re: Configure PCI Device in Windows 2k)
Kang YI:
14131: 99/01/15: HEX file format
14132: 99/01/15: Xilinx Bitstream
14133: 99/01/15: DFF/Couter behavior with clock and control signals change
<kanglc@gmail.com>:
111784: 06/11/09: Xilinx Partition for EDIF Flow (synthesis synplify)
111837: 06/11/10: Re: Xilinx Partition for EDIF Flow (synthesis synplify)
111874: 06/11/12: Re: Xilinx Partition for EDIF Flow (synthesis synplify)
<kangsotheara@gmail.com>:
156803: 14/07/03: Re: Transistor count
kangwei365@gmail.com:
116713: 07/03/15: Re: help !something wrong with Adaptive Filter (vhdl code)
116928: 07/03/20: how to make a matlab simulink wave into mif or hex form.
117821: 07/04/11: Help!! FIR Polyphase second - order interpolator
<kangwei365@gmail.com>:
116573: 07/03/13: help !something wrong with Adaptive Filter (vhdl code)
Kannan G:
43626: 02/05/27: Re: DIP4 error in Payload Contro Word in SPI4, phase2 frame.
Kant Kong:
31904: 01/06/08: Re: Block Select RAM+ Memory and NCSim
Kantha:
100923: 06/04/21: Re: problem with shift operation
101257: 06/04/28: Re: CLock Issue
<kanthi.siddela@gmail.com>:
117866: 07/04/11: how two sine signals are multiplied in VHDL language
<kaosnannaz@gmail.com>:
116171: 07/03/02: New modelsim PE student edition 6.2g and Xilinx ISE 9.1i User Linking problems
116184: 07/03/03: Re: New modelsim PE student edition 6.2g and Xilinx ISE 9.1i User Linking problems
kapatel:
154634: 12/12/04: How to transfer multiple bit data between phase shifted clock?
154638: 12/12/07: Re: How to transfer multiple bit data between phase shifted clock?
154646: 12/12/10: Re: How to transfer multiple bit data between phase shifted clock?
154647: 12/12/10: Re: How to transfer multiple bit data between phase shifted clock?
156293: 14/02/09: How to synchronize register bank used in the IP Core
156744: 14/06/13: Need help to provide input/output timing constraint for DDR Interface
156745: 14/06/13: Re: Need help to provide input/output timing constraint for DDR Interface
Kapilan Maheswaran:
12176: 98/10/02: Re: fpga-asic
Kaplan:
45470: 02/07/24: Wind River Diab Xilinx Edition
45538: 02/07/25: Re: Wind River Diab Xilinx Edition
<kapp_harald@my-deja.com>:
20662: 00/02/17: Re: Lattice isp programming problems
Kappa:
135348: 08/09/27: Re: OFDM band switch ...
136551: 08/11/21: Generate sample rate ...
136555: 08/11/21: Re: Generate sample rate ...
136557: 08/11/21: Re: Generate sample rate ...
136560: 08/11/22: Re: Generate sample rate ...
136573: 08/11/22: Re: Generate sample rate ...
136574: 08/11/22: Re: Generate sample rate ...
136580: 08/11/23: Re: Generate sample rate ...
138303: 09/02/14: Capture parallel data ...
138305: 09/02/14: Re: Capture parallel data ...
138307: 09/02/14: Re: Capture parallel data ...
141729: 09/07/05: Re: Spartan-3A Device DNA ...
141731: 09/07/05: Re: Spartan-3A Device DNA ...
142778: 09/09/01: Polynomial Function ...
142780: 09/09/01: Re: Polynomial Function ...
142805: 09/09/02: Re: Polynomial Function ...
142807: 09/09/02: Re: Polynomial Function ...
142810: 09/09/02: Re: Polynomial Function ...
142830: 09/09/03: Re: Polynomial Function ...
142831: 09/09/03: Re: Polynomial Function ...
142837: 09/09/03: Re: Polynomial Function ...
146969: 10/04/06: Extract single bit from std_logic_vector ...
146972: 10/04/06: Re: Extract single bit from std_logic_vector ...
146975: 10/04/07: Case with HEX value ...
146979: 10/04/07: Re: Case with HEX value ...
146985: 10/04/08: Re: Case with HEX value ...
146986: 10/04/08: Summing with carry problems ...
146987: 10/04/08: Re: Summing with carry problems ...
146994: 10/04/08: Re: Summing with carry problems ...
146995: 10/04/08: Re: Summing with carry problems ...
147167: 10/04/16: Clock Mux by software ...
147168: 10/04/16: Re: Read from the compact flash
Kappa (at dot):
125312: 07/10/20: DVB-T/H help me ?
126309: 07/11/19: Parallel to Serial ASI ...
126314: 07/11/19: Re: Parallel to Serial ASI ...
133599: 08/07/05: QPSK SymbolRate generator ...
133603: 08/07/05: Re: QPSK SymbolRate generator ...
133612: 08/07/06: Re: QPSK SymbolRate generator ...
133947: 08/07/20: Change clock domain for FIFO ...
Kappasm:
133644: 08/07/08: Re: QPSK SymbolRate generator ...
133976: 08/07/21: Re: Change clock domain for FIFO ...
133978: 08/07/21: Re: Change clock domain for FIFO ...
133981: 08/07/21: Re: Change clock domain for FIFO ...
133983: 08/07/21: Re: Change clock domain for FIFO ...
133988: 08/07/21: Re: Change clock domain for FIFO ...
134016: 08/07/22: PCR re-stamping this unknown ...
135302: 08/09/25: Re: OFDM band switch ...
135405: 08/10/01: Re: OFDM band switch ...
140722: 09/05/22: Re: No integer interpolation ...
140733: 09/05/23: Re: No integer interpolation ...
141726: 09/07/05: Spartan-3A Device DNA ...
kaps:
101275: 06/04/28: help me friend
101985: 06/05/09: help me to about clock in fpga
Kar:
82043: 05/04/06: Re: CPLD: collapse
82377: 05/04/11: Re: easyfpga is not easy
82466: 05/04/13: Re: State of MAX7000S I/O pins before programming
82542: 05/04/13: Re: State of MAX7000S I/O pins before programming
Kardos, Botond:
4980: 97/01/08: Re: Flex 8K boot-up problem
4981: 97/01/08: Oscillator with PLD's or FPGA's
5114: 97/01/24: Re: Altera Max Plus 2 Software bug
5458: 97/02/17: Re: What kind of functions mostly implemented using FPGAs?
5782: 97/03/14: Re: FPGA Reliability - JTAG reset
5783: 97/03/14: Re: How to count the total numbers of Product Term for Altera MaxPlusII compiler report?
6720: 97/06/19: Re: Help, FPGA Information
6723: 97/06/19: Flex 8000 confuguartion question - DCLK pin
6730: 97/06/20: Re: Flex 8000 confuguartion question - DCLK pin
7034: 97/07/25: Re: How do FPGAs outperform DSP at FFT?
<kardos@mail.matav.hu>:
4716: 96/12/05: Looking for hc0324
4735: 96/12/09: Re: Looking for hc0324
4952: 97/01/03: Flex 8K boot-up problem
Karel:
96600: 06/02/07: Software reset for the MicroBlaze
97716: 06/02/26: Re: C Manual for Microblaze Software
Karel Deprez:
143026: 09/09/15: Xilinx Spartan6: ISERDES2 and BUFIO2 (xc6slx45-2csg324)
143048: 09/09/17: Re: Xilinx Spartan6: ISERDES2 and BUFIO2 (xc6slx45-2csg324)
Kareltje:
92439: 05/11/30: Re: grabbing PCI signals, rev-eng dev board
Karen:
6885: 97/07/06: Re: Smart Card Design and Interface. How?
Karen Halgren:
113755: 06/12/20: New user help required
113762: 06/12/20: Re: New user help required
<karenwlead@my-deja.com>:
21950: 00/04/08: CLKDLL stabilty state
24346: 00/08/04: Re: tutorial on configurable system-on-chip design is available
24347: 00/08/04: Re: FPGA selection
25355: 00/09/07: XC6K still alive ??
28517: 01/01/16: negative borrow
28596: 01/01/17: back-annotation is not possible
29233: 01/02/10: any idea ?
29236: 01/02/10: Re: any idea ?
29238: 01/02/10: Re: any idea ?
29257: 01/02/11: Re: any idea ?
29280: 01/02/12: Re: any idea ?
Kari Laiholuoto:
5808: 97/03/17: Synopsys -> Altera (maxplus2) interface
Kari Runk:
57712: 03/07/04: Re: ARM+FPGA
Kari Vierimaa:
67555: 04/03/14: Re: Altera Quartus II 4.0 won't talk to ByteBasterMV
Karim EMBAREK:
16090: 99/05/02: Re: IrDA controller macro: is it easy to design?
Karim LIMAM:
15334: 99/03/19: Re: Xilinx Vhdl "'event" synthesis problem
16774: 99/06/08: Sensitivity list assumed to be complete
17118: 99/07/01: Altera 10K prices
17208: 99/07/09: Re: Altera 10K prices
28989: 01/02/01: JTAG Programming with SpartanII demo card
29022: 01/02/02: Re: JTAG Programming with SpartanII demo card
Karl:
46392: 02/08/27: Re: Altera Quartus II problems
47507: 02/09/27: Re: Is it possible to build a Ring Oscillator in an FPGA chip?
47508: 02/09/27: Re: Is it possible to build a Ring Oscillator in an FPGA chip?
47624: 02/10/01: Anyone knows of a example FPGA design which reads and writes a SmartMedia card?
47636: 02/10/01: Re: Anyone knows of a example FPGA design which reads and writes a SmartMedia card?
47787: 02/10/04: FPGA with an EPROM on it?
47978: 02/10/09: Parallel bus interface to a SmartMedia card.
48480: 02/10/18: How to read files in a CompactFlash?
49032: 02/10/30: Re: Porting from Xilinx to Altera?
55082: 03/04/25: Altera Flex 8K not holding configuration after power down.
63836: 03/12/05: Re: increase NIOS processor clock speed on APEX20K200E device
71638: 04/07/26: Re: Gate Count vs Logic Element (LE)
73483: 04/09/22: Re: Mr. Greenfield, spare us the propaganda !
74518: 04/10/13: Re: Routing PLL output
81980: 05/04/05: Re: Stupid question
82129: 05/04/07: Re: Stupid question
86121: 05/06/22: Re: 5 Volt tolerance - Altera
87619: 05/07/27: Re: Datasheet error in the Altera Cyclone 2C8F256 pindescription
87629: 05/07/27: Re: Datasheet error in the Altera Cyclone 2C8F256 pindescription
87772: 05/08/01: Re: question about use SRAM on annapolis wildstarII board
87894: 05/08/03: Re: 5V non-volatile reprogrammable FPGA/CPLD
93274: 05/12/18: Re: Altera based Video development board
93879: 06/01/03: Re: optimization tips (badly) needed
94680: 06/01/16: Re: NIOS II fmax on a Cyclone
96596: 06/02/07: Re: realize pci in fpga
97081: 06/02/16: Re: WebPACK license (and Quartus Web Edition too).
99771: 06/03/28: Re: Cyclone II EP2C70 dev kits, where are they?
99773: 06/03/29: Re: Cyclone II EP2C70 dev kits, where are they?
100642: 06/04/14: Re: Cyclone II EP2C70 dev kits, where are they?
101252: 06/04/28: Re: Cyclone II EP2C70 dev kits, where are they?
105258: 06/07/19: Re: Which PCI core for Cyclone II board?
105260: 06/07/19: Re: debouncing a switch (in hardware)
105261: 06/07/19: Re: debouncing a switch (in hardware)
107564: 06/08/30: Re: Do I need to adjust sdram clk shift when i lower my system clock?
108900: 06/09/19: Re: Are you ready for Virtex-5? We are...
109134: 06/09/21: Re: Are you ready for Virtex-5? We are...
109454: 06/09/27: Re: Are you ready for Virtex-5? We are...
113674: 06/12/19: Re: C2H problems
116366: 07/03/07: FPGA Vs ASIC design and implementation
117405: 07/03/30: Re: suggestion for choosing the right FPGA for gigabit transciever
118287: 07/04/23: Re: Stratix II - Cyclone II GATE COUNT
119733: 07/05/25: Re: Went from Xilinx to Altera: Cyclone-II and I/O pullup?
122410: 07/07/27: Re: Altera or Xilinx
124510: 07/09/25: Re: Never buy Altera!!!!
128220: 08/01/18: [paper]?FIR on GPU,CPU, FPGA, ASIC
130953: 08/04/06: system level language: why all this fuss about
132159: 08/05/16: Re: Cyclone 3 on chip termination
132160: 08/05/16: Re: Cyclone 3 on chip termination
136669: 08/11/30: make phone calls from fpga. is it possible?
136678: 08/11/30: Re: make phone calls from fpga. is it possible?
136679: 08/11/30: Re: make phone calls from fpga. is it possible?
137103: 08/12/23: which HLL for HPC applications implementation?
137121: 08/12/23: Re: which HLL for HPC applications implementation?
159440: 16/11/10: Latch/flip flip without the use of process
159443: 16/11/11: Re: Latch/flip flip without the use of process
Karl A. Student:
8063: 97/11/13: Donloading MAX7000 via JTAG, MAX PLUS 2
8064: 97/11/13: das
8065: 97/11/13: Re: Donloading MAX7000 via JTAG, MAX PLUS 2
8234: 97/12/02: JTAG reconfigure
Karl Andersson:
7824: 97/10/19: FPGA Answer to ci12103@mailbox.calypso.net
9100: 98/02/20: $3000 Cash!!!
Karl Beil:
1809: 95/09/05: Questionnaire for my Technical Writing class.
Karl Berry:
144020: 09/11/07: free software/open source projects and FPGA?
Karl de Boois:
48989: 02/10/29: Re: Porting from Xilinx to Altera?
49157: 02/11/03: Re: 16-bit FGPA CPU core (commercial)
51623: 03/01/17: Re: Bug in Quartus2 Web 2.2
55828: 03/05/21: Re: SID chip describtion
85007: 05/06/02: Re: Altera's fast NIOS update service (o;
Karl E. Vinacco:
6308: 97/05/13: VHDL or Verilog?
Karl Kristianson:
6486: 97/05/27: CADKEY '97 -100+ Available- Save $HUNDRED's EACH!!!
6532: 97/05/31: FS: CADKEY '97 -100+ Available- Save $HUNDRED's EACH!!!
6601: 97/06/04: FS: CADKEY '97 -100+ Available- Save $HUNDRED's EACH!!!
6654: 97/06/09: FS: CADKEY '97 (8.0) -100+ Available- Save $HUNDRED's EACH!!!
6683: 97/06/13: FS: CADKEY '97 (8.0)-100+ Available- Save $HUNDRED's EACH!!!
6705: 97/06/17: FS: CADKEY '97 (8.0)-100+ Available- Save $HUNDRED's EACH!!!
6737: 97/06/20: FS: CADKEY '97 (8.0)-100+ Available- Save $700.00 EACH!!!
6767: 97/06/25: FS: CADKEY '97 (8.0)-100+ Available- Save $700.00 EACH!!!
6859: 97/07/02: FS: CADKEY '97 (8.0)-100+ Available- Save $700.00 EACH!!!
Karl Olsen:
20928: 00/02/28: Asynchronous flipflops in Cypress CPLDs with Warp VHDL
20951: 00/02/29: Re: Asynchronous flipflops in Cypress CPLDs with Warp VHDL
21479: 00/03/23: Re: DCF 77
26994: 00/11/07: Spartan2 macros in WebPACK
27046: 00/11/08: Re: Spartan2 macros in WebPACK
28017: 00/12/19: Spartan2 and industrial temperatures
28063: 00/12/20: Re: Spartan2 and industrial temperatures
37221: 01/12/04: Re: XC17S00A programmable as XC17S00 for 2 XC2Ss?
53611: 03/03/17: Re: new XC95xx global clock
54279: 03/04/07: Re: Spartan-3 in docsan Webpack release notes... a joke???
55523: 03/05/11: Re: Information about XC9536 ?
63426: 03/11/21: Re: Xilinx legacy situation
64663: 04/01/10: Re: Dedicated CLK lines in CPLD
64698: 04/01/12: Re: Dedicated CLK lines in CPLD
76170: 04/11/27: Re: dual-write port BRAM with XST/Webpack
karl schrunk:
152389: 11/08/17: Spartan6 PCB debugging: how badly do you have to screw up for JTAG to
152393: 11/08/18: Re: Spartan6 PCB debugging: how badly do you have to screw up for
152402: 11/08/18: Re: Spartan6 PCB debugging: how badly do you have to screw up for
152407: 11/08/19: Re: Spartan6 PCB debugging: how badly do you have to screw up for
152427: 11/08/21: Re: Spartan6 PCB debugging: how badly do you have to screw up for
Karl W. Pfalzer:
3211: 96/04/26: Re: Inferring or design ware (modgen)?
4989: 97/01/08: Linux version for EDA
5009: 97/01/12: Re: Linux version for EDA
5047: 97/01/16: Results: Linux version for EDA
5087: 97/01/22: ANNOUNCE: Timing Correlation Product
"Karl Yung":
13208: 98/11/19: Configuring using Parallel port
Karl-Heinz Wietzke:
1779: 95/08/30: Re: AMD MACH eval package ?
<karl-heinz.rossmann@liebherr.com>:
157774: 15/03/13: Multicycle paths using clock enable (in Synplify Pro)
157781: 15/03/17: Re: Multicycle paths using clock enable (in Synplify Pro)
karl.bengtsson:
150259: 11/01/07: Low slewrate, abnormal current consumption.
150317: 11/01/10: Re: Low slewrate, abnormal current consumption.
150406: 11/01/17: Re: Low slewrate, abnormal current consumption.
<karl.robinsod@gmail.com>:
159600: 17/01/16: Terminating an Aurora link in a PC
159602: 17/01/16: Re: Terminating an Aurora link in a PC
159613: 17/01/17: Re: Terminating an Aurora link in a PC
<KarlJohansen>:
72821: 04/09/03: ADC unit with 2 input channels, 12 bit, 10MHz conversion rate, 4Ksamples FIFO, USB (or PCI on PC104+ form) interface, Linux, QNX driver
<karlski@ibm.net>:
3494: 96/06/10: UART for Actel FPGA
Karol Hennessy:
156388: 14/03/27: Re: looking for a basic PCIe example
<karollo@o2.pl>:
111661: 06/11/07: problems with using altera vhdl testbench in ModelSim
111674: 06/11/07: Re: problems with using altera vhdl testbench in ModelSim
112748: 06/11/28: pre-synthezis simulation in ModelSim for Actel
112767: 06/11/28: Re: pre-synthezis simulation in ModelSim for Actel
Karpel Alex:
27868: 00/12/13: Re: dual port ram for altera
karrelsj:
104376: 06/06/26: PicoBlaze and DDR Ram
104462: 06/06/27: Re: PicoBlaze and DDR Ram
106866: 06/08/21: OpenRISC + DDR
108530: 06/09/12: Opencores mem_ctrl
109111: 06/09/20: Re: Which soft core to use?
110505: 06/10/16: FPGA + GSM cores
110528: 06/10/17: Re: FPGA + GSM cores
113713: 06/12/19: Board for sale
<karrelsj@gmail.com>:
101177: 06/04/26: OpenRisc 1200 on a XUP
Karsten Becker:
56360: 03/06/04: Re: spartan2e vs cyclone
56363: 03/06/04: Re: Spartan-3 questions?
56396: 03/06/04: Re: spartan2e vs cyclone
56418: 03/06/04: Re: cyclone on pci?
56616: 03/06/10: Re: DVI with a Virtex-II
56618: 03/06/10: Re: DVI with a Virtex-II
57052: 03/06/22: Re: "Ethernet only" network
57727: 03/07/05: Re: NIOS tutorial for the Stratix1S10
57728: 03/07/05: Re: NIOS tutorial for the Stratix1S10
kart:
78073: 05/01/24: Urgent help regarding voltage overstressing
Kartheepan, Madasamy:
12295: 98/10/07: Re: FIR Filter Design
12296: 98/10/07: Re: FIR Filter Design
kartheic anantha:
113225: 06/12/08: Query :Regarding Synthesis Report
113230: 06/12/08: Query :Regarding Synthesis Report
karthick:
132156: 08/05/16: difference between 8.2i and 9.2i with respect to Microblaze Core
132224: 08/05/18: Re: difference between 8.2i and 9.2i with respect to Microblaze Core
133300: 08/06/24: Migrating to 9.2i from 8.2i
133308: 08/06/24: Re: Migrating to 9.2i from 8.2i
<karthick.ramu@gmail.com>:
136903: 08/12/11: Re: encrypted and unencrypted design in the same device
karthik:
55495: 03/05/09: global buffer and the dll
70569: 04/06/21: Interface Bidir IO datalines to dualport RAM within FPGA - URGENT
73350: 04/09/20: ISP PROM's : PROM programming fails
Karthik:
57885: 03/07/08: Re: information required
57937: 03/07/09: Re: information required
karthikbalaguru:
144782: 10/01/02: NOR-based Flash Memory - Design
144785: 10/01/02: Re: NOR-based Flash Memory - Design
Karthikeyan Subramaniyam:
89989: 05/10/01: Re: VHDL 2 dimension array
<karthikeyan@my-deja.com>:
20599: 00/02/15: The definitive site for ASIC jobs!
<karthiknatrajan@gmail.com>:
120841: 07/06/18: Help needed regarding addition of Custom IP core to EDK
120851: 07/06/19: Re: Help needed regarding addition of Custom IP core to EDK
KaRtiK:
65469: 04/01/29: Verilog code to Physical layout?
66377: 04/02/18: Design Verification tools and Resources ?
Kartik Krishnan:
57399: 03/06/29: Benchmarking FPGA CPU's
57517: 03/07/01: ARM C/C++ compiler independent of OS
<karunesh.ind@gmail.com>:
108531: 06/09/12: use of Barrel shifter IN ARM TDMI 9
kash:
10574: 98/06/01: beta customers needed
10659: 98/06/09: Re: FPGA Conversion
10665: 98/06/09: BREAKTHROUGH ASIC PRODUCT---Beta customers needed
10823: 98/06/23: REVOLUTIONARY ZERO NRE ASICs-update
11542: 98/08/21: Re: XC4062 mapping problems with Synopsis tools
kash johal:
10687: 98/06/10: Re: BREAKTHROUGH ASIC PRODUCT---Beta customers needed
10728: 98/06/12: Re: Fastest and biggest FPGA fast and big enough?
10917: 98/07/01: ZERO NRE ASICs update
10918: 98/07/01: ZER) NRE ASICS update
10939: 98/07/06: FREE ASIC ESTIMATOR
<kash.jt@gmail.com>:
101537: 06/05/02: Re: ISE 8.1 Comment Bug, Very hideous
kashif:
137081: 08/12/22: Need help with the I/O Standard
kashjohal:
26009: 00/09/30: Altera FPGA experts needed
Kashmir:
109304: 06/09/23: Re: Lattice ispMACH4000 eval boards
111966: 06/11/13: Re: Field Programmable Object Array
<kasmjs@erols.com>:
7851: 97/10/23: FPGA Floating Point Implementation
Kasper Pedersen:
21056: 00/03/04: Re: JTAG Programmer & Windows 2000
21091: 00/03/06: Re: JTAG Programmer & Windows 2000
21092: 00/03/06: Re: JTAG Programmer & Windows 2000
27117: 00/11/11: Re: Alliance under Linux?
44767: 02/06/29: Re: Programming a Xilinx CPDL with a Microcontroller
56702: 03/06/11: Re: Xilinx CPLD programming with microcontroller
56955: 03/06/19: Re: Xilinx Spartan download with Parallel III cable
57338: 03/06/27: Re: Configure an FPGA from the PCs Parallel port. A solution.
58160: 03/07/16: Re: JTAG and Xilinx
58311: 03/07/20: Re: XILINX frequency meter from XCELL design question.
62181: 03/10/21: Re: 74 logic to CPLD. how easy for a Newbie?
62269: 03/10/23: Re: 74 logic to CPLD. how easy for a Newbie?
66982: 04/03/02: Re: Is WebPACK 6.1 generally broken, and what of 6.2?
69242: 04/05/02: Re: Connecting a crystal to a Cyclone or Max PLD
71576: 04/07/22: Re: Converting High Rise Time clock to Low Rise time clock - Chellenge!
84565: 05/05/21: Re: VHDL vs. Schematic Capture
Kastil Jan:
143803: 09/10/27: Tcl in PlanAhead
143959: 09/11/05: Re: problem fpga aera optimization
143989: 09/11/06: Re: Does anyone ever use placement?
145075: 10/01/25: Achronix FPGA
146027: 10/03/04: Ethernet development kit
149822: 10/11/25: Readback of the Virtex5 configuration
149823: 10/11/25: Re: PlanAhead
Kate:
44035: 02/06/10: Re: Information about FPGA
Kate Atkins:
21122: 00/03/07: Re: antifuse fpga's replacing xilinx
21143: 00/03/08: Re: antifuse fpga's replacing xilinx
21635: 00/03/27: Re: FPGA & single point failure
21641: 00/03/27: Re: FPGA & single point failure
21706: 00/03/29: APS V240 board
21829: 00/04/03: Re: APS V240 board
23002: 00/06/08: Re: Deficiencies in Actel 40mx tools?
23623: 00/07/03: Re: division in FPGA - help !
24032: 00/07/24: Re: Virtex DLL problem.
25972: 00/09/28: Xilinx clkdll not driven from IBUFG
44907: 02/07/05: Re: Anyone use the full Aldec 5.1 flow?
51111: 03/01/02: Re: Actel 32300 power-up behavoiur
Kate Kelley:
48977: 02/10/28: Re: Pin locking Virtex 2 FPGA
49504: 02/11/13: Re: Incremental design question
50508: 02/12/11: Re: "new" Xilinx IOB timing paramter "Tiotp"
50552: 02/12/12: Re: *Exactly* How and when does attribute DESKEW_ADJUST affect the DCM
51141: 03/01/03: Re: *Exactly* How and when does attribute DESKEW_ADJUST affect the DCM
51145: 03/01/03: Re: Floor Planning DCM
51149: 03/01/03: Re: Xilinx Makefile for ISE 5.1i
52056: 03/01/29: Re: [help] timing closure problem on two slightly different xilinx
52099: 03/01/31: Re: [help] timing closure problem on two slightly different xilinx
52102: 03/01/31: Re: More than four clocks within a spartan-ii device?
52113: 03/01/31: Re: Floor Planning DCM
52205: 03/02/04: Re: Modules in a large design
52210: 03/02/04: Re: Partitioning interconnect in Xilinx FPGAs
52224: 03/02/04: Re: Partitioning interconnect in Xilinx FPGAs
148414: 10/07/20: Re: Xilinx' partition flow in ISE12.1
148520: 10/07/29: Re: Getting started with partial reconfiguration
Kate Meilicke:
3566: 96/06/25: Re: Routing
3580: 96/07/01: Re: sanity check for 100k gate DSP FPGA project (long)
3581: 96/07/01: Re: Need recommendation for PCI interface on 68332
4698: 96/12/02: Re: How to utilize XC4000e IOB FFs in Synopsys?
6194: 97/04/24: Re: Instatiation of Xilinx Primitives in VHDL?
6195: 97/04/24: Re: System Level Integration on Deep submicron FPGAs
6296: 97/05/09: Re: X-BLOX
6280: 97/05/08: Re: Xilinx .UCF file examples
6295: 97/05/09: Re: Xilinx .UCF file examples
6316: 97/05/14: Re: Instatiating large RAM arrays in VHDL
6374: 97/05/19: Re: X-BLOX
6399: 97/05/21: Re: X-BLOX
6479: 97/05/27: Re: What is M1?
6549: 97/06/02: Re: What is M1?
20448: 00/02/10: Re: Timing constraint on a DLL output
20615: 00/02/16: Re: Timing constraint on a DLL output
25434: 00/09/11: Re: More than 4 clocks in virtex
26806: 00/10/30: Re: xilinx floor planner issues
37025: 01/11/28: Re: How to set timing constraint in Xilinx VirtexII device when using
Kate Palmer:
55909: 03/05/23: Re: FPGA design: firmware or hardware?
56407: 03/06/04: Re: An FPGA is flying to Mars
Kate Smith:
66639: 04/02/24: Verilog Newbie Question
66651: 04/02/24: Re: Verilog Newbie Question
66666: 04/02/24: Re: Verilog Newbie Question
Kate Thompson:
34697: 01/09/04: Re: Testing ... please ignore
35031: 01/09/18: Re: Help!
katem:
11313: 98/08/04: Re: Just wondrin bout Xilinx stuff.......
15259: 99/03/16: Re: Pin constraints of Xilinx - BIG WEAKNESS
18577: 99/11/01: Re: Comparison between Altera and Xilinx
katherine:
86062: 05/06/21: TDM over Aurora
86591: 05/06/30: aurora framing
86830: 05/07/07: aurora reliability
86850: 05/07/07: Re: aurora reliability
86896: 05/07/08: Re: aurora reliability
86987: 05/07/12: Re: Connecting TigerSharc TS201 EzKIT to PCI with Spartan 3
127561: 08/01/02: spartan 3e JTAG programming
Katherine Compton:
44613: 02/06/24: FPGA 2003 Conference
51675: 03/01/18: FPGA 2003 Program and Registration
kathy:
73250: 04/09/16: beginner's question
73366: 04/09/20: question about Webpack - PACE
73398: 04/09/21: Re: question about Webpack - PACE
Kathy & Brian:
33604: 01/07/31: Xilinx Spartan XL length count question.
Kati:
144853: 10/01/07: Re: Difference among Virtex Families, FPGA Books
<kati.s.wright@gmail.com>:
140079: 09/04/27: Re: way to go Altera!
<katjasulimma@googlemail.com>:
118037: 07/04/16: Re: Why 166Mhz DDR?
kattice:
72430: 04/08/18: Re: SDRAM Controller on a cyclone dev kit
Kaustabh Duorah:
134: 94/08/26: Technology Mapping Bibliography..
Kavadias Stamatis:
18634: 99/11/04: PCI Pamette Error
KAveh Ahangar:
kavi:
81417: 05/03/23: re:WLAN in VHDL
Kavitha:
70745: 04/06/25: Post-Map Simulation
KAWAMATA:
8522: 98/01/04: ALTERA Global Signal
Kay Schubert:
63044: 03/11/13: unknown devices in JTAG chain
64146: 03/12/18: Re: www.fpga-faq.com
<--Kay-->:
63158: 03/11/17: Re: unknown devices in JTAG chain
<kayrock66@yahoo.com>:
105335: 06/07/20: Re: clock hold time problems reported in quartus II
106922: 06/08/22: Re: Using multi-cycle contraint and simulate it correctly
107117: 06/08/24: Re: high level languages for synthesis
107119: 06/08/24: Re: Why No Process Shrink On Prior FPGA Devices ?
113791: 06/12/21: Re: PLL minimum input clock frequency
113792: 06/12/21: Re: Soft processor Microblaze vs embedded core PowerPC
114213: 07/01/07: Re: Use Multi-cycle Path or Pipeline?
114215: 07/01/07: Re: how do we connect internals signals(not ports) of submodules in the top level design to trigger ports of the ila core?
114217: 07/01/07: Re: Is there a simple complex magnitude algorithm in FPGA implementation?
114218: 07/01/07: Re: Problem with unused pin on Spartan 2E
114219: 07/01/07: Re: data transfer from fast APB clock domain.
114539: 07/01/18: Re: Ethernet Interface
115682: 07/02/16: Re: Need fair opinions on choosing either Altera or Xilinx as main FPGA source
123753: 07/09/03: Re: PCB Impedance Control
<kayrock@geocities.com>:
22213: 00/05/02: Re: FPGA price vs Size
22953: 00/06/05: Re: Microprocessors in FPGA
23058: 00/06/12: Re: Problem with state machine
23081: 00/06/13: Re: Altera vs Xilinx
23082: 00/06/13: Re: Please,give me solution for "serious pad to pad delay" in Xilinx.
23117: 00/06/14: Re: Altera Output Timing Question
23119: 00/06/14: Re: difference between fpga and epld
23145: 00/06/15: Re: Verilog Questions??
<kayrock@my-deja.com>:
18675: 99/11/07: Re: Comparison between Altera and Xilinx
18674: 99/11/07: Re: Input metastability
18676: 99/11/07: Re: Price of FPGA
kays_f:
127750: 08/01/07: Re: What does this do ?
kayvon irani:
1395: 95/06/14: Any one working on Cypress PLD's ?
1412: 95/06/19: Who was the winner on latest PREP benchmarks?
1504: 95/07/04: Help with Viewlogic II
1726: 95/08/21: Any one using synthesizable HDL megacells ?
1750: 95/08/25: Quicklogic/Cypress/Warp3
1791: 95/09/03: Need verilog model
1956: 95/09/25: FPGA for a 20k gates micro-controller
1957: 95/09/25: FFT in FPGAs ?
2106: 95/10/16: Re: Needed: Suggestions for FPGA design CAD
2122: 95/10/18: Re: Library of Parametrized Modules info
2225: 95/11/06: Re: FPGA => ASIC
Kayvon Irani:
3059: 96/03/23: Re: MTI VHDL simulation w/ Xilinx
3531: 96/06/15: Re: troubles on the way from exemplar to Altera's MAX+PLUSII
3820: 96/08/06: Quick question for Model Tech. experts:
4126: 96/09/15: Re: Implement FPGA multiplier using VHDL synthesis
4721: 96/12/05: ASICs Vs. FPGA in Safety Critical Apps.
4874: 96/12/22: Re: Anyone tried a FFT in a FPGA?
4875: 96/12/22: Re: ASICs Vs. FPGA in Safety Critical Apps.
5393: 97/02/13: Re: Gate level Simulation with Mentors Quicksim from Galileo
5424: 97/02/15: Re: Gate level Simulation with Mentors Quicksim from Galileo
5446: 97/02/17: Cypress says good-bye to Anti-Fuse
5604: 97/02/27: Question on Vital Simulation with a Wrapper file(Galileo)
5958: 97/03/30: System Level Integration on Deep submicron FPGAs
6016: 97/04/05: Re: Vendors (Xilinx, Cypress) leaving antifuse market
6177: 97/04/22: Re: ISP CPLD from AMD or Cypress???
6180: 97/04/22: Re: FPGA gate counting: No truth in advertising
6487: 97/05/27: Re: Xmit data thru X-Checker of Xilinx 4000 series to program a Flash with it
7001: 97/07/21: Re: Production testing of Design with CPLD's
7032: 97/07/24: Re: How do FPGAs outperform DSP at FFT?
7185: 97/08/11: Any one getting 125MHz out of XILINX CPLDs?
7193: 97/08/12: Re: Any one getting 125MHz out of XILINX CPLDs?
8500: 97/12/25: Re: how to instantiate an LCELL in VHDL source file
8769: 98/01/24: High Voltage on xilinx FPGA/CPLD pins
8770: 98/01/24: Re: Military FPGAs
8884: 98/02/05: Xilinx and Altera CPLDs in JTAG chain
9001: 98/02/12: Why altera CPLDS are slow to power-up?
9041: 98/02/16: Re: Why altera CPLDS are slow to power-up?
9219: 98/03/02: Die Size Comparison of competing FPGAs
kaz:
154109: 12/08/09: xilinx fir compiler
154113: 12/08/10: Re: xilinx fir compiler
154204: 12/09/07: Re: xilinx fir compiler
154222: 12/09/11: Re: xilinx fir compiler
154386: 12/10/19: Re: tell QuartusII to use registers and not RAM
154387: 12/10/19: Re: tell QuartusII to use registers and not RAM
154532: 12/11/24: Re: Set-up and hold times and metastability
154534: 12/11/25: Re: Set-up and hold times and metastability
154540: 12/11/25: Re: VHDL expert puzzle
154545: 12/11/25: Re: VHDL expert puzzle
154546: 12/11/25: Re: VHDL expert puzzle
154558: 12/11/28: Re: VHDL expert puzzle
154605: 12/11/30: Re: VHDL expert puzzle
154606: 12/11/30: Re: VHDL expert puzzle
154614: 12/12/01: Re: VHDL expert puzzle
154639: 12/12/08: Is this Multicycle?
154640: 12/12/08: Re: Is this Multicycle?
154642: 12/12/08: Re: Is this Multicycle?
154670: 12/12/15: DC fifo behaviour at underflow/overflow
154672: 12/12/15: Re: DC fifo behaviour at underflow/overflow
154674: 12/12/15: Re: DC fifo behaviour at underflow/overflow
154675: 12/12/15: Re: DC fifo behaviour at underflow/overflow
154678: 12/12/16: Re: DC fifo behaviour at underflow/overflow
154680: 12/12/16: Re: DC fifo behaviour at underflow/overflow
154682: 12/12/16: Re: DC fifo behaviour at underflow/overflow
154685: 12/12/16: Re: DC fifo behaviour at underflow/overflow
154690: 12/12/17: Re: DC fifo behaviour at underflow/overflow
154805: 13/01/14: is this multicycle?
154807: 13/01/14: Re: is this multicycle?
154809: 13/01/14: Re: is this multicycle?
154814: 13/01/15: Re: is this multicycle?
157627: 15/01/08: Re: Timing Constraints: are there any
157646: 15/01/15: Re: Altera Cyclone II
157680: 15/01/27: Why two hold checks done byTimeQuest
157775: 15/03/13: Re: Multicycle paths using clock enable (in Synplify Pro)
157779: 15/03/15: Re: New invention: Systematic method of coding wave pipelined circuits in HDL
157834: 15/04/10: Re: Division by a constant
157953: 15/05/21: Re: Oqpsk Demod
158019: 15/07/10: Distributed ram timing qurry
158025: 15/07/10: Re: Distributed ram timing qurry
158028: 15/07/10: Re: Distributed ram timing qurry
158056: 15/07/30: fifo or sdram bug?
158058: 15/07/30: Re: fifo or sdram bug?
158059: 15/07/30: Re: fifo or sdram bug?
158062: 15/07/30: Re: fifo or sdram bug?
158067: 15/07/30: Re: fifo or sdram bug?
158070: 15/07/30: Re: fifo or sdram bug?
158071: 15/07/30: Re: fifo or sdram bug?
158125: 15/08/13: Re: fifo or sdram bug?
158130: 15/08/13: Re: fifo or sdram bug?
158132: 15/08/13: Re: fifo or sdram bug?
158138: 15/08/14: Re: fifo or sdram bug?
158139: 15/08/14: Re: fifo or sdram bug?
158159: 15/09/07: Re: Why is this group so quiet?
158162: 15/09/08: Re: Why is this group so quiet?
158168: 15/09/09: Re: Why is this group so quiet?
158171: 15/09/09: Re: How to understand obfuscated IP codes?
158213: 15/09/15: Re: fifo or sdram bug?
158223: 15/09/25: Re: Question about partial multiplication result in transposed FIR filter
158249: 15/09/29: Re: Automatic latency balancing in VHDL-implemented complex pipelined systems
158260: 15/09/30: Re: Automatic latency balancing in VHDL-implemented complex pipelined systems
158262: 15/09/30: Re: Automatic latency balancing in VHDL-implemented complex pipelined systems
158265: 15/09/30: Re: Automatic latency balancing in VHDL-implemented complex pipelined systems
158331: 15/10/22: Re: DC Blocker
158334: 15/10/22: Re: DC Blocker
158345: 15/10/22: Re: DC Blocker
158371: 15/10/24: Re: recovery/removal timing
158372: 15/10/24: Re: DC Blocker
158382: 15/10/25: Re: recovery/removal timing
Kazu:
147842: 10/05/26: Help (Virtex 155 and 220 compatibility) !
KB:
53448: 03/03/13: Altera Sourcing
54161: 03/04/03: Altera Cyclone
54614: 03/04/15: Re: Xilinx has released SpartanIII
54713: 03/04/16: Re: Xilinx has released SpartanIII
54722: 03/04/16: Re: Xilinx has released SpartanIII
59572: 03/08/22: Re: 22V10, ABEL & Current Design Tools?
KBG:
110045: 06/10/10: SDRAM initialisation and MCF5272
KCL:
78694: 05/02/06: error in xst
78695: 05/02/06: Re: error in xst
78764: 05/02/07: Re: Using the 7 segment displays on Xilinx Spartan 3 kit
78939: 05/02/10: Re: Graphic LCD + Keypad + printer
79040: 05/02/11: Re: ROM inference in Spartan3
79093: 05/02/14: Re: Using the 7 segment displays on Xilinx Spartan 3 kit
79094: 05/02/14: Re: Using the 7 segment displays on Xilinx Spartan 3 kit
79261: 05/02/16: Re: Xilinx Spartan 3 kit - VHDL design question
79268: 05/02/16: Re: Xilinx Spartan 3 kit - VHDL design question
79326: 05/02/17: Re: Simple counter
79456: 05/02/19: Re: Shift register example?
79458: 05/02/19: having EDK and microblaze
79508: 05/02/20: Re: Shift register example?
79509: 05/02/20: Re: Xilinx Spartan 3 kit - VHDL design question
79511: 05/02/20: Re: Shift register example?
79514: 05/02/20: Re: Graphic LCD
79532: 05/02/20: Re: Graphic LCD
79608: 05/02/21: Re: Shift register example?
79610: 05/02/21: Re: Shift register example?
79625: 05/02/22: Re: BACK to FPGA
79648: 05/02/22: Frequence max: many question from a beginner
79731: 05/02/23: generic
79733: 05/02/23: Re: Graphic LCD
79736: 05/02/23: Re: Frequence max: many question from a beginner
79741: 05/02/23: Re: The real performance leader: V4
79786: 05/02/24: Re: Multiple addition(2)
79787: 05/02/24: Re: Multiple additions
79831: 05/02/24: Re: Multiple addition(2)
79832: 05/02/24: publishing IP
79856: 05/02/25: Engineer in Eastern Europe
79866: 05/02/25: VIE in electronic and FPGA design
79898: 05/02/25: Error in ISE 6.3
79899: 05/02/25: Re: VIE in electronic and FPGA design
80112: 05/03/01: Part of a ranged signal
80216: 05/03/02: Re: spartan3 development board in Europe?
80217: 05/03/02: Re: Part of a ranged signal
80243: 05/03/02: Re: spartan3 development board in Europe?
80244: 05/03/02: Re: Need suggestion abt FFs without RST for pipelined datapath.
81034: 05/03/16: Re: Using DSP Builder with Quartus
81035: 05/03/16: Re: type states is std_logic_vector(4 downto 0);
81036: 05/03/16: Re: Xilinx webpack map/route questions
81084: 05/03/17: Re: Tornado Board and Education Kit is available.
81093: 05/03/17: Re: Newbie: Slow FPGAs
81320: 05/03/21: Re: Block RAM Initialization - RAMB16_S2
81548: 05/03/27: Mixing synchronous and asynchronous reset
81550: 05/03/27: Re: Mixing synchronous and asynchronous reset
81551: 05/03/27: reset on startup
81633: 05/03/29: looking for keyboard scancode
81635: 05/03/29: Re: looking for keyboard scancode
81669: 05/03/29: Re: looking for keyboard scancode
81806: 05/04/01: Re: Instantiate RAM in Spartan3
81873: 05/04/03: Xbox , chip mod & CPLD
81875: 05/04/03: Re: Xbox , chip mod & CPLD
83253: 05/04/26: Re: dynamic size of ports
kcl:
78042: 05/01/23: Re: ModelSim & Constant
78129: 05/01/25: Looking for french firm designing FPGA
78131: 05/01/25: Re: bi-dimensional array
78139: 05/01/25: Re: bi-dimensional array
78232: 05/01/26: Re: Xinx, FPGA Simulink Freeware/shareware ?
78448: 05/02/01: Re: Evaluating EDIF netlist
78450: 05/02/01: Oscillator for Digilent Spartan 3 Starter Kit
78456: 05/02/01: gate/xilinx slice
78464: 05/02/01: Re: gate/xilinx slice
78547: 05/02/03: problem with Modelsim 5.8 Xilinx Edition
78556: 05/02/03: Re: problem with Modelsim 5.8 Xilinx Edition
90358: 05/10/11: converting 12v signal to 3.3v
90363: 05/10/11: Re: converting 12v signal to 3.3v
90436: 05/10/13: Re: Simulink to hdl conversion
95568: 06/01/24: problem to synthetize with ISE
95774: 06/01/26: Re: problem to synthetize with ISE
97252: 06/02/20: Re: FPGA - software or hardware?
97735: 06/02/27: Re: miniuart
98369: 06/03/09: Re: Questions about counter in VHDL
98434: 06/03/10: Learning new stuff about FPGA
kclo4:
132057: 08/05/12: Re: How to input an analog signal to FPGA board for processing?
132115: 08/05/14: demo board under 500usd
133667: 08/07/09: Re: Altera FPGA and data from matlab workspace.
133668: 08/07/09: Re: SBC with ADC, 1GE, and SATA2?
133766: 08/07/14: Re: VHDL code for DDFS
142384: 09/08/08: Quartus fitter put a user pin on an already assigned pin
142385: 09/08/08: Quartus fitter trouble in auto assignement
142412: 09/08/10: Re: Spartan-6 Boards - Your Wish List
142816: 09/09/02: Re: usb3.0 PHY wrapper for Xilinx V5/V6 device
143280: 09/09/29: Re: Connect two Spartan 3E
143821: 09/10/27: Re: HI.. Help Needed Its Urgent
151179: 11/03/14: Re: pcb&bitstream
151931: 11/06/08: multiplication in indexation
151942: 11/06/11: Re: multiplication in indexation
152439: 11/08/23: [actel] resource usage by entity
kctang:
24231: 00/07/31: _ newbie want to know FPGA
29812: 01/03/12: __Cut and Paste C codes, you can have your hardware!
KD:
62867: 03/11/11: Re: ISE 5.2 to 6.1
<kd_ei@yahoo.com>:
87923: 05/08/03: Re: System Engineering in the R/D World
kdfake@spam.com:
91187: 05/11/01: Xilinx ML403 Error 1 LED
91227: 05/11/01: Re: Xilinx ML403 Error 1 LED
91304: 05/11/03: LWIP on microblaze socket limit to 2
94383: 06/01/11: Will ISE 8.1 work together with EDK 7.1?
94461: 06/01/12: Re: Will ISE 8.1 work together with EDK 7.1?
94624: 06/01/15: Re: Student Pricing Now on our Website
96021: 06/01/28: Re: XilNet server data streaming problem from PPC
96879: 06/02/12: Re: using FPGA in control field
110915: 06/10/25: Re: tcp/ip
<kdriesbe@getresponse.com>:
keat3:
28151: 00/12/23: MAKE LOTS OF MONEY!! NOT A SCAM!! IT REALLY WORKS!!
<kebm@flash.net>:
14448: 99/01/30: Re: Hold Time Violation
14449: 99/01/30: Re: Worst service in India by Xilinx
Kedar P. Apte:
74833: 04/10/20: Active Rece\onfiguration of Xilinx FPGAs
74895: 04/10/20: Partial reconfiguration of Xilinx
74897: 04/10/21: Re: Active Rece\onfiguration of Xilinx FPGAs
78284: 05/01/27: PCI X MSI Capability (XILINX Core)
78800: 05/02/08: BFM Basics
78926: 05/02/10: Basics of BFM
82185: 05/04/08: FPGA Configuration Simulation
<kedarpapte@gmail.com>:
83940: 05/05/10: PCI PCIX LoGi Core Problem
90182: 05/10/06: Altera Gate Delay Simulation
90300: 05/10/09: Re: Altera Gate Delay Simulation
92269: 05/11/25: Black Box Attribute in Quartus II
92529: 05/11/30: Ethenet Multiplexers
92530: 05/11/30: Ethenet Multiplexers
92532: 05/11/30: Re: Xilinx LUT behavior question
92595: 05/12/01: Re: Ethenet Multiplexers
92608: 05/12/02: Re: Ethenet Multiplexers
92610: 05/12/02: Re: Ethenet Multiplexers
92679: 05/12/04: Re: Black Box Attribute in Quartus II
93847: 06/01/02: Ethernet Multiplexers
94139: 06/01/06: Ethernet Encoding scheme
94152: 06/01/06: Re: Ethernet Encoding scheme
94244: 06/01/08: Re: Ethernet Encoding scheme
94338: 06/01/10: Breaking of Ethernet Frames
98137: 06/03/06: Simulation of Xilinx Rocket IO
98197: 06/03/06: Re: Simulation of Xilinx Rocket IO
98564: 06/03/12: Re: Simulation of Xilinx Rocket IO
Kee Chan:
837: 95/03/09: Smith's web page (Was: Limits on on-chip FPGA virtual .....)
3203: 96/04/24: Re: On FPGAs as PC coprocessors
Kees Bakker:
94739: 06/01/17: Re: best evm for virtex-4 and linux
105078: 06/07/13: Re: Programming the Spartan-3E Starter Kit using Linux?
124954: 07/10/12: Re: Quartus II 7.2 web edition - Linux or not?
124996: 07/10/15: Re: Quartus II 7.2 web edition - Linux or not?
Kees van Reeuwijk:
36999: 01/11/28: Is there a full open-source synthesis path for any FPGA?
37115: 01/11/30: Re: Is there a full open-source synthesis path for any FPGA?
37116: 01/11/30: Re: Is there a full open-source synthesis path for any FPGA?
37117: 01/11/30: Re: Is there a full open-source synthesis path for any FPGA?
37225: 01/12/04: Re: Is there a full open-source synthesis path for any FPGA?
76673: 04/12/08: Re: Open source FPGA EDA Tools
87441: 05/07/24: Re: July 20th Altera Net Seminar: Stratix II Logic Density
95908: 06/01/27: Re: So Xilinx, is XDL and related libraries an available open source interface?
102565: 06/05/17: Re: "disappointing" performance
kefir:
79382: 05/02/18: CRC-4 algorithm using in G.704(&G.706)
KeilSoftW:
2348: 95/11/21: Re: Device Programmer Selection
keiser anthony lynn:
9496: 98/03/18: Linux and Xchecker
11064: 98/07/16: Bitfile for Xilinx PCI ping
Keith:
37348: 01/12/07: Re: For Sale: Huge Xilinx FPGA lots
50523: 02/12/11: Re: question about fft vs. cross corelation in fpga
53137: 03/03/04: Re: conditional `include
74842: 04/10/20: bufgmux
74856: 04/10/20: Re: bufgmux
82549: 05/04/13: Re: Regarding driving of SCL and SDA pins of I2C
82551: 05/04/13: Re: Regarding driving of SCL and SDA pins of I2C
93828: 06/01/01: Re: What is the difference betwee 'Method' and 'Apparatus' in a patent claim area
99962: 06/03/31: Re: deglitching a clock
103023: 06/05/24: Re: PCI 64/66 fpga eval boards
103089: 06/05/25: Re: PCI 64/66 fpga eval boards
103774: 06/06/10: Re: stable, tested 6502 core
104768: 06/07/05: Re: Spartan3e starter kit vga mod
123868: 07/09/06: JTAG CPLD Configuration
Keith Blei:
2759: 96/02/02: Converting Altera .FIT file to Orcad SDT Symbol File
6014: 97/04/05: Pentium Pro Worth it for Altera Max Plus?
6029: 97/04/06: Re: Pentium Pro Worth it for Altera Max Plus?
6048: 97/04/08: Re: Pentium Pro Worth it for Altera Max Plus?
6149: 97/04/18: Re: Pentium Pro Worth it for Altera Max Plus?
Keith Brafford:
40633: 02/03/12: Re: Mystery two wire interface, or am I being dense?
40687: 02/03/13: Re: Mystery two wire interface, or am I being dense?
Keith Christensen:
10736: 98/06/14: Re: Free Computer --BULLSHIT! ADMAX/ComputerMania/PCmania MLM/Spam/ SCAM !!!
Keith D. Brown:
1578: 95/07/20: Lattice isp programming adapters
5694: 97/03/07: Re: DEVICE SELECTION
Keith E. Henry:
4506: 96/11/06: References - FPGA to ASIC Conversion Vendors
Keith Jasinski, Jr.:
17582: 99/08/11: Re: Clock multiplexing
17779: 99/09/02: Re: QuickLogic FPGAs
17858: 99/09/14: Lowest power FPGA
17860: 99/09/14: Re: Opinions Wanted
18952: 99/11/22: Re: How to use multiple resets?
19106: 99/11/29: Re: VHDL vs. schematic entry
19458: 99/12/22: Re: Speed grade
19459: 99/12/22: Re: Speed grade
20139: 00/01/28: Re: licenses
20233: 00/02/01: Re: Tools and how little guy is treated (was Xilinx Tools)
20243: 00/02/02: Re: Tools and how little guy is treated (was Xilinx Tools)
20301: 00/02/04: Re: Xilinx Tools
20672: 00/02/17: Re: multiplier
20673: 00/02/17: Re: Spartan-II Pricing - What gives?
20873: 00/02/24: Re: Design security
20889: 00/02/25: Re: Design security
21124: 00/03/07: Re: antifuse fpga's replacing xilinx
30542: 01/04/13: Re: Is there any free processor core for vertex series?
Keith Larson:
56149: 03/05/29: Re: JTAG madness
Keith Lockstone:
6410: 97/05/22: Inversion in a FPGA
Keith M:
138713: 09/03/05: DDR access on Spartan 3E 500 Starter Kit
138716: 09/03/05: Re: DDR access on Spartan 3E 500 Starter Kit
Keith O'Conor:
94996: 06/01/20: Sorting large amounts of floats
Keith Outwater:
6707: 97/06/17: Re: DES cracker project
Keith R. Bolson:
64651: 04/01/10: ISE6.1 rom16X1 initialization INIT
72517: 04/08/23: XC2V250 protoboard
Keith R. Williams:
19519: 99/12/29: Re: Dumb question springing from a discussion about chess on a chip...
19542: 99/12/30: Re: status during ISP
19575: 00/01/01: Re: Design security
19844: 00/01/14: Re: Design security
20002: 00/01/22: Re: Virtex Fine Pitch BGA pcb layout
20007: 00/01/23: Re: Virtex Fine Pitch BGA pcb layout
20012: 00/01/23: Re: Virtex Fine Pitch BGA pcb layout
20036: 00/01/25: Re: Virtex Fine Pitch BGA pcb layout
20041: 00/01/25: Re: Virtex Fine Pitch BGA pcb layout
20162: 00/01/29: Re: LVPECL I/O interface
20534: 00/02/14: Re: Problem in Wildforce synthesis.
20912: 00/02/27: Re: Design security
21010: 00/03/03: Re: restrictions due to signal types of Global Clock inputs for Virtex
21011: 00/03/03: SpartanXL route and place
21095: 00/03/07: Re: Design security
21096: 00/03/07: Re: SpartanXL route and place
21097: 00/03/07: Re: SpartanXL route and place
21098: 00/03/07: Re: SpartanXL route and place
21099: 00/03/07: Re: SpartanXL route and place
21100: 00/03/07: Re: SpartanXL route and place
21102: 00/03/07: Re: SpartanXL route and place
21135: 00/03/08: Re: Design security
21136: 00/03/08: Re: SpartanXL route and place
21137: 00/03/08: Re: SpartanXL route and place
21165: 00/03/09: Re: SpartanXL route and place
21166: 00/03/09: Re: SpartanXL route and place
21227: 00/03/11: Re: SpartanXL route and place
21301: 00/03/16: SpartanXL Express mode configuration
21359: 00/03/20: Re: SpartanXL Express mode configuration
21380: 00/03/21: Re: Beginner's Guide
21685: 00/03/29: Re: FPGA openness
21686: 00/03/29: Re: FPGA & single point failure
21687: 00/03/29: Re: FPGA & single point failure
21724: 00/03/30: Re: FPGA openness
21725: 00/03/30: Re: FPGA openness
21726: 00/03/30: Re: FPGA & single point failure
21818: 00/04/02: Re: FPGA openness
21844: 00/04/04: Re: FPGA openness
21894: 00/04/06: Re: PCI Bridge to Xilinx XCV*E
21921: 00/04/07: Re: PCI Bridge to Xilinx XCV*E
22055: 00/04/17: Re: FPGA/PLD design tools?
22526: 00/05/11: Re: EETools Topmax
23658: 00/07/04: Re: why???
23951: 00/07/18: Re: Xilinx Foundation 2.1 Run Times
24225: 00/07/30: Re: OT: was Re: Which one is good coding style?
24245: 00/08/01: Re: OT: was Re: Which one is good coding style?
24246: 00/08/01: Re: OT: was Re: Which one is good coding style?
24548: 00/08/13: Re: tbuf
25445: 00/09/12: Re: How many 4005s (4010s) does it take to make a general purpose CPU?
25446: 00/09/12: Re: virtex shape
25901: 00/09/25: Re: Dual monitor display possible with modelsim on a PC?
26011: 00/09/30: Re: Synthesiser comparisons (was: FPGA Express strikes again)
26025: 00/10/01: Re: FPGA Express strikes again! Xilinx response
26050: 00/10/02: Re: FPGA Express strikes again! Xilinx response
26070: 00/10/03: Re: FPGA Express strikes again! Xilinx response
26075: 00/10/03: Re: FPGA Express strikes again! Xilinx response
26071: 00/10/03: Re: multi-input adders in virtex ?
26096: 00/10/04: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
26212: 00/10/09: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
26213: 00/10/09: Re: multi-input adders in virtex ?
26249: 00/10/10: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
26251: 00/10/10: Re: multi-input adders in virtex ?
26321: 00/10/12: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
26322: 00/10/12: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
26323: 00/10/12: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
26356: 00/10/13: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
26357: 00/10/13: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
26358: 00/10/13: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
26387: 00/10/13: Re: 5V compatible Virtex
26701: 00/10/25: Re: How safe is the algorithm implemented with FPGA?
26250: 00/10/10: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
27241: 00/11/16: Re: VHDL & Spartan: How to power-up a Register to '1' ?
27547: 00/11/28: Re: Newsgroup : Accessing through Netscape Navigator
27551: 00/11/28: Re: hard or soft core for FPGA?
27658: 00/12/01: Re: DLLs driving DLLs in Virtex.
28643: 01/01/19: Re: CMOS or TTL
29197: 01/02/09: Re: Synplify on Windows2000?
29265: 01/02/11: Re: Wired-or on Virtex FPGAs
29353: 01/02/15: Re: Wired-or on Virtex FPGAs
29366: 01/02/16: Re: Rijndael
29695: 01/03/05: Re: Bad Xilinx bitstream=big bang?
29763: 01/03/08: Re: SRAM fpga cell
29995: 01/03/20: Re: Spartan-II VREF and VCCO
30301: 01/04/02: Re: XCV1000BG560: onchip ram
30567: 01/04/17: Re: XCV1000BG560: onchip ram
30694: 01/04/24: Re: CarryLogic
30958: 01/05/04: Xilinx Constraints Editor ?
31021: 01/05/09: Re: Xilinx Constraints Editor ?
31261: 01/05/16: Re: PCI The Real Hardware
31380: 01/05/21: Re: <no subject>
31758: 01/06/05: Re: one state machine
31770: 01/06/05: Re: one state machine
31773: 01/06/05: Re: one state machine
31867: 01/06/07: Re: ASIC vs FPGA designer
32054: 01/06/12: Re: Gray Code Guard bits (was Re: Help in FIFO design)
32282: 01/06/21: Re: NT vs W2K (WAS Re: Pin locking in Maxplus2)
32283: 01/06/21: Re: what tools run OK on windows 2000?
32331: 01/06/22: Re: what tools run OK on windows 2000?
32338: 01/06/23: Re: what tools run OK on windows 2000?
32339: 01/06/23: Re: what tools run OK on windows 2000?
32343: 01/06/23: Re: what tools run OK on windows 2000?
32459: 01/06/27: Re: IOB FF in Synplicity
32547: 01/06/29: Re: IOB FF in Synplicity
32548: 01/06/29: Re: IOB FF in Synplicity
32587: 01/07/01: Re: IOB FF in Synplicity
32669: 01/07/04: Re: 8031 microcontroller on FPGA development board :-(
32702: 01/07/05: Re: 8031 microcontroller on FPGA development board :-(
32789: 01/07/09: Re: Vitrtex selectram
32838: 01/07/10: Re: Online threshold limit counter
32863: 01/07/10: Re: Online threshold limit counter
33028: 01/07/15: Re: Design entry
33045: 01/07/16: Re: Design entry
33051: 01/07/16: Re: Design entry
33150: 01/07/18: Re: Working Design - Anyone
33920: 01/08/08: Re: Slightly off topic - PCs for running FPGA tools
34061: 01/08/13: Re: Slightly off topic - PCs for running FPGA tools
34145: 01/08/15: Re: I need help disassembling a JEDEC .jed file from a PLHS18P8A
34329: 01/08/21: Re: Slowing PCI for FPGA
36363: 01/11/07: Re: FPGA BGA and decoupling
36410: 01/11/08: Re: FPGA BGA and decoupling
36644: 01/11/13: Re: SDRAM Module vs. SDRAM
36684: 01/11/15: Re: Decoupling capacitors on Virtex II
36955: 01/11/27: Re: Virtex Orcad Library
37778: 01/12/20: Re: Hardware FPGA questions
37798: 01/12/20: Re: Hardware FPGA questions
38180: 02/01/08: Re: multiply (*) 11000000000
38181: 02/01/08: Re: Xilinx XC2000, XC3000, XC4000 families
38223: 02/01/09: Re: Xilinx XC2000, XC3000, XC4000 families
38966: 02/01/28: Re: Xilinx webpack
39303: 02/02/05: Re: FPGA vs GAL : Lattice
39826: 02/02/20: Re: Need good PCI book
39951: 02/02/22: Re: Replacing expensive configuration SPROM
41496: 02/03/30: Re: powerpc in virtex2pro
41508: 02/03/31: Re: Orcad Sch f/Xilinx Spartan II
41528: 02/04/01: Re: Data Compression in FPGAs
41554: 02/04/01: Re: powerpc in virtex2pro
41555: 02/04/01: Re: Data Compression in FPGAs
41656: 02/04/04: Re: Monostable multivibrator
42468: 02/04/24: Re: Newbie with signals
42540: 02/04/26: Re: Newbie with signals
42850: 02/05/04: Re: Xilinx 2GB limit... something has to be done
42968: 02/05/08: Re: VHDL: FIFO
43113: 02/05/14: Re: Architecture for high-level reconfigurable computing
43128: 02/05/14: Re: Architecture for high-level reconfigurable computing
43141: 02/05/14: Re: Architecture for high-level reconfigurable computing
43159: 02/05/14: Re: Architecture for high-level reconfigurable computing
43193: 02/05/15: Re: Architecture for high-level reconfigurable computing
43229: 02/05/16: Re: Architecture for high-level reconfigurable computing
44375: 02/06/18: Re: Xilinx ISE BaseX... What is it?
44853: 02/07/02: Re: Xilinx's 4.1i's Lastest webpack
45299: 02/07/18: Re: I want to buy 4 Xilinx FPGA
45850: 02/08/07: Re: Programming bits reverse engineering
49075: 02/10/31: Re: Which PCI-IO-Chip manufacturer to prefer?
49093: 02/10/31: Re: Chip for fine delays
51475: 03/01/14: Re: SChematic design approach compared to VHDL entry approach
51529: 03/01/15: Re: SChematic design approach compared to VHDL entry approach
51530: 03/01/15: Re: SChematic design approach compared to VHDL entry approach
51537: 03/01/15: Re: SChematic design approach compared to VHDL entry approach
51578: 03/01/16: Re: Schematic design approach compared to VHDL entry approach
53572: 03/03/16: Re: more footprints...
53595: 03/03/17: Re: more footprints...
53596: 03/03/17: Re: more footprints...
53618: 03/03/17: Re: more footprints...
54625: 03/04/14: Re: Testing engineering ability prior to work?
56089: 03/05/28: Re: JTAG madness
64372: 03/12/31: Re: A dilemma: which signal to use as a master?
64402: 04/01/01: Re: SOS : 4-bit binary divider circuit PLEASE!!!!!!!
64521: 04/01/06: Re: How do you initialize signals in VHDL?
65606: 04/02/03: Re: Design Flow: PCI or any other high-speed PC interface ?
65666: 04/02/04: Re: 4 bit divisor with flip-flop ?
Keith So:
87606: 05/07/27: Re: Xilinx Foundation ISE and WinXP/x64?
Keith Thompson:
118543: 07/04/29: Re: debounce state diagram FSM
118657: 07/05/01: Re: debounce state diagram FSM
118663: 07/05/01: Re: debounce state diagram FSM
118664: 07/05/01: Re: debounce state diagram FSM
118668: 07/05/01: Re: debounce state diagram FSM
Keith Tobin:
18049: 99/09/26: New to fpga's can you help
Keith Vertrees:
497: 94/12/08: test
Keith Williams:
56994: 03/06/20: Re: Virtex II Pro FF896 socket
59071: 03/08/07: Re: Error Generate Statement
64375: 03/12/31: Re: A dilemma: which signal to use as a master?
64381: 03/12/31: Re: A dilemma: which signal to use as a master?
81211: 05/03/19: Stratix II vs Virtex 4
86617: 05/07/01: Cyclone Board with // LVDS lines
96087: 06/01/30: Re: Remotely updating Altera FPGA configuration
95034: 06/01/20: Re: OT:Shooting Ourselves in the Foot
95063: 06/01/20: Re: OT:Shooting Ourselves in the Foot
102049: 06/05/09: Altera Max Plus II to Quartus migration tool
102132: 06/05/10: Re: Altera Max Plus II to Quartus migration tool
106900: 06/08/22: ALTERA Automotive Graphics Controller Reference Design--drivers
Keith Wootten:
8994: 98/02/12: Programming Lattice ispLSI1016 with AMD MACH cable
9252: 98/03/04: Re: Analog crossbar switch matrix IC?
9833: 98/04/08: Atmel EEPROM Programmer?
10294: 98/05/10: Re: Xilinx Configuration Problem
10428: 98/05/18: Re: Minimal ALU instruction set.
10440: 98/05/19: Re: Minimal ALU instruction set.
10995: 98/07/09: Xilinx 5200 pin swapping
11709: 98/09/02: Re: Constraining Xilinx tools to NOT use certain pins?
14788: 99/02/17: Re: Xilinx Spartan and pin-locking
20138: 00/01/28: Re: ADC to DSP... FIFO?
20219: 00/02/01: Xilinx Tools
20300: 00/02/04: Re: Xilinx Tools
21415: 00/03/22: Re: How to solder FPGA in BGA package ?
23942: 00/07/17: Xilinx Foundation 2.1 Run Times
33242: 01/07/20: Re: Working Design - Anyone
71308: 04/07/14: High Temperature FPGAs
Keith Youngblood:
54993: 03/04/23: Newbie question
keith.a.williams.3:
75331: 04/11/02: Re: "frying" FPGAs
Keith_eng_fyp:
82063: 05/04/06: Xilinx ISE Input Pins Problem
kekely:
153302: 12/01/29: Relative paths in EDK user repository TCL script
153322: 12/01/31: Re: Relative paths in EDK user repository TCL script
kelau:
93293: 05/12/19: Re: ERROR:Pack:1564: ML403 & Xilinx Platform Studio 7.1.02i
Kelly:
68193: 04/03/29: FPGA Engineer w/clearance - where do you look for a job?
68318: 04/04/01: Re: FPGA Engineer w/clearance - where do you look for a job?
69364: 04/05/08: Re: How to remove an unintended Right-click menu?
Kelly Hall:
1171: 95/05/10: Re: Compression algo's for FPGA's
19530: 99/12/29: Re: An online division unit with constant divisor
19604: 00/01/04: Re: An online division unit with constant divisor
19982: 00/01/21: Re: Biphase mark decoder
19986: 00/01/21: Re: Biphase mark decoder
21472: 00/03/22: Re: No- FPGA openness
21584: 00/03/25: Re: No- FPGA openness
25731: 00/09/18: Re: Non-disclosures in job interviews, Round Two
28315: 01/01/05: Re: Nondeterministic FSMs in hardware?
37106: 01/11/30: Re: Is there a full open-source synthesis path for any FPGA?
37153: 01/12/02: Re: Is there a full open-source synthesis path for any FPGA?
37143: 01/12/01: Re: Is there a full open-source synthesis path for any FPGA?
39708: 02/02/17: Re: Handel-C, System-C, Formal verification ???
41229: 02/03/22: Re: Pipelined sorting algorithms...
42555: 02/04/27: Re: ABEL for the Altera MAX 7000
43951: 02/06/07: Re: Scientific puzzle of formal circuit verification at next week's DAC
82454: 05/04/13: Re: Reverse engineering masked ROMs, PLAs
Kelvin:
66607: 04/02/24: What is the constraint to define the clock skews in XST?
66667: 04/02/25: Warning on DCM min frequency...
66675: 04/02/25: Re: SmartMedia writer (implments using VHDL)....
66726: 04/02/26: Re: SmartMedia writer (implments using VHDL)....
66835: 04/02/27: Re: SmartMedia writer (implments using VHDL)....
66985: 04/03/03: Does iseWebPack 6.2w has FPGA-Editor inside?
67000: 04/03/03: Design never finish routing?
67091: 04/03/05: Why does my RPM creation fail?
67401: 04/03/11: Re: Routing phases after it has completed routing?
67499: 04/03/13: Re: Does XST handles //synopsys parallel_case?
67501: 04/03/13: Re: long PAR run time for a v.v.small design in virtex II
67832: 04/03/20: Re: Added example VC++ program to download XIlinx FPGAs
67850: 04/03/21: Re: Added example VC++ program to download XIlinx FPGAs
67851: 04/03/21: Re: Added example VC++ program to download XIlinx FPGAs
67853: 04/03/21: How do I read the INIT values in blockRAM?
67871: 04/03/22: Re: How do I read the INIT values in blockRAM?
68001: 04/03/24: Re: study verilog or vhdl?
68096: 04/03/26: Re: Bus macro in partial reconfiguration
68426: 04/04/04: Constant (K) Coded Programmable State Machine for Spartan-II and Virtex-E Devices...
68428: 04/04/04: Re: Constant (K) Coded Programmable State Machine for Spartan-II and Virtex-E Devices...
68429: 04/04/04: Re: Bus macro in partial reconfiguration
68577: 04/04/08: What is the use of MAX7128?
68766: 04/04/17: Re: PCI Express specification.
70008: 04/05/27: Re: What can I do if my chip can't meet timing?
70029: 04/05/28: Re: What can I do if my chip can't meet timing?
70033: 04/05/28: Yawn...Cannot copy Acrobat Reader -write_timing_constraints YES directly into .xst file...
70059: 04/06/01: Is this a bug in ISE 6.1?
70381: 04/06/15: Re: >Math Skills = >Engineer ?
70387: 04/06/15: Re: >Math Skills = >Engineer ?
70892: 04/07/01: Compilation relation between `ifdef and //synthesis translate_off
70893: 04/07/01: How to prevent MAP from removing floating inputs?
70940: 04/07/02: Compile 30% of my multipliers with LUT?
70941: 04/07/02: Why this statement renders TWO multipliers in XST?
70988: 04/07/05: Re: Compile 30% of my multipliers with LUT?
70989: 04/07/05: Re: Compile 30% of my multipliers with LUT?
70990: 04/07/05: Re: Compile 30% of my multipliers with LUT?
71028: 04/07/06: Re: Xilinx FPGA routing question
71029: 04/07/06: Place & route question in Xilinx...
71053: 04/07/07: Difficulty in routing sinita/sinitb in block RAMs...
71102: 04/07/08: Re: Division in Xilinx
71104: 04/07/08: How to constrain a divide by 3 clock?
71129: 04/07/09: Re: How to constrain a divide by 3 clock?
71130: 04/07/09: Re: Xilinx Student Foundation Edition on Windows-XP ??
71252: 04/07/13: Re: Multi-phase Motor Controller?
71255: 04/07/13: Re: Available: Open Source VHDL parser - for free
71526: 04/07/20: Re: FPGA in a Compact Flash format.
71939: 04/08/04: Manipulation on netlist for faster simulation.
71975: 04/08/05: Re: Manipulation on netlist for faster simulation.
71982: 04/08/05: Re: Manipulation on netlist for faster simulation.
72024: 04/08/06: Re: Manipulation on netlist for faster simulation.
72029: 04/08/06: Re: Reconfigurable system
72088: 04/08/08: Re: Manipulation on netlist for faster simulation.
72148: 04/08/10: Re: Differences between FPGA & CPLD
72149: 04/08/10: Re: LEGO mindstorms and FPGA
72150: 04/08/10: Re: LEGO mindstorms and FPGA
72512: 04/08/22: Re: XST synthesis
72515: 04/08/23: Re: XST synthesis
73267: 04/09/17: How to enable connecting floating input pins to constants?
74406: 04/10/11: Micromechatronics, is there money in this area?
75688: 04/11/12: Why does NCVerilog fail to annotate these timing checks?
75817: 04/11/16: Re: Why does NCVerilog fail to annotate these timing checks?
Kelvin @ Clementi:
56800: 03/06/16: Downloading bit-stream with a microprocessor.
57356: 03/06/28: Re: Partial reconfiguration of Vertex-2 devices.
Kelvin @ SG:
64444: 04/01/05: Do all the Vertex DCM outs use same global clock tree?
64447: 04/01/05: How do I make use of local-clocks in a Virtex-2 FPGA?
64498: 04/01/06: XST cant compile with blaxkboxes.
64501: 04/01/06: Re: XST cant compile with blaxkboxes.
64506: 04/01/06: Is the P&R processing time proportional to the FPGA gate count or the size of my logic?
64534: 04/01/07: Where do XPP290 places top-level logic when all three AREA_GROUPs have DISALLOW_BOUNDARY_CROSSING on them?
64535: 04/01/07: Conversion of NCD files from 5.X to 6.1X, problem.
64585: 04/01/08: Local constant (VCC & GND) for partial reconfiguration.
64588: 04/01/08: ERROR:HDLCompilers:200 - ../../../src/iq_gen.v line 35 Target of defparam 'lut_vdd.init' does not exist
64590: 04/01/08: Improvement on the modular design methodology...
64591: 04/01/08: Re: ERROR:HDLCompilers:200 - ../../../src/iq_gen.v line 35 Target of defparam 'lut_vdd.init' does not exist
64658: 04/01/10: What is wrong with my DCM experiment? How come the testbench won't simulate DCM1.
64717: 04/01/12: Re: Is the P&R processing time proportional to the FPGA gate count or the size of my logic?
64750: 04/01/13: Re: ERROR:HDLCompilers:200 - ../../../src/iq_gen.v line 35 Target of defparam 'lut_vdd.init' does not exist
64762: 04/01/13: WARNING:MapLib:596 - Bad port net PORTTYPE, sig bus0_bm(15)
64797: 04/01/14: How do I constrain this type of design?
64855: 04/01/15: Which version of ISE Webpack has FPGA Editor on it?
64906: 04/01/16: Error in Assembly stage.
64980: 04/01/18: Re: Which version of ISE Webpack has FPGA Editor on it?
64981: 04/01/18: Re: ERROR:HDLCompilers:200 - ../../../src/iq_gen.v line 35 Target of defparam 'lut_vdd.init' does not exist
64984: 04/01/18: Deriving 36MHz from a 40MHz crystal using DCM?
65019: 04/01/19: Re: par problems with modular design for partial reconfiguration
65024: 04/01/19: How to handle top-level glue logic.
65071: 04/01/20: Re: Deriving 36MHz from a 40MHz crystal using DCM?
65072: 04/01/20: Re: Good/Affordable Stater kits
65079: 04/01/20: Why doesn't NGDBuild recognize some UCF formatting?
65090: 04/01/20: Small bit manipulation on two designs with routing differences...
65316: 04/01/24: UCF constraints for DCM outputs?
65318: 04/01/24: How come NGDBuild derive a clk_36m_tmp/4 clock?
65336: 04/01/25: Cascading of many stages of DCM...
65338: 04/01/25: How do I fix this type of errors?
65347: 04/01/26: Re: Cascading of many stages of DCM...
65428: 04/01/29: Re: building macros for Virtex-II with FPGA editor...
65458: 04/01/30: Where to get FPGA devices for testing?
65478: 04/01/30: Re: Where to get FPGA devices for testing?
65479: 04/01/30: Re: Where to get FPGA devices for testing?
65589: 04/02/03: Re: Which Environment for Xilinx Design?
65699: 04/02/05: Re: How do I fix this type of errors?
65717: 04/02/05: Abnormal routing behavior for Active Module implementation and bitstream length.
65760: 04/02/06: Re: How do I fix this type of errors?
65761: 04/02/06: Virtex 2: Partial Bitstream Generation with bitgen -r
65906: 04/02/10: Re: How may I restrain the P&R to only a small area...
65939: 04/02/10: Re: Partial reconfig flow
66166: 04/02/13: Re: Partial reconfig flow
66226: 04/02/15: Error in NetGen, "ATAL_ERROR:Anno:Engine.c:476:1.44 - Xdm Exception:"
66274: 04/02/17: Re: Partial Reconfig - PAR fails with ISE 6.1 SP3
66275: 04/02/17: Spartan-2 Bus Macro, which one also?
66417: 04/02/19: Unix workstation runs ISE 6.1 slower than a PC?
66687: 04/02/25: Re: DCM Simulation Error
66876: 04/02/28: Re: Polyphase filter
66960: 04/03/02: Re: CASCADING DCM
67142: 04/03/06: Can Verilog codes be synthesized with XIlinx XST?
67143: 04/03/06: Re: Can Verilog codes be synthesized with XIlinx XST?
67153: 04/03/07: Documentation and manuals for Quatus 3.0...
67168: 04/03/08: Re: Bus interface - read, write signals
67169: 04/03/08: Re: Documentation and manuals for Quatus 3.0...
67223: 04/03/09: Re: Xilinx announces acquisition of Triscend
67224: 04/03/09: Can `protect-ed Verilog codes be synthesized with Xilinx XST?
67243: 04/03/09: Re: Can Verilog codes be synthesized with XIlinx XST?
67244: 04/03/09: Re: Can `protect-ed Verilog codes be synthesized with Xilinx XST?
67245: 04/03/09: Re: How do I fix this type of errors?
67298: 04/03/10: Re: novice for FPGA
67300: 04/03/10: Question on synchronization multiple DCMs in Virtex-2...
67304: 04/03/10: Re: xilinx configuration problem
67325: 04/03/10: Very strange Xilinx timing report.
67326: 04/03/10: Re: novice for FPGA
67338: 04/03/10: Re: Can `protect-ed Verilog codes be synthesized with Xilinx XST?
67373: 04/03/11: Routing phases after it has completed routing?
67394: 04/03/11: Oftenly used hardware algorithm for RC4 encryption?
67442: 04/03/12: Re: Oftenly used hardware algorithm for RC4 encryption?
67444: 04/03/12: Three multipliers for FUNC_MULTI(A, B) in a 3 branch case statement?
67448: 04/03/12: Does XST handles //synopsys parallel_case?
67458: 04/03/12: Re: novice for FPGA
67618: 04/03/16: Re: UCF or XCF - which one to use ?
67722: 04/03/18: Re: "WARNING:Xst:528 - Multi-source in Unit <entity> on signal <sig> not replaced by logic."
67780: 04/03/19: Re: Added example VC++ program to download XIlinx FPGAs
67887: 04/03/22: Re: How do I read the INIT values in blockRAM?
67888: 04/03/22: Re: 64bit cpu on Xilinx
68086: 04/03/26: Estimate the gate sizes between ASIC and Virtex-2...
68267: 04/03/31: Re: Real-time Image Process on FPGA
68508: 04/04/07: XST -read_cores YES doesn't merge the NGC into the compiled file...
68555: 04/04/08: Re: XST -read_cores YES doesn't merge the NGC into the compiled file...
68564: 04/04/08: Altera Quartus Web Edition license...
68678: 04/04/14: Re: What is the use of MAX7128?
68679: 04/04/14: Re: SAA7111 YUV
68686: 04/04/14: Price of a Virtex-2 6000 chip...
68729: 04/04/16: PCI Express specification.
68840: 04/04/20: Re: PCI Express specification.
69004: 04/04/25: How do I put LOC constraint on a coregen DPRAM?
69005: 04/04/25: Re: How do I put LOC constraint on a coregen DPRAM?
69211: 04/04/30: Not enough sites to place MULT18X18?
69213: 04/04/30: Can assign same area group to multiple modules?
69272: 04/05/04: Re: Not enough sites to place MULT18X18?
69479: 04/05/12: Re: FPGA wanted
70345: 04/06/14: Design Compiler, how do I use a derating library...
70346: 04/06/14: Re: a newbie question
71035: 04/07/06: Re: Place & route question in Xilinx...
71038: 04/07/06: Applicability of mult_style in XST.
Kelvin Hsu:
40690: 02/03/13: How would I know somebody has copied my files in Unix?
40695: 02/03/13: How can I program into the EEPROM?
40899: 02/03/18: How to deal with a high fan-out net in FPGA.
40905: 02/03/18: Clock buffer and Reset example.
40972: 02/03/19: Re: DDS in an FPGA
41034: 02/03/20: Possibility of RTL and Gate-level simulation dont match?
41105: 02/03/21: Re: Possibility of RTL and Gate-level simulation dont match?
41110: 02/03/21: Re: Possibility of RTL and Gate-level simulation dont match?
41117: 02/03/21: Difference between two mulplications?
41121: 02/03/21: Re: doubt on GDSII file integration
41123: 02/03/21: Re: simulation issues
41166: 02/03/22: Re: Possibility of RTL and Gate-level simulation dont match?
41243: 02/03/23: Re: Possibility of RTL and Gate-level simulation dont match?
41280: 02/03/25: Re: simple Free FPGA tool
41321: 02/03/26: How to recover a Bluetooth data stream.
41378: 02/03/27: Re: Handel-C useless.. Move to SystemC
41396: 02/03/27: How to probe internal signals from Xilinx netlist?
41545: 02/04/02: Re: Filter design problem
41558: 02/04/02: Re: pipelined correlation block on Virtex2000?
Kelvin L.:
66519: 04/02/20: Re: Random logic verilog gate netlist generator
Kelvin Law:
22212: 00/05/02: test
Kelvin Nilsen:
416: 94/11/11: Programmable Interfaces to Rambus
Kelvin T. Leung:
9085: 98/02/18: floating point unit
Kelvin Tsai @ Singapore:
56830: 03/06/16: Re: Downloading bit-stream with a microprocessor.
57071: 03/06/23: MIPS instruction set?
57303: 03/06/27: Partial reconfiguration of Vertex-2 devices.
Kelvin XCJ:
42643: 02/04/30: Query on Power Compiler.
43347: 02/05/20: Difference between Altera and Xilinx.
43830: 02/06/04: Sigma-delta DACs.
Kelvin Xu Qijun:
41597: 02/04/03: Design of a complex filter used in Bluetooth receiver.
41681: 02/04/05: Re: hand placement
41683: 02/04/05: Re: Schematic Stuff
41774: 02/04/08: Modelsim-XE fails when simulating a VHDL model.
41792: 02/04/08: Re: How to probe internal signals from Xilinx netlist?
Kelvin, Chee:
64293: 03/12/25: Question regarding the sample design in XAPP290.
64310: 03/12/27: Bus delimiter in iseWebPACK 4.2
<Kelvin>:
29598: 01/02/28: Virtex ambit support
29600: 01/02/28: Re: Virtex ambit support
kelvins:
88001: 05/08/05: about the Hold signal of serial flash .
100428: 06/04/08: asynchronous FIFO design
100646: 06/04/14: what wrong of this counter ?
100700: 06/04/16: Re: what wrong of this counter ?
100734: 06/04/17: Re: what wrong of this counter ?
104063: 06/06/18: pad issue
114499: 07/01/17: ARM AHBA 1Kbyte boundary issue
kemalinmaili@gmail.com:
119427: 07/05/18: I need advice
<kempaj@yahoo.com>:
77038: 04/12/20: Re: Problem with SOPC Builder in Quartus 4.0
77204: 04/12/29: Re: Altera NIOS II/Stratix II vs Xilinx Products
77540: 05/01/10: Re: San Jose job offer - need advice
79436: 05/02/18: Re: nios2 flash programmer
80251: 05/03/02: Re: Nios II timing question
80312: 05/03/03: Re: Nios II timing question
80805: 05/03/11: Re: Xilinx vs Altera high-end solutions
81298: 05/03/21: Re: Is the Xilinx EDK free?
81305: 05/03/21: Re: Is the Xilinx EDK free?
83374: 05/04/28: Re: Cygwin & Nios II
84122: 05/05/12: Re: "Mine is bigger than yours..."
84165: 05/05/13: Re: "Mine is bigger than yours..."
84282: 05/05/16: Re: Is a gated oscillator using NAND okay within a Cyclone FPGA?
85019: 05/06/02: Re: Altera's fast NIOS update service (o;
85162: 05/06/06: Re: XP for NIOS2
85172: 05/06/06: Re: Generating linker script for Altera desgn
85213: 05/06/06: Re: Altera NIOS2 50.0 SOPC periphals broken???
85285: 05/06/07: Re: nios32 -> nios2 assembly porting?
85442: 05/06/09: Re: XP for NIOS2
86022: 05/06/20: Re: Design tools comparison between Xilinx, Altera and Lattice for FPGA designs
86157: 05/06/22: Re: JTAG port access in Cyclone
86247: 05/06/23: Re: nios2 gnu sources broken for amd64 linux
86250: 05/06/23: Re: Minimum allowed clock frequency for Nios 2 processor (Stratix 2)
86422: 05/06/27: Re: good bye nios (o;
87788: 05/08/01: Re: Altera Avalon Address format between Master & SDRAM controller?
92878: 05/12/08: Re: FPGA development board with digital image camera
96627: 06/02/07: Re: NMEA Decoder/Display
105369: 06/07/20: Re: Virtex-5: SoftCore processors at 200MHz !
112197: 06/11/17: Re: memory init in Altera bitfiles, (like data2mem) is it possible?
112381: 06/11/21: Re: memory init in Altera bitfiles, (like data2mem) is it possible?
122857: 07/08/08: Re: New Xilinx forum.
Ken:
34869: 01/09/12: Re: FPGA Evaluation Board for image processing
35773: 01/10/17: Re: pci-card with Virtex2?
36214: 01/11/02: Re: Implementing Filter
41500: 02/03/30: VirtexII : Any limitation on using LVDS?
52652: 03/02/18: Xilinx multi-cycle constraints report
52687: 03/02/19: Re: Xilinx multi-cycle constraints report
53577: 03/03/17: Re: more footprints...
53620: 03/03/18: Re: more footprints...
54134: 03/04/03: offset timing constraints - required?
54544: 03/04/14: Re: Hardware acceleration for raytracing purposes
54640: 03/04/15: where are the big power savings to be had?
55166: 03/04/29: RF transmitters/receivers with Xilinx Xtreme DSP Kit
55197: 03/04/30: Re: RF transmitters/receivers with Xilinx Xtreme DSP Kit
55413: 03/05/07: OT: looking for I/Q mixers/modulators for TX and RX
55422: 03/05/07: Re: OT: looking for I/Q mixers/modulators for TX and RX
56402: 03/06/04: Altera FIR Compiler from command line?
56889: 03/06/18: Xilinx ISE is putting this signal assignment in the wrong timing constraint group...
58124: 03/07/15: What are the maximum filter specs you've seen?
58380: 03/07/22: (repost) What are the maximum filter specs you've seen?
58772: 03/08/01: preventing vsimsa mgf file growth
59990: 03/09/03: Re: Compact FIR filters with multiplier blocks?
60003: 03/09/03: Re: Compact FIR filters with multiplier blocks?
60117: 03/09/05: 200MHz ucf constraints for Xilinx DA Decimation by 2
60127: 03/09/05: Re: 200MHz ucf constraints for Xilinx DA Decimation by 2
60998: 03/09/26: Re: Compact FIR filters with multiplier blocks?
61220: 03/09/30: doubling clock rate does what to power consumption?
61662: 03/10/08: Xilinx dedicated multiers vs multipliers in slice fabric
61702: 03/10/09: Re: Xilinx dedicated multiers vs multipliers in slice fabric
61762: 03/10/10: Re: Xilinx dedicated multiers vs multipliers in slice fabric
63161: 03/11/17: Synplify Pro/ISE adder carry chain - interrupted
63187: 03/11/17: Re: Synplify Pro/ISE adder carry chain - interrupted
63297: 03/11/19: How to RLOC adders in VHDL/Synplify to avoid broken carry chains?
63362: 03/11/20: Re: How to RLOC adders in VHDL/Synplify to avoid broken carry chains?
63370: 03/11/20: Re: How to RLOC adders in VHDL/Synplify to avoid broken carry chains?
63371: 03/11/20: Re: How to RLOC adders in VHDL/Synplify to avoid broken carry chains?
63377: 03/11/20: Re: How to RLOC adders in VHDL/Synplify to avoid broken carry chains?
63424: 03/11/21: Re: How to RLOC adders in VHDL/Synplify to avoid broken carry chains?
63729: 03/12/02: ngdbuild, edif2ngd Pipe ended error
63772: 03/12/03: Re: Command line in Windows?
65476: 04/01/30: Re: Is FPGA fully static?
66089: 04/02/12: is this enable structure ok for synthesis/high speed?
66100: 04/02/12: timing constraints and enables
66157: 04/02/13: Re: timing constraints and enables
66187: 04/02/13: Re: is this enable structure ok for synthesis/high speed?
67634: 04/03/16: Re: Schematic Edition Tool : Suggestions
69276: 04/05/04: [ANN] DSP for FPGAs 4-Day Course
75746: 04/11/14: Re: Digital LP filter in multiplier free FPGA
75777: 04/11/15: Re: Digital LP filter in multiplier free FPGA
75858: 04/11/17: Setup violation warning with constant signal in Modelsim/Webpack
76321: 04/11/30: CMOS capacitive loads, transition probabilities and FPGAs
76351: 04/12/01: Re: CMOS capacitive loads, transition probabilities and FPGAs
76380: 04/12/01: Re: CMOS capacitive loads, transition probabilities and FPGAs
76414: 04/12/01: Re: CMOS capacitive loads, transition probabilities and FPGAs
76415: 04/12/01: Re: CMOS capacitive loads, transition probabilities and FPGAs
77776: 05/01/17: Re: Problems in timing simulations
77821: 05/01/18: Re: Problems in timing simulations
77963: 05/01/21: Re: C programmer, what does this syntax mean?
78062: 05/01/24: Re: C programmer, what does this syntax mean?
78063: 05/01/24: Re: Poblem with Xilinx ISE
78373: 05/01/31: Re: Sensitive List Question
78441: 05/02/01: Re: Any solution for solving setup or hold time violation?
78542: 05/02/03: Source of reset for synchronous reset can lead to metastability?
79854: 05/02/25: Re: Questions on XPower: "Confidence level is shown as inaccurate"
81435: 05/03/23: DSP designs that exceed provided embedded arithmetic hardware
81442: 05/03/23: Re: DSP designs that exceed provided embedded arithmetic hardware
83772: 05/05/06: Will this DCM cascade track a frequency offset clock?
83933: 05/05/10: Re: Will this DCM cascade track a frequency offset clock?
84065: 05/05/11: Looking for Rapid prototyping system, ?Quickturn ASIC-Emulator?
84447: 05/05/19: Xilinx V2Pro DCM config and settling time questions
84522: 05/05/20: Re: Xilinx V2Pro DCM config and settling time questions
84526: 05/05/20: Re: Xilinx V2Pro DCM config and settling time questions
Ken Barr:
31109: 01/05/12: Re: SpartanII: non clock pad drives clock net ?
Ken Boorom:
15421: 99/03/23: Anyone know what happened to www.prep.org
Ken Cecka:
138462: 09/02/24: Re: Very fast counter in VirtexII
Ken Chapman:
28617: 01/01/18: Re: FPGA for radar digital downconversion
28779: 01/01/24: Re: Virtex-II officially launched
40026: 02/02/25: Re: EDIF IN A VHDL PROJECT (kcpsm.edn) in ISE4.1
41354: 02/03/26: Re: question on LFSR
41399: 02/03/27: Re: question on LFSR
50340: 02/12/09: Re: Digital filter
50391: 02/12/10: Re: Tiny Forth Processors
51512: 03/01/15: Re: filter coefficient multiplication in vhdl
51520: 03/01/15: Re: Short FIFO in Verilog / Spartan IIE
51982: 03/01/28: Re: 1024bit Adder
52455: 03/02/10: Re: FFT Size and speed
52631: 03/02/17: Re: Generating a sin wave with vhdl
53130: 03/03/04: Re: FIR Filter from Xilinx
54747: 03/04/17: Re: Advice on FPGA IIR Filter
63153: 03/11/17: Re: Xilinx UART Macro ERROR???
Ken Christensen:
24288: 00/08/02: 32-input AND and 100-input OR - can I do it fast?
Ken Chung:
8153: 97/11/21: Gigaops Reconfiguration board
8495: 97/12/24: Re: PCs vs. workstations
15841: 99/04/16: Wire-AND in longline of 4000 series?
Ken Coffman:
12248: 98/10/06: Re: Verilog Simulators
12280: 98/10/07: Re: Verilog Simulators
12323: 98/10/08: Re: FPGA core design
12347: 98/10/09: Re: LCELL delay of Altera 10K's
12494: 98/10/13: Re: gray code counter in a Xilinx fpga???
12547: 98/10/15: Re: gray code counter in a Xilinx fpga???
12648: 98/10/21: Re: gray code counter in a Xilinx fpga???
12732: 98/10/26: Re: FPGA Decouple Capacitor values
13123: 98/11/16: Re: newbie question about timing
13231: 98/11/20: Re: Major Xilinx design problems using XC4013XL or XC4020XL, M1.3-M1.5
13744: 98/12/21: Re: Xilinx Foundation vs. Altera Max Plus II
13392: 98/11/30: Re: Will XILINX survive?
13660: 98/12/16: Re: Xilinx Foundation vs. Altera Max Plus II
13414: 98/12/01: Re: HELP, Tool selection
13544: 98/12/08: Re: FPGA Synthesis tools
13947: 99/01/04: Re: 22V10 Metastability - help please
14494: 99/02/01: Re: Help for the scientifically-challenged
15205: 99/03/12: Re: Spartan, delaying a clock.
Ken Forsythe:
Ken Frawley:
52633: 03/02/17: Synopsys FC2 version 3.7.2 best so far
52663: 03/02/18: Re: Synopsys FC2 version 3.7.2 best so far
Ken Geis:
11: 94/07/28: Help: Homebrew development hardware sources...
54: 94/08/04: Sea-of-gates / FPGA ?'s
Ken Goldman:
955: 95/04/03: Re: Excuse me while I vent about Data I/O & Abel...
966: 95/04/05: Re: Excuse me while I vent about Data I/O & Abel...
1004: 95/04/12: Re: Neocad merges with Xilinx
1298: 95/05/30: Re: ABEL optimization
1530: 95/07/10: Re: AHDL reference?
1596: 95/07/24: Re: Help on Altera FLEX 8000 programming
1910: 95/09/19: Re: ECL fpga
2039: 95/10/05: Re: NEW person
2508: 95/12/21: Re: UART in PLD
2616: 96/01/11: Re: ECL PALs or FPGAs
Ken Hagan:
66928: 04/03/01: Re: OT Re: Dual-stack (Forth) processors
Ken Jaramillo:
59086: 03/08/07: Quartus II and fixing hold timing
Ken Kent:
33332: 01/07/23: HotII interrupts...
Ken Krabacher:
20161: 00/01/29: Re: ADC to DSP... FIFO?
Ken Krolikoski:
5282: 97/02/03: Re: Q is Xilinx Foundation BASE worth buying?
5306: 97/02/06: Re: Embedded SRAM in FPGAs
5307: 97/02/06: Re: Q is Xilinx Foundation BASE worth buying?
5308: 97/02/06: Re: [Q] Xilinx FPGA Resources
Ken Land:
59018: 03/08/06: Using 3rd Party IP Cores...
59213: 03/08/12: Re: Nios Clock Frequency
60494: 03/09/15: Re: What CPU for Quartus II?
60548: 03/09/16: Re: USB transceiver for FPGA
60581: 03/09/16: Re: USB transceiver for FPGA
60638: 03/09/18: Re: Nios Quartus II Question...
61229: 03/09/30: Re: USB 1.1/2.0 Implementation
61420: 03/10/03: Re: large integer support in GNUPro for Altera Nios software development
62791: 03/11/07: Re: Programmer's unpaid overtime.
64865: 04/01/15: Re: Altera NIOS cyclone edition development board problem
65673: 04/02/04: CycloneII, NiosII, StratixII more info please....
69925: 04/05/24: Re: Nios II = Microblaze
69958: 04/05/25: Re: Nios II = Microblaze
70077: 04/06/01: Re: NIOS 2 memory limitations
Ken Mac:
40133: 02/02/28: stuck in state in Spartan-II!
40140: 02/02/28: Re: stuck in state in Spartan-II!
40172: 02/03/01: Re: stuck in state in Spartan-II!
40173: 02/03/01: Re: stuck in state in Spartan-II!
40182: 02/03/01: Re: stuck in state in Spartan-II!
40272: 02/03/04: SOLVED Re: stuck in state in Spartan-II!
40275: 02/03/04: phantom timing constraints in ISE 4.1
40306: 02/03/05: Re: Asynchronous boundaries in FPGA
40309: 02/03/05: Re: phantom timing constraints in ISE 4.1
41186: 02/03/22: Re: another from newbie
43629: 02/05/28: Do I have metastability issues?
43878: 02/06/05: Re: Do I have metastability issues?
43882: 02/06/05: Interpreting coregen footprint output in terms of slices
43887: 02/06/05: Re: Interpreting coregen footprint output in terms of slices
43915: 02/06/06: Re: Do I have metastability issues?
43953: 02/06/07: Re: Do I have metastability issues?
44020: 02/06/10: where did my MHz go!
44026: 02/06/10: Re: where did my MHz go!
44028: 02/06/10: Re: where did my MHz go!
44056: 02/06/11: surely this is mad? (clock rate issues)
44062: 02/06/11: Re: surely this is mad? (clock rate issues)
44116: 02/06/12: Re: where did my MHz go!
44117: 02/06/12: Re: where did my MHz go!
44298: 02/06/17: Xilinx System Generator FIR vs Core Generator FIR
44584: 02/06/24: Will this clock divider be good on hardware?
44610: 02/06/24: Re: Will this clock divider be good on hardware?
44632: 02/06/25: Re: Will this clock divider be good on hardware?
44664: 02/06/26: Re: Will this clock divider be good on hardware?
44667: 02/06/26: why not pipeline by default?
44863: 02/07/03: Anyone use the full Aldec 5.1 flow?
45339: 02/07/19: what FIR filter coefficient bit widths do you use?
45391: 02/07/22: Re: what FIR filter coefficient bit widths do you use?
45644: 02/07/30: Maximum FIR coefficient widths on FPGA
45654: 02/07/30: Re: Maximum FIR coefficient widths on FPGA
47431: 02/09/25: coregen DA FIR 7.0 singlerate/interpolated, floorplans, SRL16s and flip-flops
47521: 02/09/27: (repost) coregen DA FIR 7.0 singlerate/interpolated, floorplans, SRL16s and flip-flops
47960: 02/10/08: Re: Why can Xilinx sw be as good as Altera's sw?
48056: 02/10/10: how do initialised signals really get set in Xilinx slices?
48060: 02/10/10: Re: how do initialised signals really get set in Xilinx slices?
48113: 02/10/11: Re: how do initialised signals really get set in Xilinx slices?
48114: 02/10/11: Re: how do initialised signals really get set in Xilinx slices?
49221: 02/11/05: multi-channel filters - how many channels?
49429: 02/11/12: repost: parallel multi-channel filters - how many channels?
49483: 02/11/13: Re: multi-channel filters - how many channels?
Ken McElvain:
14861: 99/02/20: Re: multiple clock domain problem
15500: 99/03/26: Re: keeping an Altera EAB register in synplicity
18340: 99/10/16: Re: Interconnecting LUTs on a Virtex
18395: 99/10/21: Re: VHDL carry chain RPMs
19345: 99/12/15: Re: State machine ok with binary encoding but unstable with one hot
20327: 00/02/04: Re: PMUX primitive in Sinplify
20370: 00/02/08: Re: How to get Synplicity to NOT use Global Clock for Virtex...
23435: 00/06/24: Re: Defining a reset concept for VirtexE
23436: 00/06/24: Re: CAE Software and Internet Access
23950: 00/07/17: Re: Altera fitter woes
31040: 01/05/09: Re: Synplicity/Quicklogic choosing high drive input
31041: 01/05/09: Re: Synplicity/Quicklogic choosing high drive input
31077: 01/05/10: Re: Synplicity/Quicklogic choosing high drive input
31305: 01/05/17: Re: Synplify: warnings for Verilog blackbox in VHDL
31316: 01/05/18: Re: Synplify: warnings for Verilog blackbox in VHDL
31951: 01/06/09: Re: Virtex LUT4 problems in FPGA Express
32007: 01/06/10: Re: Force tristate enable register into IOB
33050: 01/07/16: Re: Design entry
33066: 01/07/16: Re: Design entry
33651: 01/08/01: Re: Spanning the heirarchy
33757: 01/08/03: Re: Spanning the heirarchy
34407: 01/08/23: Re: Slowing PCI for FPGA
34408: 01/08/23: Re: Logic Emulation
35055: 01/09/19: Re: Synplicity logic replication
35663: 01/10/12: Re: High level synthesis will never work well :)
35719: 01/10/15: Re: Synplicity/Leonardo License Agreement Information
35721: 01/10/15: Re: Synplicity/Leonardo License Agreement Information
36195: 01/11/01: Re: High level synthesis will never work well :)
37209: 01/12/03: Re: What do you like/dislike about place and route tools?
37783: 01/12/20: Re: Defauolt Should Be "Inputs and Outputs" For IOBs
38345: 02/01/11: Re: multiply (*) 11000000000
40926: 02/03/18: New ASIC prototyping tool
40978: 02/03/19: Re: A petition for Synplify's new fature (FPGA synthesis tool)
41267: 02/03/23: Re: A petition for Synplify's new fature (FPGA synthesis tool)
41275: 02/03/24: Re: A petition for Synplify's new fature (FPGA synthesis tool)
41366: 02/03/26: Re: question on LFSR
41440: 02/03/28: Re: how to prevent infer of Mult18x18 in VirtexII
41662: 02/04/04: Re: powerpc in virtex2pro
41712: 02/04/05: Re: hand placement
42041: 02/04/13: Re: prototyping an ASIC
42564: 02/04/27: Re: synplicity 6.2.4 can not recongnize "altera_implement_in_esb" directive
42738: 02/05/01: Re: Can not get define_multicycle_path to work.
42800: 02/05/02: Re: Vertex 2 IOB- unwanted flops inside
43064: 02/05/11: Re: Xilinx-Synplicity-License issue?
44489: 02/06/21: Re: Retiming option in synplify pro
44554: 02/06/23: Re: Clock enable & Synplify 7.1
44560: 02/06/23: Re: Clock enable & Synplify 7.1
44561: 02/06/23: Re: Clock enable & Synplify 7.1
44933: 02/07/06: Re: N-bit, 2-input adder
45217: 02/07/16: Re: AT40K / FPSLIC - Place & Route tools (3rd party)?
45262: 02/07/17: Re: AT40K / FPSLIC - Place & Route tools (3rd party)?
45275: 02/07/17: Re: AT40K / FPSLIC - Place & Route tools (3rd party)?
45277: 02/07/17: Re: problem porting sync write, async read RAM to Xilinx...
45303: 02/07/18: Re: AT40K / FPSLIC - Place & Route tools (3rd party)?
45394: 02/07/22: Re: Clock-gating in Virtex-E parts
45397: 02/07/22: Re: black box components with parameters in Synplify
45412: 02/07/23: Re: black box components with parameters in Synplify
45415: 02/07/23: Re: black box components with parameters in Synplify
46204: 02/08/21: Re: How to include Xilinx library for both ModelSim and Synplify?
46215: 02/08/22: Re: How to include Xilinx library for both ModelSim and Synplify?
47821: 02/10/04: Re: system item in synplify report
48011: 02/10/09: Re: Simple Counters in Xilinx Spartan II
48363: 02/10/16: Re: Xilinx microblaze vs. picoblaze
48395: 02/10/17: Re: Xilinx microblaze vs. picoblaze
48520: 02/10/18: Re: Floorplanner RPM. How to use it?
48523: 02/10/19: Re: Floorplanner RPM. How to use it?
48537: 02/10/19: Re: Floorplanner RPM. How to use it?
48587: 02/10/21: Re: Floorplanner RPM. How to use it?
48615: 02/10/22: Re: Floorplanner RPM. How to use it?
48750: 02/10/23: Re: High Performance FPGA's - Xilinx and ??????
48763: 02/10/24: Re: FPGA XC4005E
49047: 02/10/30: Re: GlobalReset hogging routing resources
49139: 02/11/01: Re: FDRE inference in Synplify
49886: 02/11/24: Re: Why do post-synthesis simulation result fall into unknow output state 'X' or "XX..."?
50415: 02/12/10: Re: Synthesis and Design Hierarchy
50785: 02/12/19: Re: Multi cycle Paths..
50836: 02/12/20: Re: Multi cycle Paths..
50837: 02/12/20: Re: Hi xilinx
50838: 02/12/20: Re: stupid rookie timing question
51466: 03/01/14: Re: Simulate Virtex Primitive using ModelSim
51682: 03/01/19: Re: XST vs Synplify observations
53250: 03/03/08: Re: conditional `include
53296: 03/03/10: Re: conditional `include
53588: 03/03/17: Re: FPGA dev boards
54192: 03/04/04: Re: Altera not supplying Leonardo any more
54266: 03/04/06: Re: Xilinx V2.1i Licensing
54421: 03/04/10: Re: Really long vectors in VHDL
54427: 03/04/10: Re: Really long vectors in VHDL
54881: 03/04/21: Re: Boycott All Xilinx products untill they correct all ISE softwareerrors
55575: 03/05/13: Re: OK I am pissed off with Xilinx webpack.
55584: 03/05/13: Re: OK I am pissed off with Xilinx webpack.
55590: 03/05/13: Re: OK I am pissed off with Xilinx webpack.
55627: 03/05/14: Re: Can XST takes place of Synplify or FPGA Compiler?
55668: 03/05/15: Re: multiplexing resources in xilinx fpga
55985: 03/05/26: Re: attributes and generics
56719: 03/06/12: Re: Xilinx Block RAM
56773: 03/06/14: Re: DCMs and CLKDV not dividing correctly
57026: 03/06/21: Re: Quartus bug or wrong VHDL?
57359: 03/06/28: Re: why so many problems Xilinx ?
57609: 03/07/03: Re: Discrepancy in CLB Usage Report
57610: 03/07/03: Re: Fixed point signed multiplication algorithm
57933: 03/07/10: Re: Synplify and then Quartus
57934: 03/07/10: Re: how can I use a signal defined in one Architecture to another Architecture
58345: 03/07/21: Re: synplify pro
59308: 03/08/14: Re: Actel: Libero/Synplify "Run" button disabled
67354: 04/03/10: Re: Release asynchrounous resets synchronously
68127: 04/03/27: Re: Xilinx map -timing through ise gui
68202: 04/03/30: Re: CLB usage: Xilinx XCS20 and Foundation 3.1
68601: 04/04/09: Re: Problem using EDK tutorial for Memec board with Synplicity.
68997: 04/04/24: Re: What is MPGA?
70327: 04/06/12: Re: Quick question
71606: 04/07/24: Re: Looking for ways to keep diagnostic signal from being optimized
72239: 04/08/11: Re: How important are software tools while choosing FPGA
72283: 04/08/12: Re: xilinx Synthesis report - please help..
72524: 04/08/23: Re: Help, synthesis for Spartan XL; does FPGA Express licenses forISE
72544: 04/08/23: Re: Quartus, building "Safe" FMSs
73696: 04/09/28: Re: virtex2.components.all
73834: 04/09/29: Re: Pricing info for Synplify Pro Xilinx...
73375: 04/09/20: Re: Verilog vs VHDL for Loops
73531: 04/09/22: Re: Verilog vs VHDL for Loops
73533: 04/09/22: Re: Verilog vs VHDL for Loops
73638: 04/09/27: Re: virtex2.components.all
78493: 05/02/01: Re: Synopsys Designware and FPGA mapping
80061: 05/02/28: Re: Resource (FMAPs) use when using block RAMs
80136: 05/03/01: Re: block adder for Altera!
81911: 05/04/04: Re: File I/O with Synplify
82863: 05/04/18: Re: combining two EDF netlist in ISE
82983: 05/04/20: Re: actel blockram the easy way?
83087: 05/04/22: Re: Xilinx multiplier out of slices
83284: 05/04/26: Re: Rom Inference
83351: 05/04/27: Re: Synplify warning CL209
84846: 05/05/30: Re: Synplify 8.1 vs. Quartus II 5.0 QoR
85120: 05/06/05: Re: Synopsys Designware IP... can be used for Xilinx FPGA??
87126: 05/07/15: Re: Compilation error with Synplify attribute
90472: 05/10/13: Re: Simulink to hdl conversion
90518: 05/10/15: Re: Synplify Pro and automatic Retiming/Pipelining
91714: 05/11/10: Re: Anybody understand this ISE 7.1 error, and what to do about it???
92852: 05/12/07: Re: Black Box Attribute in Quartus II
99250: 06/03/21: Re: Ignoring hierachy while flagging false with with Xilinx flow.
102758: 06/05/19: Re: How to decide Fanout limit?
Ken Morrow:
34487: 01/08/27: FPGA to ASIC conversion?
43815: 02/06/03: Re: place and route simulation time
53791: 03/03/23: Can ModelSim PE/SE and XE coexist?
59226: 03/08/12: Xilinx DLL driving multiple off chip clocks
59248: 03/08/13: Re: Xilinx DLL driving multiple off chip clocks
59408: 03/08/18: Re: Xilinx DLL driving multiple off chip clocks
59455: 03/08/19: Re: Xilinx DLL driving multiple off chip clocks
60766: 03/09/22: Re: Italy is out of FPGA world?
64363: 03/12/30: Re: virtex-II problems
65186: 04/01/21: Synthesis errors?
69217: 04/04/30: Re: Not enough sites to place MULT18X18?
72274: 04/08/12: Re: xilinx Synthesis report - please help..
Ken Prager:
65940: 04/02/10: Re: iteration Vs LUT table entry vs accuracy in Cordic
Ken Reeves:
100826: 06/04/18: How is the max clock rate of a device fixed?
ken ryan:
17364: 99/07/22: Re: Workstation with Synopsys license server
18811: 99/11/17: Re: Q: implementing TCP/IP on PLD
Ken Ryan:
45780: 02/08/05: Re: VIRTEX-II pro -> LVTTL 3.3
47226: 02/09/20: Re: Has ISE 5.1i shipped?
49385: 02/11/11: Re: functional test for Xilinx virtex II Pro
63621: 03/11/26: Re: Where and How to get Nvidia Geforce 5600 public desigh graph
119794: 07/05/26: EDK9.1: XTemac + LwIP + Xilkernel + unistd.h = possible?
119846: 07/05/28: Re: EDK9.1: XTemac + LwIP + Xilkernel + unistd.h = possible?
120009: 07/05/31: Re: ISE/EDK Kubuntu linux installation issues
120071: 07/06/01: Re: ISE/EDK Kubuntu linux installation issues
120074: 07/06/01: Re: ISE/EDK Kubuntu linux installation issues
120430: 07/06/07: Re: EDK9.1: XTemac + LwIP + Xilkernel + unistd.h = possible?
120431: 07/06/07: Re: FPGA / Virtex II Pro / LWIP
120488: 07/06/08: Re: EDK9.1: XTemac + LwIP + Xilkernel + unistd.h = possible?
120489: 07/06/08: Re: FPGA / Virtex II Pro / LWIP
120557: 07/06/10: Re: xilinx windrv install on linux
121552: 07/07/08: Re: Rocketio connection Virtex2pro-Virtex4
121781: 07/07/13: Re: Xilinx ISE, EDK and some ground roules in software development
121874: 07/07/14: Re: ASM within C code in a PPC405 of VIRTEX II Pro
121989: 07/07/17: EDK9.1 LWIP network stack crashing?
122907: 07/08/10: Re: New Xilinx forum.
124692: 07/09/30: Re: PowerPC Simulation
124834: 07/10/06: Re: Virtex 13?
124948: 07/10/12: Re: FiberChannel SOF
126408: 07/11/21: Re: Problem using xilinx usb download cable in linux
126409: 07/11/21: Re: did i miss edk 9.2
131324: 08/04/19: Re: Has anyone dealt with Avnet? or NuHorizons when trying to purchase
Ken Scharf:
93570: 05/12/24: Re: Future of Microchip Development Tools?
Ken Schmidt:
20880: 00/02/25: $6 32 bit/33 MHz PCI Xilinx: Fact or Fiction?
20881: 00/02/25: Re: Xilinx PCI pinout ?
45406: 02/07/22: Xilinx ISE 4.2i Is A Step Backwards! Beware!!!
Ken Smith:
14327: 99/01/26: Re: Hysteresis on PLD Clock Inputs
34155: 01/08/15: Re: Building a clock out of a PLD
34173: 01/08/16: Re: Building a clock out of a PLD
34174: 01/08/16: Re: Building a clock out of a PLD
69112: 04/04/27: Re: Byteblaster Download cable schematics not available from altera site
74040: 04/10/02: Re: Floating Point Powers and Logs?
77745: 05/01/16: Re: What is the difference between ASIC and FPGA?.
81563: 05/03/27: Re: User I/O via Altera MAX7000S JTAG?
81614: 05/03/29: Re: User I/O via Altera MAX7000S JTAG?
88782: 05/08/28: Re: CPLD Jitter
88817: 05/08/29: Re: CPLD Jitter
95219: 06/01/21: Re: OT:Shooting Ourselves in the Foot
95224: 06/01/21: Re: OT:Shooting Ourselves in the Foot
95269: 06/01/21: Re: OT:Shooting Ourselves in the Foot
95355: 06/01/22: Re: OT:Shooting Ourselves in the Foot
95356: 06/01/22: Re: OT:Shooting Ourselves in the Foot
95556: 06/01/24: Re: OT:Shooting Ourselves in the Foot
99992: 06/04/01: Re: deglitching a clock
100016: 06/04/01: Re: deglitching a clock
Ken Soon:
116719: 07/03/16: How to use the DDR SDRAM instead of Block RAM?
116805: 07/03/19: Re: How to use the DDR SDRAM instead of Block RAM?
116852: 07/03/20: Re: How to use the DDR SDRAM instead of Block RAM?
117035: 07/03/22: Re: How to use the DDR SDRAM instead of Block RAM?
117094: 07/03/23: Re: How to use the DDR SDRAM instead of Block RAM?
117225: 07/03/27: Spartan 3E Not enough block ram.
117393: 07/03/30: Re: Spartan 3E Not enough block ram.
117550: 07/04/04: Re: Spartan 3E Not enough block ram.
117622: 07/04/05: Re: Spartan 3E Not enough block ram.
117823: 07/04/11: Re: Spartan 3E Not enough block ram.
117871: 07/04/12: Re: Spartan 3E Not enough block ram.
117908: 07/04/13: Re: Spartan 3E Not enough block ram.
118060: 07/04/17: Re: Spartan 3E Not enough block ram.
118329: 07/04/24: Re: Spartan 3E Not enough block ram.
118744: 07/05/03: Video scaler for Spartan 3E?
118745: 07/05/03: Re: Video scaler for Spartan 3E?
118819: 07/05/04: Re: Video scaler for Spartan 3E?
119077: 07/05/11: Re: Video scaler for Spartan 3E?
119279: 07/05/16: Re: Video scaler for Spartan 3E?
119337: 07/05/17: Re: Video scaler for Spartan 3E?
119339: 07/05/17: too brief documentation?
119409: 07/05/18: Re: Video scaler for Spartan 3E?
119414: 07/05/18: Re: Video scaler for Spartan 3E?
Ken Taylor:
53156: 03/03/05: Re: Issues in Outsourcing?
64478: 04/01/06: Re: 4-bit binary divider circuit PLEASE!!!!!!!
99987: 06/04/01: Re: Hierarchical FSM?
Ken Wood:
2568: 96/01/04: Re: Career value: VHDL or Verilog?
2569: 96/01/04: Re: Career value: VHDL or Verilog?
2595: 96/01/10: Re: Career value: VHDL or Verilog?
3007: 96/03/13: Re: Multiple FPGA Partitioning
Ken Yasui:
15887: 99/04/19: Re: How to write BIDIR IO in MAXPLUS2 VHDL ?
16141: 99/05/06: Re: Xilinx netlister - Workaround needed
16332: 99/05/17: Re: Xilinx demo board
17251: 99/07/15: Re: Xilinx On-Chip-Oscillator
Ken Yiu:
347: 94/10/26: Xilinx and mentor
631: 95/01/24: Xilinx Chips
659: 95/01/30: Re: Xilinx Chips
<Ken@he.net>:
Kendall Castor-Perry:
11637: 98/08/27: Re: New Evolutionary Electronics Book
kender:
76760: 04/12/10: PCI design with vhdl
kendor:
144409: 09/12/04: very wide counter (42-bit)
144467: 09/12/09: Re: very wide counter (42-bit)
Kenily:
37632: 01/12/18: is it OK?
37676: 01/12/18: Re: is it OK?
38003: 01/12/30: CRC-32 48bit(width)
38019: 01/12/31: Re: CRC-32 48bit(width)
38176: 02/01/08: multiply (*) 11000000000
Kening:
kenm:
112656: 06/11/27: Pullups and pulldowns in EDK?
112710: 06/11/27: Re: Pullups and pulldowns in EDK?
123174: 07/08/18: Re: Xilinx Constraints Question
140397: 09/05/12: Re: DSP + FPGA reference design?
Kenn Perry:
635: 95/01/24: Re: NeoCAD Experience
Kenneth:
36444: 01/11/09: How to set timing constraint in Xilinx VirtexII device when using DCM
36445: 01/11/09: Re: How to set timing constraint in Xilinx VirtexII device when using
38046: 02/01/03: Problem/Question about the timing report on Xilinx ISE 4.1
38075: 02/01/04: Re: Problem/Question about the timing report on Xilinx ISE 4.1
46075: 02/08/16: Phase shift in high frequency mode in VirtexII's DCM
46094: 02/08/19: Re: Phase shift in high frequency mode in VirtexII's DCM
46445: 02/08/30: Question on Fast CPLDs
46486: 02/09/01: Re: Question on Fast CPLDs
Kenneth A. Becker:
4186: 96/09/23: Re: manchester clock recovery
4389: 96/10/23: Re: VHDL for Xilinx designs?
Kenneth Alan Boyd Ramsay:
54641: 03/04/15: Slightly OT Re: Testing engineering ability prior to work?
Kenneth Casselman:
22541: 00/05/11: Re: EETools Topmax
Kenneth Currie:
17597: 99/08/12: Philips Semiconductors (NL) seeks digital designers
Kenneth Elmkjaer Larsen:
7915: 97/10/29: Re: Polynomial division tool for LFSR/MISR simulation
13941: 99/01/04: Re: Array Range Legal?
Kenneth Land:
59250: 03/08/13: Re: Nios Clock Frequency
59254: 03/08/13: Re: Nios Clock Frequency
60383: 03/09/11: Re: Xilinx-gdb Sources publicly available?
60519: 03/09/15: Re: USB transceiver for FPGA
60586: 03/09/16: Nios Quartus II Question...
60610: 03/09/17: Re: Nios Quartus II Question...
61081: 03/09/27: Re: Reducing Clock Speed
61082: 03/09/27: Re: NIOS and OCI
61248: 03/09/30: Re: USB 1.1/2.0 Implementation
61251: 03/09/30: Re: USB 1.1/2.0 Implementation
65896: 04/02/09: Re: Quartus II taking forever to compile
65937: 04/02/10: Re: Quartus II taking forever to compile
65972: 04/02/10: Custom Nios Results...
65989: 04/02/10: Re: Can Altera NIOS be synthesized on non-cyclone/stratix FPGAs?
65994: 04/02/10: Re: sdram controller problems
66102: 04/02/12: Re: How many PCB layers ?
66145: 04/02/12: Re: How many PCB layers ?
66190: 04/02/13: Re: How many PCB layers ?
66408: 04/02/18: Re: Source code for NIOS GNU toolchain
66443: 04/02/19: Re: Source code for NIOS GNU toolchain
66759: 04/02/26: Re: Stratix 2 ALUT architecture patented ?
66783: 04/02/26: Re: Stratix 2 ALUT architecture patented ?
66820: 04/02/26: Re: Stratix 2 ALUT architecture patented ?
66906: 04/02/29: Re: Need to speed up Stratix compiles.
66987: 04/03/02: Re: Need to speed up Stratix compiles.
66988: 04/03/02: Re: Need to speed up Stratix compiles.
67024: 04/03/03: Re: Need to speed up Stratix compiles.
67066: 04/03/04: Spec VPR Results for various processors...
67166: 04/03/07: Re: Spec VPR Results for various processors...
67260: 04/03/09: Re: copy protection on FPGA using embedded serial number
68342: 04/04/01: Can't do a single byte read in Nios?
68366: 04/04/02: Re: Can't do a single byte read in Nios?
68410: 04/04/03: Re: Can't do a single byte read in Nios?
68671: 04/04/13: Yet Another Altera Online Support Is USELESS Rant...
68690: 04/04/14: Re: Yet Another Altera Online Support Is USELESS Rant...
68697: 04/04/14: Re: Yet Another Altera Online Support Is USELESS Rant...
68916: 04/04/21: Re: NIOS: Run program from SDRAM
69325: 04/05/06: Mutiple Quartus Instances?
69350: 04/05/07: Re: Mutiple Quartus Instances?
69359: 04/05/07: SignalProbe in Quartus...
69543: 04/05/13: Re: Anyone who has worked with Altera Cyclone???
69546: 04/05/13: Re: EPCS4 Configuration+firmware, Quartus problem
69577: 04/05/14: Re: Quartus II Web Edition
69625: 04/05/16: Re: best fpga development board?
69725: 04/05/18: Nios II Going Live...
69748: 04/05/19: Re: Nios II Going Live...
69772: 04/05/19: Re: Nios II Going Live...
69816: 04/05/20: Re: Nios II Going Live...
69970: 04/05/25: Re: Nios II = Microblaze
69971: 04/05/25: Re: Nios II = Microblaze
70005: 04/05/26: Re: Nios II = Microblaze
70011: 04/05/26: Re: Nios II = Microblaze
70012: 04/05/26: Re: Economics of CPU softcores, was : Re: Nios II = Microblaze
70250: 04/06/10: Re: can't trap custom ITon NIOS
71290: 04/07/13: Re: Altera SOPC SDRAM & CLK Input?
71365: 04/07/15: Re: Nios reset behavior
71376: 04/07/16: Re: Nios reset behavior
71540: 04/07/21: Re: 32-channel PC-based logic analyzers
71585: 04/07/22: Re: 32-channel PC-based logic analyzers
72386: 04/08/17: Secret to SignalTapII Incremental Build?....
72446: 04/08/18: Re: Secret to SignalTapII Incremental Build?....
73851: 04/09/30: Re: [NIOS-II SOPC] SDRAM Read Burst Cycle Length ...
73929: 04/10/01: Re: Altera SDRAM controller - Only 2 words burst???
73969: 04/10/01: Re: Altera SDRAM controller - Only 2 words burst???
73644: 04/09/27: Re: Altera SDRAM controller - Only 2 words burst???
75088: 04/10/26: Re: PCBs for modern FPGAs.
74195: 04/10/05: Re: [NIOS-II SOPC] SDRAM Read Burst Cycle Length ...
74202: 04/10/05: Re: Altera SDRAM controller - Only 2 words burst???
74203: 04/10/05: Re: Altera SDRAM controller - Only 2 words burst???
74221: 04/10/06: Re: [NIOS-II SOPC] SDRAM Read Burst Cycle Length ...
74290: 04/10/07: Re: [NIOS-II SOPC] SDRAM Read Burst Cycle Length ...
74744: 04/10/18: Re: Open-Source MicroBlaze IP-Core working in FPGA :)
74745: 04/10/18: Re: NI*S II-verilog in Virtex FPGA
74838: 04/10/20: Anyone routing signals between balls in FBGA?
77214: 04/12/30: Re: Altera NIOS II/Stratix II vs Xilinx Products
77375: 05/01/05: Re: LEON2 or microblaze
78686: 05/02/05: Re: Altera's NIOS2 examples...
79174: 05/02/15: Any Altera FIFO not a power of 2?
79314: 05/02/17: Re: Any Altera FIFO not a power of 2?
79315: 05/02/17: Re: Any Altera FIFO not a power of 2?
79394: 05/02/18: Re: Is Altera Cyclone a good choice ?
79428: 05/02/18: Re: Altera support getting worse and worse......
79439: 05/02/18: Re: Nios performance
79443: 05/02/18: Re: Nios performance
79905: 05/02/25: Re: embedded 2005 in Nuernburg
79939: 05/02/26: Re: NiosII Vs MicroBlaze
Kenneth Le:
66386: 04/02/18: Leonardo Spectrum - preserve_signal attribute
Kenneth M. Mackenzie:
32161: 01/06/17: CFP: CASES 2001
Kenneth Porter:
20853: 00/02/24: Re: Required, 16 bit micro, with onchip protected eeprom/flash
23073: 00/06/13: Simple JTAG programmer for Altera MAX 7128A?
23298: 00/06/21: Re: Simple JTAG programmer for Altera MAX 7128A?
27746: 00/12/06: Re: ALTERA MAX PLUS LPM FIFOs
28298: 01/01/05: Re: HELP: Problem with interfacing an Altera MAX7000 device to the ISA bus
28303: 01/01/05: Re: HELP: Problem with interfacing an Altera MAX7000 device to the ISA bus
28418: 01/01/11: Re: Alliance for Linux
28450: 01/01/12: Re: Alliance for Linux
28500: 01/01/15: Re: Altera Jam player on SHARC
28505: 01/01/15: Re: Alliance for Linux - not a technical issue
Kenneth Prager:
18331: 99/10/15: Xilinx PCI Bridge
Kenneth Ryan:
56810: 03/06/16: Re: DVI with a Virtex-II
56817: 03/06/16: Re: DVI with a Virtex-II
Kenneth Seefried:
57119: 03/06/24: Re: MIPS instruction set?
Kenneth Sloan:
2108: 95/10/16: Re: Bet you can't do these....
Kenneth W. Wagner:
11409: 98/08/11: Combinatoric Divide-by-3 Algorithm
11538: 98/08/21: Re: Combinatoric Divide-by-3 Algorithm
<kenney@cix.compulink.co.uk>:
152591: 11/09/16: Re: The Manifest Destiny of Computer Architectures
<kennheinrich@sympatico.ca>:
130282: 08/03/19: Re: Optimizing an inferred counter
130353: 08/03/20: Re: Optimizing an inferred counter
130355: 08/03/20: Re: Optimizing an inferred counter
133963: 08/07/20: Re: ANNOUNCE: TimingAnalyzer version beta 0.87
133967: 08/07/20: Re: Change clock domain for FIFO ...
136086: 08/10/30: Re: ISE 9.2.03i problem
136097: 08/10/31: Re: ISE 9.2.03i problem
136113: 08/11/01: Re: ISE 9.2.03i problem
137956: 09/02/03: Re: FFT core has reversed output data
137963: 09/02/03: Re: FFT core has reversed output data
138001: 09/02/03: Re: FFT core has reversed output data
138202: 09/02/09: Re: Is this phase accumulator trick well-known???
138208: 09/02/09: Re: Is this phase accumulator trick well-known???
Kenny:
40398: 02/03/06: MXE 5.5e speed
40399: 02/03/06: How to create testbench (Verilog) easily ? Any tools ?
40458: 02/03/07: Ports disappear after generating post place and route simulation model
41152: 02/03/21: Where to get docs regarding WEP Encryption
Kenny Huang:
39010: 02/01/29: Re: Books on DSP
Kenny Ranerup:
8247: 97/12/03: Re: what is metastability time of a flip_flop
kenS:
148955: 10/09/15: Re: AES Bitstream Encryption in Virtex-4. How safe it is?
kensvebary:
151732: 11/05/12: DDR SDRAM Configuration problem on XUPV2P
Kent:
5839: 97/03/20: Is this really possible?
Kent Dahlgren:
177: 94/09/09: Re: I Cube FPIDs
Kent Dickey:
67494: 04/03/12: Re: Does XST handles //synopsys parallel_case?
Kent Krumvieda:
42131: 02/04/16: GPGA GPS Cores
42165: 02/04/17: VHDL or Verilog SW to implement GPS receiver on FPGA
43978: 02/06/07: Help!!! Stack SW versus Applications SW
Kent Lewis:
7739: 97/10/09: Praegitzer Industries Inc.'s Technical Symposium '97
Kent Orthner:
26127: 00/10/05: Re: Boundary Scan and LVDS in Virtex E
26129: 00/10/05: Re: Xilinx Licensing.
26246: 00/10/10: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
26252: 00/10/10: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
26324: 00/10/12: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
26430: 00/10/16: Re: Xilinx and CD databooks (rant)
26436: 00/10/16: Re: 5V compatible Virtex
26460: 00/10/17: Re: 5V compatible Virtex
26461: 00/10/17: Re: Xilinx and CD databooks (rant)
26462: 00/10/17: Re: ordered list
26468: 00/10/17: Re: 5V compatible Virtex
26480: 00/10/18: Re: VHDL vs Verilog
26489: 00/10/18: Re: Q: Xilinx unified libraries and synthesis
26520: 00/10/19: Re: Off subjuct, VHDL question
27565: 00/11/29: Re: Fifo design problem
27566: 00/11/29: Wide AND function.
27572: 00/11/29: Re: Wide AND function.
27769: 00/12/07: Re: FPGA Express & VHDL files
27789: 00/12/08: Spartan-II & Vertex Pin compatability.
27827: 00/12/11: Re: Cannot get chip's information from Synopsys
27860: 00/12/13: Re: Synplify PRO 6.1 + Foundation 3.1i
27861: 00/12/13: Re: TWo CLOKS in VHDL synthesis
27863: 00/12/13: Re: TWo CLOKS in VHDL synthesis
27897: 00/12/14: Re: Dual-ported RAM instantiation in Virtex-E ?
27959: 00/12/18: Re: ActiveHDL 4.1?
28048: 00/12/20: Re: 3V -> 5V clock signal level conversion
28058: 00/12/20: Re: Methods to speed up timings by hdl?
28428: 01/01/12: Re: grey code counters
29271: 01/02/12: Re: Wired-or on Virtex FPGAs
29337: 01/02/15: Re: Integrated Conf.EPROM / smaller Footprints?
29381: 01/02/17: Re: Configuration of FPGA using SPROM
29382: 01/02/17: Re: Alpha Job Consulting News
29408: 01/02/20: 5 Clocks in a spartan-II
29410: 01/02/20: Re: meeting high hold time input requirement with Virtex
29425: 01/02/21: Re: 5 Clocks in a spartan-II
29452: 01/02/22: Re: Integrated Conf.EPROM / smaller Footprints?
29482: 01/02/23: Re: Partial reconfig
29775: 01/03/09: Re: More detailed Spartan II CLB drawings?
30026: 01/03/21: Looking for Skew information
30098: 01/03/23: Re: Looking for Processor Core info/advice
30148: 01/03/26: Re: No inputs on XC9536XL
30172: 01/03/27: Re: Alternatives for Xilinx Spartan-II configuration PROM
30231: 01/03/29: Re: VHDL question
30232: 01/03/29: Re: VHDL question
30326: 01/04/03: Re: pinout in text format for Virtex-E XCV200E
30513: 01/04/12: Re: Changing Xilinx ROM contents without recompiling
30552: 01/04/16: Re: Is there any free processor core for vertex series?
31075: 01/05/11: Re: Waveforms painting
31329: 01/05/19: Re: Xilinx Service Pack 8 Now Available
31400: 01/05/22: Re: xilinx webpack problem
31439: 01/05/24: Re: xilinx webpack problem
31488: 01/05/28: Re: xilinx webpack warning !!
31489: 01/05/28: Re: free simulator
31490: 01/05/28: Re: Internal tri states
31494: 01/05/28: Fun with DLLs.
31552: 01/05/30: Re: Fun with DLLs.
31553: 01/05/30: Re: Peripheral for Microcontroller
31558: 01/05/30: Re: Fun with DLLs.
31566: 01/05/30: Re: Help with vhd
31586: 01/05/31: Re: Fun with DLLs.
31588: 01/05/31: PAD to PAD Timing Constraints. (Xilinx)
31595: 01/05/31: Re: [Q]setup-time violation
31602: 01/05/31: Re: Help with vhd
31697: 01/06/03: Re: Virtex LUT4 problems in FPGA Express
31736: 01/06/05: Re: one state machine
31737: 01/06/05: Re: Virtex LUT4 problems in FPGA Express
31786: 01/06/06: Re: Virtex LUT4 problems in FPGA Express
Kent Ross:
62721: 03/11/05: Programmer's unpaid overtime.
<kent.mou@gmail.com>:
98114: 06/03/05: Par error in Spartan-3
98146: 06/03/06: Re: Par error in Spartan-3
<kent@infoserv.com>:
625: 95/01/21: Re: ViewLogic simulation without master reset
626: 95/01/21: Re: ViewLogic simulation without master reset
1778: 95/08/31: VHDL Savy editors under UNIX?
1896: 95/09/17: Editors that understand VHDL under UNIX
kenton:
92702: 05/12/05: Use EMC to control a FIFO ?
kephart:
2627: 96/01/13: Re: [q][Reverse Engineering Protection]
2635: 96/01/16: Re: [q][Reverse Engineering Protection]
2644: 96/01/18: Re: [q][Reverse Engineering Protection]
Keren:
18050: 99/09/26: Looking for substitute for XC17*** Xilinx Prom
18080: 99/09/28: Re: Looking for substitute for XC17*** Xilinx Prom
kero:
54031: 03/04/01: Re: ModelSIM XE wave files
Kerri Golden:
42116: 02/04/16: Re: problems with Nios 2.0
42117: 02/04/16: Re: problems with Nios 2.0
51209: 03/01/06: Re: Altera SOPC Builder 2.61 problems ...
51225: 03/01/07: Re: Altera SOPC Builder 2.61 problems ...
Kerry Imming:
154573: 12/11/29: Re: VHDL expert puzzle
154578: 12/11/29: Re: VHDL expert puzzle
Kerry Veenstra:
415: 94/11/11: Re: Anyone have Altera library for Orcad?
467: 94/11/26: Re: Should I jump to Actel when using Synopsys/Altera?
<kerry@altera.comKerryVeenstra>:
190: 94/09/16: Re: Looking for Altera's FTP site
Ketan:
57735: 03/07/04: division
Ketan Poladia:
4548: 96/11/13: EDIF to BLIF format conversion.
4577: 96/11/16: EDIF to BLIF
Ketil Malde:
46603: 02/09/04: Re: Hardware Code Morphing?
Ketil Z Malde:
19788: 00/01/12: Re: HW resources increased
19814: 00/01/13: Re: HW resources increased
Kev:
72113: 04/08/09: Spartan Software
Kevin:
29248: 01/02/10: Re: double precision floating point arithmetic
109096: 06/09/20: Re: Lattice .bit file format
109180: 06/09/21: Re: Lattice .bit file format
110629: 06/10/18: Re: echo $LM_LICENCE_FILE not working
113140: 06/12/06: Re: Digitally Controlled Impedance with Lattice ECP2M FPGA's
123355: 07/08/24: hwicap for EDK 9.1
kevin:
4097: 96/09/10: asic,fpga professional assoc.
76452: 04/12/02: how to start with development of eda tools
76466: 04/12/03: Re: how to start with development of eda tools
76496: 04/12/04: Re: how to start with development of eda tools
Kevin Aylward:
25671: 00/09/17: Re: hardware compatibility and patent infringement
25867: 00/09/23: Re: hardware compatibility and patent infringement
52923: 03/02/26: Re: VLSI outsourcing?
156508: 14/04/13: Re: on-chip bypass caps
Kevin Becker:
50732: 02/12/18: Display "real" waves in simulation?
52436: 03/02/09: Signal delays
62754: 03/11/06: Arithmetics with carry
62796: 03/11/07: Re: Arithmetics with carry
62823: 03/11/08: Re: Arithmetics with carry -- got it :-)
75068: 04/10/25: Altium board again
Kevin Bowling:
160470: 18/01/27: Re: Now - not so new cheaper FPGAs
160511: 18/03/07: Lattice or Microsemi?
Kevin Brace:
33936: 01/08/08: Re: PCI Postcode Display
34180: 01/08/15: Re: Slowing PCI for FPGA
34263: 01/08/17: Re: PCI Postcode Display
34452: 01/08/24: Re: PCI Postcode Display
34521: 01/08/28: Re: PCI Postcode Display
34668: 01/09/02: Re: WebPack Con-Game
34874: 01/09/12: Re: WebPack Con-Game
34920: 01/09/13: Re: ISE 4.1
34921: 01/09/13: Re: ISE 4.1
34958: 01/09/16: Re: configuration latency for PCI bridge in FPGA
35249: 01/09/26: Re: Spartan-IIE?
35616: 01/10/11: Re: I need free PCI-Core (vhdl)!!
35676: 01/10/12: Re: I need free PCI-Core (vhdl)!!
35735: 01/10/15: Re: I need free PCI-Core (vhdl)!!
35866: 01/10/21: Re: Verilog vs. VHDL
35897: 01/10/22: Re: Verilog vs. VHDL
35898: 01/10/22: Re: Verilog vs. VHDL
36039: 01/10/26: Cloning someone else's IP core
36067: 01/10/27: Re: Cloning someone else's IP core
36103: 01/10/29: Re: Cloning someone else's IP core
36176: 01/10/31: Re: Cloning someone else's IP core
36178: 01/10/31: Re: Cloning someone else's IP core
36179: 01/10/31: Re: Cloning someone else's IP core
36180: 01/10/31: LeonardoSpectrum-Altera stability
36251: 01/11/03: Re: 64-bit PCI core for Lattice CPLD?
36258: 01/11/04: Re: Altera download problem
36271: 01/11/04: Re: How dense are FPGA/CPLD's
36274: 01/11/04: Xilinx Floorplanner Effectiveness
36275: 01/11/04: Is There a Xilinx Floorplanner Tutorial?
36337: 01/11/06: Re: Xilinx Floorplanner Effectiveness
36340: 01/11/06: Re: Xilinx Floorplanner Effectiveness
36358: 01/11/07: Re: XST synthesis
36377: 01/11/07: Re: How dense are FPGA/CPLD's
36537: 01/11/11: What is the optimal number of fanouts?
36818: 01/11/20: Re: I need a Xilinx Spartan PCI Development Board
37220: 01/12/03: How to increase clock skew for Spartan-II
37323: 01/12/06: Re: I need a Xilinx Spartan PCI Development Board
37324: 01/12/06: Re: Has anyone successfully used opencores PCI?
37325: 01/12/06: Re: Webpack Version 3: Exit with error code 0002
37327: 01/12/06: Re: URL for ordering Xilinx ise webpack 4.1i cdrom
37328: 01/12/06: Re: How to increase clock skew for Spartan-II
37329: 01/12/06: Re: How to increase clock skew for Spartan-II
37385: 01/12/09: Re: I need a Xilinx Spartan PCI Development Board
37398: 01/12/09: Re: PCI card - 2 layers versus four layers
37588: 01/12/16: How can I reduce Spartan-II routing delays to meet 33MHz PCI's Tsu < 7 ns?
37589: 01/12/16: Re: FPGA-Conversion. IP Cores
37677: 01/12/18: How can I reduce Spartan-II routing delays to meet 33MHz PCI's Tsu < 7 ns requirement?
37678: 01/12/18: Re: FPGA-Conversion. IP Cores
37690: 01/12/18: How can I reduce Spartan-II routing delays to meet 33MHz PCI's Tsu < 7
37691: 01/12/18: Re: FPGA-Conversion. IP Cores
37692: 01/12/18: Google Groups problems?
38002: 01/12/30: Re: ALTERA's Mercury CDR
38017: 01/12/31: Re: Stupid Foundation Question (Hey Peter, some Kindergarden stuff for
38018: 01/12/31: Re: instruction processor
38061: 02/01/03: Re: Virtex-2 maximum clock speed
38076: 02/01/04: Re: PCI Solution: LogiCore?
38080: 02/01/04: Re: Spartan-IIE interfacing issues
38116: 02/01/06: Re: Q:where can I find an indepth manual about P&R in Quartus II ?
38118: 02/01/06: Re: FLOORPLANNING IN XILINX
38119: 02/01/06: Re: floorplanning
38191: 02/01/08: Repost: Should clock skew be included for setup time analysis?
38230: 02/01/09: Re: Repost: Should clock skew be included for setup time analysis?
38326: 02/01/11: How to constrain the inputs of a multi-level parity generator and
38444: 02/01/14: Re: How to constrain the inputs of a multi-level parity generator and
38800: 02/01/25: Re: [Spartan-II] Fastest Possibel Output Enable Time for -5 Devices ??
38808: 02/01/25: Re: Does Xilinx Spartan-II have reserved pin for PCI?
38810: 02/01/25: Re: [Spartan-II] Fastest Possibel Output Enable Time for -5 Devices ??
38811: 02/01/25: Re: Xilinx webpack
38812: 02/01/25: Re: Pin assignment on ACEX1K
38813: 02/01/25: Re: Synthsis Tools for Xilinx
38820: 02/01/25: Re: Xilinx PCI logicore: clarification on nature of COMPLETE
38829: 02/01/26: Re: Synthsis Tools for Xilinx
38830: 02/01/26: Re: Get error that part is invalid or not supported when Run from
38848: 02/01/26: Re: Does Xilinx Spartan-II have reserved pin for PCI?
38851: 02/01/26: Re: Synthesis Tools for Xilinx
38863: 02/01/26: Re: Xilinx webpack
38894: 02/01/28: Re: Xilinx webpack
38898: 02/01/28: Re: Xilinx PCI logicore: clarification on nature of COMPLETE
38942: 02/01/28: Re: Pin assignment on ACEX1K
39014: 02/01/29: Re: Flex10KA vs MAX7000S
39015: 02/01/29: Re: Pin assignment on ACEX1K
39016: 02/01/30: Re: Pin assignment on ACEX1K
39060: 02/01/30: Re: Flex10KA vs MAX7000S
39124: 02/02/01: Re: Leonardo=>MaxPlus/Quartus Vs Synopsys=>MaxPlus/Quartus
39591: 02/02/13: What do the Spartan-II Global Clock delay binary values for 66MHz PCI
39605: 02/02/14: Re: Spartan-II becomes Vertex.
39631: 02/02/14: Re: Spartan-II becomes Vertex.
39633: 02/02/14: Re: Modelsim questions
39634: 02/02/14: Re: Spartan-II becomes Vertex.
39709: 02/02/16: Re: Speaking of ORCA...
39710: 02/02/16: Re: FPGA choices and questions
39833: 02/02/20: Re: Need good PCI book
39834: 02/02/20: Re: PCI/FPGA evaluation board
39835: 02/02/20: Re: PCI/FPGA evaluation board
39837: 02/02/20: Re: PCI/FPGA evaluation board
39897: 02/02/21: How can I do a Verilog/VHDL mixed language design in ISE WebPACK 4.1
39972: 02/02/22: Re: Need good PCI book
39973: 02/02/22: Re: Need largest CPLD devices?
39974: 02/02/22: Re: CPLD PROJECT
39975: 02/02/22: Re: CPLD PROJECT
40013: 02/02/25: Is it possible to have an output FF in IOB, but a tri-state control FF
40053: 02/02/25: Re: Is it possible to have an output FF in IOB, but a tri-state control
40054: 02/02/25: Re: Is it possible to have an output FF in IOB, but a tri-state control
40153: 02/02/28: Re: PCI book ... still confused
40207: 02/03/01: Re: PCI book ... still confused
40231: 02/03/02: Re: turnaround cycle?
40255: 02/03/03: Re: turnaround cycle?
40256: 02/03/03: Re: Xilinx MXE 5.5 v.s. ModelSim PE for Xilinx Spartan II only
40259: 02/03/04: Has anyone got Quartus II 2.0/LeonardoSpectrum-Altera NativeLink to work
40342: 02/03/05: Re: Has anyone got Quartus II 2.0/LeonardoSpectrum-Altera NativeLink to
40348: 02/03/05: Quartus II 2.0 fast fit option
40362: 02/03/05: Re: Quartus II 2.0 fast fit option
40415: 02/03/06: Re: QPRO Virtex
40479: 02/03/07: Re: Quartus II 2.0 fast fit option
40480: 02/03/07: Re: Quartus II 2.0 fast fit option
40684: 02/03/12: How do I infer a carry-chain parity generator in XST?
40692: 02/03/12: Re: How do I infer a carry-chain parity generator in XST?
40720: 02/03/13: Is XST's Keep Hierarchy option broken?
40721: 02/03/13: XST duplicates unnecessary IOB OE FFs
40723: 02/03/13: Re: nOOb: wants to start using an fpga
40760: 02/03/14: Re: XST duplicates unnecessary IOB OE FFs
40803: 02/03/15: Re: PCI design in a Spartan II which crashes in some wintel PCs
40807: 02/03/15: Re: PCI design in a Spartan II which crashes in some wintel PCs
40815: 02/03/15: Re: PCI design in a Spartan II which crashes in some wintel PCs
40849: 02/03/16: Re: XST duplicates unnecessary IOB OE FFs
40855: 02/03/16: Re: Reply to Kevin
40858: 02/03/16: Re: To Falk Brunner
40911: 02/03/18: How do I simulate two separate designs simutaneously in ModelSim XE?
40944: 02/03/18: Re: How do I simulate two separate designs simutaneously in ModelSim XE?
40945: 02/03/18: Re: How do I simulate two separate designs simutaneously in ModelSim XE?
40948: 02/03/18: Re: How do I simulate two separate designs simutaneously in ModelSim XE?
40949: 02/03/18: Re: High speed clock routing
40950: 02/03/18: Re: How do I simulate two separate designs simutaneously in ModelSim
40951: 02/03/18: Re: [Virtex 2] DCM: "Factory_JF" option box in FPGA editor question
40952: 02/03/18: Re: How do I simulate two separate designs simutaneously in ModelSim XE?
40964: 02/03/19: Re: XST duplicates unnecessary IOB OE FFs
41017: 02/03/19: Re: A petition for Synplify's new fature (FPGA synthesis tool)
41039: 02/03/20: Re: simple Free FPGA tool
41040: 02/03/20: Re: simple Free FPGA tool
41043: 02/03/20: Re: A petition for Synplify's new fature (FPGA synthesis tool)
41081: 02/03/20: Re: low cost PCI spartan board needed
41085: 02/03/20: Re: low cost PCI spartan board needed
41113: 02/03/21: Re: A petition for Synplify's new fature (FPGA synthesis tool)
41150: 02/03/21: Re: more questions
41151: 02/03/21: Re: synplify, quartus II 2.0
41153: 02/03/21: Re: more questions
41215: 02/03/22: Re: simple Free FPGA tool
41266: 02/03/23: Re: QuartusII 2.0!!!!!
41329: 02/03/26: Re: Using GCLK1 as Input on Spartan II under Foundation 4.1
41331: 02/03/26: How to activate 5V PCI I/O pads in FLEX10KE/ACEX1K?
41337: 02/03/26: FLEX10KE/ACEX1K IOE Packing Rules
41390: 02/03/27: Re: simple Free FPGA tool
41423: 02/03/27: Re: XST duplicates unnecessary IOB OE FFs
41427: 02/03/27: Re: FPGA config without boot PROM???
41448: 02/03/28: Unrecognized LUTs Inserted in A FLEX10KE/ACEX1K Design
41464: 02/03/29: Unusually Large Routing Delay From a FF To a Pin in FLEX10KE
41465: 02/03/29: Re: FPGA config without boot PROM???
41497: 02/03/30: Re: PCI Compliance..
41498: 02/03/30: Re: powerpc in virtex2pro
41546: 02/04/01: Re: Laying out the design
41575: 02/04/02: Re: How to activate 5V PCI I/O pads in FLEX10KE/ACEX1K?
41579: 02/04/02: Re: Laying out the design
41590: 02/04/02: Re: Marquis of Queensbury Rules
41637: 02/04/04: Does anyone know how bitgen's /Gclkdel option works?
41664: 02/04/04: Re: hand placement
41675: 02/04/04: Re: powerpc in virtex2pro
41685: 02/04/04: Re: hand placement
41686: 02/04/04: Re: hand placement
41689: 02/04/04: Re: hand placement
41696: 02/04/04: Re: hand placement
41698: 02/04/05: Re: Marquis of Queensbury Rules
41718: 02/04/05: Re: hand placement
41719: 02/04/05: Re: hand placement
41729: 02/04/05: Re: 32 bit accumulator/comparator PWM?
41738: 02/04/06: Re: 32 bit accumulator/comparator PWM?
41767: 02/04/07: Re: Xilinx programmer
41779: 02/04/08: Re: hand placement
41782: 02/04/08: Re: hand placement
41784: 02/04/08: Re: Xilinx 4.2i not working on my design
41785: 02/04/08: Re: Xilinx programmer
41787: 02/04/08: Re: Modelsim-XE fails when simulating a VHDL model.
41801: 02/04/08: Re: Modelsim from Altera vs Modelsim from Menthors
41802: 02/04/08: Re: XST Synthesis tool
41815: 02/04/08: Re: Xilinx programmer
41825: 02/04/08: Re: bad experience with Xilinx ISE 4.1i and Xilinx hotline suppot
41827: 02/04/08: Re: Low-cost FPGA + processor board?
41833: 02/04/08: Re: Xilinx Prototype Platforms
41838: 02/04/08: Re: Xilinx Prototype Platforms
41841: 02/04/08: Re: Low-cost FPGA + processor board?
41845: 02/04/08: Re: bad experience with Xilinx ISE 4.1i and Xilinx hotline suppot
41904: 02/04/10: Re: Low-cost FPGA + processor board?
41906: 02/04/10: Re: Xilinx programmer
41911: 02/04/10: Re: hand placement
41912: 02/04/10: Re: Webpack XST broken
41955: 02/04/11: Re: Low-cost FPGA + processor board?
41957: 02/04/11: Re: Insight service and PCI demo board question
41963: 02/04/11: Re: Insight service and PCI demo board question
41968: 02/04/11: Re: prototyping an ASIC
41973: 02/04/11: Re: prototyping an ASIC
41980: 02/04/12: Re: PCI Bridge Question
42006: 02/04/12: Re: Laying out the design
42007: 02/04/12: Re: Marquis of Queensbury Rules
42009: 02/04/12: Re: PCI Bridge Question
42044: 02/04/13: Re: webpack ISE
42045: 02/04/13: Re: PCI Bridge Question
42047: 02/04/13: Re: new to fpga's need insight
42058: 02/04/14: Re: Odd problem shows on post XST/translate simulation
42060: 02/04/14: Re: FPGA config without boot PROM???
42098: 02/04/15: Re: Looking for SpartanXL demo board
42100: 02/04/15: Re: why does my counter pause while its enable signal is still active?
42139: 02/04/16: Re: IO Standards supported in Spartan-II devices
42140: 02/04/16: A problem with PAR in ISE WebPACK 4.2
42261: 02/04/19: Re: Update -- Need help with Insight Spartan II demo board and the
42334: 02/04/20: Re: 4.2 Webpack error
42355: 02/04/21: Re: Some Questions about Pci configuration.
42359: 02/04/22: Is the following Spartan-II FG456 package LogiCORE PCI pinout correct?
42360: 02/04/22: Wanted: Standard LogiCORE PCI pinout of various Xilinx FPGAs
42395: 02/04/22: Re: Trouble assigning tri-stated output buffers in Spartan2 w/Foundation
42400: 02/04/22: Re: Is the following Spartan-II FG456 package LogiCORE PCI pinout
42440: 02/04/24: Re: Reasonably Priced Development Software ??
42470: 02/04/24: Re: virtex package
42471: 02/04/24: Re: SpartanII design considerations...
42509: 02/04/25: Re: Using 74HCT245N between Spartan-II and ISA
42543: 02/04/26: Re: webpack : how to generate a .sdf and .vhd for simulation
42576: 02/04/27: Re: SpartanII design considerations...
42603: 02/04/29: Re: SpartanII design considerations...
42606: 02/04/29: Re: Does Vertex II PRO Really work?
42641: 02/04/29: Re: Loading values in Quartus II Waveform editor
42723: 02/05/01: Duplicating IOB FFs Without I/O Pads Being Inserted in XST
42733: 02/05/01: Re: Duplicating IOB FFs Without I/O Pads Being Inserted in XST
42736: 02/05/01: Re: SpartanII design considerations...
42745: 02/05/01: Re: Vertex 2 IOB- unwanted flops inside
42785: 02/05/02: Re: SpartanII design considerations...
42802: 02/05/02: Re: Duplicating IOB FFs Without I/O Pads Being Inserted in XST
42804: 02/05/02: How can I get rid of I/O pads from a netlist generated by XST?
42899: 02/05/06: Re: PCI-32/Spartan II Pin Outs?
42900: 02/05/06: Re: PCI-32/Spartan II Pin Outs?
42916: 02/05/07: Re: Opinions on FPGA cores - best for a commercial project?
42917: 02/05/07: Re: Opinions on FPGA cores - best for a commercial project?
42942: 02/05/08: Re: State machine synthesis
42970: 02/05/08: Re: bug in XST ?
42976: 02/05/08: Does an EDIF schematic editor exist?
43022: 02/05/09: Re: Have you designed a PCI/Ethernet Adapter using a HDL?
43023: 02/05/09: Re: Eliminating Hierarchy in Xilinx XST
43025: 02/05/09: Re: PCI bus software for Xilinx PCI core
43034: 02/05/09: Re: Duplicating IOB FFs Without I/O Pads Being Inserted in XST
43036: 02/05/09: Re: Duplicating IOB FFs Without I/O Pads Being Inserted in XST
43073: 02/05/12: Re: Eliminating Hierarchy in Xilinx XST
43177: 02/05/15: Re: Eliminating Hierarchy in Xilinx XST
43180: 02/05/15: Re: Duplicating IOB FFs Without I/O Pads Being Inserted in XST
43181: 02/05/15: Re: PCI Board Project
43272: 02/05/17: Re: PCI Board Project
43273: 02/05/17: Re: PCI target with FPGA question
43315: 02/05/18: Re: Duplicating IOB FFs Without I/O Pads Being Inserted in XST
43318: 02/05/18: Re: Anyody else get spam about "FPGA Video Seminar"?
43323: 02/05/18: Re: Duplicating IOB FFs Without I/O Pads Being Inserted in XST
43333: 02/05/19: Re: Duplicating IOB FFs Without I/O Pads Being Inserted in XST
43344: 02/05/19: Re: PCI Board Project
43449: 02/05/21: Re: PCI Board Project
43459: 02/05/21: XST since ISE 4.x can actually generate an EDIF netlist!!!
43465: 02/05/21: Re: XST since ISE 4.x can actually generate an EDIF netlist!!!
43471: 02/05/21: Re: XST since ISE 4.x can actually generate an EDIF netlist!!!
43600: 02/05/26: How can I create an encrypted netlist for Altera?
43627: 02/05/28: Re: How can I create an encrypted netlist for Altera?
43877: 02/06/05: Re: How can I create an encrypted netlist for Altera?
43945: 02/06/06: Re: Quartus v/s Leonardo
43998: 02/06/08: Re: Xilinx ISE BaseX... What is it?
44225: 02/06/14: Can someone who is not a student use Xilinx Foundation 2.1i Student
44279: 02/06/15: Re: Can someone who is not a student use Xilinx Foundation 2.1i Student
44289: 02/06/16: Re: Xilinx ISE BaseX... What is it?
44290: 02/06/16: Re: Xilinx ISE BaseX... What is it?
44291: 02/06/16: Re: Xilinx ISE BaseX... What is it?
44315: 02/06/17: Re: Xilinx ISE BaseX... What is it?
44316: 02/06/17: Re: Which Synthesis tool for XILINX
44380: 02/06/18: Re: Xilinx ISE BaseX... What is it?
44381: 02/06/18: Re: Which Synthesis tool for XILINX
44391: 02/06/19: Re: 12 years experience in Digital HW/ FPGA design, looking for job in
44440: 02/06/20: Re: Xilinx ISE BaseX... What is it?
44467: 02/06/20: Re: How to generate a valid EDIF netlist?
44521: 02/06/22: Re: How to generate a valid EDIF netlist?
44611: 02/06/24: Re: Xilinx's 4.1i's Lastest webpack
44615: 02/06/24: Re: Xilinx's 4.1i's Lastest webpack
44655: 02/06/25: Re: How to generate a valid EDIF netlist?
44768: 02/06/29: Re: Xilinx's 4.1i's Lastest webpack
44771: 02/06/30: How can I preserve FFs in LeonardoSpectrum?
44787: 02/07/01: Re: How can I preserve FFs in LeonardoSpectrum?
44836: 02/07/02: Re: Converting to Altera Quartus
44837: 02/07/02: Re: Xilinx's 4.1i's Lastest webpack
44854: 02/07/02: Re: altera 10K30A synthesis
44856: 02/07/03: Re: Converting to Altera Quartus
44858: 02/07/03: Re: Xilinx's 4.1i's Lastest webpack
44859: 02/07/03: Re: Converting to Altera Quartus
44862: 02/07/03: Re: Converting to Altera Quartus
44897: 02/07/04: Re: How can I preserve FFs in LeonardoSpectrum?
44898: 02/07/04: Re: How can I preserve FFs in LeonardoSpectrum?
44927: 02/07/06: Re: Converting to Altera Quartus
44936: 02/07/06: Re: Converting to Altera Quartus
44937: 02/07/06: Re: Converting to Altera Quartus
44969: 02/07/08: Re: Newbie FPGA recommedation
44985: 02/07/08: Re: ISE 4.2i : Clock Buffer Disable
44986: 02/07/08: Re: How can I preserve FFs in LeonardoSpectrum?
45010: 02/07/09: Re: EDIF and JHDL information
45037: 02/07/10: Re: XST and Bidirectional I/O ports
45059: 02/07/11: Re: Bi-Directional Bus problem in Xilinx FPGA
45060: 02/07/11: Re: Xilinix or Altera - which dev-board?
45061: 02/07/11: Re: anyone get email about www.cradle.com ???
45176: 02/07/14: Re: EDIF netlist from XST
45207: 02/07/16: Re: How to add BUFG to an internal signal?
45224: 02/07/16: Re: I want to buy 4 Xilinx FPGA
45263: 02/07/17: Re: I want to buy 4 Xilinx FPGA
45311: 02/07/18: Re: Getting started with WebPACK and Verilog
45313: 02/07/18: Re: Problem with OpenCore PCI IP Core
45343: 02/07/19: Re: Theft protection of FPGA configuration data
45344: 02/07/19: Re: Making my own software
45347: 02/07/19: Re: Theft protection of FPGA configuration data
45348: 02/07/19: Re: I want to buy 4 Xilinx FPGA
45471: 02/07/24: Re: I want to buy 4 Xilinx FPGA
45474: 02/07/24: Re: 32-bit PCI Target core
45476: 02/07/24: Re: FPGA prototyping boards
45482: 02/07/24: Re: Translate the design from FPGA to Custom IC
45485: 02/07/24: Re: Editing constraints in WebPack
45489: 02/07/24: Re: CoreGen question of the new FFT core
45546: 02/07/25: Re: logic elements v/s logic cells
45548: 02/07/25: Re: hold time
45549: 02/07/25: Re: Xilinx ISE 4.2i Is A Step Backwards! Beware!!!
45552: 02/07/26: Re: Problem with mapping
45553: 02/07/26: Re: Problem with mapping
45566: 02/07/26: Re: Problem with mapping
45735: 02/08/02: Re: PCI Interrupt latency
45779: 02/08/05: Re: modelsim XE starter
45818: 02/08/06: Re: New XILINX ISE not supporting 4000 series FPGAs?
45859: 02/08/07: Re: Programming bits reverse engineering
45860: 02/08/07: Re: Is it necessary to instantiate IPAD, OPAD, IBUF, OBUF...?
45861: 02/08/07: Re: I want to bay 4 Xilinx FPGA
45952: 02/08/12: Re: ModelSim takes forever
45954: 02/08/12: Re: ModelSim takes forever
46034: 02/08/15: Re: Xilinx tools: which one? Esp. schematic
46129: 02/08/19: Re: xilinx pci troubles with flakey host initiator
46165: 02/08/20: Re: Resume: HW Verification Consultant (Specman)
46197: 02/08/21: Re: Academics vs 'real' FPGA use
46354: 02/08/26: Re: Anyone already on QUARTUS II V2.1 ?
46356: 02/08/26: Re: Floorplanning 101
46362: 02/08/27: Re: Anyone already on QUARTUS II V2.1 ?
46648: 02/09/04: Re: What's wrong with clearLogic?
46649: 02/09/04: Re: QUARTUS II V2.1 LINUX (C) ALTERA
46653: 02/09/04: Re: Viewing Xilinx netlist
46654: 02/09/04: Re: QUARTUS II V2.1 LINUX (C) ALTERA
46657: 02/09/04: Re: What's wrong with clearLogic?
46672: 02/09/05: Re: QUARTUS II V2.1 LINUX (C) ALTERA
46674: 02/09/05: Re: xilinx PCI prototype board
46680: 02/09/05: Re: Actel Libero
46774: 02/09/08: Re: Viewing Xilinx netlist
46918: 02/09/11: Re: Clocking an FPGA with the PCI clock
46919: 02/09/11: Re: Clocking an FPGA with the PCI clock
46920: 02/09/11: Re: Quartus 2 flow
46955: 02/09/12: Re: QUARTUS II V2.1 LINUX (C) ALTERA
46956: 02/09/12: Re: QUARTUS II V2.1 LINUX (C) ALTERA
47258: 02/09/21: Re: Cheap development package for beginner?
47927: 02/10/07: Re: Xilinx XST VHDL Compiler does not pack Registers in IOB
47967: 02/10/08: Re: Xilinx XST VHDL Compiler does not pack Registers in IOB
47969: 02/10/08: Has anyone noticed that messages posted through Mailgate.org aren't reaching this newsgroup?
47974: 02/10/08: Re: Why can't Altera sw be as good as Xilinx's sw?
48100: 02/10/10: Re: Why can't Altera sw be as good as Xilinx's sw?
48101: 02/10/10: Re: Has anyone noticed that messages posted through Mailgate.org aren't
48132: 02/10/11: Re: Simple PCI target core in XILINX Spartan2
48220: 02/10/14: Re: Simple PCI target core in XILINX Spartan2
48475: 02/10/18: Re: How assingment of IOE by Quratus Ver2.1
48476: 02/10/17: Re: Can I implement a PCI Master in a ACEX EP1k30-3 FPGA?
48477: 02/10/17: Re: PCB Design for Altera FPGA
48554: 02/10/20: Re: 32-bit PCI Target core
48944: 02/10/27: Re: How to interpret Xilinx synthesis report
49817: 02/11/21: Re: Simple PCI target core in XILINX Spartan2
50031: 02/11/28: Re: Spartan-II 2S200 PCI Board
50060: 02/11/30: Re: SDRAM technology
50061: 02/11/30: Re: Spartan-II 2S200 PCI Board
50062: 02/11/30: Re: Spartan-II 2S200 PCI Board
50063: 02/11/30: Re: Spartan-II 2S200 PCI Board
50127: 02/12/03: Re: Spartan-II 2S200 PCI Board
50153: 02/12/03: Re: free software for XC4000
50162: 02/12/03: Re: free software for XC4000
50388: 02/12/10: Re: FPGA/PCI on low budget
50390: 02/12/10: Re: FPGA/PCI on low budget
50437: 02/12/10: Re: FPGA/PCI on low budget
50457: 02/12/10: Re: State of the PCB world
50652: 02/12/15: Re: Could you explain compact PCI, PCI and PCI bridge to me?
50653: 02/12/15: Re: Packing clock enable flipflops into IOB
51007: 02/12/25: Re: Newbie Question
51047: 02/12/28: Re: Newbie Question
51420: 03/01/13: Re: SChematic design approach compared to VHDL entry approach
51430: 03/01/13: Re: FPGA to ASIC migration - Help
51432: 03/01/13: Re: FPGA to ASIC migration - Help
51469: 03/01/14: Re: Cesys xc2s_eval opinions
51472: 03/01/14: Re: SChematic design approach compared to VHDL entry approach
51588: 03/01/16: Re: Support for older Virtex
51612: 03/01/17: Re: Xilinx PCI core PCI-X compatible ?
51672: 03/01/18: Re: Student development board
51809: 03/01/22: Re: Xilinx PCI core PCI-X compatible ?
51855: 03/01/23: Re: free x86 core ip
52002: 03/01/28: Re: PCI protocol - assigning an address to my device
52022: 03/01/29: Re: vhdl core of PCI bridge
52101: 03/01/31: Re: Quartus
52215: 03/02/04: Re: difference between pci2.1 and pci2.2
52217: 03/02/04: Re: vhdl core of PCI bridge
52218: 03/02/04: Re: PCI protocol - assigning an address to my device
52239: 03/02/05: Re: vhdl core of PCI bridge
52325: 03/02/06: Quartus II 2.2 doesn't run when installed to a newly transferred hard
52340: 03/02/06: Re: Quartus II 2.2 doesn't run when installed to a newly transferred
52341: 03/02/06: Re: Quartus II 2.2 doesn't run when installed to a newly transferred
52404: 03/02/08: Re: HELP NEEDED
52709: 03/02/19: Re: Quick FPGA PCI I/O in Spartan-IIE for single peripheral
52818: 03/02/23: Re: VHDL & FPGA Design tools
52908: 03/02/25: Re: config SlewRate for PCI-pads in Xilinx WebPack ??
52909: 03/02/25: Re: expansion ROM in PCI bridge
52915: 03/02/25: Re: Licencing for downloadable FPGA tools
53285: 03/03/10: Re: PCI specification
53396: 03/03/12: Re: PCI parity question
53397: 03/03/12: Re: PCI specification
53408: 03/03/12: Re: PCI parity question
53724: 03/03/20: Re: PCI target design
53725: 03/03/20: Re: PCI specification
53947: 03/03/27: Re: Question about case statement in XilinX webpack
53948: 03/03/27: Re: Mixed VHDL and Verilog with Xilinx ISE
53949: 03/03/27: Re: Mixed VHDL and Verilog with Xilinx ISE
54075: 03/04/01: Re: parity checking trick for PCI core
54076: 03/04/01: Re: parity checking trick for PCI core
54230: 03/04/04: Re: Altera not supplying Leonardo any more
54231: 03/04/04: Re: Xilinx V2.1i Licensing
54458: 03/04/11: Re: Xilinx IOB flip flop mapping
54479: 03/04/11: Re: Xilinx IOB flip flop mapping
54480: 03/04/11: Re: Xilinx IOB flip flop mapping
66413: 04/02/19: Xilinx ISE 4.2 Unisim Block RAM bug?
66474: 04/02/19: Re: Xilinx ISE 4.2 Unisim Block RAM bug?
66611: 04/02/24: Re: Free PCI-bridge in VHDL for Spartan-IIE
66612: 04/02/24: Re: Free PCI-bridge in VHDL for Spartan-IIE
66660: 04/02/24: Re: Free PCI-bridge in VHDL for Spartan-IIE
66662: 04/02/24: Re: Free PCI-bridge in VHDL for Spartan-IIE
66664: 04/02/24: Re: Free PCI-bridge in VHDL for Spartan-IIE
66739: 04/02/26: Re: Free PCI-bridge in VHDL for Spartan-IIE
66740: 04/02/26: Re: $100 for Americans PCI-bridge in NGO netlist for Spartan-IIE (Was:
66744: 04/02/26: Re: Free PCI-bridge in VHDL for Spartan-IIE
66749: 04/02/26: Re: Free PCI-bridge in VHDL for Spartan-IIE
66795: 04/02/26: Re: Why warnings: "Input <xyz> never used???"
66913: 04/02/29: Re: Why warnings: "Input <xyz> never used???"
67838: 04/03/20: Re: PCI Development Board
68116: 04/03/26: Re: Generating Xilinx cores.
67800: 04/03/19: Re: PCI Development Board
89283: 05/09/10: Re: Has anyone successfully used opencores PCI in FPGA desings?
89455: 05/09/15: Re: PCI configuration questions.
89763: 05/09/25: Re: Getting started VHDL, VHDL for Dummies, Easy Steps for FPGA experiments
90017: 05/10/02: Re: Using LogicCORE on development board with Web ISE
90018: 05/10/02: Re: Prevue - FPGA Dev Board Sale
90142: 05/10/05: Re: Using LogicCORE on development board with Web ISE
90289: 05/10/08: Re: Xilinx WebPack and command line
91264: 05/11/02: Re: FPGA : PCI-CORE
91266: 05/11/02: Re: FPGA : PCI-CORE
91268: 05/11/02: FPGA : PCI core needed
91355: 05/11/04: Re: FPGA : PCI core needed
91384: 05/11/04: Re: FPGA : PCI-CORE
91386: 05/11/04: Re: icarus verilog
91491: 05/11/07: Re: PCI test bench
91507: 05/11/08: Re: To create an IPCORE
91546: 05/11/08: Re: PC Core AD(x) I/O Enable?
91690: 05/11/11: Re: PC Core AD(x) I/O Enable?
93573: 05/12/25: Re: Can somone work on the pci express project?
93574: 05/12/25: Re: Can somone work on the pci express project?
93577: 05/12/25: Re: Can somone work on the pci express project?
96017: 06/01/28: Re: Spartan-3 Starter Board
kevin brand:
6125: 97/04/14: seeking graphics controller/processor core
10483: 98/05/22: graphics processor
Kevin Breeding:
27418: 00/11/21: Resetting Flip-Flops in Virtex
Kevin Brown:
76740: 04/12/09: What is the purpose of the 2 registers on A and B in the V4 Extreme DSP?
78632: 05/02/04: Re: Xilinx Virtex4 / Spartan3 High Speed Designs
79756: 05/02/23: Re: The real performance leader: V4
80019: 05/02/28: Missing Virtex4 Speedfile
83644: 05/05/04: Availability of the Xilinx ML481 Development Board
83698: 05/05/05: Re: Availability of the Xilinx ML481 Development Board
Kevin Bush:
7317: 97/08/25: ANNOUNCE: VHDL Synthesis for $495
7373: 97/09/03: Re: ANNOUNCE: VHDL Synthesis for $495
7561: 97/09/22: Re: Q: Lattice Synario and ISPLSI1048
Kevin D. Drucker:
4457: 96/10/31: Re: Altera & Verilog
4467: 96/11/01: Re: What is the fastest fpga for ...
5497: 97/02/20: State Diagram Tools
5512: 97/02/21: Fifth International Symposium on FPGAs
Kevin D. Quitt:
82509: 05/04/13: Re: Reverse engineering masked ROMs, PLAs
Kevin Dale Kirmse:
21304: 00/03/16: Re: Difference between FPGA, PLD, CPLD ?
21319: 00/03/16: Re: Difference between FPGA, PLD, CPLD ?
22798: 00/05/24: Re: 8087 in FPGA?
Kevin Driscoll:
72: 94/08/08: Re: How pricey is FPGA development?
1800: 95/09/04: Re: Help Needed-FPGA Apps Eng.-Allentown,PA.-Recruiter
Kevin Goodsell:
38607: 02/01/18: Simple shift register not working
38638: 02/01/20: Re: Simple shift register not working
38639: 02/01/20: Re: Simple shift register not working
38849: 02/01/26: Re: Simple shift register not working (update)
38931: 02/01/28: Re: Simple shift register not working (update)
38940: 02/01/28: Re: Simple shift register not working (update)
38941: 02/01/28: Re: Simple shift register not working (update)
38943: 02/01/28: Re: Simple shift register not working (update)
Kevin Hansen:
42050: 02/04/13: Xilinx JTAG C Source
42096: 02/04/15: JTAG 1532 BSDL Files for xc95xxxxl
Kevin Harney:
3616: 96/07/03: Problems with ORCA c40 FPGAs
Kevin Hawes:
3790: 96/08/01: US-NH FPGA Design Engineer, Avionics
3791: 96/08/01: US-NH FPGA Computer Architecture Design Engineer
3928: 96/08/21: Digital H/W Engineer (ASIC, VHDL)
Kevin Horton:
4673: 96/11/28: SRAM Programming on the Altera NFX780
12074: 98/09/27: NFX780, where to get?
Kevin Irick:
103540: 06/06/05: Re: PCI Express and DMA
Kevin J. McCann:
29041: 01/02/03: Help for a novice. Where to begin?
Kevin Jennings:
14572: 99/02/04: Re: Opinions requested : Minc/Synario alternatives
14893: 99/02/23: Replace an Intel 82380 or 8344 with a CPLD/FPGA
15137: 99/03/09: Re: programming cplds and serial roms and fpgas
16063: 99/04/30: Re: IRQ Controller
Kevin Kelley:
70020: 04/05/27: Job Opening - Product Planning Manager
70021: 04/05/27: Sr. Design Engineering Opportunities
Kevin Kibbe:
8030: 97/11/09: Altera FLEX 10K10 prototype board
Kevin Kilzer:
59287: 03/08/14: Re: flash-disk
59288: 03/08/14: Spartan II IOB in VHDL
61184: 03/09/30: Bit error rate
61196: 03/09/30: Re: Bit error rate
61408: 03/10/03: Re: Bit error rate
61633: 03/10/08: Visualizing VHDL
Kevin Klopfenstein:
22150: 00/04/27: Xilinx "length count" question
Kevin Kolb:
3938: 96/08/22: Re: XC6200 FPGAs
Kevin Lyons:
19934: 00/01/19: Anyone interested?
Kevin M. Olson:
5819: 97/03/18: Re: Development board with multiple FPGAs
Kevin McCluskey:
1832: 95/09/07: Re: FPGA to masked gate array conversion
Kevin Morris:
94494: 06/01/12: FPGA Journal Article
95768: 06/01/25: Re: FPGA Journal Article
95758: 06/01/25: Re: Xilinx padding LC numbers, how do you feel about it?
95766: 06/01/25: Stop. Go. Yield.
Kevin Neilson:
28187: 00/12/27: Re: really fast counter in SpartanXL?
28368: 01/01/10: Re: grey code counters
28378: 01/01/10: Re: grey code counters
28384: 01/01/11: Re: grey code counters
30345: 01/04/03: Re: pseudo random numbers
30608: 01/04/19: Re: looking for comment on implementation
30767: 01/04/28: Re: Comparison of FPGA and DSP
30768: 01/04/28: C++ To Gates
30769: 01/04/28: BlockRAM outputs and the Placer
30815: 01/04/30: Re: BlockRAM outputs and the Placer
30817: 01/04/30: Re: C++ To Gates
30818: 01/04/30: Re: C++ To Gates
30819: 01/04/30: Shannon Capacity
30829: 01/04/30: Re: High resolution time measurement?
30897: 01/05/02: Re: Serial UART
30924: 01/05/03: Re: Serial UART
30929: 01/05/03: Re: Shannon Capacity
30932: 01/05/03: Re: Comparison of FPGA and DSP
31022: 01/05/09: Re: Shannon Capacity - An Apology
31438: 01/05/24: Re: FPGA consultant needed
31556: 01/05/30: Re: FPGA consultant needed
31557: 01/05/30: Re: Fragen zu PCI und FPGA
31574: 01/05/30: Re: Fragen zu PCI und FPGA
31702: 01/06/03: Re: one state machine
31703: 01/06/03: Re: XtremeDSP Ready for prime time?
31723: 01/06/04: Re: XtremeDSP Ready for prime time?
32212: 01/06/19: Re: Video Compression on an FPGA
32260: 01/06/21: Re: Two's Complement conversion for FIR coefficients
32470: 01/06/27: Re: QPSK signal processing.
32525: 01/06/29: Re: Is the Grass Greener for an Engineer in the USA?
32545: 01/06/29: Re: obfuscated tools
32754: 01/07/07: Re: Problems with Virtex Block Ram Propagation Delay
32794: 01/07/09: Re: Need some help using Synplify ... and also considering Xilinx Modular Flow
32910: 01/07/11: Re: Need to speed up VHDL accumulator on Xilinx
32946: 01/07/12: Re: *.SDC - *.UCF conversion table?
32947: 01/07/12: DLL Phase Locking in Division Mode
32964: 01/07/13: Re: Xilinx BRAM failures
33108: 01/07/17: Re: Working Design - Anyone
33110: 01/07/17: Re: regarding the constraints while writing VHDL code
33328: 01/07/23: Re: Soldering Ceramic BGA's
33758: 01/08/03: Re: 4 (8) bit Microporcessor Implementation
33759: 01/08/03: Re: Clock skew with Xilinx DLLs...
33861: 01/08/07: Re: eine Frage
33862: 01/08/07: Re: Polyphase and VHDL questions
33863: 01/08/07: Re: FPGA - VHDL Design Tools (Was: 4 (8) bit Microporcessor Implementation)
34025: 01/08/11: Re: how to acheive high frquency in Xinlinx Virtex E
34387: 01/08/23: Re: Why this mismatches in simulation and sysnthesis results ?
34419: 01/08/24: Reading Text in Verilog
34492: 01/08/28: Re: FPGA to ASIC conversion?
34663: 01/09/02: Re: DSP in OTP
35046: 01/09/19: Re: Synplicity logic replication
35117: 01/09/21: Re: comparison of performance and advantages for fpga's versus microcontroller+dsp
35169: 01/09/25: Re: Coefficient scaling question
35338: 01/09/29: Re: comparison of performance and advantages for fpga's versus microcontroller+dsp
35339: 01/09/29: Re: Active-HDL back annotated simulation and PC memory usage
36133: 01/10/31: Re: Guided Design, Xilinx Virtex-E
36177: 01/11/01: Re: searchin for High density non bga packages something like PGA.
36197: 01/11/01: Re: Synplicity, Xilinx, & unwanted BUFGs
36200: 01/11/01: Re: Cloning someone else's IP core
36225: 01/11/02: Re: Open configuration bitstreams
36227: 01/11/02: Re: Open configuration bitstreams
36333: 01/11/06: Re: Xilinx Floorplanner Effectiveness
36470: 01/11/09: Re: RLOC on RAMB4_Sn_Sn
36628: 01/11/13: Re: Interleaver and Reed Solomon Encoder example
36660: 01/11/14: Re: interleaver delay question
36846: 01/11/22: Re: read only version register usinga generic
37682: 01/12/19: Re: You take the low road and I'll ......
37683: 01/12/19: Re: Kindergarten Stuff
38161: 02/01/07: FIR Linear Interpolation
38239: 02/01/09: Re: How can I relate Virtex2 pin names and Slice XY loc?
38346: 02/01/12: Re: speech recognition - active noise cancellation
38378: 02/01/13: Re: speech recognition - active noise cancellation
38379: 02/01/13: Re: How can I relate Virtex2 pin names and Slice XY loc?
38563: 02/01/17: Re: Audio time delay circuit
38592: 02/01/18: Re: Audio time delay circuit
38611: 02/01/19: Re: Shift Register question
40670: 02/03/12: Re: Article in March Embedded Systems - "The Death of Hardware Engineering"...
40934: 02/03/18: All Digital PLL for locking DDS to input clock
40954: 02/03/19: Re: All Digital PLL for locking DDS to input clock
41068: 02/03/20: Missing Timing by 30,000 ns
41097: 02/03/20: Re: Missing Timing by 30,000 ns
41239: 02/03/23: Re: Pipelined sorting algorithms...
41249: 02/03/23: Re: Missing Timing by 30,000 ns
41306: 02/03/25: Re: question on LFSR
41309: 02/03/25: Re: Missing Timing by 30,000 ns
41369: 02/03/26: Re: question on LFSR
41449: 02/03/28: Re: I need an advice regarding a switch to a Digital Design Career
41835: 02/04/09: Re: bad experience with Xilinx ISE 4.1i and Xilinx hotline suppot
41923: 02/04/11: Re: Built in multipliers in Virtex 2000E?
42022: 02/04/13: Re: Built in multipliers in Virtex 2000E?
42091: 02/04/15: Re: FPGA parameters
43170: 02/05/15: Re: Altera/Quartus II: unconditional loop?
43182: 02/05/15: Re: Altera/Quartus II: unconditional loop?
43324: 02/05/19: Slice Usage Per Module
43476: 02/05/22: Cross Probing in Xilinx Floorplanner Quirky
43517: 02/05/22: Virtex2 Carry Chains Slow? (Tciny)
43519: 02/05/22: Re: Virtex2 Carry Chains Slow? (Tciny)
43525: 02/05/22: Inferring BlockROMs
43526: 02/05/22: Re: Inferring BlockROMs
43546: 02/05/23: Re: FPGA, VHDL : RAM initialization
43547: 02/05/23: Re: Xilinx proprietary format?
43645: 02/05/28: Re: Timing Analyzer lockups
43803: 02/06/03: Re: divide by 5
43823: 02/06/04: Re: divide by 5
43913: 02/06/06: Re: xc3042
43936: 02/06/06: Re: xc3042
43983: 02/06/07: Re: Doing Trig Functions in FPGA, EPLD
44057: 02/06/11: Re: surely this is mad? (clock rate issues)
44143: 02/06/12: Re: Digital FM demodulator in FPGA-continue
44389: 02/06/19: The Placer is Crazy
44620: 02/06/25: Re: Xilinx tools under WinXP
44698: 02/06/27: Re: Xilinx tools under WinXP
44699: 02/06/27: Re: Xilinx tools under WinXP
44716: 02/06/27: The Placer is Crazy II
45310: 02/07/18: V2 Pipelined Embedded Mulitplier PAR issues
45404: 02/07/22: Re: Clock-gating in Virtex-E parts
45418: 02/07/23: Re: How could I generated an efficient 16*16 multiplier in Vertex-II?
45445: 02/07/24: Re: delay pipes in verilog for spartan IIe?
45451: 02/07/24: Re: delay pipes in verilog for spartan IIe?
45473: 02/07/24: Re: delay pipes in verilog for spartan IIe?
45625: 02/07/29: Re: secure FPGA
45695: 02/08/01: Re: Safe design speed
47683: 02/10/02: Re: Implementing Delta-Sigma ADC and DAC in Spartan IIE
48044: 02/10/10: Re: fpgaarcade update
48355: 02/10/16: Re: Delay elements using the schematic editor (Xilinx)
48888: 02/10/26: Re: #1's in verilog
49338: 02/11/09: Re: External memory or on-chip?
49361: 02/11/11: Re: rs encode
49397: 02/11/11: Re: HDL vs RTL
49583: 02/11/16: Re: DLL again :-)
49804: 02/11/21: Re: Open source for floorplan wanted
50811: 02/12/20: Re: stupid rookie timing question
51742: 03/01/21: Re: FLEXlm
52787: 03/02/21: parameters in ANSI-style Verilog port maps
53105: 03/03/04: conditional `include
53139: 03/03/04: Re: Mac Os X for FPGA design
53158: 03/03/05: Re: conditional `include
53183: 03/03/05: Re: conditional `include
53270: 03/03/09: Re: conditional `include
53307: 03/03/10: Constant Functions in Synplify
53597: 03/03/17: Re: Non-integer ratio interpolation and decimation
54029: 03/03/31: Re: ModelSIM XE wave files
54157: 03/04/03: Re: What is DA and SLR16?
54158: 03/04/03: Re: offset timing constraints - required?
54173: 03/04/04: Re: Matrix multiply in FPGA
54810: 03/04/18: Re: LFSR MAXIMUM LENGTH
55748: 03/05/18: High-Speed Clock & Data Recovery
56021: 03/05/27: Re: High-Speed Clock & Data Recovery
56345: 03/06/03: Re: Convolutional Encoder IP: Problem on puncturing
56435: 03/06/05: Re: Xilinx Block RAM
56436: 03/06/05: Re: defparam (Synthesizable or Not?)
56437: 03/06/05: Galois Fields Applications
56873: 03/06/18: Re: Simple FEC algorithm
58087: 03/07/14: Re: An All Digital Phase Lock Loop
58088: 03/07/14: Booth Multipliers
58218: 03/07/17: Re: An All Digital Phase Lock Loop
58310: 03/07/20: Re: CRC questions
58362: 03/07/21: Re: asynchronous FIFO
58393: 03/07/22: Re: asynchronous FIFO
58402: 03/07/22: Re: Clock rate increase for FEC aplications
58726: 03/07/31: Re: Problem in Xilinx (Freq Counter) design
59527: 03/08/21: Re: DCM vs state machine
59556: 03/08/21: Re: DCM vs state machine
59717: 03/08/26: Verlog 2001 signed numbers
59872: 03/08/30: Re: DSP
59873: 03/08/30: Re: how to design this datapath unit for DSP using VHDL/Verilog?
59933: 03/09/01: Matlab: What do I need for modeling?
62538: 03/10/31: Shannon Entropy for Black Holes
62730: 03/11/06: Re: Programmer's unpaid overtime.
62803: 03/11/07: Re: Programmer's unpaid overtime.
63017: 03/11/12: Re: Frequency Doubler - VHDL/Verilog
63760: 03/12/03: Re: Command line in Windows?
63982: 03/12/10: Re: Soldering of FPGAs
64153: 03/12/18: Re: FIR Filter cores for Virtex-][
66142: 04/02/13: Re: Verilog and VHDL mix
66219: 04/02/15: Re: DCM Jitter?
66645: 04/02/24: Re: Verilog Newbie Question
66716: 04/02/25: Re: How would you...
66717: 04/02/25: Re: difference btw H/W & S/W implementations !!
66819: 04/02/27: Re: How would you...
66889: 04/02/28: Re: netlist - technology remapping
67027: 04/03/04: Re: Different Finite Field Multipliers!!!
67147: 04/03/06: Re: FPGA hangs
67379: 04/03/11: Re: Routing phases after it has completed routing?
67380: 04/03/11: Answering Machine RAM
67381: 04/03/11: CORDIC vs. LUT
67645: 04/03/16: Re: Schematic Edition Tool : Suggestions
67867: 04/03/21: Re: Virtex2
67870: 04/03/21: Re: Virtex2
67911: 04/03/22: Re: XCV2000E survived 3.3V core voltage!
68120: 04/03/27: Re: Spartan RAMB4 Timing
68158: 04/03/28: Re: Help with Xilinx Ram16X1S example VHDL code
68415: 04/04/03: Re: The Logic Behind License Renewal
68544: 04/04/07: Re: how to get XST to infer 8:1 mux or just hard code it?
68586: 04/04/08: Re: how to get XST to infer 8:1 mux or just hard code it?
68610: 04/04/09: Re: how to get XST to infer 8:1 mux or just hard code it?
68701: 04/04/14: DDS-Based PLL
68709: 04/04/15: Re: DDS-Based PLL
68755: 04/04/16: Re: Document State Machines?
68756: 04/04/16: Re: DDS-Based PLL
68758: 04/04/16: Re: DDS-Based PLL
68820: 04/04/19: Image-reject IF downmixing
68826: 04/04/19: Re: Image-reject IF downmixing
68855: 04/04/20: Re: Image-reject IF downmixing
69330: 04/05/06: Re: Wire crossing in a large partially reconfigurable design.
70716: 04/06/24: Re: Divided by 11 in VHDL
70837: 04/06/29: Re: Trouble with $readmemh in ModelSim
70857: 04/06/30: Re: Trouble with $readmemh in ModelSim
71482: 04/07/20: Re: 32-channel PC-based logic analyzers
72589: 04/08/26: Re: ring oscillator calibration
72629: 04/08/27: Xilinx DCM Spread Spectrum feature
73484: 04/09/22: Re: Ring Oscillator Redux
74059: 04/10/03: Re: Hardware Log and EXP
72998: 04/09/10: Re: Placement vs Map in 6.2i, sp3
73088: 04/09/14: Re: Virtex 4 released today
73381: 04/09/21: Ring Oscillator Redux
74141: 04/10/04: Re: Asynchronous reset timing problem
74142: 04/10/04: Re: FPGA servo motor controller
74879: 04/10/20: Re: Real numbered operations
75001: 04/10/24: Re: VCXO Emulation, or using a DLL to shift phase infinitely, or how to chase a phase forever
74196: 04/10/06: Re: Xilinx Multiple Clock Domains
74198: 04/10/06: Re: Sine function implementation in FPGA??
76048: 04/11/23: Re: Beginers Question ModelSim Signals
76274: 04/11/29: Adder Tree Placement
76664: 04/12/08: Re: Adder Tree Placement
76666: 04/12/08: Re: Adder Tree Placement
76898: 04/12/15: Inferring SRLs with INIT value
76909: 04/12/15: Re: Inferring SRLs with INIT value
76911: 04/12/15: PACE question
76955: 04/12/16: Re: Inferring SRLs with INIT value
77432: 05/01/06: Re: San Jose job offer - need advice
77695: 05/01/14: Re: Resetting FIFO
78161: 05/01/25: Re: ADPLL I Think ?
78217: 05/01/26: Re: ADPLL I Think ?
78426: 05/01/31: Re: Asynchronous Inputs Question
78463: 05/02/01: Re: Evaluating EDIF netlist
79236: 05/02/15: Protecting IP in China
79719: 05/02/23: Constant Functions in Modelsim
79826: 05/02/24: Re: Fast 28x28 multiplier + adder in Virtex4
80123: 05/03/01: Re: Resetting Virtex II BlockRAM
80520: 05/03/07: Re: Hierarchical Synchronous Design
80568: 05/03/08: Re: Good, affordable verilog simulator
80590: 05/03/08: Re: Async FIFO problem...
80657: 05/03/09: Re: Async FIFO problem...
80733: 05/03/10: conditional port generation in Verilog 2001
81600: 05/03/28: Re: using (verilog) reg as memory
81606: 05/03/28: Re: Xilinx- Extract a pin layout
81664: 05/03/29: Re: Xilinx- Extract a pin layout
82915: 05/04/19: Perl Preprocessor for HDL
82923: 05/04/19: Re: Perl Preprocessor for HDL
82924: 05/04/19: Re: Perl Preprocessor for HDL
102416: 06/05/15: Re: USB2 camera to Xilinx ML40x boards
102418: 06/05/15: Re: Floating point reality check
105927: 06/08/02: Re: Generate statements for I/O list
110315: 06/10/13: Re: VGA timing
110922: 06/10/25: Re: Xilinx Virtex4 DDR clock output
111150: 06/10/30: Re: Taking forever to synthesise (XILINX ISE 8.1i)
111667: 06/11/07: Re: chipscope
112999: 06/12/04: Re: problems with verilog SDRAM models
114293: 07/01/10: Transport Delays in Modelsim
114323: 07/01/11: Re: Transport Delays in Modelsim
114360: 07/01/12: Re: Transport Delays in Modelsim
115377: 07/02/08: Re: Initialisation of two dimensional array to known non-zero values
115383: 07/02/08: Re: Read CLB information from NCD file
115595: 07/02/14: Minimum Speed of DDR / DDR2 SDRAM w/o DLL
115684: 07/02/16: Verilog: Simulating Transport Delays on Bidirectional Tristate Lines
118307: 07/04/23: Re: ModelSim Waveform naming question
119031: 07/05/09: Re: Chipscope with custom cable?
119258: 07/05/15: Re: How low DDR2 Clock Frequency can be? To make it work on FPGA.
119259: 07/05/15: Re: Interfacing DDR RAMs to Virtex 2 Pro on Digilent boards
119260: 07/05/15: Power Consumption near Timing Failure Point
119323: 07/05/16: Re: Power Consumption near Timing Failure Point
119390: 07/05/17: Re: Proper/recommended method for driving clock out from FPGA
120330: 07/06/05: Re: System Generator vs Synplify DSP vs Simulink HDL Coder
120346: 07/06/05: Re: System Generator vs Synplify DSP vs Simulink HDL Coder
120629: 07/06/12: Re: Apart from IEEE, is there some another journals for publishing
121637: 07/07/10: Re: DDR SDRAM simulation model, ML300, Infineon
122065: 07/07/18: Re: Generating video noise.
122394: 07/07/26: Re: Xilinx, converting ncd back to edif
122452: 07/07/27: Re: Xilinx, converting ncd back to edif
122630: 07/08/01: Re: DDR Simulation Model
124010: 07/09/10: Re: Free downloadable PDF graph paper.
124149: 07/09/12: Re: XAPP851 fifo36 missing
124496: 07/09/24: Re: Verilog simple dual port memory with different input and output
124561: 07/09/26: Inferring wide adders comprising multiple DSP48s
124624: 07/09/28: Re: FPGA NTSC signal with 2 resistors and PWM
126951: 07/12/06: Re: For God's sake !! It did not work at all !!!
127051: 07/12/10: Re: DDS generator with interpolated samples for Spartan3E development
127097: 07/12/11: Re: DDS generator with interpolated samples for Spartan3E development
127192: 07/12/13: Re: Initializing Micron DDR2 Memory
127194: 07/12/13: Re: DDS generator with interpolated samples for Spartan3E development
127608: 08/01/03: Re: Xilinx, How to generate PAD file, from the UCF file
127888: 08/01/09: Re: Synthesizing big RAMs
127892: 08/01/09: Re: Creation of BUGMUX from non clock signals
128491: 08/01/28: Re: Fixedpoint Multiply/Accumulate in DSP48
128492: 08/01/28: Re: Craignell FPGA DIP Module
128493: 08/01/28: Re: Thoughts about memory controller problems
128523: 08/01/29: Re: Fixedpoint Multiply/Accumulate in DSP48
128624: 08/01/31: Re: Why does a 36 x 36 Multiplier in a Xilinx Spartan 3E require
128797: 08/02/06: Re: How to optimize my design area to fit?
129304: 08/02/20: Re: Efficient division algorithm?
129357: 08/02/21: Re: Software Defined Radio auf Xilinx Virtex 4
129361: 08/02/21: Re: Interview questions
130503: 08/03/25: Re: AWGN in vhdl
130540: 08/03/26: Re: Places to visit in Amsterdam and Brussells
130589: 08/03/27: Re: Viewing internal signals with ModelSim
130627: 08/03/28: Re: quick question
130901: 08/04/04: Re: synplify pro generates negative slack
130971: 08/04/07: Re: Xilinx inferred FIFOs
130979: 08/04/07: Re: system level language: why all this fuss about
130986: 08/04/07: Re: system level language: why all this fuss about
131205: 08/04/15: Re: Which to learn: Verilog vs. VHDL?
131206: 08/04/15: Re: Snythesis error
131207: 08/04/15: Re: Simulation tools for Xilinx ISE
131213: 08/04/15: Re: Simulation tools for Xilinx ISE
131241: 08/04/16: Re: Simulation tools for Xilinx ISE
131429: 08/04/21: Re: Very simple VHDL problem
131430: 08/04/21: Re: How to instantiate macro in verilog
131438: 08/04/21: Re: Xilinx DDR2 Interface
131440: 08/04/21: Re: Turning off the DLL to run DDR2 at very low frequency
131441: 08/04/21: Re: ANNOUNCE: Maia 0.8.2: module-level HDL verification tool
131534: 08/04/24: Re: How to instantiate macro in verilog
131535: 08/04/24: Re: Turning off the DLL to run DDR2 at very low frequency
131536: 08/04/24: Re: Verilog state machines, latches, syntax and a bet!
131588: 08/04/25: Re: Very simple VHDL problem
131697: 08/04/29: Re: Chirp generator / CORDIC algo ?
131698: 08/04/29: Re: Chirp generator / CORDIC algo ?
131700: 08/04/29: Style for Highly-Pipelined State Machines
131774: 08/05/01: Re: sobel in vhdl
131813: 08/05/02: Re: Style for Highly-Pipelined State Machines
131817: 08/05/02: Forking in One-Hot FSMs
131818: 08/05/02: Re: Forking in One-Hot FSMs
131827: 08/05/02: Re: Forking in One-Hot FSMs
131868: 08/05/05: Re: Forking in One-Hot FSMs
131869: 08/05/05: Re: Forking in One-Hot FSMs
131870: 08/05/05: Re: Style for Highly-Pipelined State Machines
131871: 08/05/05: Re: Style for Highly-Pipelined State Machines
131909: 08/05/06: NGC / EDIF Viewer
131910: 08/05/06: DSP48 Inference Template for XST
131916: 08/05/07: Re: DSP48 Inference Template for XST
131997: 08/05/09: Re: ISE 9.2 - how do I extract component/slice placements for locking
132281: 08/05/20: Re: I cannot find how to map a "record type" in my ucf file.
132545: 08/05/30: Re: Can I make ISE 9.2 ngdbuild stop generating new PERIOD specs
132870: 08/06/09: Re: readmem[b|h]
133054: 08/06/16: Re: How to define the Dout width of DA FIR logic Core
133170: 08/06/19: Re: which commercial HDL-Simulator for FPGA?
133635: 08/07/07: Re: QPSK SymbolRate generator ...
133708: 08/07/10: Re: Chipscope data port limitation to 256 bits
134006: 08/07/21: Re: Xilinx FPGA editor tips?
134035: 08/07/22: Re: help me improve this simple function
134101: 08/07/25: Re: Xilinx FPGA editor tips?
134254: 08/08/01: Re: ISE new file wizard
134359: 08/08/07: Re: RTL Schematic as EDIF
134624: 08/08/21: Re: video timing with TFP410
134843: 08/09/03: Re: XST bug on illigal states of a FSM ?
134846: 08/09/03: Re: XST bug on illigal states of a FSM ?
135192: 08/09/19: Re: Synplify Pro derived clock going out as port
135193: 08/09/19: Re: Peter says Good Bye
135222: 08/09/22: Re: Is it possible to get an RTL netlist from Xilinx tools?
135268: 08/09/23: Re: Is it possible to get an RTL netlist from Xilinx tools?
135269: 08/09/23: Re: Is it possible to get an RTL netlist from Xilinx tools?
135312: 08/09/25: Re: decimal to ieee 754 single precision floating point
135399: 08/09/30: Re: reasonable timing analysis without mapping design to IO
135415: 08/10/01: Re: Post-synthesis simulation
136012: 08/10/27: Re: Would like to try ISIM, simple question
152650: 11/09/22: Browser-Based Timing Diagram Editor
154039: 12/07/18: Initializing inferred blockRAMs / ROMs without $readmemh (Synplify)
154934: 13/02/21: Re: question about verilog ?, :
154994: 13/03/22: Inferring DSP48 PATTERNDETECT and ACIN/ACOUT cascade
155101: 13/04/15: Re: Catapult C floating point exp() function?
155105: 13/04/17: Re: Catapult C floating point exp() function?
155119: 13/04/23: Inferring Xilinx BlockRAM FIFO
155120: 13/04/23: Modelsim ought to be cheaper
155173: 13/05/22: Die size of BRAM/DSP48 in CLBs
155182: 13/05/23: Re: Die size of BRAM/DSP48 in CLBs
155184: 13/05/23: Cubic Spline Interpolator
155198: 13/05/29: Re: Cubic Spline Interpolator
155199: 13/05/29: Re: Cubic Spline Interpolator
155241: 13/06/17: Re: DDR2 Concurrent Auto Precharge
155250: 13/06/18: Re: Modelsim ought to be cheaper
155251: 13/06/18: Re: Chasing Bugs in the Fog
155255: 13/06/18: Re: Chasing Bugs in the Fog
155272: 13/06/20: Re: Modelsim ought to be cheaper
155360: 13/06/24: Re: VHDL syntheses timestamp
157724: 15/02/18: Inferring F7 / F8 Mux in Xilinx
157726: 15/02/18: Re: Inferring F7 / F8 Mux in Xilinx
157727: 15/02/18: Re: Inferring F7 / F8 Mux in Xilinx
157894: 15/05/11: 16->5 "Sort"
157896: 15/05/11: Re: 16->5 "Sort"
157897: 15/05/11: Re: 16->5 "Sort"
157909: 15/05/12: Re: 16->5 "Sort"
157910: 15/05/12: Re: 16->5 "Sort"
157911: 15/05/12: Re: 16->5 "Sort"
157912: 15/05/12: Re: 16->5 "Sort"
157913: 15/05/12: Re: 16->5 "Sort"
157917: 15/05/12: Re: 16->5 "Sort"
157923: 15/05/13: Re: 16->5 "Sort"
157987: 15/06/10: Re: Is it possible to have a parameterized verilog module name in
157988: 15/06/10: Re: Is it possible to have a parameterized verilog module name in
157989: 15/06/10: Re: Is it possible to have a parameterized verilog module name in
158281: 15/10/03: Re: DDR* SDRAM modules for simulation
158282: 15/10/03: Re: Question about partial multiplication result in transposed FIR filter
158283: 15/10/03: Re: Question about partial multiplication result in transposed FIR filter
158284: 15/10/03: Re: Correlator of a big antenna array on FPGA
158294: 15/10/05: Re: System On Chip From Microsemi
158295: 15/10/05: Re: Question about partial multiplication result in transposed FIR filter
158296: 15/10/05: Re: Question about partial multiplication result in transposed FIR filter
158357: 15/10/23: Re: Question about partial multiplication result in transposed FIR filter
158359: 15/10/23: Quad-Port BlockRAM in Virtex
158360: 15/10/23: Re: Quad-Port BlockRAM in Virtex
158386: 15/10/26: Re: Question about partial multiplication result in transposed FIR filter
158560: 15/12/25: Re: modulo 2**32-1 arith
158562: 15/12/26: Re: modulo 2**32-1 arith
158569: 15/12/29: Re: modulo 2**32-1 arith
158627: 16/02/08: Re: Fully preposterous gate arranger
158634: 16/02/17: Re: Synplify Identify with Microsemi FPGAs
158847: 16/05/05: Matlab-to-Gates for Xilinx
158849: 16/05/09: Re: Matlab-to-Gates for Xilinx
159061: 16/07/22: Mod-24: The State of High-Level Synthesis in 2016
159065: 16/07/23: Re: Mod-24: The State of High-Level Synthesis in 2016
159066: 16/07/23: Re: Mod-24: The State of High-Level Synthesis in 2016
159074: 16/07/26: Re: Mod-24: The State of High-Level Synthesis in 2016
159075: 16/07/26: Re: Mod-24: The State of High-Level Synthesis in 2016
159080: 16/07/26: Re: Mod-24: The State of High-Level Synthesis in 2016
159085: 16/07/27: Re: Mod-24: The State of High-Level Synthesis in 2016
159086: 16/07/27: Re: Mod-24: The State of High-Level Synthesis in 2016
159087: 16/07/27: Constant Mult: The State of High Level Synth (Part II)
159088: 16/07/27: Vivado parses wicked slow
159091: 16/07/27: Re: Constant Mult: The State of High Level Synth (Part II)
159093: 16/07/27: Re: Constant Mult: The State of High Level Synth (Part II)
159099: 16/07/28: Re: Vivado parses wicked slow
159107: 16/07/30: Re: Constant Mult: The State of High Level Synth (Part II)
159112: 16/08/02: Re: Vivado parses wicked slow
159114: 16/08/03: Re: Vivado parses wicked slow
159122: 16/08/05: Re: Vivado parses wicked slow
159127: 16/08/09: Re: Vivado parses wicked slow
159137: 16/08/18: Re: Multi-port memory
159139: 16/08/19: Re: Multi-port memory
159206: 16/09/01: Re: Minimal-operation shift-and-add (or subtract)
159207: 16/09/01: Re: Minimal-operation shift-and-add (or subtract)
159240: 16/09/06: Re: eliminating a DDS
159305: 16/09/30: Re: Sharing a single Lookup Table
159306: 16/09/30: Re: C to FPGA
159362: 16/10/16: Re: CORDIC in a land of built-in multipliers
159363: 16/10/16: Re: CORDIC in a land of built-in multipliers
159364: 16/10/16: Re: FPGA LABVIEW programming
159422: 16/11/01: Re: Quad-Port BlockRAM in Virtex
159426: 16/11/03: Re: Quad-Port BlockRAM in Virtex
159429: 16/11/04: Re: Quad-Port BlockRAM in Virtex
159430: 16/11/04: Re: Quad-Port BlockRAM in Virtex
159433: 16/11/05: Re: Quad-Port BlockRAM in Virtex
159436: 16/11/05: Re: Quad-Port BlockRAM in Virtex
159437: 16/11/08: Re: Quad-Port BlockRAM in Virtex
159438: 16/11/08: Re: Quad-Port BlockRAM in Virtex
159466: 16/11/19: Phrasing!
159472: 16/11/21: Re: Phrasing!
159477: 16/11/21: Re: Phrasing!
159486: 16/11/22: Re: Phrasing!
159506: 16/11/26: Re: Phrasing!
159533: 16/12/02: Re: Phrasing!
159554: 16/12/20: Re: Quad-Port BlockRAM in Virtex
159555: 16/12/20: True Random Number Gen in Virtex 7
159564: 16/12/30: Re: Slightly OT: Digital watch circuits
159581: 17/01/03: Re: Slightly OT: Digital watch circuits
159591: 17/01/05: Re: Slightly OT: Digital watch circuits
159645: 17/01/25: Re: Hardware floating point?
159665: 17/01/26: Re: Hardware floating point?
159682: 17/01/30: Re: Hardware floating point?
159707: 17/02/13: Re: All-real FFT for FPGA
159765: 17/02/25: Re: designing a fpga
159777: 17/03/02: Re: designing a fpga
159778: 17/03/02: Re: designing a fpga
159782: 17/03/03: Re: designing a fpga
159791: 17/03/03: Re: designing a fpga
159797: 17/03/07: Re: designing a fpga
159799: 17/03/07: Re: designing a fpga
159852: 17/04/11: Re: FPGA as heater
159853: 17/04/11: Re: FPGA as heater
159870: 17/04/12: Re: FPGA as heater
159876: 17/04/12: Re: FPGA as heater
159880: 17/04/13: Re: FPGA as heater
159905: 17/04/24: Re: glitching AND gate
159911: 17/04/24: Re: glitching AND gate
159912: 17/04/24: Cyclotomic FFTs
159916: 17/04/26: Re: glitching AND gate
159919: 17/04/27: Re: glitching AND gate
159938: 17/05/01: Re: RISC-V Support in FPGA
159939: 17/05/01: Re: RISC-V Support in FPGA
159941: 17/05/01: Re: RISC-V Support in FPGA
159960: 17/05/02: Re: RISC-V Support in FPGA
159967: 17/05/02: Re: RISC-V Support in FPGA
159972: 17/05/03: Re: RISC-V Support in FPGA
159975: 17/05/03: Re: RISC-V Support in FPGA
159985: 17/05/04: Re: creating a seed on a FPGA.
159986: 17/05/04: Re: RISC-V Support in FPGA
159987: 17/05/04: Re: RISC-V Support in FPGA
159996: 17/05/06: Re: RISC-V Support in FPGA
160017: 17/05/11: Re: increment or decrement one of 16, 16-bit registers
160024: 17/05/13: Re: increment or decrement one of 16, 16-bit registers
160035: 17/05/15: Re: Pipelining on Multiple Clock Edges
160038: 17/05/15: Re: Pipelining on Multiple Clock Edges
160091: 17/05/23: Re: Accelerating Face Detection on Zynq-7020 Using High Level Synthesis
160092: 17/05/23: Re: Test Driven Design?
160125: 17/06/10: Re: Article about using Non-Project Mode
160168: 17/06/30: Re: Article about using Non-Project Mode
160376: 18/01/02: Re: Qs on HDL library code and pipelining
160382: 18/01/04: Re: Qs on HDL library code and pipelining
160396: 18/01/11: Re: HDL simple survey - what do you actually use
160411: 18/01/16: Re: HDL simple survey - what do you actually use
160686: 18/10/10: Re: What to do with an improved algorithm?
160688: 18/10/11: Re: What to do with an improved algorithm?
160689: 18/10/11: Re: What to do with an improved algorithm?
160691: 18/10/16: Re: What to do with an improved algorithm?
160695: 18/10/18: Re: What to do with an improved algorithm?
160696: 18/10/18: Re: FPGA Market Entry Barriers
160697: 18/10/18: Re: FPGA Market Entry Barriers
160701: 18/10/18: Re: FPGA Market Entry Barriers
160703: 18/10/18: Re: FPGA Market Entry Barriers
160706: 18/10/19: Re: FPGA Market Entry Barriers
160707: 18/10/19: Re: FPGA Market Entry Barriers
160715: 18/10/26: Re: FPGA Market Entry Barriers
160716: 18/10/26: Re: FPGA Market Entry Barriers
160719: 18/10/26: Re: FPGA Market Entry Barriers
160726: 18/10/27: Re: FPGA Market Entry Barriers
160727: 18/10/27: Re: FPGA Market Entry Barriers
160728: 18/10/27: Re: FPGA Market Entry Barriers
160850: 18/12/06: Estimating ROM gate count in ASIC
160851: 18/12/06: Re: Estimating ROM gate count in ASIC
160852: 18/12/06: Re: Estimating ROM gate count in ASIC
160925: 18/12/20: Re: Estimating ROM gate count in ASIC
160947: 18/12/28: Re: Estimating ROM gate count in ASIC
160949: 18/12/30: Re: Estimating ROM gate count in ASIC
160951: 19/01/01: Re: Estimating ROM gate count in ASIC
161024: 19/01/13: Re: initializing a small array in Verilog
161037: 19/01/15: Re: Need help to understand: Efficient Multi-Ported Memories for FPGAs
161038: 19/01/15: Re: Need help to understand: Efficient Multi-Ported Memories for FPGAs
161040: 19/01/15: Re: Need help to understand: Efficient Multi-Ported Memories for FPGAs
161047: 19/01/16: Re: initializing a small array in Verilog
161186: 19/02/23: Re: Cyclone V decimation
161291: 19/03/23: High-level synthesis
161292: 19/03/23: Re: High-level synthesis
161298: 19/03/24: Re: High-level synthesis
161390: 19/06/27: Unique uses for the DSP48
161394: 19/06/28: Re: Unique uses for the DSP48
161401: 19/07/06: Re: Unique uses for the DSP48
161403: 19/07/08: Re: Unique uses for the DSP48
161581: 19/12/04: Anybody used Amazon AWS for HW sims?
161584: 19/12/05: Re: Anybody used Amazon AWS for HW sims?
161588: 19/12/05: Re: Enabler for New FPGA Companies
161589: 19/12/05: Re: Anybody used Amazon AWS for HW sims?
Kevin Nickels:
459: 94/11/23: Re: any XC4000 Horror Stories?
Kevin O'Mara:
63258: 03/11/18: XILINX Foundation F1.5 Build 3.1.1.35 with XCS10PC84 and Digilab XLA
63514: 03/11/24: Re: XILINX Foundation F1.5 Build 3.1.1.35 with XCS10PC84 and Digilab XLA
Kevin Shaw:
68599: 04/04/09: Xilinx PLB RapidIO LVDS Core
Kevin Smith:
6437: 97/05/23: Re: FPGA gate counting: No truth in advertising
30998: 01/05/08: Re: Routing: Completed - errors found.
30999: 01/05/08: Re: Xilinx Constraints Editor ?
Kevin Steele:
3558: 96/06/20: Re: XC1765 vs Atmel's AT17C65 Serial EEPROMs
4649: 96/11/25: Re: VHDL code editor for Windows NT.
5631: 97/03/03: Re: Customizing Viewdraw in Workview Office 7.3 ... OLE hooks?
9750: 98/04/02: Smoking Crater in a Xilinx 3k FPGA
9849: 98/04/08: Re: Smoking Crater in a Xilinx 3k FPGA
Kevin T. Hawes:
4524: 96/11/08: US FPGA Engineers
Kevin T. Mortimer:
21957: 00/04/10: Virtex Trivia
Kevin Timmons:
32143: 01/06/15: Re: looking for work
Kevin Toliver:
17629: 99/08/16: VHDL to debounce & latch input from a switch
Kevin VAZ:
32109: 01/06/14: Simulator components missing!
32240: 01/06/20: RAM_blocks inference in Leonardo Spectrum!
Kevin White:
71179: 04/07/10: C16 processor from Opencores.org
71315: 04/07/14: Re: C16 processor from Opencores.org
71833: 04/08/01: Re: SPARTANII pinout table mysteries ???
Kevin Yeoh:
50278: 02/12/07: Warnings in FPGA express
50322: 02/12/09: Re: vlsi implementation of multipliers
51154: 03/01/04: Warnings in FPGA...
Kevin Zhu:
kevin93:
131138: 08/04/11: Re: high noise/signal in a simple serial to mono dac module
143042: 09/09/16: Re: 8 phase clock output
143166: 09/09/23: Re: 8 phase clock output
143766: 09/10/24: Re: ISe 10.1 nightmare bug
143797: 09/10/26: Re: ISe 10.1 nightmare bug
149264: 10/10/12: Re: JTAG stops working!
149755: 10/11/22: Re: Debugging with a single LED
150277: 11/01/07: Re: spartan 3 xc3s1000 not getting programmed
<Kevin>:
37821: 01/12/20: Re: Hardware FPGA questions
37838: 01/12/21: Re: How can I reduce Spartan-II routing delays to meet 33MHz PCI's Tsu <
37841: 01/12/21: Re: How can I reduce Spartan-II routing delays to meet 33MHz PCI's Tsu <
37884: 01/12/23: Re: How can I reduce Spartan-II routing delays to meet 33MHz PCI's Tsu <
37885: 01/12/23: Re: How can I reduce Spartan-II routing delays to meet 33MHz PCI's Tsu <
37909: 01/12/24: Should clock skew be included for setup time analysis?
37917: 01/12/24: Re: How can I reduce Spartan-II routing delays to meet 33MHz PCI's Tsu <
37920: 01/12/24: Re: How can I reduce Spartan-II routing delays to meet 33MHz PCI's Tsu
37921: 01/12/24: Re: How can I reduce Spartan-II routing delays to meet 33MHz PCI's Tsu <
37922: 01/12/24: Re: How can I reduce Spartan-II routing delays to meet 33MHz PCI's Tsu <
37923: 01/12/24: Re: How can I reduce Spartan-II routing delays to meet 33MHz PCI's Tsu <
37924: 01/12/25: Where could I get a signal waveform editor?
<kevin@firebolt.com>:
83302: 05/04/27: Virtex slow clock multiply options?
83304: 05/04/27: Re: Virtex slow clock multiply options?
83339: 05/04/27: Re: Virtex slow clock multiply options?
84011: 05/05/11: FPGA/Embedded Design Training
86299: 05/06/24: LVTTL Spec
<kevin@nospam.nospam>:
81206: 05/03/19: Is an XC3S1500 enough to implement a MP@ML MPEG-2 decoder?
<kevin@whitedigs.com>:
118327: 07/04/23: Re: DONE problems
<kevinjwhite@comcast.net>:
89472: 05/09/15: Re: Is a CPLD appropriate for this triple PWM application?
97060: 06/02/15: Re: Altera RoHS Irony
100305: 06/04/06: Re: done pin didn't go high
<kevintsmith@compuserve.com>:
6000: 97/04/03: Vendors (Xilinx, Cypress) leaving antifuse market
6155: 97/04/18: FPGA gate counting: No truth in advertising
6170: 97/04/21: FPGA gate counts - no truth in advertising?
6390: 97/05/20: Re: FPGA gate counting: No truth in advertising
6433: 97/05/23: Re: Low power PLD?
6491: 97/05/28: Re: FPGA gate counting: No truth in advertising
<kevinwolfe@gmail.com>:
103366: 06/05/31: Re: Quartus and source control
103401: 06/06/01: Re: Quartus and source control
<kevinzh@gmail.dot.com>:
81473: 05/03/24: DDR SDRAM interface working with AMBA-AHB
KevSteele:
334: 94/10/23: High Bus Drive (24mA) FPGAs/CPLDs?
381: 94/11/02: Re: High Bus Drive (24mA) FPGAs/CPLDs?
keyrun:
93219: 05/12/15: Re: Inverter Chain Synthesis Problem
<keysoft@public.sta.net.cn>:
2156: 95/10/22: China business guide
Keyvan Irani:
16329: 99/05/16: Altera to Clear Logic Conversion
20727: 00/02/19: x18 FIFO's in Virtex
KF4KJQ:
122261: 07/07/24: Re: DDR2 w/ MIG on Xilinx ML501 Board
122265: 07/07/24: Re: DDR2 w/ MIG on Xilinx ML501 Board
122334: 07/07/25: Re: DDR2 w/ MIG on Xilinx ML501 Board
<kfalser@durst.it>:
14233: 99/01/21: Re: help w/ broken xilinx dongle
14563: 99/02/04: Timing Simulation and Foundation
<kfrod@my-deja.com>:
16980: 99/06/21: pdf files
KG7HF:
56248: 03/06/01: Re: JTAG madness
56313: 03/06/03: Re: JTAG madness
<kgbee@my-deja.com>:
21461: 00/03/23: Giving fpga's unique id
23179: 00/06/16: Re: Verilog Questions??
<kgll8ss@yahoo.com>:
125734: 07/11/02: Spartan-3 (XC3S400) DDR LVDS support?
125925: 07/11/08: Xilinx Parallel Cable IV, API spec
125928: 07/11/08: Re: Xilinx Parallel Cable IV, API spec
125951: 07/11/09: Re: Xilinx Parallel Cable IV, API spec
125957: 07/11/09: Is "Insight IJC-02" and "Xilinx parallel download cable" the same?
kh05168:
37787: 01/12/20: Re: How to initialize the block ram of xilinx SpartanII FPGA?(Verilog)
kha_vhdl:
116864: 07/03/20: create test bench of video
116901: 07/03/20: Re: create test bench of video
117159: 07/03/24: convertion real to std_logic_vector
117161: 07/03/24: Re: convertion real to std_logic_vector
117204: 07/03/26: how to read a sequence of video
117241: 07/03/27: Re: how to read a sequence of video
117269: 07/03/27: Re: how to read a sequence of video
119102: 07/05/11: how to choose the perfect fpga support
119116: 07/05/11: Re: how to choose the perfect fpga support
119128: 07/05/12: Re: how to choose the perfect fpga support
Khaled Benkrid:
13611: 98/12/12: 4000 series EDIF routing property
Khaled benkrid:
13992: 99/01/06: ARISTOTLE BOARD
14261: 99/01/22: FPGA express warning
14275: 99/01/23: Re: FPGA express warning
14352: 99/01/27: Re: FPGA express warning
14396: 99/01/28: Mirotech boards.
14397: 99/01/28: Re: FPGA express warning
14883: 99/02/23: High Fanout Signals
15072: 99/03/05: Re: High Fanout Signals
15082: 99/03/05: Re: High Fanout Signals
15073: 99/03/05: Re: High Fanout Signals
15075: 99/03/05: Re: High Fanout Signals
15074: 99/03/05: Re: High Fanout Signals
15858: 99/04/17: XC4000 LUT on the fly programming
15870: 99/04/17: Re: XC4000 LUT on the fly programming
15987: 99/04/26: Re: Using Embedded RAM in Xilinx Virtex Chips
Khaled BENKRID:
17845: 99/09/13: Foundation Express Map abnormal error
18384: 99/10/21: test`
18385: 99/10/21: test
18386: 99/10/21: test
18409: 99/10/23: Foundation 1.5i Map fatal error
18427: 99/10/23: Re: Foundation 1.5i Map fatal error
18457: 99/10/25: Problem solved?
Khaled Nsaibia:
40313: 02/03/05: Re: Book Recommendation for Designing Complex System using HDL.
khalid:
16776: 99/06/08: LINE DELAYS USING RAMS
16788: 99/06/08: Re: LINE DELAYS USING RAMS
Khalid Alotaibi:
4895: 96/12/26: BitStream in Online
6745: 97/06/23: Netlist file EDIF
10845: 98/06/25: VHDL <-> EDIF
khamkar77:
68569: 04/04/08: Re: how to get XST to infer 8:1 mux or just hard code it?
68573: 04/04/08: Re: timing constraints... again
Khan:
54639: 03/04/15: Error in Make file using XST tools
54645: 03/04/15: getting error
54646: 03/04/15: Help Required Please
54705: 03/04/16: XST and Makefile
55064: 03/04/25: LDPC Code implmentation using XILINX Vertex
55066: 03/04/25: Implementation of LDPC code using VHDL
Khan Kibria:
10734: 98/06/14: ASIC design service
11043: 98/07/14: ASIC Design Service
11721: 98/09/03: Get your chip going - beat the schdule
17371: 99/07/22: PCI Controller chip Announcement
<khan990@gmail.com>:
156148: 13/12/19: ppc405 communication with custom ip ml403
khansa:
82062: 05/04/06: VHDL to schematic conversion
82653: 05/04/15: increase in delay when a port was removed from design (Xilinx Project Navigator 5.2i)
<khanzode@my-deja.com>:
23816: 00/07/11: Re: Error: Clock skew plus hold time of destination register exceeds register-to-register delay
<khanzode@yahoo.com>:
23822: 00/07/11: Timing Simulation for Alter FPGAs
23823: 00/07/11: Timing Simulation for Alter FPGAs
<kharray.bassas@gmail.com>:
137006: 08/12/18: virtex 5 decryptor
137100: 08/12/23: bitstream protection
137498: 09/01/21: virtex5 / configuration logic
<khartman@conwin.com>:
13502: 98/12/06: Re: Why doesn't Xilinx's simulator work?
Khatib:
154254: 12/09/16: OpenTech the Largest Open Source package for FPGA designers
<khatib@ieee.org>:
25707: 00/09/18: Bluetooth core??
28223: 01/01/02: Free Tools and Designs
khbutnospam@clubbutnospam.innet.be:
85617: 05/06/12: Help with USB cable, Xilinx XUP board, Linux FC3 and EDK
Khee Hue:
46170: 02/08/21: Virtex-II LVPECL Inputs
<khiltrop@gesytec.de>:
33247: 01/07/20: Modelsim and bidir ports?
33319: 01/07/23: Antwort: Re: Modelsim and bidir ports?
68738: 04/04/16: vhdl example for use of external SRAM as a dual ported RAM?
68748: 04/04/16: Antwort: Re: vhdl example for use of external SRAM as a dual ported RAM?
68892: 04/04/21: Xilinx FPGA one project loadable, another not - any hint?
69684: 04/05/18: Xilinx WebPack 6 -> Error: 90:Portability <-- anyone can give me a hint?
69753: 04/05/19: Antwort: Re: Xilinx WebPack 6 -> Error: 90:Portability <-- anyone can give
Khim Bittle:
50691: 02/12/17: ACEX 1K Configuration Time
50694: 02/12/17: Re: ACEX 1K Configuration Time
50707: 02/12/18: Re: ACEX 1K Configuration Time
54001: 03/03/31: $4000 FPGAs
54857: 03/04/21: Re: Very low pin count FPGA
57024: 03/06/20: Re: Cyclone Migration EP1C6 to EP1C12
57375: 03/06/29: Altera Nios Benchmarks
57832: 03/07/08: Re: eCOS port for NIOS
59923: 03/09/01: Re: Are there any free version uCOSII for Nios?
60197: 03/09/08: Re: CMOS camera w/ USB2 -- crazy?
60515: 03/09/15: Re: USB transceiver for FPGA
61559: 03/10/06: Re: SDRAM types and availability
61885: 03/10/14: Altera mySupport
62174: 03/10/21: Re: 74 logic to CPLD. how easy for a Newbie?
62265: 03/10/23: Re: Altera cyclone circuit board indicator
62445: 03/10/29: Re: How to protect fpga based design against cloning?
62570: 03/11/02: Re: Video decoder and encoder IC's
63318: 03/11/19: Re: Small PLD choices
65286: 04/01/23: Altera Active Serial
65462: 04/01/29: Re: Altera Active Serial
65510: 04/01/31: Re: Altera Active Serial
65511: 04/01/31: Re: Altera Active Serial
65539: 04/02/01: Re: New USB chip for fast FPGA bitstream download
khKim:
19466: 99/12/23: Bi-directional 3-State Buffer
khoa nguyen:
66869: 04/02/28: FPGA implementation of ARM and IA32 ISA
66909: 04/02/29: Re: FPGA implementation of ARM and IA32 ISA
66992: 04/03/02: Looking for a small ARM and/or IA32 based application
khoi ha:
22154: 00/04/27: testing
22746: 00/05/22: Coregen generated FIFO not working
34096: 01/08/14: VHDL floating point arithmetic
Kholdoun TORKI:
68893: 04/04/21: ICM'2004 : Call for Papers
<khomeyard@googlemail.com>:
123950: 07/09/07: RE: FPGA/VHDL digital Design permanent role - Oxford
khoryl:
83154: 05/04/25: ml310: linux boot faillure
<khtsoi@cse.cuhk.edu.hk>:
36315: 01/11/06: Re: speed of adder in XC1000E-6
36317: 01/11/06: RLOC for a block
36320: 01/11/06: Re: RLOC for a block
36455: 01/11/09: RLOC on RAMB4_Sn_Sn
36605: 01/11/13: Synopsys+Xilinx vs Synplicity
36731: 01/11/18: Re: Q: XILINX binary .bit file header - ?
36750: 01/11/19: Re: FPGA synthesis
36760: 01/11/19: Re: FPGA synthesis
36857: 01/11/22: fix LOC on LUT1
36902: 01/11/24: Re: fix LOC on LUT1
36990: 01/11/28: reducing PAR time
37035: 01/11/29: Re: reducing PAR time
37049: 01/11/29: Re: xilinx foundation 3.1 and pentium 4
38012: 01/12/31: exclude a path in TRACE timing
38020: 01/12/31: Re: exclude a path in TRACE timing
<khtsoi@pc89122.cse.cuhk.edu.hk>:
93901: 06/01/03: Coding style
93952: 06/01/04: Re: Coding style
<khtsoi@pc90026.cse.cuhk.edu.hk>:
34391: 01/08/23: xchecker under Linux
34499: 01/08/28: download bitstream to FPGA
34536: 01/08/29: Re: download bitstream to FPGA
34585: 01/08/30: Re: download bitstream to FPGA
34586: 01/08/30: Re: download bitstream to FPGA
34592: 01/08/30: Re: download bitstream to FPGA
34673: 01/09/03: Linux download bitstream [w/ source]
34960: 01/09/17: INIT attribute of SRL16E
34964: 01/09/17: Re: INIT attribute of SRL16E
35921: 01/10/24: RLOC under VHDL
36270: 01/11/05: speed of adder in XC1000E-6
52246: 03/02/05: Xilinx ISE optimization
52250: 03/02/05: Re: Xilinx ISE optimization
52257: 03/02/05: Re: Distributing component without source
52298: 03/02/06: Re: Switching synthesis tools
52593: 03/02/15: Re: Implementing BIG state machhine
<khurley@ea.com>:
581: 95/01/10: Re: Fpga programming
673: 95/02/02: Re: "on-fly" reprogrammable devices/research
Ki:
106021: 06/08/05: FPGA interface to serial ADC
106135: 06/08/08: Re: FPGA interface to serial ADC
106314: 06/08/11: Re: FPGA interface to serial ADC
kia rui:
103646: 06/06/07: LVTTL, LVCMOS or 3.3V-PCI?
103915: 06/06/14: LVTTL or LVCMOS for PCI Signaling?
<kian.zarrin@gmail.com>:
128922: 08/02/10: loading unisim in modelsim problem while testin xilinx ipcore
129863: 08/03/07: Re: loading unisim in modelsim problem while testin xilinx ipcore
<kicdonc@tiscali.fr>:
108974: 06/09/19: Re: E1 to ethernet conversion
115204: 07/02/02: Re: ISE 9.1 SAY YOURS OPINION
<kickass4ever@my-dejanews.com>:
12393: 98/10/11: Re: Xilinix Foundation Install?
Kicn:
133669: 08/07/09: Configure registers of CMOS Sensor by Spartan3
133694: 08/07/10: Re: Configure registers of CMOS Sensor by Spartan3
kierenj:
86347: 05/06/26: Re: Module integration, odd state machine behaviour (verilog), etc!
86358: 05/06/26: Re: Module integration, odd state machine behaviour (verilog), etc!
86443: 05/06/28: Re: Module integration, odd state machine behaviour (verilog), etc!
<kierenj@handtheband.com>:
86333: 05/06/25: Module integration, odd state machine behaviour (verilog), etc!
kil:
122414: 07/07/27: regarding the post PnR timing simulation.....
122424: 07/07/27: Re: regarding the post PnR timing simulation.....
kilgor:
111386: 06/11/02: Re: Implementing the Aurora Example Design V2.4(2.5) to a Virtex4
111387: 06/11/02: Aurora v2.5 for V4FX - No "channel_up" in post-routed simulation during 200 us
111436: 06/11/02: Re: Aurora v2.5 for V4FX - No "channel_up" in post-routed simulation during 200 us
111466: 06/11/03: Re: Aurora v2.5 for V4FX - No "channel_up" in post-routed simulation during 200 us
112168: 06/11/17: Re: Aurora IP core vs. RocketIO wizard
kim:
42758: 02/05/02: Re: DDR SDRAM Controller
Kim Carter:
10655: 98/06/09: Re: How about Lattice ispLSI?
10681: 98/06/10: Re: How about Lattice ispLSI?
10695: 98/06/11: Re: How about Lattice ispLSI?
23020: 00/06/09: Re: TTL device Libraries
Kim Enkovaara:
38124: 02/01/06: Re: asic vs. fpga
43702: 02/05/30: Re: place and route simulation time
57297: 03/06/27: Re: Xilinx Webpack bugs bugs bugs
67672: 04/03/17: Re: Speed of Linux vs Solaris
68087: 04/03/26: Re: study verilog or vhdl?
73920: 04/10/01: Re: FPGA vs ASIC area
74295: 04/10/07: Re: modelsim crashs with large ram simulation model
76749: 04/12/10: Re: Open source FPGA EDA Tools
77600: 05/01/12: Re: Asynchronous signals and simulation
79571: 05/02/21: Re: Antti Lukats: all my past live projects to be published...
79584: 05/02/21: Re: Antti Lukats: all my past live projects to be published...
79789: 05/02/24: Re: Hardcopy Vs ASIC
80064: 05/03/01: Re: FPGA tool benchmarks on Linux systems
80158: 05/03/02: Re: FPGA tool benchmarks on Linux systems
80161: 05/03/02: Re: FPGA tool benchmarks on Linux systems
89544: 05/09/19: Re: Generating Modelsim Verilog resource libraries - pointers/questions
89583: 05/09/20: Re: Generating Modelsim Verilog resource libraries - pointers/questions
89629: 05/09/21: Re: Generating Modelsim Verilog resource libraries - pointers/questions
90796: 05/10/21: Re: Best Async FIFO Implementation
91453: 05/11/07: Re: PCI test bench
91806: 05/11/14: Re: open-sourced FPGA (vhdl, verilog, C variants) design libraries,
94334: 06/01/10: Re: tcam implemented in fpga
97935: 06/03/02: Re: How do I make dual-port RAM from single port RAM?
98277: 06/03/08: Re: Asynchronous FIFO design question
98668: 06/03/14: Re: How do I handle this memory related issue?
99587: 06/03/27: Re: OpenSPARC released
100071: 06/04/03: Re: ModelSim Designer
111747: 06/11/09: Re: How to simulate netlist with gated clock?
113424: 06/12/13: Re: FPGA : Async FIFO, Programmable full
113471: 06/12/14: Re: FPGA : Async FIFO, Programmable full
113472: 06/12/14: Re: How does FPGA tools infer FIFO
113884: 06/12/28: Re: ethernet checksum nightmare
113890: 06/12/28: Re: ethernet checksum nightmare
114076: 07/01/04: Re: DC timing violation, what to do first?
114347: 07/01/12: Re: ethernet checksum nightmare
114555: 07/01/19: Re: Different Modelsim versions disagree in same backannotation!
114643: 07/01/22: Re: Different Modelsim versions disagree in same backannotation!
115522: 07/02/13: Re: How to develop STM-16 framer in FPGA
115621: 07/02/15: Re: Need fair opinions on choosing either Altera or Xilinx as main
124118: 07/09/12: Re: Stratix III Memory usage efficiency
124205: 07/09/14: Re: Is post-place and route simulation useful?
125218: 07/10/18: Re: FPGA quiz3, or where Antti did give up and does not know answer
125648: 07/10/31: Re: FPGA vs ASIC
126455: 07/11/23: Re: EDK + Modelsim simulation : Memory allocation failure
126804: 07/12/03: Re: What tools do you use ? Why ?
129723: 08/03/04: Re: my Spartan-4 wishlist
130054: 08/03/14: Re: DDR3 speed, Altera vs Xilinx
130559: 08/03/27: Re: Synoplify ???
132297: 08/05/21: Re: Stratix IV Announced
132604: 08/06/03: Re: Are FPGAs headed toward a coarse granularity?
133260: 08/06/23: Re: which commercial HDL-Simulator for FPGA?
134997: 08/09/10: Re: Are Xilinx tools that bad, or am I missing something?
136485: 08/11/19: Re: Aligned PLL clocks in RTL simulation
136786: 08/12/05: Re: Equivalent ASIC Gate Estimate
136852: 08/12/09: Re: FPGA-ASIC Migration
138010: 09/02/04: Re: Spartan-6
138013: 09/02/04: Re: Why the second flip-flop in Virtex-6?
138014: 09/02/04: Re: Why the second flip-flop in Virtex-6?
138024: 09/02/04: Re: Why the second flip-flop in Virtex-6?
138062: 09/02/05: Re: Why the second flip-flop in Virtex-6?
138103: 09/02/06: Re: Experiencing problems when moving an FPGA-based implementation
138530: 09/02/26: Re: Configure FPGA via PCIe
138554: 09/02/27: Re: Configure FPGA via PCIe
138610: 09/03/02: Re: Configure FPGA via PCIe
138617: 09/03/02: Re: Configure FPGA via PCIe
138649: 09/03/03: Re: Configure FPGA via PCIe
138673: 09/03/04: Re: Lattice announces ECP3
138756: 09/03/09: Re: Spartan 6 3.3V (was Re: Virtex6 Virtex4 FPGA compatibility)
140139: 09/04/30: Re: ASIC from working FPGA design
140496: 09/05/15: Re: XILINX license model restricts longtime availability
140583: 09/05/19: Re: XILINX license model restricts longtime availability
140603: 09/05/20: Re: XILINX license model restricts longtime availability
140746: 09/05/25: Re: Muli-Cycle Path Constrains in RTL
141477: 09/06/25: Re: SRAM vs Flash based FPGA one more time
141637: 09/07/02: Re: pinout
141640: 09/07/02: Re: Cheapest FPGA with decent PCI- e interface ?
142913: 09/09/08: Re: Choice of Language for FPGA programming
143065: 09/09/18: Re: To Xilinx: Regarding the download manager
143132: 09/09/23: Re: view memory contents in modelsim
143133: 09/09/23: Re: view memory contents in modelsim
143634: 09/10/19: Re: where can price list of FPGA be found?
143986: 09/11/06: Re: Does anyone ever use placement?
144403: 09/12/04: Re: Does Xilinx sync FIFO use dual port memory? Does this affect
145942: 10/03/01: Re: Frustration with Vendors!
145967: 10/03/02: Re: Frustration with Vendors!
145968: 10/03/02: Re: Spice simulation of IBIS details - model examples
146297: 10/03/11: Re: Tier Logic introduces the world's first 3D FPGA
146298: 10/03/11: Re: Tier Logic introduces the world's first 3D FPGA
146327: 10/03/12: Re: Tier Logic introduces the world's first 3D FPGA
146416: 10/03/17: Re: Any advice on which is the best book on CMOS digital circuit
146436: 10/03/18: Re: Xilinx Spartan6 Virtex6 Rollout
146568: 10/03/23: Re: Why hardware designers should switch to Eclipse
146697: 10/03/26: Re: Xilinx Spartan6 Virtex6 Rollout
147289: 10/04/22: Re: I'd rather switch than fight!
147290: 10/04/22: Re: I'd rather switch than fight!
147504: 10/04/29: Re: xilinx arm finally announced
149671: 10/11/16: Re: cool BGA pattern
151454: 11/04/11: Re: Do people do this by hand?
152755: 11/10/19: Re: Altera FPGA weirdness
153332: 12/02/02: Re: Design Notation VHDL or Verilog?
158995: 16/06/02: Re: Explicitly setting a variable to undefined
Kim Gunnar Enkovaara:
27940: 00/12/15: Re: Verilog or VHDL
27949: 00/12/16: Re: Verilog or VHDL
28174: 00/12/24: Re: Verilog or VHDL
28182: 00/12/25: Re: Verilog or VHDL
Kim Hofmans:
6726: 97/06/19: Re: 100MHz SDRAMs with Xilinx?
6982: 97/07/18: Xabel mapping into xilinx
8058: 97/11/12: Dr watson & M1
8238: 97/12/02: M1 : UCF file problems
8699: 98/01/20: Re: XC4000Xl IOB switch. charact. ???
8698: 98/01/20: XC4000Xl IOB switch. charact. ???
10039: 98/04/23: XC4000XL and Ground Bouncing
10589: 98/06/03: Re: Foundation M1.4 functional simulation problems
16421: 99/05/21: Re: Xilinx M1.5 Crash
Kim Noer:
50094: 02/12/02: WARNING:Xst:646 - Signal <vcc> is assigned but never used ? (ISE 4.2wp2)
50098: 02/12/02: Re: WARNING:Xst:646 - Signal <vcc> is assigned but never used ? (ISE 4.2wp2)
50133: 02/12/03: ISE Impact 4.2 and Windows XP parallel port - works then it doesn't?
Kim Povlsen:
149089: 10/09/30: Re: Spartan 3 DCM problem
149101: 10/10/01: Re: FPGA design not working!
149204: 10/10/07: Re: Add custom Ip to EDK - No result from sw registers
149213: 10/10/08: Re: help with bad synchronous description error
149304: 10/10/15: Re: Newbie question IO pin and Spartan6
149305: 10/10/15: Re: How to disable EDK instantiated IOBs?
kim tae-chang:
14183: 99/01/18: Free max+plus ll simulator on win95
Kim-Ee Yeoh:
56423: 03/06/04: Re: ANN: Confluence -> Python for Hardware Verification
Kimiko Nemoto:
4489: 96/11/05: recent FPGA boards ?
Kin Hing Leung:
613: 95/01/19: Re: [shin]OrCad .sch to Xilinx .xdf conversion seeking
King:
63289: 03/11/19: Embedded Development Kit + performance
65821: 04/02/07: Xilinx EDK and FSL
66487: 04/02/20: Floating point calculation in Microblaze
king:
40028: 02/02/25: Comparison between two FPGAs- what is decisive factor?
101061: 06/04/24: How to avoid lossing channel bonding when using Rocket IO?
101120: 06/04/25: Re: How to avoid lossing channel bonding when using Rocket IO?
101237: 06/04/27: Re: How to avoid lossing channel bonding when using Rocket IO?
101855: 06/05/07: Re: How to avoid lossing channel bonding when using Rocket IO?
108237: 06/09/06: how can I decrease the time cost when synthesis and implement
King ComputerSearch:
11084: 98/07/17: Pre-IPO - Lead Hardware Engineer - Board Level/SONET - Marlborough, MA
king_azman:
93760: 05/12/29: PPC405 on ISE
93957: 06/01/03: Re: PPC405 on ISE
97414: 06/02/21: Cannot use ML310 DDR
97561: 06/02/23: Re: Cannot use ML310 DDR
KingCharles:
136394: 08/11/14: Host driver
kingkang:
68842: 04/04/20: Altera fpga pins problem
73854: 04/09/30: Programming Cyclone 1C20 board
74944: 04/10/22: cyclone config problem in my board
74948: 04/10/22: Re: cyclone config problem in my board
75244: 04/10/31: Board-level clock phase delay calculation in the fpga board?
82124: 05/04/07: Sdram controller on the Altera Cyclone board!
KingOfDisaster:
148855: 10/09/04: We need an administrator for the group to fight spam
154995: 13/03/23: Re: full tcp offload solution with tcp session setup/teardown support
Kip Ingram:
50431: 02/12/10: Re: Tiny Forth Processors
50434: 02/12/10: Re: Tiny Forth Processors
50492: 02/12/11: Re: Power consumption question
50516: 02/12/11: Re: hardware image processing - log computation
50517: 02/12/12: Re: Power consumption question
50568: 02/12/13: Re: hardware image processing - log computation
156066: 13/11/21: Re: Granularity of components for FPGA synthesis?
156067: 13/11/21: Re: Legal Issues Reproducing Old CPU
156069: 13/11/21: Re: Legal Issues Reproducing Old CPU
156103: 13/11/22: Re: Granularity of components for FPGA synthesis?
Kip Mussatt:
27515: 00/11/27: Re: Schematics & VHDL
Kiran:
52606: 03/02/15: Help wanted on Installing Xilinx on Win NT
61282: 03/10/01: Parameterized Multiplier in Xilinx FPGA
71934: 04/08/03: Guidelines for Timing Closure on FPGAs
71986: 04/08/04: Re: Guidelines for Timing Closure on FPGAs
121942: 07/07/16: QuartusII Web Edition software question
122200: 07/07/23: Re: QuartusII Web Edition software question
Kiran Bond:
12652: 98/10/21: 6th Reconfigurable Architectures Workshop (RAW '99)
17413: 99/07/26: Re: Looking for proceedings
Kiran Kumar Bondalapati:
4192: 96/09/24: FPGA Routing Question
Kiran M:
76475: 04/12/03: Dev board to experiment with pci interface?
76988: 04/12/18: Programming Virtex II in slave select MAP mode?
Kiran Nimmagadda:
7118: 97/08/01: Problems with Lattice pDS+
Kiran Puttegowda:
48935: 02/10/27: Hard macro
Kiran V Bulusu:
48003: 02/10/09: Re: Gate array & standard cell based design.
<kiransr.ckm@gmail.com>:
128387: 08/01/24: How to choose an FPGA for High speed applications
129814: 08/03/05: how to optimize a design for speed
<kiredr@nowhere.com>:
Kiren Tanna:
43077: 02/05/13: JVM using FPGAs
Kirill 'Big K' Katsnelson:
18974: 99/11/23: Re: implementing TCP/IP on PLD
60293: 03/09/09: Spartan-3 3S50 in Web ISE 5.2i = no block RAM, no multiplier?
Kirk:
46169: 02/08/20: QDR Controller
49302: 02/11/08: Help on using multiple ABEL sources
Kirk A Daley:
27864: 00/12/13: Synthesis Tools
Kirk A Weedman:
511: 94/12/15: LOGIC MINIMIZATION
566: 95/01/05: OrCad schematics -> Concept Schematics
685: 95/02/06: VERILOG
Kirk George:
46159: 02/08/20: FREE 1/2 day tutorial: "The Xilinx Virtex II PRO - PowerPC 405 Architecture Familiarization"
Kirk Hobart:
2421: 95/12/03: Re: Atmel Web Site
3451: 96/06/01: Re: Xilinx - OrCAD users
3955: 96/08/24: Re: Want to learn FPGA! Please advise......
4130: 96/09/17: Re: manchester clock recovery
Kirk Saban:
20236: 00/02/02: Re: Tools and how little guy is treated (was Xilinx Tools)
30253: 01/03/29: Re: Xilinx Core generator with WebPack ISE
Kirsten and Thomas Rounds:
3766: 96/07/27: Re: ATT serial EEPROMs
Kirstie Wong:
67715: 04/03/17: "WARNING:Xst:528 - Multi-source in Unit <entity> on signal <sig> not replaced by logic."
67728: 04/03/17: Re: "WARNING:Xst:528 - Multi-source in Unit <entity> on signal <sig> not replaced by logic."
67743: 04/03/18: Re: "WARNING:Xst:528 - Multi-source in Unit <entity> on signal <sig> not replaced by logic."
67744: 04/03/18: Re: "WARNING:Xst:528 - Multi-source in Unit <entity> on signal <sig> not replaced by logic."
Kirton Morris:
15698: 99/04/08: Help: Need Tech. Info on PGA's and FPGA's
16094: 99/05/02: Any Material on advances in FPGA Technology
Kishore:
102943: 06/05/23: Verilog vs VHDL
103000: 06/05/24: System Generator Eval version for Malab R2006a
103259: 06/05/29: System Generator cc1 error
105417: 06/07/22: Re: Spartan III development: which tools, what kind of PC?
120643: 07/06/12: Re: xilinx spartan3e kit ddr sdram
<kishore2k4@gmail.com>:
102793: 06/05/20: JTAG chaining of two different Xilinx Spartan 3E boards
<kishoremi2@gmail.com>:
108887: 06/09/18: regarding 4 bit multiplier
kislo:
116943: 07/03/21: Re: OFFSET and Data Clock Skew?
119210: 07/05/15: coregen -> simulation error in modelsim
120886: 07/06/19: Weird behavior in debuggin using XMD
121534: 07/07/06: Debugging in EDK
127148: 07/12/12: Spartan 3e pin question
127181: 07/12/13: Re: Spartan 3e pin question
127336: 07/12/18: BGA reflow soldering using vapor phase
127492: 07/12/28: Spartan 3E 3.3V configuration reverse current situation
128208: 08/01/18: Xpower decoupling network summary
128314: 08/01/22: FPGA decoupling calculation
128323: 08/01/22: Re: FPGA decoupling calculation
128362: 08/01/23: Re: FPGA decoupling calculation
128390: 08/01/24: Re: FPGA decoupling calculation
129537: 08/02/27: SPI indirect programming using spartan 3e
130010: 08/03/12: microblaze to blockram - Byte-Writes
130039: 08/03/13: Re: microblaze to blockram - Byte-Writes
130706: 08/03/30: fpga reset (re-initialize) of spartan3e
130717: 08/03/31: increase memory of microblaze
130722: 08/03/31: Re: increase memory of microblaze
131147: 08/04/12: Spartan3E startup problems
131148: 08/04/12: Re: Spartan3E startup problems
131157: 08/04/13: Re: Spartan3E startup problems
131158: 08/04/13: Re: Spartan3E startup problems
131171: 08/04/14: Chipscope 9.2 in XPS
132048: 08/05/11: RLC package parasitics
132102: 08/05/13: power supply noise margin
132419: 08/05/26: Xilinx IO drive level constrain
132435: 08/05/27: Re: Xilinx IO drive level constrain
Kissingers:
87748: 05/07/30: Re: [JTAG] How to force a FPGA to reprogram itself from a prom with JTAG ?
kits59@gmail.com:
108465: 06/09/11: Simulating EDK 8.1i System using ModelSim 6.1e
108466: 06/09/11: Re: Simulating EDK 8.1i System using ModelSim 6.1e
108512: 06/09/12: Re: Simulating EDK 8.1i System using ModelSim 6.1e
108590: 06/09/13: Re: Simulating EDK 8.1i System using ModelSim 6.1e
KITT:
7410: 97/09/07: University FPGA Project
kittyawake@gmail.com:
83866: 05/05/08: EDK: user logic on opb bus in microblaze system
85378: 05/06/08: linker script
85533: 05/06/10: linker script!!!
86174: 05/06/22: Need some help with understanding MDM
<kittyawake@gmail.com>:
82006: 05/04/05: EDK-Creating new peripheral
82258: 05/04/09: EDK: Microblaze with XMdstub
82313: 05/04/10: Re: EDK: Microblaze with XMdstub
82666: 05/04/15: EDK:input to microblaze
82717: 05/04/16: EDK: microblaze local memory
82808: 05/04/18: Re: EDK:input to microblaze
Kiyoshi Takagi:
48559: 02/10/20: modelsim and linux help
Kiyoung SON:
37267: 01/12/06: where is designed FPGA for apple II computer...?
37268: 01/12/06: where is designed FPGA for APPLE....?
KJ:
20938: 00/02/29: Re: Asynchronous flipflops in Cypress CPLDs with Warp VHDL
34483: 01/08/27: Looking for a synthesizable JPEG coder core
99782: 06/03/29: Re: Keystroke saving w/ IEEE.Numeric_Std
100032: 06/04/01: Re: Doubt about SERDES
100061: 06/04/02: Re: Doubt about SERDES
100062: 06/04/02: Re: Doubt about SERDES
100174: 06/04/04: Re: Altera Stratix II GX LVDS max speed
100605: 06/04/13: Re: PCB Stack
100625: 06/04/13: Re: PCB Stack
100639: 06/04/14: Re: humble suggestion for Xilinx
100651: 06/04/14: Re: PCB Stack
100882: 06/04/20: Re: Is there anything fundamentally wrong with this code?
101128: 06/04/26: Re: Heating problem of the CPLD
101146: 06/04/26: Re: What is the best way to clock data in on one clock edge and out on another?
101485: 06/05/02: Re: Quartus and source control
102881: 06/05/22: Possible output drive strength when using Micron DDR and Stratix II DDR Controller
102913: 06/05/23: Re: Possible output drive strength when using Micron DDR and Stratix II DDR Controller
103025: 06/05/24: Re: Stopping Quartus using multipliers?
103276: 06/05/30: Re: Power Up delay in FPGA !!!!!
103978: 06/06/16: Re: LVTTL or LVCMOS for PCI Signaling?
104174: 06/06/20: Re: Quartus 6.0 Fitter Critical Warning
104197: 06/06/21: Re: Quartus 6.0 Fitter Critical Warning
104934: 06/07/10: Re: The FFs with synchronous reset perform worse?
104978: 06/07/11: Re: The FFs with synchronous reset perform worse?
105005: 06/07/11: Re: Assigning unused pins in Quartus II
105217: 06/07/18: Re: Opencore ddr_controller
105270: 06/07/19: Re: corrupted data when accessing dual port bram in Cyclone II
105297: 06/07/19: Re: corrupted data when accessing dual port bram in Cyclone II
105310: 06/07/20: Re: corrupted data when accessing dual port bram in Cyclone II
105318: 06/07/20: Re: Inferring a Xilinx FIFO
105446: 06/07/23: Re: Hardware book like "Code Complete"?
105463: 06/07/24: Re: ROM implementation
105468: 06/07/24: Re: Hardware book like "Code Complete"?
105488: 06/07/24: Re: Hardware book like "Code Complete"?
105489: 06/07/24: Re: Hardware book like "Code Complete"?
105491: 06/07/24: Re: Hardware book like "Code Complete"?
105494: 06/07/24: Re: Hardware book like "Code Complete"?
105497: 06/07/24: Re: Hardware book like "Code Complete"?
105541: 06/07/25: Re: Hardware book like "Code Complete"?
105542: 06/07/25: Re: Hardware book like "Code Complete"?
105547: 06/07/25: Re: Hardware book like "Code Complete"?
105607: 06/07/27: Re: Spartan 3 clock to output tristate timing
106056: 06/08/07: Re: DDR2 SRAM Stratix II questions
106072: 06/08/07: Re: How do I treat "default" case which is useless?
106082: 06/08/07: Re: How do I treat "default" case which is useless?
106089: 06/08/07: Re: How do I treat "default" case which is useless?
106093: 06/08/07: Re: DDR2 SRAM Stratix II questions
106101: 06/08/07: Re: How do I treat "default" case which is useless?
106105: 06/08/07: Re: DDR2 SRAM Stratix II questions
106107: 06/08/07: Re: DDR2 SRAM Stratix II questions
106272: 06/08/10: Re: Switching two (synchronous) clocks with variable phase difference, without glitching or period loss
106298: 06/08/10: Re: Altera SOPC ModelSim question
106308: 06/08/11: Re: consistancy in synthesis/ simulation model
106377: 06/08/12: Re: Clock domain crossing (again)
106378: 06/08/12: Re: JOP as SOPC component
106381: 06/08/12: Re: JOP as SOPC component
106384: 06/08/12: Re: JOP as SOPC component
106385: 06/08/12: Re: JOP as SOPC component
106394: 06/08/12: Re: JOP as SOPC component
106453: 06/08/13: Re: JOP as SOPC component
106459: 06/08/13: Re: JOP as SOPC component
106463: 06/08/13: Re: JOP as SOPC component
106464: 06/08/13: Re: JOP as SOPC component
106465: 06/08/13: Re: JOP as SOPC component
106482: 06/08/14: Re: JOP as SOPC component
106483: 06/08/14: Re: consistancy in synthesis/ simulation model
106487: 06/08/14: Re: how to declare a Wishbone interface with 4 bit port size and granularity?
106504: 06/08/14: Re: consistancy in synthesis/ simulation model
106510: 06/08/14: Re: JOP as SOPC component
106804: 06/08/20: Re: Problem with "don't care"
106852: 06/08/21: Re: Modelsim SE Simulation
106859: 06/08/21: Re: Newbie frustration
106976: 06/08/23: Re: JOP as SOPC component
107016: 06/08/23: Re: JOP as SOPC component
107028: 06/08/23: USB PHYs and drivers that folks have used
107064: 06/08/24: Re: JOP as SOPC component
107066: 06/08/24: Re: USB PHYs and drivers that folks have used
107110: 06/08/24: Re: JOP as SOPC component
107184: 06/08/25: Re: JOP as SOPC component
107185: 06/08/25: Re: JOP as SOPC component
107189: 06/08/25: Re: JOP as SOPC component
107253: 06/08/25: Re: Style of coding complex logic (particularly state machines)
107298: 06/08/26: Re: USB PHYs and drivers that folks have used
107325: 06/08/26: Re: high level languages for synthesis
107417: 06/08/28: Re: Style of coding complex logic (particularly state machines)
107418: 06/08/28: Re: high level languages for synthesis
107420: 06/08/28: Re: Style of coding complex logic (particularly state machines)
107424: 06/08/28: Re: Style of coding complex logic (particularly state machines)
107438: 06/08/28: Re: Style of coding complex logic (particularly state machines)
107463: 06/08/28: Re: Style of coding complex logic (particularly state machines)
107483: 06/08/29: Re: JOP as SOPC component
107487: 06/08/29: Re: placing addiional caps across existing caps to reduce noise
107577: 06/08/30: Re: JOP as SOPC component
107587: 06/08/30: Re: Style of coding complex logic (particularly state machines)
107591: 06/08/30: Re: Style of coding complex logic (particularly state machines)
107673: 06/08/31: Re: behavioral vs post-P&R simulation mismatch
107795: 06/09/01: Re: bidirectional connection between two bidirectional ports
107799: 06/09/01: Re: bidirectional connection between two bidirectional ports
107963: 06/09/03: Re: Qestion about the ability of synthesis
108081: 06/09/05: Re: bidirectional connection between two bidirectional ports
108105: 06/09/05: Re: Exploring Quartus' Messages and Warnings
108248: 06/09/07: Re: how can I decrease the time cost when synthesis and implement
108333: 06/09/08: Re: ddr with multiple users
108358: 06/09/08: Re: ddr with multiple users
108362: 06/09/08: Re: Negative slack
108374: 06/09/09: Re: Xilinx ISE ver 8.2.02i is optimizing away and removing "redundant" logic - help!
108387: 06/09/10: Re: HOLD violations in Xilinx fpga
108388: 06/09/10: Re: Xilinx ISE ver 8.2.02i is optimizing away and removing "redundant" logic - help!
108389: 06/09/10: Re: how can I decrease the time cost when synthesis and implement
108424: 06/09/11: Re: Xilinx ISE ver 8.2.02i is optimizing away and removing "redundant" logic - help!
108425: 06/09/11: Re: Xilinx ISE ver 8.2.02i is optimizing away and removing "redundant" logic - help!
108426: 06/09/11: Re: ddr with multiple users
108437: 06/09/11: Re: ddr with multiple users
108438: 06/09/11: Re: Xilinx ISE ver 8.2.02i is optimizing away and removing "redundant" logic - help!
108463: 06/09/11: Re: Xilinx ISE ver 8.2.02i is optimizing away and removing "redundant" logic - help!
108464: 06/09/11: Re: Functional and Post-Synthesis Simulation
108499: 06/09/12: Re: Xilinx ISE ver 8.2.02i is optimizing away and removing "redundant" logic - help!
108522: 06/09/12: Re: Xilinx ISE ver 8.2.02i is optimizing away and removing "redundant" logic - help!
108564: 06/09/13: Re: Xilinx ISE ver 8.2.02i is optimizing away and removing "redundant" logic - help!
108948: 06/09/19: Re: resets on synplicity inferred RAMs
109038: 06/09/20: Re: Buffering the critical path.
109338: 06/09/24: Re: Altera Avalon Bus VHDL stop error?
109356: 06/09/25: Re: Now on 8.2.03i Re: Xilinx ISE ver 8.2.02i is optimizing away and removing "redundant" logic - help!
109360: 06/09/25: Re: Altera Avalon Bus VHDL stop error?
109406: 06/09/26: Re: Now on 8.2.03i Re: Xilinx ISE ver 8.2.02i is optimizing away and removing "redundant" logic - help!
109463: 06/09/27: Re: Now on 8.2.03i Re: Xilinx ISE ver 8.2.02i is optimizing away and removing "redundant" logic - help!
109542: 06/09/28: Re: Is it worth learning SOPC Builder, DSP Builder & Nios Processor?
109550: 06/09/28: Re: PUBLISHABLE PAPER RELATED TO FPGA!
109570: 06/09/29: Re: state machine
109571: 06/09/29: Re: bit vs std_logic
109728: 06/10/04: Re: ISE timing errors
109758: 06/10/05: Re: An implementation of a clean reset signal
109764: 06/10/05: Re: ISE timing errors
109765: 06/10/05: Re: ISE timing errors
109769: 06/10/05: Re: An implementation of a clean reset signal
109851: 06/10/06: Re: An implementation of a clean reset signal
109853: 06/10/06: Re: An implementation of a clean reset signal
109854: 06/10/06: Re: Instantiating Altera M4K block without MegaWizard
109860: 06/10/06: Re: Instantiating Altera M4K block without MegaWizard
109862: 06/10/06: Re: Instantiating Altera M4K block without MegaWizard
109865: 06/10/06: Re: An implementation of a clean reset signal
109943: 06/10/09: Re: An implementation of a clean reset signal
109944: 06/10/09: Re: nicer code => slower code??
109977: 06/10/09: Re: An implementation of a clean reset signal
109987: 06/10/09: Re: Antifuse, lower cost?
109992: 06/10/09: Re: An implementation of a clean reset signal
109994: 06/10/09: Re: An implementation of a clean reset signal
109995: 06/10/09: Re: An implementation of a clean reset signal
110011: 06/10/09: Re: An implementation of a clean reset signal
110047: 06/10/10: Re: Quartus II 6.0
110048: 06/10/10: Re: longest webcase record
110104: 06/10/11: Re: Quartus II 6.0: System clock has been set back
110139: 06/10/11: Re: Quartus II 6.0: System clock has been set back
110379: 06/10/14: Re: FPGA comparision
110463: 06/10/16: Re: User peripherals within a Nios system
110475: 06/10/16: Re: longest webcase record -- understandably so
110476: 06/10/16: Re: User peripherals within a Nios system
110518: 06/10/17: Re: Newbie : Please give me an idea about programming an FPGA
110558: 06/10/17: Re: Need info: Altera dual-port & fifo act different (func vs VITAL)
110885: 06/10/25: Re: What should I do with std.textio.all of ModelSim
110919: 06/10/25: Re: Meta-stable problem with MAX-II ?
110941: 06/10/25: Re: Am I seeing meta-stable or what?
111008: 06/10/27: Re: What should I do with std.textio.all of ModelSim
111117: 06/10/29: Re: A pre-emptive strike against blaming the chip
111122: 06/10/30: Re: image processing
111211: 06/10/31: Re: Dual Port RAM
111213: 06/10/31: Re: A pre-emptive strike against blaming the chip
111215: 06/10/31: Re: A pre-emptive strike against blaming the chip
111223: 06/10/31: Re: A pre-emptive strike against blaming the chip
111224: 06/10/31: Re: Dual Port RAM
111246: 06/10/31: Re: Dual Port RAM
111249: 06/10/31: Re: Dual Port RAM
111355: 06/11/02: Re: Spectre of Metastability Update
111357: 06/11/02: Re: Dual Port RAM
111359: 06/11/02: Re: Interface standards (was Re: Dual Port RAM)
111360: 06/11/02: Re: Interface standards (was Re: Dual Port RAM)
111361: 06/11/02: Re: Interface standards (was Re: Dual Port RAM)
111362: 06/11/02: Re: Dual Port RAM
111363: 06/11/02: Re: Dual Port RAM
111377: 06/11/02: Re: Dual Port RAM
111451: 06/11/03: Re: Spectre of Metastability Update
111478: 06/11/03: Re: Spectre of Metastability Update
111527: 06/11/04: Re: Interface standards (was Re: Dual Port RAM)
111546: 06/11/05: Re: Interface standards (was Re: Dual Port RAM)
111566: 06/11/06: Re: Interface standards (was Re: Dual Port RAM)
111567: 06/11/06: Re: reset
111577: 06/11/06: Re: reset
111586: 06/11/06: Re: reset
111881: 06/11/12: Re: Pad to Setup, Clock to Pad
111902: 06/11/13: Re: Pad to Setup, Clock to Pad
111922: 06/11/13: Re: regarding changing serial data out to LVDS form
112136: 06/11/16: Re: Validity of data on rising edge of clock
112157: 06/11/17: Re: Hpw to remove combinational loops in quartus s/w
112312: 06/11/20: Re: Q on duty cycle
113284: 06/12/10: Re: Writing output signals to text file (VHDL)?
113317: 06/12/11: Re: Writing output signals to text file (VHDL)?
113334: 06/12/11: Re: Writing output signals to text file (VHDL)?
113451: 06/12/14: Re: FPGA : Async FIFO, Programmable full
113470: 06/12/14: Re: How does FPGA tools infer FIFO
113486: 06/12/14: Re: FPGA : Async FIFO, Programmable full
113645: 06/12/19: Re: Frequency divider ?
113647: 06/12/19: Re: Frequency divider ?
113727: 06/12/20: Re: Tracing UNKNOWN drivers
113830: 06/12/23: Re: Help with xilinx simulation?
113843: 06/12/24: Re: Signal <foo> is assigned but never used. XST Warning help
113864: 06/12/26: Re: Judge complex degree by state numbers?
113866: 06/12/26: Re: better ways for debugging?
113870: 06/12/26: Re: Help with xilinx simulation?
113881: 06/12/28: Re: Why AHDL didn't catch on like Verilog or VHDL?
113956: 06/12/30: Re: SPI slave problem
113967: 06/12/31: Re: Memory controller design
114003: 07/01/02: Re: Memory controller design
114182: 07/01/06: Re: Problem with unused pin on Spartan 2E
114229: 07/01/08: Re: (-1)*xn operation in FPGA
114247: 07/01/08: Re: dynamically created blockRAM contents?
114397: 07/01/14: Re: Judge complex degree by state numbers?
114749: 07/01/23: Re: NIOS II Application startup issues
114790: 07/01/24: Re: How to make a clock delay?
114976: 07/01/28: Re: How to make an internal signal embedded deep in hierarchy to a gloal output signal
115723: 07/02/17: Re: Xilinx ISE WebPack Simulation Problem
115806: 07/02/21: Re: newbie question
115830: 07/02/21: Re: how to use STD_LOGIC_VECTOR2
115852: 07/02/22: Re: VHDL code for Generating registers
115916: 07/02/25: Re: Making a 32KB BRAM block, virtex-4
115930: 07/02/26: Re: Making a 32KB BRAM block, virtex-4
116264: 07/03/06: Re: VHDL and Latch
116265: 07/03/06: Re: VHDL and Latch
116277: 07/03/06: Re: VHDL and Latch
116304: 07/03/07: Re: VHDL and Latch
116322: 07/03/07: Re: VHDL and Latch
116374: 07/03/07: Re: Introducing picosecond delay between two output signals
116432: 07/03/08: Re: VHDL and Latch
116433: 07/03/08: Re: Large power planes vs. power islands vs. slits for decoupling
116654: 07/03/14: Re: VHDL and Latch
116661: 07/03/15: Re: SEC:U Problem getting rid of bit latch errors
116672: 07/03/15: Re: doubt in verilog coding
116775: 07/03/17: Re: Use of both positive reference and negative reference of the same signal for Xilinx chips would cause additional LUT delay?
117001: 07/03/21: Re: Austin the Altera Mole
117664: 07/04/06: Re: OT Re: Gray code in asynchronous FIFO design.
119138: 07/05/12: Re: how to choose the perfect fpga support
119357: 07/05/17: Re: VHDL newbie: building sequential circuits with basic gates
119453: 07/05/19: Re: VHDL newbie: building sequential circuits with basic gates
119465: 07/05/20: Re: VHDL newbie: building sequential circuits with basic gates
119476: 07/05/21: Re: VHDL newbie: building sequential circuits with basic gates
119481: 07/05/21: Re: Timing not met but working on board
119490: 07/05/21: Re: Filtering the FPGA reset signal
120660: 07/06/13: Re: Unused clock pins tied inactive?
121951: 07/07/16: Re: Timing in Modelsim
121988: 07/07/16: Re: Revisit: Altera vs Xilinx (NIOS II vs Microblaze)
122094: 07/07/19: Re: modelsim Warning "VIOLATION ON D WITH RESPECT TO CLK"
122892: 07/08/09: Re: New Xilinx forum.
122978: 07/08/13: Re: Xilinx 13th August opportunity
123229: 07/08/20: Re: At what frequencies is it acceptable to generate a clock from a register?
123460: 07/08/28: Re: New keyword 'orif' and its implications
123507: 07/08/29: Re: Strange behaviour of a design
123686: 07/09/01: Re: PCB Layers
123710: 07/09/02: Re: Null statement in VHDL
123742: 07/09/03: Re: Null statement in VHDL
123750: 07/09/03: Re: New keyword 'orif' and its implications
123971: 07/09/08: Re: Is it possible to perform gate level simulation on a design without a reset?
123973: 07/09/09: Re: Is it possible to perform gate level simulation on a design without a reset?
124115: 07/09/12: Re: Quick question for an Altera wizard
124182: 07/09/13: Re: Uses of Gray code in digital design
124199: 07/09/14: Re: Is post-place and route simulation useful?
124223: 07/09/14: Re: Uses of Gray code in digital design
124673: 07/09/29: Re: 2 leg crystal on FPGA: Lattice vs Xilinx
124759: 07/10/03: Re: Detecting if an error happened in ModelSim
124844: 07/10/07: Re: Daisy chaining FPGA with CPLDs
125273: 07/10/18: Re: VHDL trivia?
125304: 07/10/19: Re: Error using SOPC builder - "Custom SDRAM" with 8-bits gives error with Signal "az_be_n"
125349: 07/10/23: Re: Changing refresh rate for DRAM while in operation?
125448: 07/10/25: Re: Changing refresh rate for DRAM while in operation?
125512: 07/10/26: Re: Xilinx Isolate circuitry
125594: 07/10/29: Re: FPGA Configuration
125758: 07/11/03: Re: How do I meet this memory IO with least resources on FPGA?
125761: 07/11/03: Re: How do I meet this memory IO with least resources on FPGA?
125835: 07/11/06: Re: not totally repulsive
125876: 07/11/07: Re: Custom processor developement issues
125879: 07/11/07: Re: Custom processor developement issues
126193: 07/11/16: Re: VHDL language is out of date! Why? I will explain.
126240: 07/11/17: Re: Quartus II warning: "pass-through logic has been added"
126243: 07/11/18: Re: Quartus II warning: "pass-through logic has been added"
126259: 07/11/18: Re: synthesizing vqm with parameters with quartus 7.1sp1
126260: 07/11/18: Re: Quartus II warning: "pass-through logic has been added"
126261: 07/11/18: Re: Quartus II warning: "pass-through logic has been added"
126468: 07/11/23: Re: How to simulate these example CORDIC code?
126558: 07/11/27: Re: What's the difference for VHDL code between simulation and
126572: 07/11/28: Re: using fpga as programmable connection
126601: 07/11/28: Re: Behavioral Simulation working but Post-route Simulation is not.
126624: 07/11/28: Re: Gnd plane coupling with DDR routing from FPGA <-> DDR?
126638: 07/11/29: Re: What's the difference for VHDL code between simulation and synthesis?
126667: 07/11/29: Re: Gnd plane coupling with DDR routing from FPGA <-> DDR?
126668: 07/11/29: Re: Gnd plane coupling with DDR routing from FPGA <-> DDR?
126716: 07/11/30: Re: Pipelining of FPGA code
126752: 07/11/30: Re: What's the difference for VHDL code between simulation and synthesis?
126772: 07/12/01: Re: Traffic Light with counter
126837: 07/12/04: Re: What's the difference for VHDL code between simulation and synthesis?
126844: 07/12/04: Re: What's the difference for VHDL code between simulation and synthesis?
126845: 07/12/04: Re: What's the difference for VHDL code between simulation and synthesis?
126901: 07/12/05: Re: why do i see negative clock hold time
126914: 07/12/06: Re: What's the difference for VHDL code between simulation and synthesis?
126948: 07/12/06: Re: How to simulate these example CORDIC code?
126949: 07/12/06: Re: How can I get data from Altera Triple Speed Ethernet (TSE) MAC
126965: 07/12/07: Re: How can I get data from Altera Triple Speed Ethernet (TSE) MAC
126989: 07/12/07: Re: Pin assignment with Quartus II for PCB placement
127005: 07/12/08: Re: How can I get data from Altera Triple Speed Ethernet (TSE) MAC through Avalon bus?
127012: 07/12/08: Re: Which FPGA and memory to use? The eternal X vs. A question.
127018: 07/12/08: Re: DDS generator with interpolated samples for Spartan3E development board
127023: 07/12/09: Re: What's the difference for VHDL code between simulation and synthesis?
127024: 07/12/09: Re: What's the difference for VHDL code between simulation and synthesis?
127288: 07/12/17: Re: What timing constraint value should be set for input/output module?
127341: 07/12/19: Re: sampling error between 2 clocks
127357: 07/12/19: Re: sampling error between 2 clocks
127365: 07/12/19: Re: sampling error between 2 clocks
127374: 07/12/19: Re: sampling error between 2 clocks
127426: 07/12/24: Re: DQS contention with ddr_sdr from Opencores
127448: 07/12/26: Re: Core Generators...
127485: 07/12/28: Re: Core Generators...
127579: 08/01/03: Re: round,fix and floor algortihms
127685: 08/01/05: Re: integer to binary conversion
127686: 08/01/05: Re: question on AND
127687: 08/01/05: Re: question on AND
127691: 08/01/05: Re: integer to binary conversion
127698: 08/01/05: Re: conversion problem
127739: 08/01/07: Re: conversion problem
127788: 08/01/08: Re: Core Generators...
127850: 08/01/09: Re: Real examples of metastability causing bugs
127854: 08/01/09: Re: Real examples of metastability causing bugs
128067: 08/01/14: Re: Complex Multiply
128080: 08/01/14: Re: Complex Multiply
128094: 08/01/15: Re: Complex Multiply
128129: 08/01/16: Re: Quartus II Incremental compilation?
128269: 08/01/19: Re: New user of ModelSim XE III v6.2 Starter - problems simulating a simple RAM.
128324: 08/01/22: Re: FPGA decoupling calculation
128330: 08/01/22: Re: Is it possible to define an Integer so it could be incremented
128334: 08/01/22: Re: Is it possible to define an Integer so it could be incremented
128343: 08/01/22: Re: Is it possible to define an Integer so it could be incremented
128370: 08/01/23: Re: Is it possible to define an Integer so it could be incremented and return to 0.
128461: 08/01/27: Re: FPGA decoupling calculation
128464: 08/01/27: Re: FPGA decoupling calculation
128465: 08/01/27: Re: FPGA decoupling calculation
128467: 08/01/27: Re: FPGA decoupling calculation
128599: 08/01/31: Re: I need a SDRAM controller
128669: 08/02/02: Re: Internal signal names in ModelSim
128776: 08/02/06: Re: Simple Memory Read problem, help appreciated
128782: 08/02/06: Re: Simple Memory Read problem, help appreciated
128827: 08/02/07: Re: Single Top FPGA Tips
128848: 08/02/07: Re: Single Top FPGA Tips
128888: 08/02/08: Re: Question to VHDL code fragment
129034: 08/02/13: Re: setup time not met in Quartus
129095: 08/02/14: Re: setup time not met in Quartus
129197: 08/02/18: Re: Define the primary clock with XST in VHDL
129226: 08/02/19: Re: Strange "Style guide" requirements...
129228: 08/02/19: Re: Efficient division algorithm?
129246: 08/02/19: Re: Efficient division algorithm?
129247: 08/02/19: Re: Efficient division algorithm?
129248: 08/02/19: Re: Efficient division algorithm?
129775: 08/03/05: Re: clock distribution accross boards
129841: 08/03/06: Re: Blast from the past
130000: 08/03/12: Re: infer block ram with mismatched port width
130031: 08/03/13: Re: ALTERA SOPC : ptf-sopc files
130073: 08/03/14: Re: Design entries for FSM
130109: 08/03/14: Re: Detecting a pulse with minimum width
130236: 08/03/18: Re: dual clock fifo
130248: 08/03/18: Re: vhdl type conversions
130250: 08/03/18: Re: vhdl type conversions
130275: 08/03/19: Re: Optimizing an inferred counter
130293: 08/03/19: Re: dual clock fifo
130344: 08/03/20: Re: Is there a means to conditional synthesis in VHDL?
130412: 08/03/22: Re: High speed memory read and transfer via rocket IO..
130452: 08/03/25: Re: BYTE shifter
130586: 08/03/27: Re: VHDL document generation utilities
130651: 08/03/29: Re: async clk input, clock glitches
130660: 08/03/29: Re: async clk input, clock glitches
130663: 08/03/29: Re: async clk input, clock glitches
130687: 08/03/30: Re: Synthesisable Timer in VHDL
130690: 08/03/30: Re: async clk input, clock glitches
130692: 08/03/30: Re: async clk input, clock glitches
130694: 08/03/30: Re: async clk input, clock glitches
130695: 08/03/30: Re: async clk input, clock glitches
130698: 08/03/30: Re: async clk input, clock glitches
130699: 08/03/30: Re: async clk input, clock glitches
130702: 08/03/30: Re: async clk input, clock glitches
130788: 08/04/01: Re: Antii, can you give us an update?
130992: 08/04/08: Re: Avalon Bus <-> Wishbone Bus
131146: 08/04/12: Re: simple example with timing problems
131260: 08/04/17: Re: how do I test signals in a testbench that are 1 or 2 levels down
131307: 08/04/18: Re: New to FPGA : Timing Closure
131400: 08/04/21: Re: synchronous reset problems on FPGA
131404: 08/04/21: Re: Synthesis Comparison
131418: 08/04/21: Re: Synthesis Comparison
131419: 08/04/21: Re: not inferred RAM, on QII
131420: 08/04/21: Re: ANNOUNCE: Maia 0.8.2: module-level HDL verification tool
131431: 08/04/21: Re: ANNOUNCE: Maia 0.8.2: module-level HDL verification tool
131432: 08/04/21: Re: Very simple VHDL problem
131503: 08/04/23: Re: Verilog state machines, latches, syntax and a bet!
131530: 08/04/24: Re: Verilog state machines, latches, syntax and a bet!
131568: 08/04/25: Re: noob question
131610: 08/04/25: Re: Virtex-4 inrush power-on current
131619: 08/04/26: Re: Virtex-4 inrush power-on current
131722: 08/04/30: Re: Style for Highly-Pipelined State Machines
131798: 08/05/02: Re: Quartus v7.x fitting bug
131812: 08/05/02: Re: quick question
131822: 08/05/02: Re: quick question
131832: 08/05/02: Re: Forking in One-Hot FSMs
131833: 08/05/02: Re: Style for Highly-Pipelined State Machines
131867: 08/05/05: Re: Forking in One-Hot FSMs
131876: 08/05/06: Re: Forking in One-Hot FSMs
131877: 08/05/06: Re: Style for Highly-Pipelined State Machines
131994: 08/05/09: Re: 5 V oscillator output to GCLK
132009: 08/05/09: Re: 5 V oscillator output to GCLK
132010: 08/05/09: Re: 5 V oscillator output to GCLK
132011: 08/05/09: Re: 5 V oscillator output to GCLK
132031: 08/05/10: Re: 5 V oscillator output to GCLK
132033: 08/05/10: Re: 5 V oscillator output to GCLK
132251: 08/05/19: Re: I cannot find how to map a "record type" in my ucf file.
132328: 08/05/21: Re: bizarre state machine behavior
132468: 08/05/28: Re: Sequentially syncrhronous
132475: 08/05/28: Re: signal value at power up
132476: 08/05/28: Re: Sequentially syncrhronous
132486: 08/05/28: Re: Sequentially syncrhronous
132493: 08/05/28: Re: Sequentially syncrhronous
132565: 08/05/31: Re: cutoff frequency
132584: 08/06/02: Re: Help with $setuphold
132591: 08/06/02: Re: clock divider
132636: 08/06/04: Re: Counter implementation with ise problem
132653: 08/06/04: Re: Xilinx vs Altera
132707: 08/06/05: Re: ANNOUNCE:-- TimingAnalyzer Free Version -- Draw timing diagrams
132710: 08/06/05: Re: ANNOUNCE:-- TimingAnalyzer Free Version -- Draw timing diagrams
132729: 08/06/05: Re: HDL tricks for better timing closure in FPGAs
132795: 08/06/06: Re: HDL tricks for better timing closure in FPGAs
133096: 08/06/18: Re: Fixed point number hardware implementation
133108: 08/06/18: Re: Synthesis results when testing for 'X' and 'U'
133112: 08/06/18: Re: Fixed point number hardware implementation
133150: 08/06/19: Re: Fixed point number hardware implementation
133309: 08/06/24: Re: Cycle-based or Event-based simulation?
133313: 08/06/24: Re: Migrating to 9.2i from 8.2i
133393: 08/06/26: Re: Xilinx register inits
133394: 08/06/26: Re: Xilinx register inits
133414: 08/06/27: Re: Xilinx register inits
133429: 08/06/28: Re: Standard forms for Karnaugh maps?
133613: 08/07/06: Re: Help to SImulate Uart TX
133724: 08/07/11: Re: Fixed point number hardware implementation
133737: 08/07/12: Re: multicyle and false path in FPGA Design
133742: 08/07/12: Re: How to simulate baud rate generator?
133745: 08/07/12: Re: Strange ddr controller bugs.
133760: 08/07/13: Re: Strange ddr controller bugs.
133761: 08/07/13: Re: Fixed point number hardware implementation
133801: 08/07/15: Re: Fifo Simulation Error
133813: 08/07/16: Re: Fifo Simulation Error
133815: 08/07/16: Re: Fifo Simulation Error
133821: 08/07/16: Re: unified protocol
133956: 08/07/20: Re: Change clock domain for FIFO ...
133985: 08/07/21: Re: why holdtime is not considerd for Tclkmax calculation
134080: 08/07/24: Re: Quartus2 pin assignment
134082: 08/07/24: Re: Quartus2 pin assignment
134114: 08/07/26: Re: Creating new operators
134317: 08/08/06: Re: Altera sues Zilog - signs of desperation from Programmable Vendor
134329: 08/08/06: Re: Altera sues Zilog - signs of desperation from Programmable Vendor
134413: 08/08/09: Re: eliminating individual array registers?
134415: 08/08/09: Re: eliminating individual array registers?
134421: 08/08/09: Re: Block Rams
134439: 08/08/10: Re: eliminating individual array registers?
134462: 08/08/11: Re: Optimizing a LUT-based pow(val, 2.2)
134531: 08/08/16: Re: why does inferred RAM cause synthesis times to explode?
134551: 08/08/17: Re: why does inferred RAM cause synthesis times to explode?
134557: 08/08/18: Re: why does inferred RAM cause synthesis times to explode?
134590: 08/08/20: Re: why does inferred RAM cause synthesis times to explode?
134868: 08/09/04: Re: XST bug on illigal states of a FSM ?
134898: 08/09/05: Re: XST bug on illigal states of a FSM ?
134903: 08/09/05: Re: XST bug on illigal states of a FSM ?
134907: 08/09/06: Re: XST bug on illigal states of a FSM ?
134964: 08/09/08: Re: XST bug on illigal states of a FSM ?
134978: 08/09/09: Re: XST bug on illigal states of a FSM ?
134992: 08/09/09: What version of ISE is availabe for Virtex5?
135058: 08/09/12: Re: Quartus II compile speedup with New Quad Core Intel machine
135165: 08/09/18: Re: Clock Enable safe?
135171: 08/09/19: Help~ How to develope with FPGA board?
135177: 08/09/19: Re: Clock Enable safe?
135251: 08/09/23: Re: Use of divided clocks inside modules
135252: 08/09/23: Re: duty cycle significance
135257: 08/09/23: Re: Use of divided clocks inside modules
135263: 08/09/23: Re: Use of divided clocks inside modules
135313: 08/09/25: Please recommend good textbook or technical report about FPGA
135334: 08/09/26: Re: Clocking Sync Burst SRAM
135352: 08/09/27: Re: 50 Ohm Analog Output of FPGA
135361: 08/09/28: Re: Clocking Sync Burst SRAM
135364: 08/09/28: Re: Clocking Sync Burst SRAM
135380: 08/09/29: Re: Clocking Sync Burst SRAM
135397: 08/09/30: Re: reasonable timing analysis without mapping design to IO
135445: 08/10/02: Re: Low frequency clock generation - need help
135522: 08/10/06: Re: Low frequency clock generation - need help
135568: 08/10/08: Re: How to synthesize a delay of around 10 ns in FPGA?
135598: 08/10/09: Re: Xilinx VHDL inferred RAMs
135725: 08/10/13: converting MATLAB to VHDL
135738: 08/10/14: Re: sensitive fpga
135877: 08/10/20: Re: Cyclone III, DP RAM, and Verilog
135971: 08/10/24: Re: again: statemachine bug in Quartus II Web Edition Software v8.0
136022: 08/10/28: Re: FPGA RAM clock connection
136090: 08/10/30: Re: ISE 9.2.03i problem
136098: 08/10/31: Re: ISE 9.2.03i problem
136199: 08/11/05: Re: Critical Path
136247: 08/11/07: Re: Setting FSM encoding in VHDL or in UCF for Xilinx
136248: 08/11/07: Re: Setting FSM encoding in VHDL or in UCF for Xilinx
136254: 08/11/07: Re: Setting FSM encoding in VHDL or in UCF for Xilinx
136262: 08/11/07: Re: Setting FSM encoding in VHDL or in UCF for Xilinx
136263: 08/11/07: Data transfer between CPU and FPGA over PCI bus
136308: 08/11/10: Re: Altera Quartus DDR2 Megacore function: local_address input: row, col, bank?
136398: 08/11/14: Re: Number of GCLKs: 9 out of 8 112% (OVERMAPPED)
136483: 08/11/18: how to implement an application with external memory in ISE?
136519: 08/11/19: Re: how to implement an application with external memory in ISE?
136583: 08/11/23: Re: hi need help in VHDL code For Input sequence Design
136690: 08/12/01: Re: simulation results is correct but synthesis result is not correct
136703: 08/12/02: Re: simulation results is correct but synthesis result is not correct
136745: 08/12/03: Re: Relationship between high and low speed clocks
136749: 08/12/03: Re: Relationship between high and low speed clocks
136750: 08/12/03: Re: Relationship between high and low speed clocks
136751: 08/12/03: Re: Relationship between high and low speed clocks
136762: 08/12/04: Re: Timing analysis of related clocks
136858: 08/12/09: Re: Inverting bus connection order in Verilog
136867: 08/12/09: Re: Sampling a clock
136871: 08/12/10: Re: Sampling a clock
136876: 08/12/10: Re: Sampling a clock
136897: 08/12/11: Re: Sampling a clock
136958: 08/12/16: Re: i2c interface
136972: 08/12/16: Re: i2c interface
136973: 08/12/16: Re: i2c interface
136978: 08/12/16: Re: i2c interface
136979: 08/12/16: Re: i2c interface
137016: 08/12/18: Re: Looking for a strategy to identify nets in post-map netlist
137041: 08/12/20: Re: PLL and clock in altera cyclone 2 fpga
137141: 08/12/27: Re: Generation of WR and RD signal for ASYNC FIFO
137355: 09/01/10: Re: what is the difference between two process model & one process model
137368: 09/01/12: Re: what is the difference between two process model & one process model
137386: 09/01/13: Re: Counter: natural VS std_logic_vector
137393: 09/01/13: Re: Counter: natural VS std_logic_vector
137420: 09/01/15: Re: Counter: natural VS std_logic_vector
137437: 09/01/16: Re: Counter: natural VS std_logic_vector
137587: 09/01/22: Altera Stratix II can support Floating point operators?
138060: 09/02/04: Re: Core interface protocol
138128: 09/02/06: Re: clk synchronization of reset signal
138180: 09/02/08: Re: clk synchronization of reset signal
138458: 09/02/23: Re: Cyclone2 4-phase clock generation
138524: 09/02/25: Re: Converting state machine encoding to std_logic_vector
138655: 09/03/03: Re: Re-synthesizing with minor changes
138660: 09/03/03: Re: Re-synthesizing with minor changes
138732: 09/03/06: Re: 2 Modules working independently but not together on FPGA
138766: 09/03/09: Re: Timing requirements for generating off-chip clock with DDR
139011: 09/03/18: Re: false path assignment for clock boundary crossing.
139077: 09/03/19: Re: Xilinx XAPP052 LFSR and its understanding
139305: 09/03/25: Re: FPGAs in automotive apps
139308: 09/03/25: Re: FPGAs in automotive apps
139575: 09/04/04: Re: Modulo-10 counter
139576: 09/04/04: Re: Modulo-10 counter
139815: 09/04/14: Re: reset & analog circuits
139825: 09/04/15: Re: What is the minimum acceptable slack on a signal
140049: 09/04/25: Re: Noise in Stratix3?
140053: 09/04/25: Re: Noise in Stratix3?
140298: 09/05/07: Re: problem during port mapping
140308: 09/05/08: Re: Quartus II negative bus dimensions in Schematic file
140334: 09/05/09: Re: difficulty during processing
140335: 09/05/09: Re: difficulty during processing
140738: 09/05/23: Re: Port assignment question
140930: 09/05/29: Re: I don't like xilinx (again)
141540: 09/06/26: Re: New feauture in Spartan-6 FPGA's: SELF DESTRUCT !!
141915: 09/07/16: Re: Using OPEN in port map
141965: 09/07/20: Re: How do you handle build variants in VHDL?
142022: 09/07/22: Re: How do you handle build variants in VHDL?
142033: 09/07/22: Re: How do you handle build variants in VHDL?
142042: 09/07/22: Re: How do you handle build variants in VHDL?
142043: 09/07/22: Re: How do you handle build variants in VHDL?
142252: 09/07/30: Re: Using OPEN in port map
142264: 09/07/30: Re: Using OPEN in port map
142274: 09/07/31: Re: Using OPEN in port map
142416: 09/08/10: Re: Using OPEN in port map
142464: 09/08/12: Re: Is it possible to use OSERDES and ISERDES primitives internal to
142485: 09/08/12: Re: Is it possible to use OSERDES and ISERDES primitives internal to
142529: 09/08/14: Re: Using carry chain of counters for term count detect
142582: 09/08/18: Re: Post sythesys vs FPGA board implementation
142688: 09/08/26: Re: Why there is multi-source error in these VHDL code?
142739: 09/08/29: Re: Does ModelSim or any simulator software have a function similar
143060: 09/09/17: Re: VHDL: obtaining the length of a record
143122: 09/09/22: Re: VHDL question
143123: 09/09/22: Re: VHDL question
143130: 09/09/22: Re: VHDL question
143131: 09/09/22: Re: VHDL question
143139: 09/09/23: Re: Xilinx XST and counter synthesis problem
143337: 09/10/02: Re: Very interesting finding about V4 CLB configuration bits
143505: 09/10/13: Re: ASIC Prototyping using FPGA
143543: 09/10/15: Re: What is the basis on flip-flop replaced by a latch
143579: 09/10/16: Re: What is the basis on flip-flop replaced by a latch
143586: 09/10/16: Re: What is the basis on flip-flop replaced by a latch
143610: 09/10/18: Re: What is the basis on flip-flop replaced by a latch
143620: 09/10/18: Re: FSM-states after reconf.
143629: 09/10/19: Re: FSM-states after reconf.
143770: 09/10/24: Re: Generating delay using logic gates
143843: 09/10/29: Re: Best way to model a large external ROM in a simulation? (XST
143857: 09/10/30: Re: Simple state machine output question
143864: 09/10/30: Re: Simple state machine output question
144019: 09/11/07: Re: Does anyone ever use placement?
144169: 09/11/16: Re: Having trouble with Xilinx timing constraints
144207: 09/11/19: Re: AvalonST to Avalon MM Bridge
144229: 09/11/20: Re: AvalonST to Avalon MM Bridge
144311: 09/11/25: Re: Going mad trying to solve PLL setup/hold timing violation issues
144336: 09/11/27: Re: Going mad trying to solve PLL setup/hold timing violation issues
144339: 09/11/27: Re: Going mad trying to solve PLL setup/hold timing violation issues
144344: 09/11/28: Re: Going mad trying to solve PLL setup/hold timing violation issues
144360: 09/11/30: Re: XST 11.2 Takes a lot of memory and never completes the synthesis
144386: 09/12/02: Re: This works, this does not... why?
144387: 09/12/02: Re: This works, this does not... why?
144422: 09/12/05: Re: This works, this does not... why?
144510: 09/12/12: Re: post route simulation
144519: 09/12/12: Re: Does a 1-bit mux glitch if only one input is known to change at
144523: 09/12/12: Re: Does a 1-bit mux glitch if only one input is known to change at
144533: 09/12/13: Re: Does a 1-bit mux glitch if only one input is known to change at
144538: 09/12/13: Re: Does a 1-bit mux glitch if only one input is known to change at
144539: 09/12/13: Re: Does a 1-bit mux glitch if only one input is known to change at
144551: 09/12/14: Re: Power dynamic managment in FPGA design
144567: 09/12/15: Re: what is Timing generating before interfacing?
144568: 09/12/15: Re: what is Timing generating before interfacing?
144611: 09/12/20: Re: Memory Latency
144640: 09/12/21: Re: Memory Latency
144744: 09/12/30: Re: VHDL: assignment to two different fields of the record in two
144745: 09/12/30: Re: More details: VHDL: assignment to two different fields of the
144747: 09/12/30: Re: More details: VHDL: assignment to two different fields of the
144759: 09/12/30: Re: ADC problem on spartan3E
144761: 09/12/30: Re: ADC problem on spartan3E
144956: 10/01/17: Re: Simulation of VHDL code for a vending machine
144966: 10/01/17: Re: Simulation of VHDL code for a vending machine
144967: 10/01/17: Re: Simulation of VHDL code for a vending machine
144977: 10/01/18: Re: Simulation of VHDL code for a vending machine
145517: 10/02/12: Re: VHDL vs Verilog
145658: 10/02/17: Re: How a state machine is constructed using latches?
145930: 10/02/28: Re: Frustration with Vendors!
145940: 10/02/28: Re: Frustration with Vendors!
146133: 10/03/06: Re: Modelsim PE vs. Aldec Active-HDL (PE)
146134: 10/03/06: Re: Modelsim PE vs. Aldec Active-HDL (PE)
146153: 10/03/06: Re: Modelsim PE vs. Aldec Active-HDL (PE)
146734: 10/03/26: Re: PCB routing issues for sync SRAM
146760: 10/03/27: Re: PCB routing issues for sync SRAM
146771: 10/03/28: Re: PCB routing issues for sync SRAM
146772: 10/03/28: Re: PCB routing issues for sync SRAM
146832: 10/03/29: Re: PCB routing issues for sync SRAM
146848: 10/03/30: Re: PCB routing issues for sync SRAM
146922: 10/04/01: Re: Which is the most beautiful and memorable hardware structure in a
146953: 10/04/03: Re: Is there a way to implement division by variables other than 2 in
146990: 10/04/08: Re: Summing with carry problems ...
147043: 10/04/11: Re: I'd rather switch than fight!
147049: 10/04/12: Re: I'd rather switch than fight!
147065: 10/04/12: Re: I'd rather switch than fight!
147327: 10/04/22: Re: confusion with ADC/DAC interface implementation
147328: 10/04/22: Re: I'd rather switch than fight!
147330: 10/04/22: Re: I'd rather switch than fight!
147337: 10/04/23: Re: I'd rather switch than fight!
147338: 10/04/23: Re: I'd rather switch than fight!
147369: 10/04/23: Re: I'd rather switch than fight!
147541: 10/04/30: Re: I'd rather switch than fight!
147542: 10/04/30: Re: I'd rather switch than fight!
147549: 10/05/01: Re: I'd rather switch than fight!
147550: 10/05/01: Re: Synplify constraint problem
147552: 10/05/01: Re: Synplify constraint problem
147578: 10/05/04: Re: FIFO Depth Calculation
147579: 10/05/04: Re: FIFO Depth Calculation
147584: 10/05/05: Re: FIFO Depth Calculation
147616: 10/05/07: Re: sopc builder custom component and passing parameters to VHDL
147621: 10/05/08: Re: I'd rather switch than fight!
147628: 10/05/09: Re: I'd rather switch than fight!
147629: 10/05/09: Re: repeting outputs of counter
147653: 10/05/12: Re: I'd rather switch than fight!
147718: 10/05/18: Re: Xilinx Synthesis Tool generates clock signals from combinatorial
148194: 10/06/26: Re: Free bitmap font
148440: 10/07/22: Re: Using std_ulogic at synthesis level
148441: 10/07/22: Re: Using std_ulogic at synthesis level
148444: 10/07/23: Re: Using std_ulogic at synthesis level
148452: 10/07/24: Re: Using std_ulogic at synthesis level
148457: 10/07/24: Re: Altera EDA Netlist Writer
148458: 10/07/24: Re: Weighted Round Robin Arbiter
148471: 10/07/26: Re: Connecting "signed" to "std_logic_vector" ports.
148472: 10/07/26: Re: Connecting "signed" to "std_logic_vector" ports.
148476: 10/07/26: Re: sdram stable clock
148493: 10/07/27: Re: RS-Latch
148513: 10/07/28: Re: Connecting "signed" to "std_logic_vector" ports.
148514: 10/07/28: Re: Connecting "signed" to "std_logic_vector" ports.
148521: 10/07/29: Re: Connecting "signed" to "std_logic_vector" ports.
148540: 10/07/30: Re: Connecting "signed" to "std_logic_vector" ports.
148576: 10/08/03: Re: Connecting "signed" to "std_logic_vector" ports.
148596: 10/08/04: Re: Vendor Tool Stability
148597: 10/08/04: Re: Connecting "signed" to "std_logic_vector" ports.
148622: 10/08/09: Re: VHDL newbie- stuck just weeks before project submission
148624: 10/08/09: Re: Signal value clears for no reason [VHDL, ISE 10.1]
148633: 10/08/10: Re: Multiple builds with different top-level generic
148637: 10/08/10: Re: Signal value clears for no reason [VHDL, ISE 10.1]
148724: 10/08/18: Re: VDHL initializing
148736: 10/08/18: Re: VDHL initializing
148833: 10/08/31: Re: dct verilog
148930: 10/09/11: Re: Question about OC PCI Cores
149008: 10/09/20: Re: Xilinx XST and a State Machine - A Mystery
149009: 10/09/20: Re: Xilinx XST and a State Machine - A Mystery
149066: 10/09/27: Re: Xilinx XST and a State Machine - A Mystery
149102: 10/10/01: Re: FPGA design not working!
149282: 10/10/13: Re: FSM Problem with inout signal
149597: 10/11/09: Re: Statemachine debugging with Chipscope
149620: 10/11/11: Re: Statemachine debugging with Chipscope
149633: 10/11/12: Re: Statemachine debugging with Chipscope
149699: 10/11/17: Re: Using a single port SRAM
149724: 10/11/20: Re: Multiple Reset Inputs
149739: 10/11/21: Re: Multiple Reset Inputs
149741: 10/11/21: Re: Procedures and Registers
149794: 10/11/24: Re: Altera EP2C8A -- dead PLL
150062: 10/12/08: Re: Concurrent Logic Timing
150184: 10/12/29: Re: Error in Clock Divider!
150225: 11/01/03: Re: Error in Clock Divider!
150226: 11/01/03: Re: Error in Clock Divider!
150227: 11/01/03: Re: Timing violation when initializing "some" FSMs and not others
150255: 11/01/05: Re: Error in Clock Divider!
150286: 11/01/07: Re: Error in Clock Divider!
150416: 11/01/18: Re: Verilog Book for VHDL Users
150516: 11/01/25: Re: FPGA changes behaviour when the resource's usage percentage changes
150616: 11/01/27: Re: Simple clock question
150787: 11/02/10: Re: Designing in Altium
150788: 11/02/10: Re: Simple clock question
150791: 11/02/10: Re: Simple clock question
150892: 11/02/19: Re: Mathematical definition of an FPGA
151191: 11/03/14: Re: ping pong buffer overflow issue
151317: 11/03/22: Re: Via in Hyperlynx linesim
151343: 11/03/25: Re: Measuring the delay between two rising edges in modelsim
151441: 11/04/08: Re: Do people do this by hand?
151575: 11/04/20: Re: Free Model Foundry USB3300
151635: 11/04/27: Re: same RTL on two same boards giving different behaviour
151637: 11/04/27: Re: same RTL on two same boards giving different behaviour
151755: 11/05/14: Re: Counter clocks on both edges sometimes, but not when different IO
151767: 11/05/15: Re: Counter clocks on both edges sometimes, but not when different IO
151806: 11/05/18: Re: Scoping a glitch
151807: 11/05/18: Re: Counter clocks on both edges sometimes, but not when different IO
151818: 11/05/20: Re: Scoping a glitch
151823: 11/05/21: Re: Can a glitch-free mux be designed in an FPGA?
151825: 11/05/21: Re: Can a glitch-free mux be designed in an FPGA?
151827: 11/05/21: Re: Scoping a glitch
151828: 11/05/21: Re: Can a glitch-free mux be designed in an FPGA?
151884: 11/05/30: Re: Package constants (VHDL)
151996: 11/06/20: Re: Sporadic simulation result with modelsim
152014: 11/06/21: Re: Sporadic simulation result with modelsim
152020: 11/06/22: Re: Sporadic simulation result with modelsim
152225: 11/07/22: Re: Post-map simulation: timing violation and delays
152345: 11/08/10: Re: Verilog, VHDL, sync and async resets
152444: 11/08/23: Re: vhdl:passing generic sized arrays to functions?
152447: 11/08/23: Re: vhdl:passing generic sized arrays to functions?
152593: 11/09/16: Re: clock enable for fixed interval
152684: 11/09/30: Re: VHDL problem
152702: 11/10/04: Re: macro
152703: 11/10/04: Re: Testbench
152847: 11/10/27: Re: Clock Phase Fun on Cyclone III
153267: 12/01/22: Re: clock enable question
153269: 12/01/22: Re: clock enable question
153298: 12/01/28: Re: Design Notation VHDL or Verilog?
153410: 12/02/18: Re: problem with Global Clock pin and normal IO pin as Clock input
153506: 12/03/19: Re: Record type <-> std_logic_vector conversion - Python script
153512: 12/03/20: Re: Record type <-> std_logic_vector conversion - Python script
153546: 12/03/27: Re: FPGA communication with a PC (Windows)
153926: 12/06/29: Re: The definition of comnatorial prcess?
153936: 12/07/01: Re: The definition of comnatorial prcess?
153937: 12/07/01: Re: The definition of comnatorial prcess?
153943: 12/07/01: Re: The definition of comnatorial prcess?
153945: 12/07/02: Re: Generate a pulse with a definite width
153947: 12/07/02: Re: The definition of comnatorial prcess?
153951: 12/07/02: Re: Generate a pulse with a definite width
153963: 12/07/04: Re: The definition of comnatorial prcess?
154012: 12/07/11: Re: Completely puzzled: Strange shift register behaviour
154022: 12/07/12: Re: Completely puzzled: Strange shift register behaviour
154026: 12/07/13: Re: Completely puzzled: Strange shift register behaviour
154027: 12/07/13: Re: Completely puzzled: Strange shift register behaviour
154515: 12/11/22: Re: Set-up and hold times and metastability
154568: 12/11/28: Re: VHDL expert puzzle
154585: 12/11/29: Re: VHDL expert puzzle
154609: 12/11/30: Re: VHDL expert puzzle
154617: 12/12/01: Re: VHDL expert puzzle
154633: 12/12/03: Re: VHDL expert puzzle
155136: 13/04/25: Re: Modelsim ought to be cheaper
155507: 13/07/09: Re: VHDL syntheses timestamp
155610: 13/07/29: Re: seperate high speed rules for HDL?
156155: 13/12/23: Re: Use of latches in FSMs
156268: 14/02/01: Re: PathFinder Source Code (in C)
156399: 14/03/28: Re: Xilinx ISERDESE2 deserializer primitive behaviour
156418: 14/04/03: Re: Simulation deltas
156422: 14/04/03: Re: Simulation deltas
156430: 14/04/04: Re: Simulation deltas
156435: 14/04/05: Re: Simulation deltas
156442: 14/04/06: Re: Simulation deltas
156450: 14/04/07: Re: Simulation deltas
156520: 14/04/14: Re: Help: Altera megafunctions, Quartus II
156524: 14/04/14: Re: more than 58'000 false paths...
156532: 14/04/15: Re: more than 58'000 false paths...
156593: 14/05/06: Re: The USB FPGA?
156623: 14/05/14: Re: Undriven outputs of a module in Quartus II Synthesis
156636: 14/05/17: Re: Undriven outputs of a module in Quartus II Synthesis
156686: 14/06/04: Re: Partial Reconfiguration clock enable problem
156812: 14/07/03: ECP5 support in Latest Diamond 3.2 IDE from Lattice ( 64-bit Linux
156832: 14/07/06: Re: ECP5 support in Latest Diamond 3.2 IDE from Lattice ( 64-bit
157279: 14/11/17: Re: disadvantages of inferring latches
157281: 14/11/17: Re: disadvantages of inferring latches
157289: 14/11/17: Re: disadvantages of inferring latches
157293: 14/11/17: Re: disadvantages of inferring latches
157315: 14/11/20: Re: Bypass Xilinx flexlm license check
157326: 14/11/22: Re: Bypass Xilinx flexlm license check
157330: 14/11/22: Re: Bypass Xilinx flexlm license check
157445: 14/12/10: Re: VHDL Synchronization- two stage FF on all inputs?
157509: 14/12/13: Re: VHDL Synchronization- two stage FF on all inputs?
157587: 14/12/22: Re: How to automatically allocate multiple bit fields into constant
157652: 15/01/20: Re: Altera Cyclone II
157672: 15/01/22: Re: Send a pulse across clocks
157830: 15/04/06: Question about summation function
158023: 15/07/10: Re: Calculate dynamic power at fmax in Quartus
158057: 15/07/30: Re: fifo or sdram bug?
158063: 15/07/30: Re: fifo or sdram bug?
158121: 15/08/11: Re: Strange way to route design.
158129: 15/08/13: Re: fifo or sdram bug?
158136: 15/08/14: Re: fifo or sdram bug?
158137: 15/08/14: Re: fifo or sdram bug?
158140: 15/08/14: Re: fifo or sdram bug?
158145: 15/08/14: Re: fifo or sdram bug?
158148: 15/08/18: Re: Finally! A Completely Open Complete FPGA Toolchain
158315: 15/10/20: Re: Sum of 8 numbers in FPGA
158394: 15/10/29: Re: recovery/removal timing
158396: 15/10/29: Re: recovery/removal timing
158399: 15/10/29: Re: recovery/removal timing
158401: 15/10/29: Re: recovery/removal timing
158404: 15/10/29: Re: recovery/removal timing
158415: 15/10/30: Re: recovery/removal timing
158418: 15/10/30: Re: recovery/removal timing
158424: 15/10/30: Re: recovery/removal timing
158516: 15/12/15: Re: modulo 2**32-1 arith
158517: 15/12/15: Re: modulo 2**32-1 arith
158520: 15/12/16: Re: modulo 2**32-1 arith
158521: 15/12/16: Re: modulo 2**32-1 arith
158525: 15/12/16: Re: modulo 2**32-1 arith
158526: 15/12/16: Re: modulo 2**32-1 arith
158528: 15/12/16: Re: modulo 2**32-1 arith
158529: 15/12/16: Re: modulo 2**32-1 arith
158665: 16/03/04: Re: How to define a counter whose width is big enough to hold integer 27?
158681: 16/03/07: Re: How to define a counter whose width is big enough to hold integer 27?
158688: 16/03/07: Re: How to define a counter whose width is big enough to hold integer 27?
158690: 16/03/08: Re: How to define a counter whose width is big enough to hold integer 27?
158700: 16/03/27: Re: FPGA Internal or external USB PHY/SIE ??
158771: 16/04/07: Re: FPGA Internal or external USB PHY/SIE ??
158862: 16/05/12: Re: Using an FPGA to drive the 80386 CPU on a real motherboard
158934: 16/05/25: Re: Explicitly setting a variable to undefined
159092: 16/07/27: Re: Vivado parses wicked slow
159319: 16/10/05: Re: How do I preserve Hazard safety terms?
159326: 16/10/06: Re: How do I preserve Hazard safety terms?
159441: 16/11/10: Re: Latch/flip flip without the use of process
159525: 16/12/02: Re: Phrasing!
159530: 16/12/02: Re: Phrasing!
159532: 16/12/02: Re: Phrasing!
160206: 17/08/06: Re: sram
160209: 17/08/06: Re: sram
160210: 17/08/06: Re: sram
160214: 17/08/06: Re: sram
160215: 17/08/06: Re: sram
160218: 17/08/06: Re: sram
160219: 17/08/06: Re: sram
160449: 18/01/23: Clock distribution /Resynchronizing
160467: 18/01/25: Clock distribution /Resynchronizing
160491: 18/02/16: Scripts to maintain list of addresses in VHDL core communicating with
160853: 18/12/06: Re: How to make Altera-Modelsim free download version to work?
160855: 18/12/06: Re: How to make Altera-Modelsim free download version to work?
160862: 18/12/08: Re: How to make Altera-Modelsim free download version to work?
160882: 18/12/13: Re: What is the name of the circuit structure that generates a state
160883: 18/12/13: Re: What is the name of the circuit structure that generates a state
160889: 18/12/14: Re: What is the name of the circuit structure that generates a state
160890: 18/12/14: Re: How to make Altera-Modelsim free download version to work?
160893: 18/12/14: Re: How to make Altera-Modelsim free download version to work?
160904: 18/12/15: Re: What is the name of the circuit structure that generates a state
160908: 18/12/16: Re: What is the name of the circuit structure that generates a state
160909: 18/12/16: Re: What is the name of the circuit structure that generates a state
160910: 18/12/16: Re: What is the name of the circuit structure that generates a state
160938: 18/12/23: Re: What is the name of the circuit structure that generates a state
160940: 18/12/23: Re: What is the name of the circuit structure that generates a state
160957: 19/01/05: Can I use Verilog or SystemVerilog to write a state machine with
160970: 19/01/07: Re: Can I use Verilog or SystemVerilog to write a state machine with
160980: 19/01/08: Re: Can I use Verilog or SystemVerilog to write a state machine with
160982: 19/01/08: Re: Can I use Verilog or SystemVerilog to write a state machine with
160983: 19/01/08: Re: Can I use Verilog or SystemVerilog to write a state machine with
160986: 19/01/08: Re: Can I use Verilog or SystemVerilog to write a state machine with
160993: 19/01/09: Re: Can I use Verilog or SystemVerilog to write a state machine with
160995: 19/01/09: Re: Can I use Verilog or SystemVerilog to write a state machine with
161005: 19/01/09: Re: Can I use Verilog or SystemVerilog to write a state machine with
161010: 19/01/10: Re: Can I use Verilog or SystemVerilog to write a state machine with
161209: 19/03/14: Implementation of Modbus Slave using only FPGA, without any softcore
161358: 19/04/22: Re: FIFO timing, the right way
161424: 19/08/09: Re: VHDL TIME support in Vivado
161425: 19/08/09: Re: Why differences between Merly-type and Moore-type clock-gated
161432: 19/08/12: Re: VHDL TIME support in Vivado
161444: 19/09/25: Re: How to write a correct code to do 2 writes to an array on same cycle?
161446: 19/09/25: Re: How to write a correct code to do 2 writes to an array on same cycle?
161454: 19/09/26: Re: New keyword "if_2" for HDL is suggested for dealing with 2-write
161455: 19/09/26: Re: How to write a correct code to do 2 writes to an array on same cycle?
161459: 19/09/26: Re: How to write a correct code to do 2 writes to an array on same cycle?
161461: 19/09/27: Re: Here is new definition for keyword "if_2", version 2.
161532: 19/11/26: Re: New coding method for a state machine in groups in HDL
161543: 19/11/28: Re: New coding method for a state machine in groups in HDL
161557: 19/11/29: Re: New coding method for a state machine in groups in HDL
161573: 19/11/30: Re: New coding method for a state machine in groups in HDL
161574: 19/11/30: Re: New coding method for a state machine in groups in HDL
161578: 19/12/03: Re: New coding method for a state machine in groups in HDL
161648: 20/02/13: How to generate bits info for a record structure?
161653: 20/02/14: Re: How to generate bits info for a record structure?
161659: 20/02/14: Re: How to generate bits info for a record structure?
161682: 20/04/03: Re: No more gate-level simulation. for Cyclone V !!!
161690: 20/04/16: Re: No more gate-level simulation. for Cyclone V !!!
<KJ>:
80449: 05/03/06: Re: Newby Getting started with FPGA
<Kjacek@cyanic.org>:
84411: 05/05/18: XPS: Create/Import File structure
<kjasapara@yahoo.com>:
115506: 07/02/12: Unable to load FPGA image from the prom
kjc:
129178: 08/02/17: Re: Xilinx BSCAN primitives proper use
Kjetil Eriksen Vistnes:
64728: 04/01/12: The Fifo in xapp258
kjhales:
43576: 02/05/24: Targeting Virtex with WebPack
<kjhales@catalpatechnology.com>:
109171: 06/09/21: Xilinx MIG fails
109247: 06/09/22: Re: Xilinx MIG fails
kk:
97220: 06/02/19: Did anyone doing research on power electronics control using FPGA?
KK6GM:
150612: 11/01/27: Simple clock question
KKay:
110177: 06/10/11: Cyclone PLL
<kkdeep@my-deja.com>:
28329: 01/01/07: which fpga architecture?
28620: 01/01/18: what placement and route tool?
29069: 01/02/05: in-out pad uasage in fpga compiler II
<kkhan@airmail.net>:
8751: 98/01/23: Re: hdl, schematic, simulation, graphical front ends: (was xilinx stock)
8664: 98/01/18: ahdl to vhdl
kkoorndyk:
123776: 07/09/04: vnavigator problem
123923: 07/09/07: Re: Clock boundary crossing
126976: 07/12/07: Re: Synplify .sdc file
127965: 08/01/11: Re: Cant capture data with Chipscope 7.1
130384: 08/03/21: Actel SX-A Timing Constraints Issues
130390: 08/03/21: Re: Actel SX-A Timing Constraints Issues
132912: 08/06/10: Re: Deskew Clock on Synchronous Bus
133202: 08/06/20: Re: which commercial HDL-Simulator for FPGA?
138296: 09/02/13: Re: MicroBlaze Programming
144252: 09/11/23: Re: How to script Xilinx ISE - xflow, batch file, tcl, ?
145139: 10/01/29: Re: FPGA Editor - Post Route Simulation after changes in Ncd file
146028: 10/03/04: Re: Laptop for FPGA design?
147363: 10/04/23: Re: OFFSET and OFFSET out
148836: 10/09/01: Re: Xilinx Series 7 device availability
149767: 10/11/23: Re: Synthesis/place and route with Solid-State Drives
149788: 10/11/24: Re: Synthesis/place and route with Solid-State Drives
157138: 14/10/17: Re: Non-project mode Vivado simulation?
157201: 14/10/31: Re: XILINX PCIe read of slow device
157809: 15/03/31: Re: Intel in Talks to buy Altera
157924: 15/05/13: Re: ZYNQ temperature
159641: 17/01/25: Re: VHDL Editors (esp. V3S)
160660: 18/09/04: Re: What to do with an improved algorithm?
161051: 19/01/26: Re: Altera Cyclone replacement
161059: 19/01/28: Re: Altera Cyclone replacement
161063: 19/01/30: Re: Altera Cyclone replacement
161092: 19/01/31: Re: ARM + FPGA CPU Module running Yocto Linux?
161373: 19/06/13: Re: bare-metal ZYNQ
kkps:
45776: 02/08/05: AES (rijndael) Ip core
<kkumar@northernpower.com>:
90224: 05/10/06: FPGA behaviour when its used resource is >90% ?
kl31n:
78005: 05/01/22: Power Analisys with MicroBlaze
78067: 05/01/24: Re: Power Analisys with MicroBlaze
78082: 05/01/24: Re: Power Analisys with MicroBlaze
78083: 05/01/24: Re: Power Analisys with MicroBlaze
78095: 05/01/24: Re: Power Analisys with MicroBlaze
93067: 05/12/13: Xilinx floating point core 1.0
93122: 05/12/14: Re: Xilinx floating point core 1.0
93124: 05/12/14: Re: Xilinx floating point core 1.0
<klaro@my-deja.com>:
23886: 00/07/14: Re: Dual Port RAM
Klaus:
136164: 08/11/04: Critical Path
136165: 08/11/04: Re: Critical Path
136168: 08/11/04: Re: Critical Path
136175: 08/11/04: Re: Critical Path
136196: 08/11/05: Re: Critical Path
Klaus Bickert:
90569: 05/10/17: Re: Xilinx IMPACT Problem... detects 101 unknown devices
Klaus Bickertt:
90187: 05/10/06: Re: Xilinx IMPACT Problem... detects 101 unknown devices
Klaus Falser:
6980: 97/07/18: Production testing of Design with CPLD's
16400: 99/05/20: Re: Onboard JTAG-programming Xilinx CPLD with Found.Series?
16402: 99/05/20: Makefile for Xilinx Foundation 1.4
16883: 99/06/16: Re: 3 Questions with XILINX CPLD
17324: 99/07/21: Xilinx CPLD ChipViewer
17812: 99/09/07: Re: xilinx software
18029: 99/09/24: Problems with Xilinx Webpack 2.1
18539: 99/10/29: Problems with Xilinx CPLD's
18792: 99/11/16: Re: WHERE can I find xc9536_v2.bsd??!
19146: 99/12/02: Re: data serializer/decoder FPGA solution
20017: 00/01/24: Re: Easy to program PLD
20469: 00/02/11: Re: Xilinx error message
21071: 00/03/06: Xilinx Parallel Cable III and 3.3V
21924: 00/04/07: Re: Power up set
21981: 00/04/11: Re: setup and hold time violation
21982: 00/04/11: Re: Xilinx Foundation 2.1 error
22870: 00/05/29: Re: Fitting problems with WebPack
22995: 00/06/08: Re: Xilinx foundation Student Edition problem.
24164: 00/07/28: Re: implementation problem of Foundation 2.1i
24173: 00/07/28: FPGAExpress fe_shell and FSM encoding
24175: 00/07/28: Re: FPGAExpress fe_shell and FSM encoding
24300: 00/08/03: Re: foundation 2.1i problems
25456: 00/09/12: Re: Clock skew in XILINX CPLD
25915: 00/09/26: Re: Using the xilinx "pull-up to 5V" in VHDL
25942: 00/09/27: Re: Using the xilinx "pull-up to 5V" in VHDL
25976: 00/09/28: Re: FPGA Express pb
26424: 00/10/16: Re: palasm
26729: 00/10/26: Re: timing simulation with Xilinx and Fusion/SpeedWave
27060: 00/11/09: Re: problem with XC95288 with PC-104
27408: 00/11/21: Re: Xilinx and Tri state I/O
27536: 00/11/28: Re: 150MHz LVDS vs. 75MHz TTL
27627: 00/11/30: Re: 150MHz LVDS vs. 75MHz TTL
27905: 00/12/14: Re: Decoding output from incremental encoder...
27997: 00/12/19: Re: JTAG protocol
28332: 01/01/08: Re: Jedec to tms/tdi wiggles
28708: 01/01/22: Re: About programming cables
29147: 01/02/08: VHDL-Mode
29295: 01/02/13: Re: Programming a CPLD
29340: 01/02/15: Re: Programming a CPLD
29870: 01/03/14: Re: Xilinx webpack supported pachages
30029: 01/03/21: Re: Do I need to tie unused CPLD pins to GND?
30061: 01/03/22: Re: Do I need to tie unused CPLD pins to GND?
30105: 01/03/23: Re: what to do with I/O pins during powerup or during jtag programming
30201: 01/03/28: Re: Powerup problems with XC9500XL
30873: 01/05/02: Re: Shannon Capacity
30874: 01/05/02: Re: Shannon Capacity
30912: 01/05/03: Re: Shannon Capacity
31232: 01/05/16: Re: Can't drive?
31519: 01/05/29: Re: Help on LVDS
31641: 01/06/01: Re: gated clock: simple question
32080: 01/06/13: Re: Xilinx webpack annoyances (long and whiny)
32449: 01/06/27: Re: clock speed in XC95288XL
33379: 01/07/25: Re: Homemade Xilinx parallel cable problem
33422: 01/07/26: Re: Homemade Xilinx parallel cable problem
33594: 01/07/31: Re: Schematic user info
33907: 01/08/08: Re: interfacing XILINX XC95 to PC parallell port
34054: 01/08/13: Re: PCI Postcode Display
35102: 01/09/21: Hitop Warning hi434
35445: 01/10/05: Beware : Xilinx JTAG programmer Impact does not support older XC9500s
62601: 03/11/03: Re: Xilinx Weback 6.1i - Java Exception
63045: 03/11/13: Re: fitting Xilinx CPLD - I/O Pin Termination
63415: 03/11/21: XC9500 design does not fit into Coolrunner
63535: 03/11/25: Re: XC9500 design does not fit into Coolrunner
63701: 03/12/01: Re: XC9500 design does not fit into Coolrunner
67249: 04/03/09: Re: LVDS
67779: 04/03/19: Re: LVDS
72956: 04/09/09: Re: VHDL code for 16-32 bit counter for quadrature encoder signals (A-B)
75390: 04/11/04: Re: XILINX Webpack VHDL synthesis question (unnecessary MUX infered)
81464: 05/03/24: Re: Xilinx backups
81892: 05/04/04: Re: XC95108 problem
83044: 05/04/22: Re: Simulation in modelsim.... Multiple Drivers.......
83045: 05/04/22: Re: Xilinx ISE Warning: FF/Latch <> is unconnected in block <>
84444: 05/05/19: Re: Problems with Constraints (Xilinx, ISE 6.3)
85488: 05/06/10: Re: ISE/EDK 6.3 vs 7.1...
86579: 05/06/30: Re: PROM Generation question
86581: 05/06/30: Re: PROM Generation question
88171: 05/08/11: Re: Cypress CY7B923/33 models
90233: 05/10/07: Re: Question about metastability that's been on my mind for a while
97740: 06/02/27: Re: The 95108 cpld is getting heated when connected by CRO
114402: 07/01/15: Gigabit Ethernet UDP/IP
114404: 07/01/15: Re: Gigabit Ethernet UDP/IP
115192: 07/02/02: Re: XST broken for XC9536?
Klaus Mayer:
128697: 08/02/04: 4-bit table look-up
128701: 08/02/04: Re: 4-bit table look-up
Klaus Mitskowski:
104271: 06/06/22: Amirix AP120, U-Boot and uartlite
Klaus Niedermayer:
135122: 08/09/17: Random Mask Generation on FPGAs
135125: 08/09/17: Re: Random Mask Generation on FPGAs
Klaus Petersen:
133037: 08/06/14: Simulate Microblaze in System Generator
133336: 08/06/25: Writing to memory shared with System Generator
Klaus Schleisiek:
77139: 04/12/25: Re: Clock Synchronization
77140: 04/12/25: Synchronous design and power consumption
77147: 04/12/25: PS: Synchronous design and power consumption
Klaus Vestergaard Kragelund:
45305: 02/07/18: Xilinx XC9500/XC9500XL versus XC5200 Questions
45504: 02/07/24: 8bit Magnitude Comparator
45508: 02/07/24: Re: 8bit Magnitude Comparator
45509: 02/07/24: Re: 8bit Magnitude Comparator
45511: 02/07/25: Re: 8bit Magnitude Comparator
49292: 02/11/07: Re: WebPACK 5.1 SP2
50284: 02/12/07: Re: CPLD current measurement
54828: 03/04/19: Re: Webpack 5.2 Install problems?
55259: 03/05/01: Re: Low power, high temperature CPLD
56414: 03/06/04: Re: An FPGA is flying to Mars
58025: 03/07/12: Re: Graduation Day: My first 4-layer PCB
62235: 03/10/22: Re: 74 logic to CPLD. how easy for a Newbie?
63811: 03/12/04: Re: Command line in Windows?
Klaus-Guenter Leiss:
3711: 96/07/19: Re: Atmel EEPROMs 17C65: again
6693: 97/06/16: Re: ATMEL 17Cxxx ISP function ( no change of RESET/_OE )
30939: 01/05/04: Re: Serial UART
42269: 02/04/19: Re: 8051 Core for Motor Electronics
42372: 02/04/22: Re: 8051 Core for Motor Electronics
43561: 02/05/24: Re: Time for a new computer. Suggestions?
Klee:
20269: 00/02/03: wrong ID from XC9536
20280: 00/02/03: capacitor !
Klemen:
48545: 02/10/20: problems with Insight 2S100 demo board
48596: 02/10/21: Re: problems with Insight 2S100 demo board
48911: 02/10/26: for what do you use fpga's
49192: 02/11/04: new to fpga, what language is better to start with
58147: 03/07/15: mac & phy interface
Kleven Bingham:
60001: 03/09/03: Re: HDL Designer from Mentor
Klix:
55891: 03/05/22: Nois generator - project
55924: 03/05/23: Re: Nois generator - project
Kload:
50709: 02/12/18: Different Versions of Coregen
52718: 03/02/20: Bus Attributes in Xilinx 2.1i Schematic Editor
59906: 03/09/01: What does + synthesize to?
62109: 03/10/20: Virtex CLB
62111: 03/10/20: Re: Virtex CLB
62248: 03/10/23: Strange Timing Problem
62253: 03/10/23: Re: Strange Timing Problem
62254: 03/10/23: Another strage timing problem
62495: 03/10/31: TNM on Tristate buffers
kmawjood:
141419: 09/06/23: XUPV2P board and EDK 10.1
<kmk1978@gmail.com>:
123305: 07/08/23: how to bidirectional signal in xilinx EDK tool ?
kmlpatel@gmail.com:
89364: 05/09/13: Re: ISE 7.1i & Linux / reg code question
107735: 06/08/31: Re: How to active a disappeared HDL source file in the project of ISE webpack
118633: 07/05/01: Re: ise9.1i regid not working on x64
KMS:
144943: 10/01/16: Re: Simulation of VHDL code for a vending machine
kn:
42115: 02/04/16: Need Help to Implement Div Operation
knguyen:
14091: 99/01/12: Re: smallest DCT algorithm?
knight:
134705: 08/08/26: Saving PAR Constraints
134725: 08/08/27: Timing analyser
134736: 08/08/28: Re: Timing analyser
134737: 08/08/28: Re: Saving PAR Constraints
134943: 08/09/07: Signed multiplication
135124: 08/09/17: 1QN representation
135223: 08/09/22: Re: 1QN representation
135925: 08/10/21: Interesting EDK error !!!
135927: 08/10/22: Re: Interesting EDK error !!!
135947: 08/10/23: Re: Interesting EDK error !!!
136184: 08/11/04: EDK 9.1, Lwip stack, Generate Library and BSPs error
136393: 08/11/14: MAC PHY Configuration
138618: 09/03/02: ODDR output to use internally
138623: 09/03/02: Re: ODDR output to use internally
138790: 09/03/10: Xilinx TEMAC Core
139521: 09/04/02: Maximum frequency
Knoll:
66625: 04/02/24: Re: Free PCI-bridge in VHDL for Spartan-IIE
66655: 04/02/24: Re: Free PCI-bridge in VHDL for Spartan-IIE
<knowak@natlab.research.philips.com>:
18353: 99/10/18: PREP benchmarks
Knut Arne Vedaa:
8732: 98/01/22: FAQ?
8799: 98/01/27: Opinions wanted on PLD selection
Knut Tvete:
2429: 95/12/05: Median filter
2430: 95/12/05: Median filter
2431: 95/12/05: Median filter
2432: 95/12/05: Median filter
2433: 95/12/05: Median filter
Kobayashi,:
39450: 02/02/11: Re: Multiple clock domein synchronization.
<kobelai15@gmail.com>:
122967: 07/08/12: edk+uclinux ??? <about make dep>
122976: 07/08/13: Re: edk+uclinux ??? <about make dep>
123088: 07/08/15: about mb-gcc error???
koce:
127128: 07/12/12: Re: Altera ByteBlaster II schematic
koch@mikro.uni-stuttgart.de:
3196: 96/04/23: Re: 8051-type macrocell available
<kode@bridgeport.edu>:
29634: 01/03/02: Differences in VHDL coding for FPGA & CPLD
<kodtest99@yahoo.com>:
33090: 01/07/17: Help me please in one test.
koen Gadeyne:
6659: 97/06/10: Re: ATMEL 17Cxxx ISP function
Koen Van Renterghem:
53671: 03/03/19: Bit patching of Xilinx VIRTEX-II devicex?
112447: 06/11/22: Virtex 4 Internal Tristate (BUFT)?
112560: 06/11/24: Re: run a counter without a clock
113425: 06/12/13: Ones' complement addition
113473: 06/12/14: Re: Ones' complement addition
114040: 07/01/03: Re: Bitstream programming
114559: 07/01/19: Re: Ones' complement addition
114701: 07/01/23: Re: Ones' complement addition
114913: 07/01/26: Re: Timing Diagram Tool
<koen.gadeyne@barco.company>:
17750: 99/08/30: Xilinx Synopsis bug (with exploit :-) [ was: Re: FPGA Express: Not enough storage...(etc.)]
Koenraad Schelfhout:
11647: 98/08/28: [Fwd: FGPA-express : is there a way to use scripts ?]
11642: 98/08/28: FGPA-express : is there a way to use scripts ?
12229: 98/10/06: Re: RAM Implementation in Altera Flex10K100A
14608: 99/02/06: Re: dual port RAM on XC4000
31009: 01/05/09: Re: SYnopsys Library Compiler and LUT synthesis
Koenraad Schelfhout VH14 8993:
6826: 97/07/01: Which Xilinx devices of the 40xxE, 40xxEX series available ?
7481: 97/09/16: Choosing a good pin assignment for multiple-xilinx prototype.
7492: 97/09/17: Re: Choosing a good pin assignment for multiple-xilinx prototype.
8059: 97/11/13: changing default eprom output in MaxPlusII
8390: 97/12/12: Re: what is metastability time of a flip_flop
8788: 98/01/27: comparing asic gates with gates in FPGA's
8812: 98/01/28: Re: comparing asic gates with gates in FPGA's
8857: 98/02/02: equivalent number of gates for a 4-input look-up table ?
9129: 98/02/23: Re: PROBS W/ ALTERA MAX+PLUS II 8.2 S/W
9152: 98/02/25: MaxPlus2 : incomplete menu texts
9151: 98/02/25: Re: PROBS W/ ALTERA MAX+PLUS II 8.2 S/W
9795: 98/04/06: Re: VHDL in synopsys -> M1
10271: 98/05/08: Re: Xilinx Routing Delay
10510: 98/05/26: Re: Partitioning an a large design in Altera's Max+Plus II
11075: 98/07/17: Re: Shift Invarient Bit Transform
koethe.daniel.de@googlemail.com:
138339: 09/02/16: Re: DDR3 with Spartan-3
kofeyok:
73186: 04/09/15: question about types in VHDL
73423: 04/09/21: Re: question about types in VHDL
koh bongseok:
10941: 98/07/06: Altera MAX+PLUS 8.1
10940: 98/07/06: Altera MAX+PLUS 8.1
Koh Kim Huat:
237: 94/09/30: AT&T ORCA FPGA
401: 94/11/08: Re: Xilinx chip partitioning
847: 95/03/12: Re: FPGA multi-chip modules ?
=?KOI8-R?B?4NLBIPLVzdHOw8XX?=:
141471: 09/06/25: Re: SRAM vs Flash based FPGA one more time
=?koi8-r?B?88HXwSD2ydfBzs/XyT8gKFNhdmEgWnhpdmFub3ZpY2gp?=:
20904: 00/02/26: ISP in the Field
20916: 00/02/27: Re: Generating a Higher Frequency Clock from a Lower One in FPGA
Koichi Suzuki:
7909: 97/10/29: Re: Altera EPC1 and Chipmaster 6000
10096: 98/04/27: Re: MAXPLUS II ver7.1 & EPM 7128LC84,7160LC84
10097: 98/04/27: Re: Altera 10K20 Configuration problem
<kojung@gmail.com>:
78848: 05/02/08: Re: xil_printf not working as expected (cont.)
Kolaga Gold:
9869: 98/04/09: Xilinx XC9500 series -- software?
10172: 98/04/30: Re: Q: XILINX Foundation
Kolaga Xiuhtecuhtli:
12922: 98/11/05: Re: New free FPGA CPU
15974: 99/04/24: Xilinx FPGA eval board
15984: 99/04/25: Re: Xilinx FPGA eval board
kolar:
150680: 11/02/03: Dynamic Voltage switching for FPGA IO
150738: 11/02/08: Looking for Level Shifter supporting dual voltage 3.3V/2.9V and 1.8V
Kolin Paul:
47727: 02/10/02: Help on Selecting FPGA Board
47729: 02/10/02: Re: TCP/IP in FPGA
47730: 02/10/02: Re: TCP/IP in FPGA
47778: 02/10/03: Re: Help on Selecting FPGA Board
49019: 02/10/29: Re: Information--conference paper
49960: 02/11/26: Re: Anybody know of vendors of PCI boards with FPGAs?
50194: 02/12/04: FPGA Actual Power Measurement
50233: 02/12/05: Re: FPGA Actual Power Measurement
50236: 02/12/05: Re: FPGA Actual Power Measurement
Kolja:
138767: 09/03/09: Re: FPGA IO Routing
138872: 09/03/12: Re: speeding hough tranformation in microblaze
138892: 09/03/13: Re: DMCA and Google Groups
138955: 09/03/16: Re: SPI controller for FPGA
139368: 09/03/27: Re: best soft core(s) that have C compiler support
139399: 09/03/28: Re: best soft core(s) that have C compiler support
139642: 09/04/08: Re: Two stage synchroniser,how does it work?
139855: 09/04/16: Re: What is the minimum acceptable slack on a signal
140794: 09/05/26: Re: Adders with multiple inputs?
141138: 09/06/08: Re: Where are new Xilinx FPGAs ?
141509: 09/06/26: Re: IF board for fpga?
141583: 09/06/28: Re: 6/6 infos
141848: 09/07/13: Re: How to implementa an FSM in block ram
142279: 09/08/01: Re: Single ended LVDS into FPGA
142431: 09/08/11: Re: algorithm implementation in IC
142885: 09/09/05: Re: Interfacing variable-speed functional units
142891: 09/09/06: Re: Choice of Language for FPGA programming
143039: 09/09/16: Re: 8 phase clock output
143346: 09/10/04: Re: Very interesting finding about V4 CLB configuration bits
Kolja Sulimm:
35770: 01/10/17: Re: System Gates
Kolja Sulimma:
29945: 01/03/19: Spartan-II VREF and VCCO
29946: 01/03/19: Re: Virtex USB solution
29949: 01/03/19: IRDY/TRDY (was Re: More detailed Spartan II CLB drawings?)
29959: 01/03/19: Re: IRDY/TRDY (was Re: More detailed Spartan II CLB drawings?)
29960: 01/03/19: Re: TOA measurement
29962: 01/03/19: Re: Spartan-II VREF and VCCO
29969: 01/03/19: Re: TOA measurement
29979: 01/03/20: Re: TOA measurement
29994: 01/03/20: Re: TOA measurement
30013: 01/03/20: Re: TBUFs in Virtex and later chips, going out of fashion, what instead
30016: 01/03/20: Re: IRDY/TRDY (was Re: More detailed Spartan II CLB drawings?)
30030: 01/03/21: Re: IRDY/TRDY (was Re: More detailed Spartan II CLB drawings?)
30031: 01/03/21: Re: IRDY/TRDY (was Re: More detailed Spartan II CLB drawings?)
30107: 01/03/23: Re: Looking for Processor Core info/advice
30131: 01/03/24: Re: How to find out where par placed things?
30141: 01/03/25: No inputs on XC9536XL
30143: 01/03/25: Re: No inputs on XC9536XL
30205: 01/03/28: Re: No inputs on XC9536XL
30236: 01/03/29: Re: Recommended Oscillators for DLL's at 25 MHz
30268: 01/03/30: Re: HAL-15
30417: 01/04/07: Re: FPGA configuration from processor
30426: 01/04/07: Re: xilinx price lists
30457: 01/04/09: Re: small, fast, w/ PECL?
30495: 01/04/11: Re: How to specify Spartan2 GSR/GTS for Synthesis
30530: 01/04/12: Re: Is this realistic?
30531: 01/04/12: Re: Is this realistic?
30558: 01/04/17: Re: PCMCIA implemented with Xilinx. Spec info needed.
30565: 01/04/17: Re: compression
30570: 01/04/17: Download Cable Mystery Solved
30682: 01/04/23: Re: looking for comment on implementation
30716: 01/04/25: Re: SPARTAN vs VERTEX
30766: 01/04/28: Re: Setting Pins High
30775: 01/04/28: Re: Comparison of FPGA and DSP
30783: 01/04/28: Re: C++ To Gates
30790: 01/04/29: Re: C++ To Gates
30803: 01/04/30: Re: C++ To Gates
30804: 01/04/30: Re: C++ To Gates
30812: 01/04/30: Re: FPGA-CPLD
30841: 01/05/01: Re: C++ To Gates
30859: 01/05/01: Re: High resolution time measurement?
30870: 01/05/02: Re: High resolution time measurement?
30871: 01/05/02: Re: ccd imaging with fpga
30895: 01/05/02: Re: Shannon Capacity
30898: 01/05/02: Re: Serial UART
30913: 01/05/03: Re: FPGA application survey question
30927: 01/05/03: Re: Serial UART
30940: 01/05/04: Re: FPGA application survey question
31014: 01/05/09: Re: Virtex-2 - experiences ?
31067: 01/05/10: Re: Finally, an FPGA tool chain for Linux (Altera Quartus II)
31084: 01/05/11: Re: Finally, an FPGA tool chain for Linux (Altera Quartus II)
31115: 01/05/12: Re: Finally, an FPGA tool chain for Linux (Altera Quartus II)
31116: 01/05/12: Re: Finally, an FPGA tool chain for Linux (Altera Quartus II)
31122: 01/05/12: Re: Finally, an FPGA tool chain for Linux (Altera Quartus II)
31126: 01/05/12: Re: Implementation Of LUT in Vertex-E
31176: 01/05/14: Re: Huffman decoders
31201: 01/05/15: Re: SRAM fpga cell
31276: 01/05/17: Re: Xilinx Service Pack 8 Now Available
31523: 01/05/29: Re: xilinx webpack warning !!
31529: 01/05/29: Re: Spartan2 PCI-IP Core @ power-up
31573: 01/05/30: Re: Is anybody using FPGAs for scientific computing?
31674: 01/06/02: Re: Spartan2 PCI-IP Core @ power-up
31676: 01/06/02: Re: Spartan2 PCI-IP Core @ power-up
31709: 01/06/04: Re: one state machine
31716: 01/06/04: Re: one state machine
31752: 01/06/05: Re: one state machine
31774: 01/06/05: Re: one state machine
31865: 01/06/07: Re: one state machine
31910: 01/06/08: Re: On the prices of the FPGA and how to buy it
31920: 01/06/08: Re: Studentlab with Xilinx tools
31954: 01/06/09: Re: Flash programming via FPGA's JTAG ????
32006: 01/06/10: Re: one state machine
32035: 01/06/11: Re: On the prices of the FPGA and how to buy it
32060: 01/06/12: Re: Doing Ethernet in a Virtex ?
32150: 01/06/16: Re: Virtex II multiplier question
32151: 01/06/16: Re: Virtex II multiplier question
32422: 01/06/26: Re: Alpha Particle
32435: 01/06/26: Stupid Xilinx Patent
32437: 01/06/26: Re: Stupid Xilinx Patent
32452: 01/06/27: Re: Stupid Xilinx Patent
32486: 01/06/27: Re: Stupid Xilinx Patent
32487: 01/06/28: Re: Stupid Xilinx Patent
32488: 01/06/28: Re: Xilinx Patent
32489: 01/06/28: Re: Cheap ECL-TTL translator
32531: 01/06/29: Re: Clock Speed using Modern ASIC technology
32533: 01/06/29: Re: Newbee and FAQ
32582: 01/07/01: Re: Newbee and FAQ
32656: 01/07/04: Re: xr16vx: a GPL 16-bit xr16 microcontroller in JHDL
32685: 01/07/05: Re: clock frequency synthesizer for FPGA
32816: 01/07/10: Re: What chip!?
32852: 01/07/10: How do I distribute cores?
32862: 01/07/10: Re: How do I distribute cores?
32894: 01/07/11: Re: How do I distribute cores?
32918: 01/07/11: Re: need help implementing state diagram of a 2input mealy machine!
33776: 01/08/04: Re: Homemade Xilinx parallel cable problem + new question
33777: 01/08/04: Re: multi-context FPGA
34312: 01/08/20: Re: Virtex-II and 5V devices
34433: 01/08/24: Re: SmartMedia
34482: 01/08/27: Re: Slowing PCI for FPGA
34654: 01/09/01: Re: Defending Austin Franklin
35546: 01/10/10: Re: Help reading from SmartMedia cards
35560: 01/10/10: Re: 155MHz to DLL in Spartan II
35684: 01/10/13: Re: I need free PCI-Core (vhdl)!!
35744: 01/10/16: Re: System Gates
35879: 01/10/22: Looking for benchmark bitstreams
36045: 01/10/27: Re: Cloning someone else's IP core
36083: 01/10/28: Re: Cloning someone else's IP core
36144: 01/10/31: Re: Field Programmable Logic in energy poor environments
36145: 01/10/31: Re: Cloning someone else's IP core
36146: 01/10/31: Re: Cloning someone else's IP core
36147: 01/10/31: Re: Cloning someone else's IP core
36215: 01/11/02: Re: Cloning someone else's IP core
36216: 01/11/02: Re: Field Programmable Logic in energy poor environments
36264: 01/11/04: Re: Field Programmable Logic in energy poor environments
44000: 02/06/08: Re: divide by 5
44288: 02/06/16: Re: fpga and ultra highspeed counters
44368: 02/06/18: Re: what's the use of BlockRAM
44369: 02/06/18: Re: Seeking CPLD/FPGA recomendation
44524: 02/06/22: Re: fpga and ultra highspeed counters
44756: 02/06/29: Re: 5V tolerance
45974: 02/08/13: Xilinx XST inferred Block-RAM Initialization
46176: 02/08/21: Re: I2C License
46228: 02/08/22: Re: I2C License
46906: 02/09/11: Re: XCR3384XL availability
47156: 02/09/19: XST ROM Synthesis
47161: 02/09/19: Re: Xilinx ISE5.1 and Windows NT
47301: 02/09/23: Re: Xilinx ISE5.1 and Windows NT
47900: 02/10/07: Re: LPT voltage level and Xilinx CPLD programming?
47912: 02/10/07: Re: .13 micron - what does it indicate
47966: 02/10/08: Re: LPT voltage level and Xilinx CPLD programming?
47972: 02/10/08: Re: LPT voltage level and Xilinx CPLD programming?
48303: 02/10/15: Re: DIY Xilinx Parallel Cable III
48591: 02/10/21: Using MXE II starter as a restricted user
48684: 02/10/22: Re: Using MXE II starter as a restricted user
48686: 02/10/22: Re: 6502 core available
49386: 02/11/11: Re: LU-decomposition
49807: 02/11/21: Re: Xilinx programming and PCI printer port
50024: 02/11/28: Re: question about programmable oscillator ?
50426: 02/12/10: Re: FPGA/PCI on low budget
50840: 02/12/20: Re: A/D converter in FPGA
51803: 03/01/22: Re: Lecroy Research Systems - what happened?
52060: 03/01/30: Re: Huffman Encoder and Decoder in verilog/ vhdl
52673: 03/02/18: Re: PCMCIA + FPGA/CPLD
52674: 03/02/18: Re: PCB Design for a Xilinx Spartan-II FPGA
52771: 03/02/21: Re: PCB Design for a Xilinx Spartan-II FPGA
52898: 03/02/25: Re: Delay element in Virtex2
52987: 03/02/27: Re: Spartan II PCB, I/O pins consederations
53441: 03/03/13: Re: [Xilinx] Looking for Parallel Cable III ...
53442: 03/03/13: Re: Buying memory for FPGA...
53537: 03/03/15: Re: What is the diff between FPGA and CPLD?
53886: 03/03/26: Re: FPGA specs
53938: 03/03/27: Re: FPGA specs
54062: 03/04/01: Re: Xilinx announces 90nm sampling today!
55109: 03/04/27: Re: visualising a shift register using an LUT
55629: 03/05/14: Re: XC9536 - how to make my own programing device for this chip ?
55809: 03/05/20: Re: smallest embedded cpu.
56084: 03/05/28: Re: High-Speed Clock & Data Recovery
56546: 03/06/09: Re: Xilinx Spartan download with Parallel III cable
56891: 03/06/18: Re: BCH or Hamming Code
57891: 03/07/09: Re: Rant mode ON
58080: 03/07/14: Re: Graduation Day: My first 4-layer PCB
58721: 03/07/31: Re: Pricing question....
58766: 03/08/01: Re: Pricing question....
58974: 03/08/05: Re: Patent granted for "system on a chip" framework?
59754: 03/08/27: Re: How to listen to music through an FPGA pin?
59924: 03/09/01: Re: Moving Sum
61517: 03/10/06: Re: Digesting runs of ones or zeros "well"
62168: 03/10/21: Re: CPU vs. FPGA vs. RAM
62461: 03/10/30: Re: Xilinx Spartan3: Price
62660: 03/11/04: Re: Building the 'uber processor'
62860: 03/11/10: Re: Home grown CPU core legal?
63358: 03/11/20: Re: 400 Mb/s ADC
63373: 03/11/20: Re: 400 Mb/s ADC
63603: 03/11/26: Re: graphic card accelarator vs. FPGA: which is better for the following task?
63620: 03/11/26: Re: what is the fastest speed that FPGA deals with CPU?
63646: 03/11/27: Re: what is the fastest speed that FPGA deals with CPU?
64180: 03/12/19: Re: Spartan3 availability
64327: 03/12/28: Spartan3 prices again...
64357: 03/12/30: Re: Spartan3 prices again...
64359: 03/12/30: Re: Xilinx Parallel cable
64395: 04/01/01: Re: SOS : 4-bit binary divider circuit PLEASE!!!!!!!
64618: 04/01/09: Spartan3 IOB without supply
64657: 04/01/10: Re: Spartan3 IOB without supply
64923: 04/01/16: Spartan-3 VCCINT
64986: 04/01/18: Re: Spartan-3 VCCINT
65027: 04/01/19: Re: Spartan3 prices again...
65250: 04/01/22: Re: Altera/Xilinx Distributor in Europe?
65277: 04/01/23: Re: xilinx 70% tracking rule
65315: 04/01/24: Re: Random data generator...
65319: 04/01/24: Re: is this a good idea
65341: 04/01/25: Re: FPGA machine-level specification?
65657: 04/02/04: Re: how to get a vendor id of a pci
65715: 04/02/05: Re: PS/2 Keyboard opencore (keyboard side) available ???
65774: 04/02/06: Re: Do Xilinx Fix Their Prices?
65808: 04/02/06: Re: Pricing, 101
66160: 04/02/13: Re: Peter's 1Hz-640MHz Synth project
66482: 04/02/20: Re: GZIP algorithm in FPGA
66526: 04/02/21: Lead Free Packages
66929: 04/03/01: Re: Stratix 2 ALUT architecture patented ?
69832: 04/05/21: Re: Nios II Going Live...
70511: 04/06/18: Re: compressing Xilinx bitstreams
70574: 04/06/21: Re: compressing Xilinx bitstreams
70734: 04/06/25: Re: Divided by 11 in VHDL
70944: 04/07/02: Re: *RANT* Ridiculous EDA software "user license agreements"?
71105: 04/07/08: Re: *RANT* Ridiculous EDA software "user license agreements"?
71470: 04/07/19: Re: Compact FPGA Board?
71535: 04/07/21: Re: Spartan 3 termination question (DCI)
71618: 04/07/25: Re: Cheap FPGA's
71645: 04/07/26: Re: Cheap FPGA's
72396: 04/08/17: Re: Xilinx VQ100 package drawings?
74026: 04/10/02: Re: Open-Source MicroBlaze IP-Core working in FPGA :)
72841: 04/09/04: Re: spartan3 pci above 33MHz
73008: 04/09/10: Re: new to fpga
73223: 04/09/16: Re: Virtex 4 released today
73249: 04/09/16: Re: Looking for a Design for a Small FPGA Board
73328: 04/09/19: Re: adder VS increment
73391: 04/09/21: Re: Stratix II vs. Virtex 4 - features and performance
73545: 04/09/23: Re: How to design a programming parallel cable
73546: 04/09/23: Spartan-3 VCCIO ramp up time
73643: 04/09/27: Re: How to design a programming parallel cable
73659: 04/09/27: Re: spartan-3 sram
73682: 04/09/28: Re: has anyone tried implementing Serpent?
74063: 04/10/03: Re: Open-Source MicroBlaze IP-Core working in FPGA :)
74064: 04/10/03: Re: Open-Source MicroBlaze IP-Core working in FPGA :)
74213: 04/10/06: Re: JOP on Spartan-3 Starter Kit
74225: 04/10/06: Re: Hash algorithm for hardware?
74257: 04/10/06: Re: JOP on Spartan-3 Starter Kit
74710: 04/10/17: Re: What was the first FPGA?
74712: 04/10/17: Re: How can FPGAs be used for high speed data acquisition????
74742: 04/10/18: Re: How can FPGAs be used for high speed data acquisition????
76405: 04/12/01: Re: Weird XPower results for FSMs and different FPGAs
76429: 04/12/02: Re: Weird XPower results for FSMs and different FPGAs
76467: 04/12/03: Re: Weird XPower results for FSMs and different FPGAs
76617: 04/12/07: Re: Performance claims
76711: 04/12/09: Re: Open source FPGA EDA Tools
76754: 04/12/10: Re: Open source FPGA EDA Tools
76787: 04/12/12: Re: Software controllable clock generator, Xilinx Virtex-II
76944: 04/12/16: Re: Digital clock synthesis
76968: 04/12/17: Re: PCI doubt
77309: 05/01/04: Re: Using LM317S adjustable linear regulator for Spartan 3?
77310: 05/01/04: Re: EU patent debate, any effects on FPGA-design?
77328: 05/01/04: Re: Using LM317S adjustable linear regulator for Spartan 3?
77329: 05/01/04: Re: EU patent debate, any effects on FPGA-design?
77330: 05/01/04: Re: Whither common courtesy ?
77331: 05/01/04: Re: EU patent debate, any effects on FPGA-design?
78208: 05/01/26: Re: Xilinx Engineering Samples [JTAG issues]
78290: 05/01/28: LVDS without termination
78376: 05/01/31: Re: LVDS without termination
78377: 05/01/31: Re: LVDS without termination
78471: 05/02/01: Re: Oscillator for Digilent Spartan 3 Starter Kit
78545: 05/02/03: Re: MP3 Player Project
78546: 05/02/03: Re: LVDS without termination
78561: 05/02/03: Re: LVDS without termination
78585: 05/02/03: Re: LVDS without termination
78744: 05/02/07: Impact with Linux Kernel 2.6.x
78777: 05/02/08: Re: usb 2.0 micromodule
78807: 05/02/08: Re: SimmStick FPGA module
79478: 05/02/19: Re: why to use FIFO on FPGA?
79499: 05/02/20: Re: SPI serial output counter or latch?
79643: 05/02/22: Re: Xilinx: Pitfalls of chaining DLLs
79645: 05/02/22: Re: hdl:lament
80035: 05/02/28: Re: I2C protocol to communicate between FPGAs
80072: 05/03/01: Re: I2C protocol to communicate between FPGAs
80276: 05/03/03: Re: Maximum Current utilized by Spartan-3
80348: 05/03/04: Re: Displays an image in the XS Board RAM on a VGA monitor
80373: 05/03/04: Re: Maximum Current utilized by Spartan-3
80540: 05/03/08: Re: Surge in S2? ~3 amperes at cold for a millisecond
80808: 05/03/11: Re: Over-Sampling
81063: 05/03/17: Re: How much current does an LED take?
81112: 05/03/17: Re: Newbie: Slow FPGAs
81119: 05/03/18: Re: Newbie: Slow FPGAs
81356: 05/03/22: Re: PowerPC soft-core?
81359: 05/03/22: Re: VREF for SSTL out only / PCB
81428: 05/03/23: Re: OPB component for serial Flash?
81621: 05/03/29: Re: Multi-FPGA PCB data aggregation?
81771: 05/03/31: Re: exp(-x) function
82782: 05/04/18: Re: Spartan 3E slower that Spartan 3?
82990: 05/04/21: Re: Soft CPU vs Hard CPU's
83296: 05/04/27: Re: dynamic size of ports
83298: 05/04/27: Re: *RANT* Ridiculous EDA software "user license agreements"?
83310: 05/04/27: Re: Virtex slow clock multiply options?
83524: 05/05/02: Re: Frequency Limit !!
83574: 05/05/03: Re: Xilinx 6.2i EDK
83820: 05/05/07: Re: Using capacitor to slow the rise time.
83941: 05/05/10: Re: Which chip should I use?
84458: 05/05/19: Re: Spartan 3 CPI
85348: 05/06/08: Re: Fast/low area Sorting hardware.
85635: 05/06/13: Re: Searching FPGA board for private use
85852: 05/06/17: AbusivepPricing information in marketing publications
85984: 05/06/19: Re: AbusivepPricing information in marketing publications
86490: 05/06/29: Re: Good FPGA for an encryptor
86525: 05/06/29: Re: Good FPGA for an encryptor
86815: 05/07/07: Re: Xilinx Virtex 4 device technology
87205: 05/07/19: Re: Driving the FPGA output.
87305: 05/07/21: Re: Design is too large for the device! xc3s400
87306: 05/07/21: Re: Design is too large for the device! xc3s400
87451: 05/07/24: Re: Fastest way to compute floating point log and exp
87484: 05/07/25: Re: July 20th Altera Net Seminar: Stratix II Logic Density
88353: 05/08/16: Re: AHDL Abandoned in Quartus?
88449: 05/08/18: Re: State Machine and BUFG
88532: 05/08/22: Re: USB Blaster
88544: 05/08/22: Re: Peter Alfke's SPDT Switch Debouncer
88853: 05/08/30: Re: Array of slope A/Ds in FPGA?
89102: 05/09/05: Re: PPC405 32 bit aligned accesses
89398: 05/09/14: Re: fan out capability of FPGA
89478: 05/09/16: Re: Small (OEM-)Memory Modules (SRAM/FLASH/DRAM)
89588: 05/09/20: Re: Reprogramming FPGA over PCI???
89842: 05/09/28: Re: Dolby Digital AC-3 Decode on an FPGA - Possible ? Big ?
89944: 05/09/30: Re: Prob in Synthesizing and Simulating large Mux
90167: 05/10/06: Re: Systolic array architectures
90194: 05/10/06: Re: How to make XST understand to pack mux(A,B,A+B) in a single level
90196: 05/10/06: Re: Systolic array architectures
90198: 05/10/06: Re: .lib file for Xilinx FPGAs?
90200: 05/10/06: Re: .lib file for Xilinx FPGAs?
90266: 05/10/07: Re: Virtex4 shift register layout: Horizontal or vertical?
90416: 05/10/12: Re: converting 12v signal to 3.3v
90447: 05/10/13: Re: IO interface standard of fpga
90510: 05/10/15: Re: Synplify Pro and automatic Retiming/Pipelining
90515: 05/10/15: Re: Storing a file onto FPGA
90536: 05/10/16: Re: 3.3v<->5V
90793: 05/10/21: Re: MAC Architectures
90801: 05/10/21: Re: Rosetta Results
90810: 05/10/21: Re: MAC Architectures
90817: 05/10/21: Re: EDK/ISE : unroutable design
90850: 05/10/23: Re: low power design and unused i/os
90936: 05/10/25: Re: Rosetta Results
90976: 05/10/26: Re: MAC Architectures
91020: 05/10/27: Re: Xilinx ISERDES
91064: 05/10/28: Re: MAC Architectures
91137: 05/10/31: Re: Sigma-Delta A/D
91138: 05/10/31: Re: array type implementable in ISE?
91367: 05/11/04: Re: FPGA C Compiler on sourceforge.net (TMCC derivative)
91400: 05/11/05: Re: FPGA C Compiler on sourceforge.net (TMCC derivative)
91633: 05/11/10: Re: In Xilinx, how do I delay a signal by a fraction of a clock cycle?
91785: 05/11/13: Re: AVNET's Spartan3 400 dev board & PCI
92092: 05/11/22: Re: architecture
92100: 05/11/22: Re: Patient Monitors: Reading RS232 output w/ an FPGA
92382: 05/11/29: Re: Why does two channels of ADC give different outputs?
92386: 05/11/29: Re: Why does two channels of ADC give different outputs?
92397: 05/11/29: Re: instruction counts and cache hits/misses on FPGA
92497: 05/11/30: Re: grabbing PCI signals, rev-eng dev board
92499: 05/11/30: Re: Why does two channels of ADC give different outputs?
92544: 05/12/01: Re: Multi-layer switch network?
92716: 05/12/05: Re: Xilinx Adder Subtracter Core (What's Wrong With Xilinx People??!)
92726: 05/12/05: Re: Is it legal to write an logical equation for a FPGA LUT in claims
92879: 05/12/08: Re: I2C controller chipset to interface with FPGA
92982: 05/12/10: Re: Adding "super-LUTs" to FPGA, good idea ?
93249: 05/12/16: Re: Interfacing externally clocked data to an FPGA (Spartan 3)
93396: 05/12/21: Re: Place and Route Algorithms
93399: 05/12/21: Re: Patents and (possible) Plagiarism, Anyone ever been in a similar
93415: 05/12/21: Re: Place and Route Algorithms
93553: 05/12/24: Re: RTL for Z8000 series CPU?
93710: 05/12/29: Re: What is 'drive strength' for? (Spartan 3)
93835: 06/01/01: Re: Fitting circuits to fpga LUTs
94140: 06/01/06: Re: PCI compliance ?
94214: 06/01/08: Re: PCI compliance ?
94396: 06/01/11: Re: FPGA configuration time for PCI identification ?
94397: 06/01/11: Re: Software- to- PCI design communication.
94729: 06/01/17: Re: FPGA Journal Article
94536: 06/01/13: Re: OT: RoHS and Lead?
94640: 06/01/15: Re: Any FPGA with programming info available?
95217: 06/01/21: Re: Hi :-) Someone build a parallel JTAG cable like the xilinx one
95571: 06/01/24: Re: help:dual-edge flip-flop possible using Verilog?
95920: 06/01/27: Re: So Xilinx, is XDL and related libraries an available open source
96009: 06/01/28: Re: Virtex-4 ISERDES and ADS527X ADCs
96032: 06/01/28: Re: Virtex-4 ISERDES and ADS527X ADCs
96062: 06/01/29: Re: Virtex-4 ISERDES and ADS527X ADCs
96031: 06/01/28: Re: Virtex-4 ISERDES and ADS527X ADCs
96173: 06/01/31: Re: Xilinx Legal
96193: 06/01/31: Re: Xilinx Legal
96167: 06/01/31: Re: Xilinx Legal
96179: 06/01/31: Re: Xilinx Legal
96255: 06/02/01: Re: Xilinx Legal
96984: 06/02/14: Re: ModelSim Licence problem
97359: 06/02/21: Re: Is FPGA code called firmware?
97833: 06/02/28: Re: tricks to make large PLAs fast?
97884: 06/03/01: Re: tricks to make large PLAs fast?
97885: 06/03/01: Re: tricks to make large PLAs fast?
98519: 06/03/12: Re: Plateform FLASH PROM configuration using a Microblaze.
98568: 06/03/13: Re: fpga to 5v ttl logic
98647: 06/03/14: Re: Question about multi write ports RAM in FPGA?
98696: 06/03/15: Re: Entity with Multiple Architectures
98744: 06/03/15: Re: Why does Xilinx hate version control?
99178: 06/03/21: Re: VHDL LUT
99424: 06/03/24: Re: this JTAG thing is a joke
99848: 06/03/30: Re: how can one get a netlist consisting of SLICEs?
99930: 06/03/31: Re: how can one get a netlist consisting of SLICEs?
100480: 06/04/10: Re: 8:1 MUX implementaion in XILINX and ALTERA
100562: 06/04/12: Re: PCI speed.
100615: 06/04/13: Re: why the best code are the random codes ?
100641: 06/04/14: Re: PCB Stack
100668: 06/04/15: Re: PCB Stack
100670: 06/04/15: Re: Counting bits
100680: 06/04/16: Re: Counting bits
100720: 06/04/17: Re: Where is the xilinx online store gone?
100722: 06/04/17: Re: Where is the xilinx online store gone?
100899: 06/04/20: Re: Multiple Independent Circuits on a Single FPGA
100941: 06/04/21: Re: Reliability CPLD/FPGA vs Microcontroller
100981: 06/04/22: Re: Video circle generator
100982: 06/04/22: Re: Reliability CPLD/FPGA vs Microcontroller
101065: 06/04/25: Re: Opinions on Viva
101082: 06/04/25: Re: Simulated Quartus II delays are much greater than measured
101083: 06/04/25: Re: Max and Argmax across 1,000 unsigned 10-bit numbers
101132: 06/04/26: Re: Simulated Quartus II delays are much greater than measured
101133: 06/04/26: Virtex-4 MGTPower Distribution
101149: 06/04/26: Re: What is the best way to clock data in on one clock edge and out
101246: 06/04/28: Re: LED Driver
101411: 06/04/30: Re: design optimization
101491: 06/05/02: Re: Async FPGA ~2GHz
101499: 06/05/02: Re: design optimization
101567: 06/05/03: Re: Improvement suggestions for Xilinx ChipScope
101573: 06/05/03: Re: Chaining multiple Xilinx "Six Easy Pieces" Clock Doubler
101575: 06/05/03: Re: Chaining multiple Xilinx "Six Easy Pieces" Clock Doubler
101636: 06/05/04: Re: Interfacing Spartan 3 board to PC parallel port??
101648: 06/05/04: Re: Cordic-based Sine Computer in MyHDL
101653: 06/05/04: Re: Cordic-based Sine Computer in MyHDL
101973: 06/05/09: Re: Putting the Ring into Ring oscillators
101999: 06/05/09: Re: Putting the Ring into Ring oscillators
102026: 06/05/09: Re: Putting the Ring into Ring oscillators
102155: 06/05/11: Re: sqrt(a^2 + b^2) in synthesizable VHDL?
102359: 06/05/15: Re: Virtex 5 announced
102373: 06/05/15: Re: Virtex 5 announced and sampling
102375: 06/05/15: Re: Virtex 5 announced
102377: 06/05/15: Re: Virtex 5 announced and sampling
102437: 06/05/16: Re: Virtex 5 announced and sampling
102531: 06/05/17: Re: ADC implementation on FPGA ?
102709: 06/05/19: Re: generate a square signal with a 3.8 ns "plate"
102743: 06/05/19: Re: generate a square signal with a 3.8 ns
102820: 06/05/21: Re: Have someone implementate the cpu86 or sparc embeded processor
102903: 06/05/23: Re: xilinx pricing discrepancy
102911: 06/05/23: Re: Superscalar Out-of-Order Processor on an FPGA
102979: 06/05/24: Re: FPGA delay generator
103014: 06/05/24: Re: FPGA delay generator
103203: 06/05/28: Re: Report for routing resource usage?
103360: 06/05/31: Re: How do I scale a 9-b signed 2's complement data by 17/sqrt(21)?
103361: 06/05/31: Re: How do I scale a 9-b signed 2's complement data by 17/sqrt(21)?
103382: 06/06/01: Re: How do I scale a 9-b signed 2's complement data by 17/sqrt(21)?
103542: 06/06/05: Re: Webpack larger than CDs
103563: 06/06/06: Re: Webpack larger than CDs
103658: 06/06/07: Re: Problems with ISE logic optimization
104065: 06/06/18: Re: High speed differential to single ended
104066: 06/06/18: Re: LVTTL or LVCMOS for PCI Signaling?
104108: 06/06/19: Re: LVTTL, LVCMOS or 3.3V-PCI?
104259: 06/06/22: Re: comp.arch.fpga : Selection of Device
104265: 06/06/22: Re: JTAG - Boundary Scan s/w using Byteblaster or Parallel 4 cable
104693: 06/07/04: Re: Chaos in FF metastability
104792: 06/07/06: Re: How much time does it need to sort 1 million random 64-bit/32-bit
104839: 06/07/07: Re: How much time does it need to sort 1 million random 64-bit/32-bit
104854: 06/07/07: Re: How much time does it need to sort 1 million random 64-bit/32-bit
104892: 06/07/08: Re: Chaos in FF metastability
105751: 06/07/31: Re: Sorting algorithm for FPGA availlable?
105752: 06/07/31: Re: High-speed ADC+ Rocket I/O capability FPGA board
105758: 06/07/31: Re: Rocket IO as a high speed sampler
105871: 06/08/02: Re: Programmable pulse generator
105888: 06/08/02: Re: Programmable pulse generator
105991: 06/08/04: Re: Xilinx PCI Core burst problem
106207: 06/08/09: Re: Who is your favourite FPGA guru?
106264: 06/08/10: Re: ISE software bug???
106542: 06/08/15: Re: Crystal input for FPGA
106555: 06/08/15: Re: IIR filter example ?
106609: 06/08/16: Re: Maximum Current Draw of FPGA
106628: 06/08/16: Re: Open-source JTAG software?
106682: 06/08/17: Re: Open-source JTAG software?
106756: 06/08/18: Re: FFT on an FPGA
106777: 06/08/18: Re: Problem with "don't care"
106784: 06/08/19: Re: FFT on an FPGA
106785: 06/08/19: Re: FFT on an FPGA
106788: 06/08/19: Re: FFT on an FPGA
106827: 06/08/20: Re: Speed vs Area Optimisation
106961: 06/08/23: Re: PCIe latency
107059: 06/08/24: Re: fastest FPGA
107288: 06/08/26: Re: fastest FPGA
107301: 06/08/26: Re: What is the truth about the Virtex5 ?
107403: 06/08/28: Re: Spartan 3 and 5V input
107406: 06/08/28: Re: placing addiional caps across existing caps to reduce noise
107910: 06/09/02: Re: 5V FPGAs & CPLDs in 2006?
107922: 06/09/02: Re: Here are the URLs (was Re: Impossible to download WebPACK?)
108012: 06/09/04: Re: How to resolve a Xilinx 8.1 BlockRAM problem
108020: 06/09/04: Re: bidirectional connection between two bidirectional ports
108215: 06/09/06: Re: Forth-CPU design
108216: 06/09/06: Re: Forth-CPU design
108256: 06/09/07: Re: Forth-CPU design
108357: 06/09/08: Re: Why No Process Shrink On Prior FPGA Devices ?
108421: 06/09/11: Re: Forth-CPU design
108479: 06/09/12: Re: FPGA timing
108504: 06/09/12: Re: FPGA timing
108667: 06/09/15: Re: Linear Interploation Algorithms
108725: 06/09/15: Re: Digilent 3S200 pcb + webpack ISE 8.2 + service pack
109128: 06/09/21: Re: Buffering the critical path.
109369: 06/09/25: Re: Help required regarding PCI Master core
109756: 06/10/05: Re: Just a matter of time
109845: 06/10/06: Re: a clueless bloke tells Xilinx to get a move on
110016: 06/10/09: Re: Antifuse, lower cost?
110086: 06/10/11: Re: FPGA and ZBT/NoBL SRAM timing issue
110405: 06/10/15: Re: Xilinx FPGAs in battery-powered scenarios
110408: 06/10/15: Re: Xilinx FPGAs in battery-powered scenarios
110706: 06/10/20: Xilinx PCIe 8-lane endpoint constraints
110760: 06/10/21: Re: Xilinx PCIe 8-lane endpoint constraints
110964: 06/10/26: Re: OT: FPGA soft-core humor
110965: 06/10/26: Re: OT: FPGA soft-core humor
111499: 06/11/04: Re: Spectre of Metastability Update
112233: 06/11/18: Re: pulse jitter due to clock
112234: 06/11/18: Re: pulse jitter due to clock
112384: 06/11/21: Re: pulse jitter due to clock
112386: 06/11/21: Re: pulse jitter due to clock
113313: 06/12/11: Re: approximation of an exponential ramp?
113431: 06/12/13: Re: what are your current SoC design for ?
113496: 06/12/14: Virtex-V MGT SONET alignment
113515: 06/12/15: Re: Virtex-V MGT SONET alignment
113525: 06/12/15: Re: How does FPGA tools infer FIFO
114486: 07/01/17: Re: Can I use 3.3V clock into the MGTCLK? MGT RocketIO
129626: 08/02/29: Re: Need info on systolic arrays in actual use
129641: 08/03/01: Re: Need info on systolic arrays in actual use
129680: 08/03/03: Re: Virtex-5 FXT coming soon?
129695: 08/03/03: Re: Virtex-5 FXT coming soon?
129697: 08/03/03: clock distribution accross boards
129728: 08/03/04: Re: clock distribution accross boards
129729: 08/03/04: Re: clock distribution accross boards
129730: 08/03/04: Re: clock distribution accross boards
129732: 08/03/04: Re: clock distribution accross boards
129771: 08/03/05: Re: clock distribution accross boards
129923: 08/03/10: Re: its regarding to the Max Frequency in xilinx FPGA
129981: 08/03/12: Re: VME 2 Ghz clock generator
129982: 08/03/12: Re: Design complexity in Logic cells - Virtex-5 FPGA
129986: 08/03/12: Re: Convert some table into combinatorial circuit + optimization
129991: 08/03/12: Re: VME 2 Ghz clock generator
130020: 08/03/13: Re: Almost offtopic about HDL optimizing.
130021: 08/03/13: Re: Design complexity in Logic cells - Virtex-5 FPGA
130101: 08/03/14: Re: Almost offtopic about HDL optimizing.
130153: 08/03/17: Re: Designing CPU
130155: 08/03/17: Re: DDR3 speed, Altera vs Xilinx
130171: 08/03/17: Xilinx Webcase Workflow
130175: 08/03/17: Re: Xilinx Webcase Workflow
130309: 08/03/20: Re: A Challenge for serialized processor design and implementation
130329: 08/03/20: Re: ISE 10.0 finally with multi-threading and SV support ?
130376: 08/03/21: Re: ISE 10.0 finally with multi-threading and SV support ?
130377: 08/03/21: Re: Is there a means to conditional synthesis in VHDL?
130420: 08/03/23: Re: ISE 10.0 finally with multi-threading and SV support ?
130421: 08/03/23: Re: High speed memory read and transfer via rocket IO..
130438: 08/03/24: Re: ISE 10.0 finally with multi-threading and SV support ?
130478: 08/03/25: Re: ISE 10.0 finally with multi-threading and SV support ?
130479: 08/03/25: Re: Xilinx PLEASE FIX YOUR servers (ISE 10.1)
130521: 08/03/26: Re: ISE 10.0 finally with multi-threading and SV support ?
130723: 08/03/31: Re: ISE 10.1 - Initial experience
130758: 08/04/01: Re: ISE 10.1 - Initial experience
130764: 08/04/01: Re: ISE 10.1 - Initial experience
130812: 08/04/02: Re: Xst_Choice nodes
130914: 08/04/04: Re: EDK 10.1 first impressions
130960: 08/04/07: Re: system level language: why all this fuss about
130962: 08/04/07: Re: system level language: why all this fuss about
131087: 08/04/10: Re: Disable optimisation - Ring oscillator
131094: 08/04/10: Re: 32 bit multiplier
131408: 08/04/21: Re: Synthesis Comparison
131747: 08/04/30: Re: how to optimize this comparator for better synthesis result?
131789: 08/05/02: Re: PCI Express Switch
131988: 08/05/09: Re: 5 V oscillator output to GCLK
132092: 08/05/13: Re: 5 V oscillator output to GCLK
132128: 08/05/15: Re: FPGA imp
132134: 08/05/15: Re: FPGA imp
132168: 08/05/16: Re: Incorporating FPGAs on PCBs
132239: 08/05/19: Re: 2-bit Pseudo Random Number Generator
132276: 08/05/20: Re: synthesis...
132340: 08/05/22: 1250gbps input on virtex-5
132354: 08/05/23: Re: 1250gbps input on virtex-5
132401: 08/05/26: Re: 1250gbps input on virtex-5
132428: 08/05/27: Re: signal value at power up
132515: 08/05/29: Re: Are FPGAs headed toward a coarse granularity?
132520: 08/05/29: Re: Are FPGAs headed toward a coarse granularity?
132546: 08/05/30: Re: Are FPGAs headed toward a coarse granularity?
132847: 08/06/09: Re: TI DSP + Virtex-5 using EMIF interface
132913: 08/06/10: Strange Virtex-4FX 8b10b encoding behaviour
133093: 08/06/18: Re: Synthesis results when testing for 'X' and 'U'
133103: 08/06/18: Re: Synthesis results when testing for 'X' and 'U'
133104: 08/06/18: Re: Synthesis results when testing for 'X' and 'U'
133110: 08/06/18: Re: Synthesis results when testing for 'X' and 'U'
133180: 08/06/19: Re: Mapping the DCM clock output onto a global buffer
133263: 08/06/23: Re: virtex-5: can't use DCM (too low input frequency)
133337: 08/06/25: Re: FPGA based database searching
134528: 08/08/16: Re: why does inferred RAM cause synthesis times to explode?
134751: 08/08/28: Re: Genode FPGA graphics project launched
134753: 08/08/28: Re: Genode FPGA graphics project launched
134781: 08/08/29: Re: Genode FPGA graphics project launched
134785: 08/08/30: Re: Genode FPGA graphics project launched
135369: 08/09/29: Re: Difference between PLD and General purpose CPU`
135407: 08/10/01: Re: Difference between PLD and General purpose CPU`
135423: 08/10/01: Re: if data moves faster faster than the Clock....
135712: 08/10/13: Re: How to synthesize a delay of around 10 ns in FPGA?
135863: 08/10/18: Re: Embedded Linux on V5 FXT
135956: 08/10/24: Re: How to synthesize a delay of around 10 ns in FPGA?
136121: 08/11/02: Re: FPGA implementation of a PCI module
136132: 08/11/03: Re: FPGA implementation of a PCI module
136397: 08/11/14: Re: Host driver
136443: 08/11/17: Re: purpose of MULTAND
136447: 08/11/17: Re: purpose of MULTAND
136559: 08/11/21: Re: Generate sample rate ...
136590: 08/11/24: Re: Generate sample rate ...
136635: 08/11/27: Re: added jitter on FPGAs
137938: 09/02/02: Re: Why the second flip-flop in Virtex-6?
138072: 09/02/05: Re: how to cope with read cycle latency in block ram on Xilinx device
144552: 09/12/14: Re: Does a 1-bit mux glitch if only one input is known to change at
144578: 09/12/16: Re: what is Timing generating before interfacing?
144579: 09/12/16: Re: Does a 1-bit mux glitch if only one input is known to change at
144981: 10/01/18: Re: bit vs std_logic (was Re: Simulation of VHDL code for a vending
145132: 10/01/28: Re: DPA vs FPGA Security?
145141: 10/01/29: Re: DPA vs FPGA Security?
145230: 10/02/02: Re: vhdl divider
145266: 10/02/04: Re: synthesizing a completely empty design for an FPGA to measure
145267: 10/02/04: Re: synthesizing a completely empty design for an FPGA to measure
145273: 10/02/04: Re: synthesizing a completely empty design for an FPGA to measure
145591: 10/02/15: Re: optimal no of inputs to be given in a test bench
145900: 10/02/27: Re: Frustration with Vendors!
146662: 10/03/25: Re: EMC discussion
146663: 10/03/25: Re: EMC discussion
147408: 10/04/26: Re: Inferring mutipliers
147527: 10/04/30: Re: xilinx arm finally announced
147572: 10/05/04: Re: FIFO Depth Calculation
147678: 10/05/14: Re: Two PCIe Endpoints in one Virtex-6?
148482: 10/07/27: Re: Connecting "signed" to "std_logic_vector" ports.
148515: 10/07/29: Re: Connecting "signed" to "std_logic_vector" ports.
148583: 10/08/03: Re: Xilinx EasyPath Pricing
148621: 10/08/09: Re: VHDL newbie- stuck just weeks before project submission
148919: 10/09/10: Re: Divide clock by 4/5 in Spartan 3A?
149032: 10/09/22: Re: Xilinx XST and a State Machine - A Mystery
149074: 10/09/29: Re: Virtex5 minimodule
149192: 10/10/06: Re: Xilinx Artix 7 - When?
149274: 10/10/13: Re: Calculating SFDR in FPGA
149278: 10/10/13: Re: store data into fpga
149682: 10/11/17: Re: Maximum speed SPI on Spartan3a?
149712: 10/11/20: Re: Spartan3 device with long availability
149992: 10/12/06: Re: Concurrent Logic Timing
150057: 10/12/08: Re: Concurrent Logic Timing
150078: 10/12/10: Re: Interfacing DS92LV1021 with FPGA serdes
150092: 10/12/10: Re: Interfacing DS92LV1021 with FPGA serdes
150132: 10/12/15: Re: ISIM simulation speed
150472: 11/01/24: Re: Prime number testing on FPGA
150890: 11/02/19: Re: Mathematical definition of an FPGA
150891: 11/02/19: Re: Mathematical definition of an FPGA
150901: 11/02/20: Re: Mathematical definition of an FPGA
151138: 11/03/10: Re: Anti-benchmarking clauses
151154: 11/03/12: Re: pcb&bitstream
151192: 11/03/14: Re: pcb&bitstream
151242: 11/03/17: Re: pcb&bitstream
151256: 11/03/18: Re: pcb&bitstream
151271: 11/03/19: Re: pcb&bitstream
151491: 11/04/13: Desperately looking for XC5VFX30T-3FFG665
151866: 11/05/26: Re: PCI Express Cable
152078: 11/06/30: Re: digitization of sensor array
152107: 11/07/07: Re: Virtex 5 Rocket IO design for reading in ADC data.
152148: 11/07/13: Re: Looking for a FPGA board
152212: 11/07/21: Re: Speed attained by virtex 6
152242: 11/07/26: Re: Question on PCI-express verssus Standard PCI performance
152251: 11/07/27: Re: VHDL horror in Xcell 76
152403: 11/08/18: Re: extracting D from 1 / D*D
152963: 11/11/05: Re: PCI Express development board
153111: 11/12/02: Re: Is it possible to save the FPGA state periodically?
153207: 12/01/06: Re: Trying to select a development board, can somebody help me make
153397: 12/02/16: Re: LUT6 FPGAs and Carry Logic
153403: 12/02/16: Re: LUT6 FPGAs and Carry Logic
153474: 12/03/06: Re: FPGA Area
153475: 12/03/06: Re: FPGA Area
153966: 12/07/05: Re: Generate a pulse with a definite width
153976: 12/07/06: Re: Generate a pulse with a definite width
154246: 12/09/12: Re: New(?) fast binary counter for FPGAs without carry logic (e.g.
155500: 13/07/08: Re: VHDL syntheses timestamp
155501: 13/07/08: Re: FPGA board with 4 channel 500Msps ADC?
155716: 13/08/19: Re: seperate high speed rules for HDL?
Kolja Waschk:
76889: 04/12/15: JTAG vs. Passive Serial Config speed
101463: 06/05/01: Re: FPGA Single LED Demos: FPGA board for a good ideas/suggestions
101464: 06/05/01: Re: FPGA Single LED Demos: FPGA board for a good ideas/suggestions
103194: 06/05/28: Re: Altium Livedesign eval boards - can you add a configuration prom?
104494: 06/06/28: How to comm with Altera JTAG UART (from custom host software)?
104553: 06/06/29: Re: Altium Designer LiveDesign Evaluation Kits (once again)
128917: 08/02/10: Re: impact bug or wrong interpretation of xsvf layout?
<kolja@prowokulta.org>:
25284: 00/09/05: XC4013 available
25314: 00/09/06: Re: XC4013 available
25321: 00/09/06: Re: XC3000A Configuration data
25341: 00/09/07: Re: XC3000A Configuration data
25365: 00/09/08: Re: DCT implementation using FPGA
25411: 00/09/11: Re: Numerically-Controlled Crystal Oscillator (NCXO) or Digitally-Controlled Crystal Oscillator (DCXO) Designs
25470: 00/09/12: Re: Is this practical?
26562: 00/10/20: Re: How safe is the algorithm implemented with FPGA?
26714: 00/10/25: Re: How safe is the algorithm implemented with FPGA?
26741: 00/10/26: Re: How safe is the algorithm implemented with FPGA?
27374: 00/11/20: Re: In the news
27580: 00/11/29: Re: Gates in a typical small MPU
27375: 00/11/20: Re: In the news
27722: 00/12/05: Re: Issues with Spartan II
27741: 00/12/05: Re: Issues with Spartan II
28723: 01/01/22: Re: Virtex-II officially launched
28745: 01/01/23: Re: Virtex-II officially launched
28746: 01/01/23: Re: Virtex-II officially launched
28852: 01/01/26: Re: Foundation FPGA Editor hard macros in VHDL
28853: 01/01/26: Re: UK parts
28856: 01/01/26: Re: how to reduce number of gates in xor reducing in crc computing?
28911: 01/01/29: Re: XtremeDSP seminar comments -- Virtex-II 4xPowerPC chip multiprocessor!
29107: 01/02/06: Re: can -(A+B) computed in one level of logic ?
29272: 01/02/12: Re: double precision floating point arithmetic
29273: 01/02/12: Re: Wired-or on Virtex FPGAs
<kollarameshk@gmail.com>:
111299: 06/11/01: Re: xup virtex2 pro
111439: 06/11/03: JTAG connection for chipscope
111554: 06/11/05: Re: JTAG connection for chipscope
kolopipo:
143492: 09/10/13: Handwritten recognition using FPGA
<koltes@fmi.uni-passau.de>:
127868: 08/01/09: Identification of FPGA Development Board
127871: 08/01/09: Re: Identification of FPGA Development Board
Komatose:
22130: 00/04/26: Re: Is there any DSP and FPGA based board suitable to motor drive
22131: 00/04/26: PID on FPGA
22147: 00/04/27: Re: PID on FPGA
Konrad Burylo:
34709: 01/09/04: Re: XC2V3000-4BF957
Konrad Eisele:
49144: 02/11/01: MMU for Leon finished -> porting linux
53355: 03/03/11: Leon processor + MMU + linux port
62717: 03/11/05: Announcement
62787: 03/11/07: Re: Announcement
64768: 04/01/13: Open source ARM, Version 0.1
65755: 04/02/05: Update: Open source ARM, Version 0.4
66421: 04/02/19: Open Source Arm core version_0.5
68538: 04/04/07: Arm clone version 0_8
68626: 04/04/10: Free Arm Version 0.8
Kons Henrik Bohre:
29186: 01/02/09: Can a Virtex control its own reconfiguration?
Konstantin Dols:
76790: 04/12/12: UART receiver
76841: 04/12/14: Re: UART receiver
Konx:
144275: 09/11/24: FPGA + ASIC: generate signals and readout
kookoo4systemverilog:
132834: 08/06/08: Aldec Active-HDL and Xilinx/Altera FPGA-vendor library support
kooos:
51876: 03/01/24: Byteblaster
Koorndyk:
139000: 09/03/18: Re: uB and external CPU communications
139498: 09/04/01: Re: Digital design references for timing, etc.
141978: 09/07/20: Re: Do you prefer paper or plastic... er, I mean paper or e-books?
kopriva:
74982: 04/10/22: Q: configuring FPGA Spartan2
75127: 04/10/26: Re: JTAG Registers
kops:
29399: 01/02/19: 1/32
<koradaprudvi@gmail.com>:
159393: 16/10/24: verilog code
Korenje:
109229: 06/09/22: Re: Dell Laptop for Embedded Work
korg:
26721: 00/10/26: Fpga vs. ASIC
27621: 00/11/30: Job opportunities
<korthner@inf.furukawa.co.jp>:
26093: 00/10/04: Xilinx Licensing.
<korthner@my-deja.com>:
23637: 00/07/04: Serial Number embedded in PROM.
23662: 00/07/04: Re: Serial Number embedded in PROM.
23663: 00/07/05: Re: Programming Virtex with the MultiLINX cable
23664: 00/07/05: Re: Virtex DLL deskew of board clock with a clock/2
kosby:
11574: 98/08/25: looking a job around Austin
kossyma:
38445: 02/01/14: how do i implement it?
38453: 02/01/15: remainder
Kosta Xonis:
115277: 07/02/05: [Q]: Is Digilent still in business ???
115280: 07/02/05: Re: Is Digilent still in business ???
Kostas:
17970: 99/09/20: Re: Lowest power FPGA
18060: 99/09/27: Re: Obtaining a Synopsys site ID
18062: 99/09/27: Re: What are the Virtex REV connections?
53372: 03/03/12: FPGA BitStream
Kostas Marinis:
29360: 01/02/16: Implementing a 64-bit/66MHz PCI controller
Kostas Siozios:
47937: 02/10/08: Academic FPGA Cad Tools
Kotek Barajazz:
76168: 04/11/27: dual-write port BRAM with XST/Webpack
kouki:
155201: 13/06/03: openCv and NiosII IDE
Koustav:
120218: 07/06/03: Create and Import Peripheral in EDK
121092: 07/06/25: Interfacing expansion ports thru EDK
121275: 07/06/29: Interfacing a camera to a fpga
122109: 07/07/19: Interfacing the EDK based video decoder
122124: 07/07/19: Using the EDK based video decoder
123336: 07/08/23: Inout ports in EDK
127495: 07/12/28: Architectural level CMP simulators
<koustav79@gmail.com>:
119256: 07/05/15: Interfacing DDR RAMs to Virtex 2 Pro on Digilent boards
119257: 07/05/15: Interfacing DDR RAMs to Virtex 2 Pro on Digilent boards
119311: 07/05/16: Re: Interfacing DDR RAMs to Virtex 2 Pro on Digilent boards
119313: 07/05/16: Re: Interfacing DDR RAMs to Virtex 2 Pro on Digilent boards
119492: 07/05/21: Error in NGDBuild
119702: 07/05/24: Docs on s/w interfacing EDK based design
119768: 07/05/25: Interfacing EDK application code with Specific BRAMs on FPGA
119781: 07/05/25: Re: Interfacing EDK application code with Specific BRAMs on FPGA
119792: 07/05/25: Re: Interfacing EDK application code with Specific BRAMs on FPGA
kowari:
79836: 05/02/24: Synthesis question
79842: 05/02/24: Re: Synthesis question
<koyel.aphy@gmail.com>:
156018: 13/11/10: how does PC communicate with FPGA?
kpatel -at- xilinx -dot- com:
72173: 04/08/10: Re: Newbie Xilinx Question: How to keep past designs?
72608: 04/08/26: Re: Xilinx Command Prompt
73819: 04/09/29: Re: Cheaper way to get Xilinx Core generator
KPDURHAM:
16621: 99/05/31: !US-NC-Chapel Hill-FPGA Design Engineer/HOT
kpk:
64367: 03/12/31: SOS : 4-bit binary divider circuit PLEASE!!!!!!!
kquinn:
15563: 99/03/30: PC Interfacing
<kraemerm@my-dejanews.com>:
11473: 98/08/18: XC4062 mapping problems with Synopsis tools
Kraig Lund:
29218: 01/02/09: Re: what exactly is the dff between fpga and cpld?
krakatoa:
149955: 10/12/03: Re: Opinions on Lattice ECP3
149957: 10/12/03: Re: Opinions on Lattice ECP3
Kranthi Q:
73070: 04/09/13: New to Xilinx Software - help with downlaod
<krassi@bulinfo.net>:
112541: 06/11/24: MicroBlaze & top module?
krby_xtrm:
91302: 05/11/02: using Spartan3 DCM in ActiveHDL
<krc.1987@gmail.com>:
127447: 07/12/26: Core Generators...
krebs:
69738: 04/05/19: C-code to control FPGA with Leon
69827: 04/05/21: Re: C-code to control FPGA with Leon
70390: 04/06/15: how to connect my IP-Core to Microblaze in EDK and ISE with IPIF
Krem:
145391: 10/02/08: Re: Matching hadware and software CRC
Kresten Nørgaard:
19692: 00/01/08: 100 MHz counters
19768: 00/01/11: Re: 100 MHz counters
19879: 00/01/15: Re: Lattice
23333: 00/06/22: VHDL - ripple carry counter
52600: 03/02/15: Altera disassembler
52794: 03/02/22: Timing diagram input
52974: 03/02/27: Re: Timing diagram input
56596: 03/06/10: Re: Orcad 2 Quartus
63513: 03/11/24: Reconstructing source code from JED file
Kriki:
73241: 04/09/16: PLL in CPLD
kris:
54769: 03/04/17: rloc in verilog / tutorial for creating macros
54865: 03/04/21: declaration of macro
55457: 03/05/08: accurate power measurements
55463: 03/05/08: Re: accurate power measurements
57350: 03/06/27: defparam LUT_4
62322: 03/10/26: Does a dont_use statement exist?
Kris Heyrman:
85737: 05/06/14: Re: Help with USB cable, Xilinx XUP board, Linux FC3 and EDK
85786: 05/06/15: Re: Help with USB cable, Xilinx XUP board, Linux FC3 and EDK
88992: 05/09/02: Followup: USB cable, Xilinx XUP, EDK/ISE 7.1, Fedora Core 3
Kris Jacobs:
6908: 97/07/08: Try Me!
Kris Neot:
85793: 05/06/16: Idea exploration - Image stabilization by means of software.
85832: 05/06/17: Re: Idea exploration - Image stabilization by means of software.
85834: 05/06/17: Idea exploration 1.1 - Inertia based angular sensor.
85838: 05/06/17: Re: Idea exploration - Image stabilization by means of software.
85839: 05/06/17: Re: Idea exploration 1.1 - Inertia based angular sensor.
85847: 05/06/17: Re: Idea exploration - Image stabilization by means of software.
86272: 05/06/24: How do I convert a polynomial into a parallel scrambler formula?
86283: 05/06/24: Re: How do I convert a polynomial into a parallel scrambler formula?
86288: 05/06/24: Re: How do I convert a polynomial into a parallel scrambler formula?
86363: 05/06/27: Re: How do I convert a polynomial into a parallel scrambler formula?
Kris Nichols:
31005: 01/05/09: Need Advice on what Xilinx Tools to purchase
31583: 01/05/30: IEEE VHDL library support in HDL compilers
31605: 01/05/31: Re: IEEE VHDL library support in HDL compilers
34656: 01/09/02: Problems with Synthesis and Implementation in Xilinx Foundation 3.3i
36614: 01/11/13: Xilinx port warnings
36615: 01/11/13: 'Timing' simulation in ModelSIM
36631: 01/11/13: Re: 'Timing' simulation in ModelSIM
36634: 01/11/13: Xilinx problems using constants in the input ports of entities
36638: 01/11/13: Re: Xilinx problems using constants in the input ports of entities
36724: 01/11/17: Problem sythesizing libraries in Xilinx 4.1i
36988: 01/11/28: What does a 'Slice' refer to in a Xilinx MAP report?
40294: 02/03/05: Xilinx EDA support for run-time reconfiguration
Kris Vorwerk:
42211: 02/04/18: Re: Telecom Bus info
48919: 02/10/26: Re: Who has some Lecture materialson I2C Bus?
48920: 02/10/26: Re: C to verilog
52618: 03/02/16: About automatically programming my FPGA
81230: 05/03/19: Re: Spartan 3E vs. Cyclone2
81618: 05/03/29: Re: C++ code to FPGA
82153: 05/04/07: Re: Single Event Functional Interrupts (SEFI) in Virtex
86024: 05/06/20: Re: FPGAs: Where will they go?
88154: 05/08/10: Re: Hiding data inside a FPGA
89832: 05/09/27: Re: Any suggestions for prototyping in an ARM environment?
126087: 07/11/14: Re: Non-volatile FPGA in a small package
126105: 07/11/14: Re: Non-volatile FPGA in a small package
126111: 07/11/14: Re: fpga based designs
126112: 07/11/14: Re: Capability of a FPGA device.
126986: 07/12/07: Re: selecting FPGA
127008: 07/12/08: Re: Which FPGA and memory to use? The eternal X vs. A question.
127131: 07/12/12: Re: Debugging designs that are running on FPGA
127163: 07/12/12: Re: FPGA Board design basics
127765: 08/01/07: Re: Processor in CPLD
127873: 08/01/09: Re: How to program FPGA permanently?
128040: 08/01/14: Re: Debbuging a RISC processor on an FPGA
128051: 08/01/14: Re: sine and cosine wave generation
128400: 08/01/24: Re: Random Number Generation in VHDL
128423: 08/01/25: Re: Initialize RAM in IGLOO
128595: 08/01/31: Re: Actel Fusion FPGA
128665: 08/02/02: Re: Design security for pre-Virtex2 parts ?
kris2552:
132223: 08/05/18: SKEW greater than Time period of CLK
krish:
143835: 09/10/28: Re: Tcl in PlanAhead
KrishK:
69966: 04/05/25: Creating Orcad symbol for FPGA with large pin counts
krishna:
71734: 04/07/29: connecting entities
Krishna:
117672: 07/04/06: How to use the 8LEDs on DIO4 when connected to Virtex 2 Pro kit?
Krishna Kumar:
71600: 04/07/23: PCI Core implementation in Spartan 2E FG456 package
71647: 04/07/26: Re: PCI Core implementation in Spartan 2E FG456 package
71727: 04/07/28: Spartan 2E FG456 package file
71894: 04/08/03: Spartan 3 errata and pricing
71946: 04/08/04: Re: Spartan 3 errata and pricing
72255: 04/08/12: FPGA programming issue with Xilinx POD and PROM
72263: 04/08/12: Xilinx POD internal circuit diagram
Krishna Mohan:
4750: 96/12/11: Re: Altera Max+Plus
krishna P V:
35968: 01/10/25: Re: Fpga Synthesis Process
krishna.janumanchi@gmail.com:
105812: 06/08/01: Re: FPGA : BUG in ISE- View RTL Schematics ?
106848: 06/08/21: Modelsim SE Simulation
106904: 06/08/22: Re: Modelsim SE Simulation
111071: 06/10/27: Re: Jumps in FPGA implemented integrator
111376: 06/11/02: Re: Rad-hard (neutron/SEU and space) tutorial?
111558: 06/11/06: Re: post-synthesis simulation issues with ModelSim
krishna1234:
86160: 05/06/22: reading file from CF with 4VSX35 and EDK
86876: 05/07/07: Re: microblaze and 64 bit memory over PLB bus
Krishnakumar Rao:
33638: 01/08/01: post synthesis simulation
33809: 01/08/05: Urgent-Simulation with Leo. Spec
<krishnam@nital.stpp.soft.net>:
19490: 99/12/25: Re: EDIF and VITAL
Krishnan:
28976: 01/02/01: 64-bit counter @ 200 MHz on FPGA?
28983: 01/02/01: Re: 64-bit counter @ 200 MHz on FPGA?
<krishnans@hotmail.com>:
94454: 06/01/11: Re: "failed to create empty document"
94562: 06/01/13: Re: Xilinx ISE 8.i Editor
126391: 07/11/20: Re: FPGA Editor (9.2.03i) under Linux x86_64
kriskumar:
73312: 04/09/18: Please help me find the source of this glossary
Krist Neot:
85126: 05/06/06: Anyone has datasheet for the LCD on a Palm's Tungsten W?
85234: 05/06/07: How do I find out the connection of the LCD I took out from a digital camera?
85336: 05/06/08: How to deal with misplaced module in ISE?
85340: 05/06/08: Re: How do I find out the connection of the LCD I took out from a digital camera?
Kristen_G_Kosar:
30626: 01/04/19: Digital Design Positions Available
Krister Lagerstrom:
52: 94/08/04: Re: FPGA based processors ?
Krister Wikstrom:
17664: 99/08/21: Re: microcontroller vs FPGA
kristian:
137897: 09/02/02: FFT core has reversed output data
137932: 09/02/02: Re: FFT core has reversed output data
137985: 09/02/03: Re: FFT core has reversed output data
Kristian Klaus:
139113: 09/03/21: plb_emc with flash and datawidth matching
139114: 09/03/21: Re: plb_emc with flash and datawidth matching
139130: 09/03/21: Re: plb_emc with flash and datawidth matching
Kristian Rye Vennesland:
30361: 01/04/04: DSP Volume-control in FPGA
30474: 01/04/10: Re: free software
30670: 01/04/23: Altera DSP Design Kit
Kristian Wiklund:
33237: 01/07/20: Re: SystemC
Kristo Godari:
155987: 13/11/04: Verilog Binary Division
155993: 13/11/04: Re: Verilog Binary Division
155994: 13/11/04: Verilog module not working,binary division,shifting problem!!
155997: 13/11/04: Re: Verilog module not working,binary division,shifting problem!!
kristoff:
159042: 16/07/06: need some help with altera quartus
159045: 16/07/06: Re: need some help with altera quartus
159265: 16/09/18: requirement for PC for VHDL design
159289: 16/09/23: Re: requirement for PC for VHDL design
159294: 16/09/26: Re: requirement for PC for VHDL design
159295: 16/09/26: learning verilog
159297: 16/09/26: Re: learning verilog
159594: 17/01/16: I/O switching speed of Xilinx spartan 6 or Altera EP4CE10
159605: 17/01/17: Re: I/O switching speed of Xilinx spartan 6 or Altera EP4CE10
159620: 17/01/19: Re: I/O switching speed of Xilinx spartan 6 or Altera EP4CE10
159749: 17/02/24: designing a fpga
159761: 17/02/25: Re: designing a fpga
159763: 17/02/25: Re: designing a fpga
159769: 17/02/26: Re: designing a fpga
159830: 17/04/04: handshacking between modules, best practices ?
159832: 17/04/04: Re: handshacking between modules, best practices ?
159836: 17/04/05: Re: handshacking between modules, best practices ?
159933: 17/04/30: Re: RISC-V Support in FPGA
159955: 17/05/02: Re: RISC-V Support in FPGA
159978: 17/05/04: creating a seed on a FPGA.
159983: 17/05/04: Re: RISC-V Support in FPGA
160012: 17/05/11: size lattice iCE40 config files
160022: 17/05/12: Re: size lattice iCE40 config files
160173: 17/07/22: sram
160175: 17/07/22: Re: sram
160179: 17/07/23: Re: sram
Kristopher:
99430: 06/03/24: Support for Precision2005c
Kristopher Miller:
6299: 97/05/10: Desperate college students need help!!!
<krl@semel.fi.spam.wonderful.spam>:
57474: 03/07/01: Re: the skew and race condition
Kroko:
69241: 04/05/02: Re: CPLD input
72786: 04/09/01: Spartan 3 Starter Kit and ISE WebPACK
72803: 04/09/02: Re: Spartan 3 Starter Kit and ISE WebPACK
72805: 04/09/02: Re: Spartan 3 Starter Kit and ISE WebPACK
72832: 04/09/03: Re: Spartan 3 Starter Kit and ISE WebPACK
kron:
114439: 07/01/16: Two newbie Chipscope questions
115006: 07/01/29: Conversion from Xilinx ISE 7 to 8 fails
123096: 07/08/16: Fighting with Compact Flash
124055: 07/09/11: Re: Fighting with Compact Flash
krunal:
129187: 08/02/17: Interface on board ADC to Spartan 3E startkit
131549: 08/04/24: delta sigma adc.....
krw:
69122: 04/04/27: Re: transport applications
70356: 04/06/14: Re: SDRAM
103042: 06/05/24: Re: PCI 64/66 fpga eval boards
103166: 06/05/26: Re: PCI 64/66 fpga eval boards
108023: 06/09/04: Re: Please help me with (insert task here)
121902: 07/07/14: Re: ESR Meter - design contest
128197: 08/01/17: Re: effect of xray on fpga electronic circuits
131334: 08/04/19: Re: Survey: FPGA PCB layout
131337: 08/04/19: Re: Survey: FPGA PCB layout
131364: 08/04/20: Re: Survey: FPGA PCB layout
131375: 08/04/20: Re: Survey: FPGA PCB layout
131452: 08/04/21: Re: Survey: FPGA PCB layout
131453: 08/04/21: Re: Survey: FPGA PCB layout
131458: 08/04/21: Re: Survey: FPGA PCB layout
131460: 08/04/21: Re: Survey: FPGA PCB layout
131602: 08/04/25: Re: Survey: FPGA PCB layout
131625: 08/04/26: Re: Survey: FPGA PCB layout
131650: 08/04/27: Re: Survey: FPGA PCB layout
132386: 08/05/24: Xilinx LogicCore Direct Instantiation
132489: 08/05/28: Re: Xilinx LogicCore Direct Instantiation
132533: 08/05/29: Re: Xilinx LogicCore Direct Instantiation
132734: 08/06/05: Re: Xilinx cuts 250 jobs.
139416: 09/03/28: Re: added jitter on FPGAs
139430: 09/03/29: Re: added jitter on FPGAs
139440: 09/03/29: Re: added jitter on FPGAs
139460: 09/03/30: Re: added jitter on FPGAs
142201: 09/07/28: Re: cool chart
142207: 09/07/28: Re: cool chart
142208: 09/07/28: Re: cool chart
159366: 16/10/16: Re: Microsoft's FPGA Translates Wikipedia in less than a Tenth of a Second
159376: 16/10/17: Re: Microsoft's FPGA Translates Wikipedia in less than a Tenth of a Second
<krw@att.bizzz>:
154408: 12/10/27: Re: Altera delivery
154426: 12/10/28: Re: Re: Altera delivery
154428: 12/10/28: Re: Re: Altera delivery
krw@att.bizzzzzzzzzzzz:
147376: 10/04/24: Re: voltage divider calcs
147799: 10/05/24: Re: Software bloat (Larkin was right)
147823: 10/05/25: Re: Software bloat (Larkin was right)
147847: 10/05/26: Re: Software bloat (Larkin was right)
148269: 10/07/03: Re: fooling the compiler
148272: 10/07/03: Re: fooling the compiler
149621: 10/11/11: Re: cool BGA pattern
149641: 10/11/12: Re: cool BGA pattern
149679: 10/11/16: Re: cool BGA pattern
149696: 10/11/17: Re: cool BGA pattern
149703: 10/11/18: Re: cool BGA pattern
150449: 11/01/22: Re: Xilinx news
150451: 11/01/22: Re: Xilinx news
150457: 11/01/23: Re: Xilinx news
150458: 11/01/23: Re: Xilinx news
150459: 11/01/23: Re: Xilinx news
150465: 11/01/23: Re: Xilinx news
150467: 11/01/23: Re: Xilinx news
150469: 11/01/23: Re: Xilinx news
150499: 11/01/24: Re: Xilinx news
150610: 11/01/27: Re: Xilinx news
152472: 11/08/27: Re: cheating Arria FPGA i/o count
152484: 11/08/28: Re: cheating Arria FPGA i/o count
152485: 11/08/28: Re: cheating Arria FPGA i/o count
152489: 11/08/28: Re: cheating Arria FPGA i/o count
152891: 11/10/30: Re: Altera FPGA weirdness
152894: 11/10/30: Re: Altera FPGA weirdness
152913: 11/10/31: Re: Altera FPGA weirdness
152923: 11/11/01: Re: Altera FPGA weirdness
152926: 11/11/01: Re: Altera FPGA weirdness
152929: 11/11/01: Re: Altera FPGA weirdness
153216: 12/01/08: Re: voltage drop on STRATIX FPGA supply planes
<krw@notreal.com>:
159839: 17/04/10: Re: FPGA as heater
159858: 17/04/11: Re: FPGA as heater
159860: 17/04/11: Re: FPGA as heater
160331: 17/12/13: Re: FPGA one-shot
160338: 17/12/14: Re: FPGA one-shot
160342: 17/12/14: Re: FPGA one-shot
160349: 17/12/14: Re: FPGA one-shot
160352: 17/12/15: Re: FPGA one-shot
160353: 17/12/15: Re: FPGA one-shot
Krysti Shough:
29917: 01/03/16: XACT 5.2.1 & Viewdraw 6.0
Kryten:
75601: 04/11/10: Re: Research Project Re: Graphics Processor
75632: 04/11/11: Re: Research Project Re: Graphics Processor
75672: 04/11/12: Re: Research Project Re: Graphics Processor
75721: 04/11/13: Re: Obsolete processors resurected in FPGAs
75749: 04/11/14: Re: Obsolete processors resurected in FPGAs
75758: 04/11/14: Re: Obsolete processors resurected in FPGAs
76107: 04/11/25: ISE 6 recompiles but loader complains about device ID mismatch
76181: 04/11/27: When JTAG programming Xilinx FPGA, should other pins be constrained?
76200: 04/11/28: Re: When JTAG programming Xilinx FPGA, should other pins be constrained?
76208: 04/11/29: Re: When JTAG programming Xilinx FPGA, should other pins be constrained?
76494: 04/12/04: Re: SD Cards
76505: 04/12/04: Re: SD Cards
76734: 04/12/09: Re: Atari 10-in-1 Joystick
77279: 05/01/03: Re: Free IP-Core for FPGA Config from MMC-Cards
77288: 05/01/03: Re: Free IP-Core for FPGA Config from MMC-Cards
77653: 05/01/13: Re: Programming and copyright
77680: 05/01/13: Re: Programming and copyright
77716: 05/01/15: Re: Programming and copyright
77942: 05/01/20: Re: Copying/Reverse Engineering PAL
77956: 05/01/21: Re: Copying/Reverse Engineering PAL
77970: 05/01/21: Re: Copying/Reverse Engineering PAL
78007: 05/01/22: Re: Copying/Reverse Engineering PAL
78012: 05/01/22: Re: How to get 1.8432 MHz out of 24 MHz with Sparten-3?
78111: 05/01/25: Re: Copying/Reverse Engineering PAL
78136: 05/01/25: Re: Copying/Reverse Engineering PAL
78137: 05/01/25: Re: Copying/Reverse Engineering PAL
78176: 05/01/26: Re: Copying/Reverse Engineering PAL
78185: 05/01/26: Re: Copying/Reverse Engineering PAL
78205: 05/01/26: Re: Copying/Reverse Engineering PAL
78239: 05/01/27: Re: Copying/Reverse Engineering PAL
79024: 05/02/11: Re: Writing IP-Cores while sleeping ;)
79967: 05/02/27: Re: I2C protocol to communicate between FPGAs
79988: 05/02/28: Re: I2C protocol to communicate between FPGAs
80011: 05/02/28: Re: I2C protocol to communicate between FPGAs
80012: 05/02/28: Re: I2C protocol to communicate between FPGAs
80433: 05/03/05: Re: Newby Getting started with FPGA
80474: 05/03/06: Re: Newby Getting started with FPGA
80476: 05/03/07: Re: Newby Getting started with FPGA
80527: 05/03/07: Re: Newby Getting started with FPGA
80606: 05/03/09: Re: Asynchronous processor !?!
80608: 05/03/09: Re: Asynchronous processor !?!
80704: 05/03/10: Re: Spontaneous Board Reset
82168: 05/04/07: Re: Interesting article about Xilinx FPGAs in the new Cray
82406: 05/04/12: Re: Reverse engineering masked ROMs, PLAs
82492: 05/04/13: Re: Regarding driving of SCL and SDA pins of I2C
82887: 05/04/19: Re: Declining a job offer
84061: 05/05/11: Re: FPGA/Embedded Design Training
85504: 05/06/10: Re: I2C clock stretching(XILINX reference design)
85563: 05/06/10: Re: I2C clock stretching(XILINX reference design)
85747: 05/06/15: Re: Best Practices for Hardware Designers
85751: 05/06/15: Re: Best Practices for Hardware Designers
86505: 05/06/29: Re: Good FPGA for an encryptor
87072: 05/07/14: Re: Wanted: I2C RAM pre-loader VHDL module
88093: 05/08/09: Re: START /STOP sync pattern
90919: 05/10/25: Re: OSD implementation in FPGA
90921: 05/10/25: Re: SoC Processor design at gate level for edu
91676: 05/11/10: Re: Is this even true???
91733: 05/11/11: Re: Is this even true???
91765: 05/11/12: Re: FPGA KIT recommendation
92843: 05/12/07: Re: I2C controller chipset to interface with FPGA
92994: 05/12/11: Re: MMC(MultiMedia Card) interfacing with FPGA
92996: 05/12/11: Re: MMC(MultiMedia Card) interfacing with FPGA
95111: 06/01/20: Re: OT:Shooting Ourselves in the Foot
97914: 06/03/01: Re: FPGA communication, I2C and DAC
101546: 06/05/02: Re: FPGA Single LED Demos: FPGA board for a good ideas/suggestions
101820: 06/05/07: Re: BurchED FPGA Expansion Modules, 4-for-1 offer
103705: 06/06/08: Re: stable, tested 6502 core
105015: 06/07/12: Re: Development Boards -Your chance to suggest features
109557: 06/09/28: bit vs std_logic
109563: 06/09/29: Re: bit vs std_logic
111175: 06/10/30: Re: Taking forever to synthesise (XILINX ISE 8.1i)
111352: 06/11/02: Re: Taking forever to synthesise (XILINX ISE 8.1i)
111512: 06/11/04: Re: Scientific Computing on FPGA
111715: 06/11/08: Re: can you please help me VHDL coding on CSMA and DCF based project of wireless LAN
117712: 07/04/08: Re: Floppy to FPGA?
119146: 07/05/13: Re: how to choose the perfect fpga support
119616: 07/05/24: Re: Binary to BCD
119707: 07/05/24: Re: 6502 and CPU licences in general
119800: 07/05/26: Re: 6502 and CPU licences in general
kryten_droid:
33577: 01/07/31: Re: i2c master
33584: 01/07/31: Re: i2c master
34040: 01/08/12: Xilinx webpack vs. Student edition software
34708: 01/09/04: Re: fpga dev
36370: 01/11/07: Re: FPGA suppliers for hobbyists?
36534: 01/11/11: Re: Quadrature Encoder Sampling Time
36535: 01/11/11: Re: ZX81 production run, is there any interest?
36641: 01/11/14: Re: ZX81 production run, is there any interest?
36841: 01/11/21: Re: Low cost Spartan2 FPGA board
37872: 01/12/22: Re: You take the low road and I'll ......
39005: 02/01/30: Real-world keyboard signals
53774: 03/03/22: Xilinx WebPack 4.2 not compiling code that compiled on 3.3
55470: 03/05/09: Re: I want a 800 k gates FPGA in 40 pin DIL
57053: 03/06/22: Re: What's the difference between ASIC and FPGA?
57076: 03/06/23: Re: vga controller
57114: 03/06/24: Re: regarding I2C protocols
57165: 03/06/24: Re: regarding I2C protocols
57166: 03/06/24: Re: How to Capture a VGA display EXTERNALLY
57237: 03/06/26: Re: How to Capture a VGA display EXTERNALLY
58756: 03/08/01: Re: VHDL Book Recommendations Please
59775: 03/08/28: Re: Lithium cell on Virtex2 Pro
59785: 03/08/28: Re: Lithium cell on Virtex2 Pro
62045: 03/10/17: Re: VFDs
62416: 03/10/29: Re: How to protect fpga based design against cloning?
62450: 03/10/30: Re: How to protect fpga based design against cloning?
62518: 03/10/31: Are there more I/O pins than I/O blocks?
62593: 03/11/03: Re: Are there more I/O pins than I/O blocks?
62662: 03/11/04: Re: Building the 'uber processor'
Kryvor:
125900: 07/11/08: Re: Non-volatile FPGA in a small package
150392: 11/01/15: Re: Actel Designer: how to compile VHDL top & EDIF submodule together?
Krzych:
148284: 10/07/04: software for xc3000
148295: 10/07/05: Re: software for xc3000
Krzycho:
14864: 99/02/21: Eval Activ-VHDL only for 30 day :(
14873: 99/02/22: Re: Eval Activ-VHDL only for 30 day :(
14874: 99/02/22: Re: Eval Activ-VHDL only for 30 day :(
krzychosz:
66576: 04/02/23: VQM to EDIF
Krzysztof Kepa:
130570: 08/03/27: Re: A Challenge for serialized processor design and implementation
130577: 08/03/27: Re: A Challenge for serialized processor design and implementation
130579: 08/03/27: Re: A Challenge for serialized processor design and implementation
130889: 08/04/04: Re: Protecting design from being downloaded on other (similar) FPGA devices
135183: 08/09/19: Re: Help~ How to develope with FPGA board?
136835: 08/12/08: Re: encrypted and unencrypted design in the same device
138471: 09/02/24: Re: Configure FPGA via PCIe
138475: 09/02/24: Re: Configure FPGA via PCIe
143974: 09/11/05: Re: Need some help creating a ring oscillator on a Spartan-3AN
143976: 09/11/05: Re: Need some help creating a ring oscillator on a Spartan-3AN
145183: 10/01/31: Re: synthesizing a completely empty design for an FPGA to measure quiescent current
Krzysztof Olesiejuk:
53855: 03/03/25: Re: Permanent Local Damage to FPGA
57798: 03/07/07: Re: Nios bash acting bizzar
Krzysztof Przednowek:
86313: 05/06/24: State of unused pins in Spartan II.
91771: 05/11/12: AVNET's Spartan3 400 dev board & PCI
91874: 05/11/15: Re: AVNET's Spartan3 400 dev board & PCI
92452: 05/11/30: Re: grabbing PCI signals, rev-eng dev board
Krzysztof Rozniak:
9089: 98/02/19: XACT6 & ORCAD IV
9204: 98/03/02: Help with ViewLogic 4
9276: 98/03/05: Re: Help with ViewLogic 4
11147: 98/07/21: Re: EEPROM <> XC1700 ?
Krzysztof Szczepanski:
41604: 02/04/03: Pullup of Spartan-2
44821: 02/07/02: Configuring VIRTEX with init states of FF
56594: 03/06/10: XC95288 programming problem
56663: 03/06/11: Re: XC95288 programming problem
57982: 03/07/11: VIRTEX switching IO voltage 3.3V / 2.5V
63093: 03/11/14: Stratix & PLL
63643: 03/11/27: Re: overshoot problem of EPM7128S
76301: 04/11/30: Re: Config Spartan3 in serial slave mode
76552: 04/12/06: Virtex II : 3V3 to 1,8V IOB VCC
84615: 05/05/23: RISCWatch and JTAG
84971: 05/06/02: Re: regional clk to dcm? possible or not?
Krzysztof Wisniewski:
133855: 08/07/17: Re: usb core block diagram
Kshitij:
127251: 07/12/15: System Generator Design examples for spartan3, virtex 2pro?
<ksteele@cerfnet.com>:
949: 95/04/01: Re: Neocad merges with Xilinx
<ksteele@motnengr.com>:
1337: 95/06/02: Re: Latch up in Xilinx 3000 Series FPGA's. Part smokes & smells bad.
1336: 95/06/02: Re: AT&T serial EEPROMS
<ksteele@silcom.com>:
1660: 95/08/11: Re: Clocking methods - which is prefered?
1661: 95/08/11: Re: Xilinx PROMs
KsTiger:
35474: 01/10/07: Re: Xilinx Foundation vs. ISE
ksy:
75949: 04/11/20: 5V PCI interface using Spartan3
<kt8128@gmail.com>:
158077: 15/08/02: Re: Picking the best synthesis result before implementation
158078: 15/08/02: Re: Picking the best synthesis result before implementation
158082: 15/08/02: Re: Picking the best synthesis result before implementation
Kuan Zhou:
31486: 01/05/27: Help on LVDS
31580: 01/05/30: Help on Xilinx 6200
31668: 01/06/01: Re: Help on Xilinx 6200
31669: 01/06/01: CMOS technology in Xilinx 6200
32157: 01/06/15: Long interconnect in FPGA
32672: 01/07/04: Re: Problem with resolution functions
32678: 01/07/04: Re: How to estimate the number of CLBs ?
34042: 01/08/12: Fast Mux and low power voltage reference
36393: 01/11/08: Can Xilinx recognize the critical path in the design
36520: 01/11/10: Re: Can Xilinx recognize the critical path in the design
37244: 01/12/04: Where to get JBit or Jroute
47759: 02/10/03: A MAC design question
49872: 02/11/22: An Virtex FPGA architecture question
49900: 02/11/24: Re: An Virtex FPGA architecture question
50155: 02/12/03: Re: XC5204 bitstream
50300: 02/12/08: Re: Virtex archtecture question
50304: 02/12/08: Re: Virtex archtecture question
50309: 02/12/08: Re: Virtex archtecture question
50854: 02/12/20: Re: Virtex2Pro question
51053: 02/12/28: Virtex architecture newbie question
51276: 03/01/09: Power usage of CLOCK in FPGA
51294: 03/01/09: Re: Power usage of CLOCK in FPGA
51500: 03/01/14: How to add pins in ISE 4.2
51540: 03/01/16: Virtex II pro architecture question
51563: 03/01/16: Re: How to add pins in ISE 4.2
51873: 03/01/24: What's the difference between LUT and RAM?
51902: 03/01/25: Re: What's the difference between LUT and RAM?
51915: 03/01/25: Re: Why so many pins?
51917: 03/01/25: Re: Why so many pins?
51926: 03/01/26: Re: Why so many pins?
52524: 03/02/12: difficulty in designing butterfly processor
52557: 03/02/13: Re: Multicontext FPGA
52572: 03/02/14: Re: Multicontext FPGA
52573: 03/02/14: Re: Multicontext FPGA
52958: 03/02/26: Re: FPGA arch.
56241: 03/06/01: Difficulty in getting the interconnect power
56974: 03/06/19: How to design an adaptive filter
58363: 03/07/21: Distributed RAM
58370: 03/07/21: Re: Distributed RAM
59607: 03/08/23: What is the context switching time
68950: 04/04/22: What is MPGA?
68995: 04/04/23: Re: What is MPGA?
108510: 06/09/12: Cmult in System Gnerator
108749: 06/09/15: System Generator Bug
kubik:
72191: 04/08/11: why?
73610: 04/09/25: xilinx spice models
76230: 04/11/29: fpga prices
76232: 04/11/29: Re: fpga prices
77509: 05/01/08: a general question
77525: 05/01/09: Re: a general question
80847: 05/03/12: vhdl netlist synthesized
kude:
148784: 10/08/24: Text compression Huffman Encoder and Decoder
148791: 10/08/24: Re: Text compression Huffman Encoder and Decoder
148879: 10/09/06: Re: Text compression Huffman Encoder and Decoder
148880: 10/09/06: Re: Text compression Huffman Encoder and Decoder
148932: 10/09/12: Re: Text compression Huffman Encoder and Decoder
148933: 10/09/12: Re: Text compression Huffman Encoder and Decoder
149258: 10/10/12: Dynamic huffman Text encoder/Decoder
149674: 10/11/16: Huffman Encoder
149715: 10/11/20: Huffman encoder/Decoder For Text data compression
149923: 10/12/02: Help help help on Huffman Encoder
150801: 11/02/13: LUT for my vhdl code
kudla:
41137: 02/03/21: synplify, quartus II 2.0
41179: 02/03/22: Re: synplify, quartus II 2.0
kugel:
3416: 96/05/28: Re: Looking for free FPGA softw./Xilinx
<kuisuf@highmtngifts.com>:
<kulak@my-deja.com>:
18997: 99/11/23: Re: Virtex FIFO w/ Block RAM
19336: 99/12/14: Re: VirtexE availability?
19337: 99/12/14: Re: HDL editor?
kuldeep:
35181: 01/09/25: fir filter
35211: 01/09/25: Re: fir filter on ASIC
35267: 01/09/27: Re: fir filter
43876: 02/06/04: synthesis issue
Kuldeep Simha:
7115: 97/08/01: PCI Interface
<kulkarku@math.net>:
98125: 06/03/05: How to choose FPGA/CPLD ?
98134: 06/03/06: Re: How to choose FPGA/CPLD ?
98138: 06/03/06: Re: How to interface ASIC on a PCB and and an FPGA
99596: 06/03/27: spartan FPGA with PLCC package
99672: 06/03/27: Re: spartan FPGA with PLCC package
100368: 06/04/07: what is architectural diffrence between block ram & distributed ram?
100556: 06/04/11: Re: Very basic question
<kulkarni.shailesh@gmail.com>:
101608: 06/05/03: Interfacing Spartan 3 board to PC parallel port??
101630: 06/05/03: Re: Interfacing Spartan 3 board to PC parallel port??
kumar:
67113: 04/03/05: Testing a Verilog design after synthesis in Xilinx ISE
67117: 04/03/05: Testing a verilog design after synthesis in Xilinx ISE
67486: 04/03/12: targetting Verilog Design on FPGA of RC200, Data Input from PC??
67503: 04/03/12: Re: Testing a Verilog design after synthesis in Xilinx ISE
69793: 04/05/19: Debugging - Post-synthesis simulation
69921: 04/05/24: NGDBUILD warnings...please help
112220: 06/11/17: query in a design
112221: 06/11/17: Re: query in a design
112304: 06/11/19: query in delay chains
Kumar:
39844: 02/02/20: Problem While Downloading to Spartan 2 FPGA using JTAG
39912: 02/02/21: Re: Problem While Downloading to Spartan 2 FPGA using JTAG
39916: 02/02/21: Re: Problem While Downloading to Spartan 2 FPGA using JTAG
39918: 02/02/21: Re: Problem While Downloading to Spartan 2 FPGA using JTAG
39935: 02/02/22: Re: Problem While Downloading to Spartan 2 FPGA using JTAG
40055: 02/02/25: Re: Problem While Downloading to Spartan 2 FPGA using JTAG
42326: 02/04/20: logic does not work at higher frequency
42410: 02/04/23: Re: logic does not work at higher frequency
42411: 02/04/23: Factor of 2 problem while using xilinx multiplier core
44955: 02/07/08: problem while generating clk1x,clk2x,clk180 clocks from CLKDLL
89052: 05/09/03: Logic??
89058: 05/09/04: Re: Logic??
89223: 05/09/08: Re: Logic??
Kumar Deepak:
111407: 06/11/02: Re: Xilinx ISE Webpack - Any usable simulator for the Linux platform ?
Kumar Vijay Mishra:
73766: 04/09/29: PSL pros and cons
73221: 04/09/15: VHDL Design for running sorter
75101: 04/10/26: Help on Quartus Megafunction on Dual Port RAM sought...
76943: 04/12/16: Problem with SOPC Builder in Quartus 4.0
Kumaran:
63181: 03/11/17: Acek 1K - Quartus II - timing issues
63240: 03/11/18: Re: Acek 1K - Quartus II - timing issues
63384: 03/11/20: Re: Acek 1K - Quartus II - timing issues
Kumaran Selvaratnam:
49890: 02/11/24: Re: What's the matter with "clock skew and data delay"?
49906: 02/11/25: Re: What's the matter with "clock skew and data delay"?
51092: 02/12/31: Re: Unused FPGA I/O Pins?
52459: 03/02/10: Re: Synthesis Scripts
56449: 03/06/05: Re: Topic for Masters Project
<kumarator@gmail.com>:
133659: 08/07/08: Re: ISE Simulator
133682: 08/07/09: Re: ISE Simulator
Kunal:
46517: 02/09/02: Hardware Code Morphing?
46552: 02/09/03: Re: Hardware Code Morphing?
81756: 05/03/31: Re: How to map FPGA pin outputs and use User Constraints File (UCF) ?
84954: 05/06/01: Quick way to synthesize pcores in EDK
90503: 05/10/14: Re: Help me
90504: 05/10/14: Re: Xilinx ML403 Board Beginner
90588: 05/10/17: Re: Xilinx ML403 Board Beginner
90598: 05/10/17: FPGA timming
90600: 05/10/17: Re: FPGA timming
90618: 05/10/17: Re: FPGA timming
90659: 05/10/18: Re: Program FPGA from PowerPC in V2P
90756: 05/10/20: Re: to write the driver for my own ip core
90770: 05/10/20: Re: Avnet Technical Support Terrible!!!
90858: 05/10/23: Re: clock frequency after RTL synthesis vs PAR
90885: 05/10/24: Re: SoC Processor design at gate level for edu
90901: 05/10/24: Re: Xilinx ML403 Many warnings
91006: 05/10/26: Re: Cost to go from FPGA to ASIC
91092: 05/10/28: Re: Virtex-4: SLICEM and SLICEL, why? (Peter Alfke?)
91112: 05/10/29: Re: How to reduse the logic.
91184: 05/10/31: Re: question on sw tools for xilnx FPGA
91185: 05/10/31: Re: Cost to go from FPGA to ASIC
91213: 05/11/01: Re: Mitrion-C
117649: 07/04/05: PCI FPGA Dev Board Suggestions
117650: 07/04/05: Re: PCI FPGA Dev Board Suggestions
117676: 07/04/06: Re: PCI FPGA Dev Board Suggestions
117850: 07/04/11: lwIP, temac, and DMA
118191: 07/04/19: Summer with fpgas
118205: 07/04/19: Re: Summer with fpgas
118219: 07/04/19: Re: Summer with fpgas
122616: 07/08/01: Re: ASIC Digital Design Blog
123042: 07/08/15: System ACE failure on ML405
123082: 07/08/15: Re: System ACE failure on ML405
123690: 07/09/02: Re: Strange behaviour of a design
123691: 07/09/02: Re: Strange behaviour of a design
Kunal Shenoy:
91267: 05/11/02: Re: Newbie. Clocks.
91503: 05/11/07: Re: Easy Xilinx Platform Studio Question
91536: 05/11/08: Re: Easy Xilinx Platform Studio Question
91540: 05/11/08: Re: Easy Xilinx Platform Studio Question
91621: 05/11/09: Re: In Xilinx, how do I delay a signal by a fraction of a clock cycle?
91627: 05/11/09: Re: In Xilinx, how do I delay a signal by a fraction of a clock cycle?
91672: 05/11/10: Re: Signal timing problem
91887: 05/11/15: Re: Multiple Waits 2 Xilinx WebPack???
92410: 05/11/29: Re: instruction counts and cache hits/misses on FPGA
92838: 05/12/07: Re: Embedded ppc405 w/o RAM?
94094: 06/01/05: Re: Timing constraints (again)
94109: 06/01/05: Re: Do you name your FPGA?
95552: 06/01/23: Re: Xilinx Partial Reconfiguration add-on module
99315: 06/03/22: Re: Xilinx RAM16_S9.V model syntax problem
<kunals.spam.account@gmail.com>:
111975: 06/11/13: Xilinx ML310 programming failure
115246: 07/02/04: BFM and Verilog custom IP
<kundanmit@gmail.com>:
129486: 08/02/26: Using ICAP in s3a to reconfigure
kunil:
112302: 06/11/19: Spartan-3E slice resources
112420: 06/11/21: Re: Spartan-3E slice resources
112848: 06/11/29: Re: SPI Flash on Avnet Spartan 3E Eval Kit
113295: 06/12/10: Re: FPGA+Ethernet
114710: 07/01/23: FPGA power supply design
114760: 07/01/23: Re: FPGA power supply design
115782: 07/02/20: Re: Do you like Virtex-5 ?
115835: 07/02/21: Re: Do you like Virtex-5 ?
<kunilkuda@gmail.com>:
109952: 06/10/08: Xilinx distributor in South East Asia
110445: 06/10/15: Re: Xilinx distributor in South East Asia
Kuo:
120748: 07/06/15: Help on clock forwarding with Virtex-5
120761: 07/06/15: Re: help on clock fowarding between 2 FPGAs
120829: 07/06/18: Re: help on clock fowarding between 2 FPGAs
120881: 07/06/19: synthesis translate_off
121268: 07/06/29: Xilinx ngdbuild question
121273: 07/06/29: Re: Xilinx ngdbuild question
kurapati:
84622: 05/05/23: Same problem
84691: 05/05/24: problem with system ACE file on ML403 board
84719: 05/05/25: re:xilinx virtex 4 download cable
84733: 05/05/25: generate systemACE file
84792: 05/05/27: Re: Virtex 4 configuration frames
84793: 05/05/27: compact flash configuration on ml403 board
84875: 05/05/31: generate systemACE file in EDK
84920: 05/06/01: how to generate system ACE file in EDK
85020: 05/06/02: re:xilinx virtex 4 download cable
85897: 05/06/17: implementing webserver application
85898: 05/06/17: found edk example
86066: 05/06/21: problems in using TEMAC
87171: 05/07/18: re:Hard Ethernet MAC for Virtex-4 FX12
87189: 05/07/18: ethernet EMAC cores available for Microblaze
Kurt:
37431: 01/12/10: About special promotion of Synplicity's Synplify? FPGA synthesis solution
37455: 01/12/11: Re: About special promotion of Synplicity's Synplify? FPGA synthesis solution
37456: 01/12/11: Re: About special promotion of Synplicity's Synplify? FPGA synthesis solution
53254: 03/03/08: Does ByteBlasterMV support the Cyclone EP1C6 configured for 3.3V I/O?
Kurt Kaiser:
113412: 06/12/13: electrical interface problem LVPECL - LVDS multi-inputs
113456: 06/12/14: Re: electrical interface problem LVPECL - LVDS multi-inputs
Kurt Müller:
67811: 04/03/19: Leonardo Spectrum error message
Kurt R. Zaske:
2206: 95/11/01: Re: FREE $$$ MAKING SOFTWARE !!!
Kurt Rosenhagen:
1039: 95/04/19: Re: $40 Million For NeoCAD & A New FPGA Synthesis Tool
<kurtw1@my-dejanews.com>:
15953: 99/04/23: A 225K Web Bookmark manager Recommand
Kutaj Vamor:
89759: 05/09/25: Getting started VHDL, VHDL for Dummies, Easy Steps for FPGA experiments
<kutfeu@t4hsj5l.com>:
Kutlu Aricanli:
971: 95/04/05: Re: Aptix (Field Programmable Interconnect) ??
Kuznetsov Dmitry:
15163: 99/03/10: Re: Startup issues with 24c04 eeprom and I2C interface
15192: 99/03/12: Re: Startup issues with 24c04 eeprom and I2C interface
15867: 99/04/17: Re: Altera 10K and High Density FLASH Memory
15926: 99/04/21: Re: EEPROM for XC4010XL
<kvbjmt@nowhere.com>:
KVLKCL:
45793: 02/08/06: Re: Translate the design from FPGA to Custom IC
45794: 02/08/06: Re: Soundchip?
KVN Mailing List:
15886: 99/04/19: AP-ASIC'99 - Call For Papers
<kvoskaki@nps.edu>:
133472: 08/06/30: Design of a BFSK transmitter/receiver using Xilinx System Generator
KVP:
75081: 04/10/26: Clock Extraction from Bi-Phase Data
kwaj:
65907: 04/02/10: VHDL:Dividing a real number by two??
Kwaj:
65663: 04/02/04: Re: Passing user-defined types through the port (global variables??)
Kwong Chan:
18605: 99/11/03: Xlinx FPGA
18649: 99/11/05: Re: Xlinx FPGA
18668: 99/11/06: Re: Xlinx FPGA
28526: 01/01/16: How to implement a 5-variable function in a CLB?
28555: 01/01/17: Re: How to implement a 5-variable function in a CLB?
kwong lau hei:
5907: 97/03/25: Xilinx 4013 cannot configuration
kyeyk:
92603: 05/12/02: Virtex 4 IDELAY implementation
92795: 05/12/07: re:Virtex 4 IDELAY implementation
Kyle:
89876: 05/09/28: newbie questions: Xilinx vs. Altera tools and parts
Kyle Davis:
43769: 02/06/02: Looking for FPGA board with USB interface
43787: 02/06/03: Re: Looking for FPGA board with USB interface
43828: 02/06/04: Re: Looking for FPGA board with USB interface
43856: 02/06/04: Re: Looking for FPGA board with USB interface
51791: 03/01/22: Xilinx Foundation and ISE compatibility
51792: 03/01/22: Re: VHDL or Verilog?
51796: 03/01/22: Re: Xilinx Foundation and ISE compatibility
52595: 03/02/15: Xilinx Flex License Utility
52822: 03/02/24: Static 1 and Static 0 Hazard
54236: 03/04/05: Question about Xilinx Classes
54527: 03/04/13: Non Blocking Assignment
54793: 03/04/18: Non Volatile FPGA
55511: 03/05/11: PacMan game in FPGA
55572: 03/05/13: Xilinx ISE Student Edition
55730: 03/05/17: Re: Urgent: About ModelSim XEII Starter
56539: 03/06/09: FPGA Development Board
Kyle Geske:
16725: 99/06/04: Memec 8250 core with Xilinx Spartan device
Kyle Guichard:
48472: 02/10/17: HELP please! creating FPGA for first time
49923: 02/11/25: problems programming/verifying fpga using ISE 5.1
Kyle H.:
105481: 06/07/24: EDK Using External Ports to toggle FPGA pins
105622: 06/07/27: Re: EDK Using External Ports to toggle FPGA pins
105634: 06/07/27: Re: *.bit and *.elf Files
105637: 06/07/27: Re: *.bit and *.elf Files
105823: 06/08/01: XPS 7.1 to 8.1 Warnings
105827: 06/08/01: Re: XPS 7.1 to 8.1 Warnings
105830: 06/08/01: Re: XPS 7.1 to 8.1 Warnings
109037: 06/09/20: Re: Xilinx PowerPC slower than FPGA Design?
109044: 06/09/20: Re: Xilinx PowerPC slower than FPGA Design?
109060: 06/09/20: Re: Xilinx PowerPC slower than FPGA Design?
109063: 06/09/20: Re: MicroFpga = program an FPGA as it would be a MCU !
110547: 06/10/17: Getting info from XST, Homework Question, netlist, reports, etc...
110724: 06/10/20: Re: Getting info from XST, Homework Question, netlist, reports, etc...
kyokpae acn:
66778: 04/02/26: Re: Suggestions: Eval/Demo Board.
kyori:
113567: 06/12/16: DSP or FPGA for high-speed image processing?
113817: 06/12/22: Re: DSP or FPGA for high-speed image processing?
113819: 06/12/22: Re: DSP or FPGA for high-speed image processing?
kypilop:
111020: 06/10/27: Have you experience to program the APA series using FlashPro Lite?
111800: 06/11/10: Over power consumption of APA1000.... What's the problem??
113206: 06/12/08: About Unstable Operation of ACTEL(A3P1000)....
113214: 06/12/08: Re: About Unstable Operation of ACTEL(A3P1000)....
kyprianos:
128785: 08/02/06: Partial Reconfiguration of Virtex-5: ISE and EAPR?
128835: 08/02/07: Re: Partial Reconfiguration of Virtex-5: ISE and EAPR?
128864: 08/02/07: Re: Partial Reconfiguration of Virtex-5: ISE and EAPR?
129637: 08/02/29: Re: ICAP attached to Microblaze on Virtex 2-pro..
129638: 08/02/29: Re: ICAP attached to Microblaze on Virtex 2-pro..
129671: 08/03/02: Re: ICAP attached to Microblaze on Virtex 2-pro..
Kyriakos Vlachos:
31794: 01/06/06: Mapping a Library
kyrten:
68676: 04/04/13: pi/4 DQPSK demapping
Kyungjin Jang:
16248: 99/05/12: Re: Synopsys DC & Modelsim
Kyutaeg Oh:
13629: 98/12/15: [Altera]Unrecognized Devices..
<kzietlow@my-dejanews.com>:
13237: 98/11/20: functional simulation w/ Alliance???
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