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On Aug 12, 1:02=A0am, Test01 <cpan...@yahoo.com> wrote: > =A0I have a design1 that uses OSERDES and ISERDES prmitives to serialize > and de-seriliaze the data at the I/O. =A0This design1 seems to be > working fine but we need to use it test some other design - design2. > So we would like to connect the design1 to design2 inside the virtex4 > FPGA and test it in the real hardware. =A0There is some justification to > do this so for now please go along with it. > > As it is OSERDES and ISERDES primitives are for the I/O pins to > communicate to the outside world at higher speed. =A0But in my > application i need to use that serial interface in the Virtex4 fabric > itself to test the design2. > > I am under the impression that using ISERDES and OSERDES in this > manner is not possible. =A0Is that correct? =A0I can create my own > serializer and de-serilizer that can work in the fabric but I am not > sure if there is a better way to do this. > > Thanks. > > CP yes not internally accessible AnttiArticle: 142451
On 2009-08-11, jc <jcappello@optimal-design.com> wrote: > > Thanks for responding, Jon. So is your interpretation that the DDR2 > control does look at the LSB's? They don't move the starting address, they change the order of the bytes (the exact same bytes you would have gotten with LSB=0). -- Ben Jackson AD7GD <ben@ben.com> http://www.ben.com/Article: 142452
On Aug 11, 5:41=A0pm, "Antti.Luk...@googlemail.com" <Antti.Luk...@googlemail.com> wrote: > On Aug 12, 1:02=A0am, Test01 <cpan...@yahoo.com> wrote: > > > > > > > =A0I have a design1 that uses OSERDES and ISERDES prmitives to serializ= e > > and de-seriliaze the data at the I/O. =A0This design1 seems to be > > working fine but we need to use it test some other design - design2. > > So we would like to connect the design1 to design2 inside the virtex4 > > FPGA and test it in the real hardware. =A0There is some justification t= o > > do this so for now please go along with it. > > > As it is OSERDES and ISERDES primitives are for the I/O pins to > > communicate to the outside world at higher speed. =A0But in my > > application i need to use that serial interface in the Virtex4 fabric > > itself to test the design2. > > > I am under the impression that using ISERDES and OSERDES in this > > manner is not possible. =A0Is that correct? =A0I can create my own > > serializer and de-serilizer that can work in the fabric but I am not > > sure if there is a better way to do this. > > > Thanks. > > > CP > > yes > not internally accessible > > Antti- Hide quoted text - > > - Show quoted text - Is it OK if I create my own seriallizer and de-serilizer in Virtex4 fabric to replace the ISERDES and OSERDES? Are there any issues in doing so? Are there other easier solutions in this scenerio? Thanks for the response.Article: 142453
On Aug 9, 9:14=A0pm, Theo Markettos <theom+n...@chiark.greenend.org.uk> wrote: > glen herrmannsfeldt <g...@ugcs.caltech.edu> wrote: > > In most cases, the mass market software sells in large enough > > quantities to overcome a small side usage. =A0If not, then a new > > business model is needed. =A0Note that no grocery items are protected > > by AES, and yet they seem to be able to seel them and make a profit. I chuckle each time I read this. > Coming in a little late at this thread, but anyway... > > One way to tackle this issue is general economics. =A0Don't try to drive = your > product into the ground by piling it high with layers of costly DRM (whic= h > may well backfire on you, and may distract from your actual market > intentions). =A0So build a better product than the competition, or a chea= per > one, or build up enough of a market share by being first that imitations > don't matter (like I suspect Apple doesn't care about $10 Chinese knockof= f > MP3 players because they're hardly in the same marketplace). Thanks for the input. It has not been established as a fact that DRM is costly. It may consist only of software, it may consist only of a single $10 chip. this is paint with a broad brush. In fact without it maybe more costly not to have it. Comparison with 'build your product' more competitive, is assuming the cloning/ tampering is coming from competitive source and the comparison with Apple not so good in the space of FPGA product. Medical company make eye laser machine with FPGA based DSP and related contro. Products sold through distributors worldwide. When distributor get 'update' distributor re-program ALL customer systems for 'good will' and in other case program for money to distributor privately and not to company who provide the update. > The next way is to think about security economics. =A0If it costs someone > $1million to clone your product, is it worth it? =A0What about $100K, $10= K, > $1K? =A0So make it economically unaffordable to do so. =A0Now Russian or = Chinese > labour is cheap, so this has become more difficult of late. =A0But, for > example, Datel put in $17million (IIRC) into reverse engineering Sony's > MagicGate chip (the DRM controller Sony's MemoryStick flash format) and > didn't succeed. =A0The chip was a mass of random gates, with no structure= . > With semi-automated netlist generation tools they got a netlist, but it > didn't work. So the $1k is probably most accurate. Even complex FPGA board, easy to clone. http://www.techworld.com/security/news/index.cfm?newsid=3D101464 > > That investment, if successful, would probably have been worthwhile given > the worldwide sales of MemorySticks. =A0But if your field is smaller, you= r > attacker has to spend less money before it becomes economically infeasibl= e. > So perhaps simply potting your board in epoxy is enough (but a bit of a p= ain > from a service point of view). Potting is a good anti-tamper technique, but how many use it? it may not be good just as you point out for returns/service hence i look for other way to secure > If you're worried about your board being repurposed for something else, m= ake > their life difficult. =A0Use wierd connectors, and route all the traces o= n an > internal PCB layer so they can't easily be tapped and patched (a mistake = the > Xbox people made). =A0If the attacker has to spend $100 on parts and some > hours customising your board almost everyone probably won't bother. =A0An= d if > your board costs much more than $100 less than another major application > area, just increase the faff-cost to the customiser until they're level. agree. This was presented at HOST 2009, fellow showed Xbox PCB and said first part was to put ground plane on top/bottom and that would of prevented part attack. second stepto secure JTAG and third to secure FPGA (if present). > If someone is really keen, they'll be desoldering FPGAs or depackaging yo= ur > chip, applying lasers or Focused Ion Beams to it, looking at its EM > emissions or many other evil things. =A0The way to protect against that i= s > either to make that economically infeasible (so reduce the gain from doin= g > this) or else apply a higher level control. =A0I may have an attack where= I'm > able to deduce a PIN in 50 guesses. =A0But if the bank only allows me thr= ee, > I'll only be successful about 6% of the time (and to do this frequently > enough to get a decent return I run the risk that I'm intercepted and loc= ked > up). > Or a combination may apply. =A0So, despite all the security in smartcards= , > let's assume I can copy your bank card. I can go to ATMs and withdraw lot= s > of money. =A0This is only worthwhile if the cost for me to clone the card= was > less than you have in your account. =A0But the bank will notice this unus= ual > pattern after a while and block the card. =A0So even if I clone Bill Gate= s' > card I can't go on raiding his account forever. =A0If the bank blocks the= card > before I've received back the investment I put in in cracking the card, t= he > attack isn't worth it. many opinions on why not needed, answer not apprently to add security to FPGA but to create why not needed based on supermarket, based on using different connectors and other anecdotal stories and opinion on economics. Yes I read Sandeep very good stuff, i feel at least not alone in my desire for security despite all the discussion i make my product more competitive and that will solve FPGA security issue. It dos not address making product 'platform' and preventing someone from tampering to 'jailbreak' it from using my specific product add-ons. DOD security is a real issue. I found this: http://www.at.dod.mil/at-sc_references.htm unfortunate, i miss the course which was today tmorrow Best Wishes RajeshArticle: 142454
http://www.cl.cam.ac.uk/~mgk25/tamper.pdf This also very good in explaining simple low cost attacks. tamper not a concern if you are academic or make fpga hobbyist boards or you avnet/xilixn/altera demo board. no one care. If you make commerical product it maybe quite a concern. Make sure fpga not programmed with jtag and used for attack, pcb/ic have protection against physical attack, jtag not used for attack, no-traces on top/bottom for probing, conformal coat if you can do it RajeshArticle: 142455
A functional copy of an old homecomputer like Apple ][ or C64 could motivate students mostly to learn logic design, i think. Especially because of it's history and perfekt technical explanations (e.g. inside APPLE ][) Don't know if there are any legal issues here. The Apple ][ design could be partitioned into several legacy chips like DRAM or the 6502 and Z80 (which can be replaced by cores also) and small FPGA boards, e.g. representing functional units like a graphics, Z80 add-on, or floppy controller. Some small units also could be alternatively build with TTL stuff only. A digital clock for the first logic design lessons is a nice idea. Could be done with the Xilinx Starter kits Spartan3E or Spartan 3A/AN with 2 of our 3digit led display modules side by side: http://www.oho-elektronik.de/pics/UM_OHO_DY1.pdf MIKE -- www.oho-elektronik.de OHO-Elektronik Michael Randelzhofer FPGA und CPLD Mini Module Klein aber oho ! Kontakt: Tel: 08131 339230 mr@oho-elektronik.de Usst.ID: DE130097310Article: 142456
"M.Randelzhofer" <techseller@gmx.de> writes: > A functional copy of an old homecomputer Or better, have it ship pre-programmed to be a standalone web browser - softcpu; drivers for vga, keyboard, mouse, ethernet; mini-OS, browser. Plug everything in and go, then learn how to do it yourself.Article: 142457
DJ Delorie wrote: > Or better, have it ship pre-programmed to be a standalone web browser > - softcpu; drivers for vga, keyboard, mouse, ethernet; mini-OS, > browser. Plug everything in and go, then learn how to do it yourself. This would be a lifetime project for most students. I think starting with low-level gates is a good idea. First with real ones, like 7400 DIL. Then maybe with schematics editor and FPGAs, because it is much easier to build with the mouse than with wires, but the result, testing in real hardware, is the same. Finally some simple programs in VHDL. There are always some students who want to implement a web browser after this :-) -- Frank Buss, fb@frank-buss.de http://www.frank-buss.de, http://www.it4-systems.deArticle: 142458
M.Randelzhofer <techseller@gmx.de> wrote: >A functional copy of an old homecomputer like Apple ][ or C64 could motivate >students mostly to learn logic design, i think. I don't think so. This will work only with students older than 40, because fresh new students around 20 have never seen such computer and have no feelings for it. OlafArticle: 142459
"Muzaffer Kal" <kal@dspia.com> wrote in message news:3ij385lab9krukgklp7lkbm3l9olbac40b@4ax.com... > On Tue, 11 Aug 2009 19:43:29 +0000 (UTC), glen herrmannsfeldt > <gah@ugcs.caltech.edu> wrote: > >>Muzaffer Kal <kal@dspia.com> wrote: >> >>< Maybe it's because there are a lot of behavioral synthesis products >>< for C which actually work (or at least much more promising these days >>< (albeit very expensive)). >> >>What do you mean by 'work'? >> > Check out the following products and decide for yourself: > Mentor Catapult C > Celoxica Handel C > Forte CSynthesizer > Synfora PICO Some lunchtime reading: http://www.deepchip.com/gadfly/gad071409.html I agree with Muzaffer and IMHO behavioural (untimed) synthesis is definitely the way forward. Currently with all these tools (at least CatapultC) you still need to be a hardware engineer to drive them but with each new release the swingometer is slowly moving towards the dark (software) side. Hans www.ht-lab.comArticle: 142460
What would be a widely useful feature is the inclusion of a FTDI FT2232H USB2.0 Hi-speed interface - this is a really easy way to get 20mbytes/sec bandwidth from a PC with minimal work at either end. Depending on space, one of : 1) 2232H chip on board with standard or mini-USB connector 2) pair of Headers for the FT2232H mini module ( 2x26 pin 0.1" headers) 3) Single 2-row header for just the CN2 header of the module. If you look at the pinouts you'll see that by putting a standard 0.1" jumper link between pins 1 and 3 of their CN1 header, you can do everything else to get the high-speed sync parallel interface or one of the two async parallel interfaces with just CN2 - you just need to link the VCCIO and 3V3 pins on this header and put the grounds in the right place This could also be used as a general-purpose IO header for other applications. Unless you're really pushed for space, the cost/usefulness tradeoff of option 3 has to be a no-brainer....Article: 142461
Hello group,
I am trying to acces some IOB from within a partial reconfigurable
module (prm).
The arch would look like this:
/- IOB
|
|---------------------|----|
||--------------| |---|---||
|| | | ||
|| static part | | PRM ||
|| |-| ||
|| |-| ||
|| |-| ||
|| |-| ||
|| | | ||
|| | | ||
|| | | ||
||--------------| |-------||
|--------------------------|
Between both modules, there are the busmacros.
Those are working great. Anyway, the IOB located above the prm must be
connected to the prm. No busmacros. I tried so by connecting the IOB
(named debug_io(21)) within the toplevel design.
++++++++++++++++++++++++
mod_can_wrapper: mod_can
port map (
...
id => debug_io(21),
...
);
++++++++++++++++++++++++
The problem appears while running 'par':
++++++++++++++++++++++++
ERROR: Net debug_io_21_IBUF crosses a region boundary and is not part of
a slice macro.
Nets crossing region boundaries must be part of a slice macro
++++++++++++++++++++++++
I remeber setting the -iobuf option of 'xst' to no, so the module itself
does not add ibufs to the interface signals.
My question is: How can I access IOBs from within the module?
Thanks for your help
Sincerely
-- Fabian Schuh
Article: 142462We are already looking at the FT2232H and related parts principally for performance. It's not as elegant a solution as the FT232R that we have in existing designs and also several of the launch candidates. It would be nice if FTDI did a high performance version of the FT232R but meanwhile we will look at the FT2232H. In the idea world a FTDI style part, with all the easy use stuff, and with the performance of the Cypress familiy of parts would be the ideal as a manufacturer. We do have some plans for add on modules using the FTDI parts as well. Also some upgrades of our existing Cypress based USB2 module are coming. John Adair Enterpoint Ltd. On 12 Aug, 09:57, Mike Harrison <m...@whitewing.co.uk> wrote: > What would be a widely useful feature is the inclusion of a FTDI FT2232H = USB2.0 Hi-speed interface - > this is a really easy way to get 20mbytes/sec bandwidth from a PC with mi= nimal work at either end. > > Depending on space, one of : > 1) 2232H chip on board with standard or mini-USB connector > 2) pair of Headers for the FT2232H mini module ( 2x26 pin 0.1" headers) > 3) Single 2-row header for just the CN2 header of the module. If you look= at the pinouts you'll see > that by putting a standard 0.1" jumper link between pins 1 and 3 of their= CN1 header, you can do > everything else to get the high-speed sync parallel interface or one of t= he two async parallel > interfaces with just CN2 - you just need to link the VCCIO and 3V3 pins o= n this header and put the > grounds in the right place =A0 > This could also be used as a general-purpose IO header for other applicat= ions. > > Unless you're really pushed for space, the cost/usefulness tradeoff of op= tion 3 has to be a > no-brainer....Article: 142463
John Adair <g1@enterpoint.co.uk> wrote: > We are already looking at the FT2232H and related parts principally > for performance. It's not as elegant a solution as the FT232R that we > have in existing designs and also several of the launch candidates. It > would be nice if FTDI did a high performance version of the FT232R but > meanwhile we will look at the FT2232H. In the idea world a FTDI style > part, with all the easy use stuff, and with the performance of the > Cypress familiy of parts would be the ideal as a manufacturer. In what area the FT232R is mnore elegant. With very few external muxes with the FT2232H you can - serve the JTAG Chain and provide a high speed links to the PC readable as COMx or ttyUSBx - or provide two high speed links to the PC readable as COMx or ttyUSBx - or provide one 20 MB+/s link. No need to generate UART data... -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 142464
On Aug 11, 6:02=A0pm, Test01 <cpan...@yahoo.com> wrote: > > I am under the impression that using ISERDES and OSERDES in this > manner is not possible. =A0Is that correct? =A0I can create my own > serializer and de-serilizer that can work in the fabric but I am not > sure if there is a better way to do this. > If you need to test specifics about the encoded SERDES signals, then you need to bring them out to I/O pins and do your testing. Functionally the combination of OSERDES and ISERDES implements a delay. This can be implemented with flip flops. To emulate the composite OSERDES/ISERDES function simply connect design 1 and design 2 together with a bank of flops that implements the net clock cycle delay that occurs with these primitives. If you'd also like to emulate clock skew between the two domains then use a fifo to connect the two designs instead. Generate the 'design 2' clock by taking the 'design 1' clock off chip and then back in on another I/O pin. If you want to be able to vary the clock skew then put a discrete delay line in before feeding the 'design 2' clock back into the device. Kevin JenningsArticle: 142465
In article <1se3s9w5bxodj.1jbhy6iv9zya3$.dlg@40tude.net>, Frank Buss <fb@frank-buss.de> writes: |> |> This would be a lifetime project for most students. I think starting with |> low-level gates is a good idea. First with real ones, like 7400 DIL. Then |> maybe with schematics editor and FPGAs I like to object here. At our university we're teaching VHDL to undergrads and grads; the former have no previous knowledge of hardware design. Therefore, they start with simple tasks like blinkenlights and stuff, but then quickly move on to design a VGA picture generator, and finally create their own pong clone, altering the original gameplay by further ideas ranging from auto-player, multi-ball, reverse-gravity etc. (A presentation of this course was recently given at CDNlive2009 in Munich.) In the grad course, the students design and *manually* implement (i.e. not using EDK but doing completely custom designs) their own multicore CPUs incl. VGA output, with a demo program to be implemented which e.g. is a distributed Mandelbrot set computation. Both courses take 4 hours per week and run for 14 weeks, i.e. during the teaching time of a semester. Letting them implement low-level gates doesn't really achieve much in terms of HDL design; and teaching them the old way of constructing schematics based on a prefabricated set of standard chips also doesn't do much good regarding the use of *high-level* hardware-design languages. RainerArticle: 142466
The FT232R is nice because it does not need external eeprom, crystal and the trming caps and resistors. It is all in the very small tiny QFN package. All these bits are external to the FT2232 unless I missed something and hence takes X10-20 the pcb area which is still small but noticeable. For all this it is also very cheap even in low numbers. If you don't need performance the FT232R is pretty much in a class of it's own although I think there may be some compeditor parts now trying to catch up and do the same. John Adair Enterpoint Ltd. On 12 Aug, 11:25, Uwe Bonnes <b...@elektron.ikp.physik.tu- darmstadt.de> wrote: > John Adair <g...@enterpoint.co.uk> wrote: > > We are already looking at the FT2232H and related parts principally > > for performance. It's not as elegant a solution as the FT232R that we > > have in existing designs and also several of the launch candidates. It > > would be nice if FTDI did a high performance version of the FT232R but > > meanwhile we will look at the FT2232H. In the idea world a FTDI style > > part, with all the easy use stuff, and with the performance of the > > Cypress familiy of parts would be the ideal as a manufacturer. > > In what area the FT232R is mnore elegant. > > With very few external muxes with the FT2232H you can > - serve the JTAG Chain and provide a high speed links to the PC > =A0 readable as COMx or ttyUSBx > - or provide two high speed links to the PC > =A0 readable as COMx or ttyUSBx > - or provide one 20 MB+/s link. > > No need to generate UART data... > > -- > Uwe Bonnes =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0b...@elektron.ikp.physik.tu-dar= mstadt.de > > Institut fuer Kernphysik =A0Schlossgartenstrasse 9 =A064289 Darmstadt > --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 142467
Wearing one of my other hats as an an employeer, one of the things that we don't get are graduates with an understanding, of what they are actually getting, when they synthesise a FPGA design. Engineers of my generation that actually worked with 74 series logic etc.and retrained in FPGAs generally can visualise logic much easier and can cope with low level interpretation of designs when there is an issue. We do have more than occassional call for that skill when we are fixing difficult FPGA designs. However I don't think doing major student projects in schematic is called for but some basic understanding, of small end low level stuff, would be useful . John Adair Enterpoint Ltd. On 12 Aug, 13:15, buc...@atbode100.lrr.in.tum.de (Rainer Buchty) wrote: > In article <1se3s9w5bxodj.1jbhy6iv9zya3$....@40tude.net>, > =A0Frank Buss <f...@frank-buss.de> writes: > |> > |> This would be a lifetime project for most students. I think starting w= ith > |> low-level gates is a good idea. First with real ones, like 7400 DIL. T= hen > |> maybe with schematics editor and FPGAs > > I like to object here. > > At our university we're teaching VHDL to undergrads and grads; the former > have no previous knowledge of hardware design. Therefore, they start with > simple tasks like blinkenlights and stuff, but then quickly move on to > design a VGA picture generator, and finally create their own pong clone, > altering the original gameplay by further ideas ranging from auto-player, > multi-ball, reverse-gravity etc. (A presentation of this course was recen= tly > given at CDNlive2009 in Munich.) > > In the grad course, the students design and *manually* implement (i.e. no= t > using EDK but doing completely custom designs) their own multicore CPUs > incl. VGA output, with a demo program to be implemented which e.g. is > a distributed Mandelbrot set computation. > > Both courses take 4 hours per week and run for 14 weeks, i.e. during the > teaching time of a semester. > > Letting them implement low-level gates doesn't really achieve much in > terms of HDL design; and teaching them the old way of constructing > schematics based on a prefabricated set of standard chips also doesn't > do much good regarding the use of *high-level* hardware-design languages. > > RainerArticle: 142468
On Aug 12, 7:15=A0am, buc...@atbode100.lrr.in.tum.de (Rainer Buchty) wrote: > > Letting them implement low-level gates doesn't really achieve much in > terms of HDL design; and teaching them the old way of constructing > schematics based on a prefabricated set of standard chips also doesn't > do much good regarding the use of *high-level* hardware-design languages. > > Rainer I agree. It has been 25 years since I was in school, but today's students need to learn boolean logic, not TTL logic. Learning with HDL not only gets them headed in the right direction (don't use schematics for logic design), but also helps avoid some of the pitfalls of "netlist" coding styles in HDL (this process is gates, that process is registers, etc.) Most of today's students have some background in SW, and while HW design is not SW design, the similarities WRT the process are substantial. SW techniques like scope control (not talking about tweaking knobs on a lab instrument here), information hiding, development for maintenance and support, testing, etc. all apply to HDL design as well, not to mention the benefits of learning HDL testbench techniques. And to make all of this "real", they can implement it on an FPGA development board. (there, I got it back on the OP's subject). AndyArticle: 142469
Dear all, I'm looking for the equivalent system gate figures (like in Actel Igloo series) of Altera Cyclone II devices. Specifically, an equivalent for the EP2C50 in the Igloo series. Any suggestion / link is highly appreciated. NagarajArticle: 142470
On Wed, 12 Aug 2009 03:14:11 -0700 (PDT), John Adair <g1@enterpoint.co.uk> wrote: >We are already looking at the FT2232H and related parts principally >for performance. It's not as elegant a solution as the FT232R that we >have in existing designs and also several of the launch candidates. It >would be nice if FTDI did a high performance version of the FT232R but >meanwhile we will look at the FT2232H. In the idea world a FTDI style >part, with all the easy use stuff, and with the performance of the >Cypress familiy of parts would be the ideal as a manufacturer. By elegant do you just mean in terms of parts count ? In other respects the 2232H can pretty much be used as a faster 232R - the software interface, and user-configurable VID/PID stuff is the same - you can even make it appear like a COM port on steroids. I've only tested it in output-only mode, and it will sustain about 20Mbytes/sec (60MB/sec burst within a packet). The 232R's internal oscillator is a bit jittery, so probably not really up to higher rates, and the external eeprom isn't really a big deal. >We do have some plans for add on modules using the FTDI parts as well. >Also some upgrades of our existing Cypress based USB2 module are >coming. > >John Adair >Enterpoint Ltd. > >On 12 Aug, 09:57, Mike Harrison <m...@whitewing.co.uk> wrote: >> What would be a widely useful feature is the inclusion of a FTDI FT2232H USB2.0 Hi-speed interface - >> this is a really easy way to get 20mbytes/sec bandwidth from a PC with minimal work at either end. >> >> Depending on space, one of : >> 1) 2232H chip on board with standard or mini-USB connector >> 2) pair of Headers for the FT2232H mini module ( 2x26 pin 0.1" headers) >> 3) Single 2-row header for just the CN2 header of the module. If you look at the pinouts you'll see >> that by putting a standard 0.1" jumper link between pins 1 and 3 of their CN1 header, you can do >> everything else to get the high-speed sync parallel interface or one of the two async parallel >> interfaces with just CN2 - you just need to link the VCCIO and 3V3 pins on this header and put the >> grounds in the right place >> This could also be used as a general-purpose IO header for other applications. >> >> Unless you're really pushed for space, the cost/usefulness tradeoff of option 3 has to be a >> no-brainer....Article: 142471
On Aug 12, 4:15=A0pm, Nagaraj <nagaraj.shivarama...@gmail.com> wrote: > Dear all, > > I'm looking for the equivalent system gate =A0figures (like in Actel > Igloo series) of Altera Cyclone II devices. Specifically, an > equivalent for the EP2C50 in the Igloo series. > > Any suggestion / link is highly appreciated. > > Nagaraj EP2C50 ? MANY IGLOOS :) a lot of them :) well generic rule: when you move FROM Actel to Xilinx or Altera you are instantly FREE and happy, well this is relative, but the other way is much more painful for sure the gate count figures are not good usually for any comparison AnttiArticle: 142472
In article <e0cebfb5-1f3a-416f-b981-f6d6f2f6847a@s15g2000yqs.googlegroups.com>,
John Adair <g1@enterpoint.co.uk> writes:
|> Wearing one of my other hats as an an employeer, one of the things
|> that we don't get are graduates with an understanding, of what they
|> are actually getting, when they synthesise a FPGA design.
|> Engineers of my generation that actually worked with 74 series logic etc.and
|> retrained in FPGAs generally can visualise logic much easier and can
|> cope with low level interpretation of designs when there is an issue.
I'm fully with you there, but I would think that forcing people towards
space/area-constraint design would achieve similar understanding.
Personally, I believe that the major problem these days (be it hardware
or software design) is that people have somewhat "unlimited" resources
at their hands. The average computer's emory size has increased 3 orders
of magnitude during the last 25 years, likewise the logic capacity of
FPGAs is now at a size which was unbelievable even 10 years ago.
|> We do have more than occassional call for that skill when we are
|> fixing difficult FPGA designs. However I don't think doing major
|> student projects in schematic is called for but some basic
|> understanding, of small end low level stuff, would be useful .
Agreed, but probably not that low-level as Frank suggested, i.e. trying
to transform 74xx into VHDL models. Especially as the understanding
required for those kind of jobs definitely includes understanding of
the architecture and how things may be mapped onto it.
Regarding the mentioned undergrad course, one goal was getting an idea on
what it takes to create certain machine setups in hardware; in this very
case it was meant for preservation, i.e. designing full-system emulators
where the original software would still run on. The final lab project
therefore was about a compatible re-creation of an existing arcade machine
within an FPGA. Here, the focus was more put on understanding "alien" code,
extending it, and and making it work within an own design rather than
writing anything own stuff as required in the preceding tasks.
If you're interested, the poster gives a quick overview:
http://itec.uka.de/~buchty/pub/2009-cdnlive-poster.pdf
with the extended abstract being this:
http://itec.uka.de/~buchty/pub/2009-cdnlive.pdf
Rainer
Article: 142473On Aug 12, 6:21=A0am, KJ <kkjenni...@sbcglobal.net> wrote: > On Aug 11, 6:02=A0pm, Test01 <cpan...@yahoo.com> wrote: > > > > > I am under the impression that using ISERDES and OSERDES in this > > manner is not possible. =A0Is that correct? =A0I can create my own > > serializer and de-serilizer that can work in the fabric but I am not > > sure if there is a better way to do this. > > If you need to test specifics about the encoded SERDES signals, then > you need to bring them out to I/O pins and do your testing. > > Functionally the combination of OSERDES and ISERDES implements a > delay. =A0This can be implemented with flip flops. =A0To emulate the > composite OSERDES/ISERDES function simply connect design 1 and design > 2 together with a bank of flops that implements the net clock cycle > delay that occurs with these primitives. > > If you'd also like to emulate clock skew between the two domains then > use a fifo to connect the two designs instead. =A0Generate the 'design > 2' clock by taking the 'design 1' clock off chip and then back in on > another I/O pin. =A0If you want to be able to vary the clock skew then > put a discrete delay line in before feeding the 'design 2' clock back > into the device. > > Kevin Jennings I am not trying to test the specifics of OSERDES and ISERDES in design1. Design1 contans a split transaction serial bus exerciser that I need to use to test design2. But design1 uses OSERDES and ISERDES primitves to serilize the bit stream of the split transaction bus as it was intended for normal I/O application. Here I am trying to figure out if I can use design1 as is to test design2. It seems that at minimum I need to replace the ISERDES and OSERDES with my own serilizer and derserilizer verilog models to keep the low effort level. I am trying to avoid designing design1 from scratch in order to test design2.Article: 142474
On Aug 12, 6:40=A0pm, Test01 <cpan...@yahoo.com> wrote: > On Aug 12, 6:21=A0am, KJ <kkjenni...@sbcglobal.net> wrote: > > > > > > > On Aug 11, 6:02=A0pm, Test01 <cpan...@yahoo.com> wrote: > > > > I am under the impression that using ISERDES and OSERDES in this > > > manner is not possible. =A0Is that correct? =A0I can create my own > > > serializer and de-serilizer that can work in the fabric but I am not > > > sure if there is a better way to do this. > > > If you need to test specifics about the encoded SERDES signals, then > > you need to bring them out to I/O pins and do your testing. > > > Functionally the combination of OSERDES and ISERDES implements a > > delay. =A0This can be implemented with flip flops. =A0To emulate the > > composite OSERDES/ISERDES function simply connect design 1 and design > > 2 together with a bank of flops that implements the net clock cycle > > delay that occurs with these primitives. > > > If you'd also like to emulate clock skew between the two domains then > > use a fifo to connect the two designs instead. =A0Generate the 'design > > 2' clock by taking the 'design 1' clock off chip and then back in on > > another I/O pin. =A0If you want to be able to vary the clock skew then > > put a discrete delay line in before feeding the 'design 2' clock back > > into the device. > > > Kevin Jennings > > I am not trying to test the specifics of OSERDES and ISERDES in > design1. =A0Design1 contans a split transaction serial bus exerciser > that I need to use to test design2. =A0But design1 uses OSERDES and > ISERDES primitves to serilize the bit stream of the split transaction > bus as it was intended for normal I/O application. =A0Here I am trying > to figure out if I can use design1 as is to test design2. =A0It seems > that at minimum I need to replace the ISERDES and OSERDES with my own > serilizer and derserilizer verilog models to keep the low effort > level. I am trying to avoid designing design1 from scratch in order to > test design2.- Hide quoted text - > > - Show quoted text - connect some IO pins in direct loopback making own replacement for iserder/oserdes is not reasonable, and may work differently Antti
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