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Threads Starting Jun 1996
3450: 96/06/01: Mike Diack: PldShell -> Max+Plus2 conversion
3453: 96/06/01: Jeff Sampson: Re: PldShell -> Max+Plus2 conversion
3452: 96/06/01: Felix K.C. CHEN: specify fanout limit for individual net (input pin) with Exemplar
3455: 96/06/02: <sbaker@best.com>: PLDCon Xtension - On the Web
3458: 96/06/03: Kalyan Gokhale: RS422 Connections and Pin-outs
3459: 96/06/03: Mark Fanara: Re: RS422 Connections and Pin-outs
3469: 96/06/05: Arnim Littek: Re: RS422 Connections and Pin-outs
3471: 96/06/04: Peter: Re: RS422 Connections and Pin-outs
3481: 96/06/06: Mark Fanara: Re: RS422 Connections and Pin-outs
3467: 96/06/04: Todd Funderburg: Re: RS422 Connections and Pin-outs
3460: 96/06/03: Scott Kroeger: Re: Xilinxs FPGAs (newbies)
3461: 96/06/03: Peter Alfke: Re: Xilinxs FPGAs (newbies)
3466: 96/06/03: <tobias@nord.eunet.no>: Xilinxs FPGAs (newbies)
3468: 96/06/04: EDA Research: "State-of-the-Art" in ASIC design today
3472: 96/06/05: Suthikshn Kumar Channarapathnaramachandra: FPGA Companies
3475: 96/06/05: Peter Alfke: Re: FPGA Companies
3479: 96/06/06: Jeff Hunsinger: Re: FPGA Companies
3488: 96/06/08: Peter: Re: FPGA Companies
3504: 96/06/11: John L. Smith, Principal Engineer: Re: FPGA Companies
3617: 96/07/03: John W. Schwegler: Re: FPGA Companies
3619: 96/07/04: Felix K.C. CHEN: Re: FPGA Companies
3514: 96/06/12: Jeffrey C. Marden: Re: FPGA Companies
3473: 96/06/05: pcad user: FPGA error
3474: 96/06/05: Jo Dale Carothers: Low Power Special Issue
3476: 96/06/05: Jo Dale Carothers: New Deadline---IPCCC'97 CFP
3477: 96/06/06: Alex Krynev: FPGA Design flow
3480: 96/06/06: Donnelly: Re: FPGA Design flow
3478: 96/06/06: Vp2000kit-Alvin: Mixing verilog and schematic for Altera MAX9000
3482: 96/06/06: Al Sabay: wtb Lattice isplsi1048c-70lq
3483: 96/06/06: bob winters: Is someone using...
3484: 96/06/07: Don Husby: Re: Is someone using...
3485: 96/06/07: xess: low-cost FPGA development system offer
3487: 96/06/07: Alex Krynev: HEX - .LCA decompilation
3489: 96/06/10: Hubert Pujol: Schematic compare
3502: 96/06/11: Philip Freidin: Re: Schematic compare
3490: 96/06/10: alain arnaud: XUMA Digest #2
3491: 96/06/10: alain arnaud: XUMA Digest #3
3492: 96/06/10: Scott A. Hauck: FPGA'97 Call for Papers
3493: 96/06/10: Starry Hung: Wanted: HDL CD-ROM DECODER
3494: 96/06/10: <karlski@ibm.net>: UART for Actel FPGA
3499: 96/06/11: Peter: Re: UART for Actel FPGA
3506: 96/06/11: Peter Alfke: Re: UART for Actel FPGA
3521: 96/06/14: Arnim Littek: Re: UART for Actel FPGA
3528: 96/06/15: Eric Edwards: Re: UART for Actel FPGA
3530: 96/06/15: Scott Kroeger: Re: UART for Actel FPGA
3533: 96/06/16: Peter Alfke: Re: UART for Actel FPGA
3539: 96/06/17: Peter: Re: UART for Actel FPGA
3495: 96/06/11: Felix K.C. CHEN: troubles on the way from exemplar to Altera's MAX+PLUSII
3526: 96/06/14: Doug Dillon: Re: troubles on the way from exemplar to Altera's MAX+PLUSII
3531: 96/06/15: Kayvon Irani: Re: troubles on the way from exemplar to Altera's MAX+PLUSII
3535: 96/06/17: Felix K.C. CHEN: Re: troubles on the way from exemplar to Altera's MAX+PLUSII
3496: 96/06/11: Rainer Scharnow: Xtal Osc. at XC31xxA
3503: 96/06/11: Philip Freidin: Re: Xtal Osc. at XC31xxA
3510: 96/06/12: Rainer Scharnow: Re: Xtal Osc. at XC31xxA
3513: 96/06/12: Peter Alfke: Re: Xtal Osc. at XC31xxA
3497: 96/06/11: Erik de Castro Lopo: Xilinx 4013E and PCI
3507: 96/06/12: Richard Gregg: Re: Xilinx 4013E and PCI
3518: 96/06/13: Steven C. Gerson: Re: Xilinx 4013E and PCI
3498: 96/06/11: Manfred Aigner: Double Port Ram - Xact Libs
3501: 96/06/11: Philip Freidin: Re: Double Port Ram - Xact Libs
3515: 96/06/12: Roberta Fulton: Re: Double Port Ram - Xact Libs
3516: 96/06/13: Andy Gulliver: Re: Double Port Ram - Xact Libs
3520: 96/06/13: Roberta Fulton: Re: Double Port Ram - Xact Libs
3509: 96/06/11: Phil Roberts: Re: Double Port Ram - Xact Libs
3524: 96/06/14: Richard Lomas: Re: Double Port Ram - Xact Libs
3500: 96/06/11: John Cooley: %% Trolling For DAC Dirt... From Users & The "Dark Side" %%
3505: 96/06/11: Eric McCaughrin: Re: %% Trolling For DAC Dirt... From Users & The "Dark Side" %%
3508: 96/06/12: Andrew Cannon: Xilinx 4013E and PCI
3512: 96/06/12: David Holmes: Re: Xilinx 4013E and PCI
3511: 96/06/12: Gurpreet S. Bhullar: Wanted Info on faults in FPGAs
3544: 96/06/18: Philip Freidin: Re: Wanted Info on faults in FPGAs
3517: 96/06/13: Mark Shand: External SRAM, XC4000 and clock hackery
3519: 96/06/13: <jma@gotham.super.org>: >Received: from mailserv.esat.kuleuven.ac.be by netcomsv.netcom.com with SMTP (8.6.12/SMI-4.1)
3522: 96/06/14: Alexandru Seibulescu: Fintronic USA Inc. Announcement
3523: 96/06/14: Steve Casselman: Reconfigurable Computing
3525: 96/06/14: Andre' DeHon: Reconfigurable Computing -- Figures of Merit
3527: 96/06/14: Kalyan Gokhale: FPGA Conversions
3529: 96/06/15: <no-one@nowhere.com>: Re: FPGA Conversions
3538: 96/06/17: Melissa Abato: Re: FPGA Conversions
3532: 96/06/16: Johnson Wu: To subscribe
3536: 96/06/17: Felix K.C. CHEN: Re: synthesized VHDL output
3537: 96/06/17: Ludger Schulte: XC4025
3541: 96/06/18: Christian Grebe: Re: XC4025
3540: 96/06/18: Neville Miles: JTAG Boundary Scan
3542: 96/06/18: Thomas Hadlich: Q: Xilinx Foundation stuff?
3545: 96/06/18: Jo Depreitere: CLB size
3546: 96/06/18: Don Husby: Workview-Office doesn't work with ORCA
3547: 96/06/18: Don Husby: Viewlogic netlist flattener for ORCA (and Xilinx)
3548: 96/06/19: Andre' DeHon: CLB Size
3549: 96/06/19: johnson edward eric: Xilinx CLB allocation question
3550: 96/06/20: Andrew Metcalfe: Re: Xilinx CLB allocation question
3551: 96/06/19: Lance Gin: Re: Xilinx CLB allocation question
3563: 96/06/24: Rob Froyd: Re: Xilinx CLB allocation question
3564: 96/06/24: Lance Gin: Re: Xilinx CLB allocation question
3552: 96/06/20: Mark Goldberg: Agencies Avaliable
3553: 96/06/20: DeanNelson: XC1765 vs Atmel's AT17C65 Serial EEPROMs
3554: 96/06/20: Rainer Scharnow: Re: XC1765 vs Atmel's AT17C65 Serial EEPROMs
3555: 96/06/20: alain arnaud: Re: XC1765 vs Atmel's AT17C65 Serial EEPROMs
3556: 96/06/20: Rune Baeverrud: Re: XC1765 vs Atmel's AT17C65 Serial EEPROMs
3558: 96/06/20: Kevin Steele: Re: XC1765 vs Atmel's AT17C65 Serial EEPROMs
3557: 96/06/20: David McKenna: Re: XC1765 vs Atmel's AT17C65 Serial EEPROMs
3559: 96/06/21: Manfred Aigner: Routing
3566: 96/06/25: Kate Meilicke: Re: Routing
3560: 96/06/23: Tony Clark: Altera place and route
3561: 96/06/23: Peter Fenn: FPGA & PCB Design tools?
3562: 96/06/24: * Atmel FPGA Apps *: Atmel AT17C65/128/256 Serial EEPROM Memories.
3565: 96/06/25: alain arnaud: Re: Atmel AT17C65/128/256 Serial EEPROM Memories.
3567: 96/06/25: Peter Alfke: Re: Atmel AT17C65/128/256 Serial EEPROM Memories.
3568: 96/06/26: Ray Andraka: Re: Atmel AT17C65/128/256 Serial EEPROM Memories.
3570: 96/06/26: Peter: Re: Atmel AT17C65/128/256 Serial EEPROM Memories.
3569: 96/06/26: Richard Meacham: XC3100A Tristates
3573: 96/06/27: Peter Alfke: Re: XC3100A Tristates
3571: 96/06/27: Ben Stuyts: Need recommendation for PCI interface on 68332
3574: 96/06/27: Erik de Castro Lopo: Re: Need recommendation for PCI interface on 68332
3594: 96/07/02: Jim Sackman: Re: Need recommendation for PCI interface on 68332
3581: 96/07/01: Kate Meilicke: Re: Need recommendation for PCI interface on 68332
3608: 96/07/03: Richard Meacham: Re: Need recommendation for PCI interface on 68332
3572: 96/06/27: APURVA A BRAHMBHATT: HELP:Foundation VHDL on WIN95
3586: 96/07/01: JimBrakefd: Re: HELP:Foundation VHDL on WIN95
3575: 96/06/28: John Cooley: INDUSTRY GADFLY "Why I Hate Wally"
3589: 96/07/02: Stephan Gehring: Re: INDUSTRY GADFLY "Why I Hate Wally"
3596: 96/07/02: John Cooley: Re: INDUSTRY GADFLY "Why I Hate Wally"
3597: 96/07/02: Carl Wuebker: Re: INDUSTRY GADFLY "Why I Hate Wally"
3598: 96/07/02: Patrick Madden: Re: INDUSTRY GADFLY "Why I Hate Wally"
3603: 96/07/02: Joseph LoCicero IV: Re: INDUSTRY GADFLY "Why I Hate Wally"
3601: 96/07/02: Steven Bird: Re: INDUSTRY GADFLY "Why I Hate Wally"
3627: 96/07/05: Art Marriott: Re: INDUSTRY GADFLY "Why I Hate Wally"
3609: 96/07/03: Peter: Re: INDUSTRY GADFLY "Why I Hate Wally"
3576: 96/06/30: David Decker: sanity check for 100k gate DSP FPGA project (long)
3579: 96/06/30: Jonathan Griffitts: Re: sanity check for 100k gate DSP FPGA project (long)
3580: 96/07/01: Kate Meilicke: Re: sanity check for 100k gate DSP FPGA project (long)
3577: 96/06/30: Bob Elkind: FPGA ==> ASIC (GA and/or Std Cell)
3578: 96/06/30: Ehud Reshef: Using XC4000 Primary Clocks from Verilog
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
