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In article <4p3418$i0l@hilder.ee.mu.OZ.AU>, skc@ee.mu.OZ.AU (Suthikshn Kumar Channarapathnaramachandra) wrote: > Hi all, > > I am looking for companies which manufacture FPGAs > based on the following technologies: > > E/EEPROM, Antifuse(Si-electrode) and Antifuse(Metal-electrode). > To the best of my knowledge there are no FPGAs based on EPROM or EEPROM ( or FLASH ) technology, but you may want to check whether you accept the industry-standard (?) definition of FPGA vs CPLD. Most FPGAs are SRAM-besed, but you excluded that technology from you request. Antifuse-based FPGA are available from Actel, Quicklogic, and Xilinx. The alphabetical, historical, and antifuse-revenue order all happen to be identical. I think all these companies have an interesting www home page. Peter Alfke, Xilinx ApplicationsArticle: 3476
DEADLINE EXTENSION
*********************************************************************
Due to numerous requests the deadline for paper submission
has been extended to June 14, 1996 deadline for paper
*********************************************************************
Call for Papers
1997 IEEE Intl. Performance, Computing, and Communications Conference
IPCCC'97
Scottsdale, Arizona, U.S.A.
February 5--7, 1997
http://www.ece.arizona.edu/conferences/ipccc97
You are invited to participate in the 1997 IEEE International
Performance, Computing, and Communications Conference, sponsored
by the IEEE Communications Society, in cooperation with the IEEE
Computer Society. This international conference provides a forum
for the presentation and exchange of current work in computers,
communications, their synergism, and their applications. In addition
to participation by the academic community, we particularly wish
to encourage the involvement of practitioners in industrial, business,
and government settings.
*********************************
* Hot Topics for IPCCC'97 *
*********************************
Topics of interest include, but are not limited to, the following:
ATM/B-ISDN
Mobile computing
Multimedia
Network management, control, & security
High-speed networks
Network architectures & design
Optical computing
Protocol, modeling, & analysis
Optical networks
Parallel & distributed algorithms/systems
Video network systems
Fault tolerance & reliability
Quality of service
Performance analysis, modeling, & simulation
Wireless communications
Object-oriented communications
Performance measurement
Communication & multiprocessor systems
VLSI implementations
Computing & communications using the WWW
Telecommunications
Traffic modeling & performance evaluation
Applications
Internet & World Wide Web
Network operating systems
Mobile networks
Submission Procedures
---------------------
Submitted papers must have at least 11-point font size, no more than
4 lines per inch, and no more than 5000 words (about 12 pages),
including figures and references. Authors should obtain company and
government clearances prior to submission of the papers. Please
submit five copies of the complete paper (including an abstract) by
June 14, 1996, to the Program Chair.
We also solicit proposals for special topics and panel sessions. Please
contact the Program Chair for proposal guidelines.
All papers will be reviewed by the Program Committee. They will be judged
with respect to their quality, originality, and relevance. Accepted
papers will be published in the conference proceedings, conditional upon
the author's advance registration. Awards will be given for the best
paper and for the best presentation.
Author's Schedule
-----------------
Submission of papers: June 14, 1996
Notification of acceptance: September 10, 1996
Final camera-ready paper: November 4, 1996
Tutorials
---------
Proposals for half-day or full-day tutorials related to the conference
topics are invited. For tutorial submission, consult the conference
web page or contact the Tutorials Chair.
General Chair
-------------
Prof. Jo Dale Carothers
Electrical & Computer Engineering
The University of Arizona
Tucson, AZ 85721
Tel. (520) 621--8733
FAX (520) 621--8076
E-mail: carothers@ece.arizona.edu
Vice Chair
----------
Prof. Mohammad S. Obaidat
Dept. of Electrical Engineering
The City College
The City University of New York
Convent Ave. at 140th St.
New York, NY 10031
Tel. (212) 650--6621
FAX (212) 650--8249
E-mail:obaidat@ee-mail.engr.ccny.cuny.edu
Program Chair
-------------
Prof. Roy Jenevein
Dept. of Computer Science
The University of Texas at Austin
Austin, Texas, 78712 U.S.A.
Tel. (512) 471--9722
FAX (512) 346--6459
E-mail: jenevein@cs.utexas.edu
Tutorials
---------
Nasr Ullah
Motorola Corp.
6501 William Cannon Dr. West
Mail Drop OE42
Austin, TX 78735 U.S.A.
Tel. (512) 891--3668
FAX: (512) 891--2638
E-mail: nasr_ullah@email.sps.mot.com
Article: 3477Hi, All. Here is another newcomer to this business. And as all newcomers, I have a lot of different questions. But above all here we need to understand is there any possibility to convert hex files (PROM located) into design schematic files of ViewDraw.Article: 3478
Hi all I am trying to mix a verilog description into a schematic design. The verilog code will be synthesize by Synopsys and the schematic tool is Cadence Composer. The problem is that when sysnopsys synthesis the code, it will target the device, while in cadence composer the altera library is equivalent to the standard TTL. Hence I am having problem trying to generate the correct edif file for Max plus 2. I would finaly put the design into an Altera MAX9000. Does anybody knows how to do it ? Please let me know. Thanks alvin lim internet : alvinl@tmi.com.sgArticle: 3479
In article 0506961141060001@appsmac-1.xilinx.com, peter@xilinx.com (Peter Alfke) writes: > To the best of my knowledge there are no FPGAs based on EPROM or EEPROM ( > or FLASH ) technology I believe Zycad makes flash based FPGAs, though I've never heard of anyone actually using them. ---------------------------------------------------------------------- Jeff Hunsinger jeffh@oakhill-csic.sps.mot.comArticle: 3480
Why, are you trying to backwards engineer a design?Article: 3481
Peter wrote: > > >There are two standards for 422/485 pinouts. One is EIA 449 (37 pin), > >the other is ANSI/TIA/EIA-530-A (25 pin). Yes CTS/RTS are supported. > > I work a lot with 422/485, and I think the only "standard" is the > 37-way thing, which dates back many years. And it is pretty useless > because a DB37 is huge. > > All the other "standards" are within one or another manufacturer's > product range only. > > Peter. I am using a HP protocol analyzer. It supports the 449 and 530 pinouts. In fact I have a copy of the EIA/TIA-530-A standard. It is titled "High speed 25-position interface for Data terminal equipment and Data Circuit-Terminating Equipment, Including Alternative 26-posistion connector". When you write "standard" do you mean "widely used"?Article: 3482
If anyone knows of a distributor or any source for 18 pcs. of Lattice ISPLSI1048C-70LQ, please e-mail me (sabay@onramp.net). I am in urgent need of these parts and I sure would appreciate any info. Al Sabay Design Engineer Integrated Solutions Inc. 214-245-9377Article: 3483
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Article: 3484hldco@cinenet.net wrote: > > Is someone using... your computer without your knowledge? Sometimes I use it without my knowledge but only when I'm really paranoid. Instead of sending this guy the traditional termcaps file, I think we should start a new camp.arch.fpga tradition and send him your favorite .lca or .ncd file. And remember to forward a copy to root@cinenet.netArticle: 3485
XESS Corp. has a special $99 offer on an FPGA development system with complete hardware and software. You can find details at http://www.xess.com/FPGA/netoffer.html Our apologies for the commercial interruption.Article: 3486
Thomas Hadlich wrote: > > This thread is interesting, I have some experience with Synopsys, > but work mostly with ASYL+ (from IST Grenoble.fr). When I worked with > Synopsys I didn't look at the state encoding stuff, so I learned > something new now.. > But ASYL+ offers several state encoding options (one hot,optimized > compact, Gray, Johnson, sequential, random) where things like long paths > and succesive code is regarded, you can also choose the type of > flip-flop - > well you can also leave it to the synthesizer..(like most the time :) > The manual says, if you want to have real one hot encoding then use > an enumerated type for the states and leave the encoding to the > synthesizer. There was a company at DAC that was basically selling a front-end preprocessor for Synopsys; their claim was that their tool regerated your FSM code, such that synopsys would do a much better job synthesizing it. They claimed to get good results; I have no data either way. But, it wouldnt' suprise me if it was possible to get better results out of synopsys in specific areas; it seems like synopsys experts are worth a lot of bucks out there, and that means that it's a hard tool to manage well. Erik JessenArticle: 3487
Hi All, Does anybody have any info about software which could help to convert hex files which represent the programming of XC3030A FPGA back to LCA files. Best Regards, AlexArticle: 3488
>I believe Zycad makes flash based FPGAs, though I've never heard of anyone >actually using them. I have for a long time wondered if anyone will make FLASH-based FPGAs. This would be the ideal thing: the easy in-place multiple reprogrammability of Xilinx, with the facility to *not* have to do it at every power-up. Peter.Article: 3489
Hello, I have an hold schematic (8 sheets) on DASH for a Xilinx 3064. I have files such as ".xnf", ".lca", ".rpt" ... I want to get a new one for update purpose. We reentry the schematic on compass and reroute the 3064. But net are rename and file differ from the hold ones. My problem is the following : How can I be sure that the new design is equivalent to the first one ? The matter is not to do formal proof but to be able to get a same checksum for both designs. Does anybody get experiences for this problem ? Thank you for your help. --------------------------- Hubert Pujol D. R. M. Matra - Transport - International 48 - 56 rue Barbes BP 531 92542 Montrouge Cedex Tel 33 1 49 65 71 65 Fax 33 1 49 65 72 39 e-mail hubert.pujol@matra-transport.fr ---------------------------Article: 3490
Xilinx Users Mailing List Digest 2 5/30/96 1. Subject: pcm data management module 2. Subject: details and tools 3. Subject: Re: XUMA Digest 1 (XNF -> VHDL tool) 4. Subject: editlica picture --> Wfw // solution!! 5. Subject: 5.1 Tools & Viewlogic Problem 6. Subject: "tied" option Let me know if you would like me to reflect onto this mailing list, articles posted to comp. arch.fpga that are of interest to users of Xilinx tools and Xilinx devices. ====================================================================== >From bierre@sasibtlc.inet.it Mon May 27 14:06:24 1996 Subject: pcm data management module Hi' I'm searching some application about data management pcm data E1 with fpga xilinx (xc52xx family). Firstly i need information about a state machine for control sincronization of serial stream, and some idea on data framers logic. best regards Roberto Bonomi e-mail bierre@sasibtlc.inet.it ========================================================================== >From IJ.McCrum@ulst.ac.uk Sun May 26 23:42:45 1996 Subject: details and tools Sorry, my last post mentioned chipmunk... I sent the post and then read the news.... there is a new version of chipmunk updated May 1996 and in the apprpriate web pages it mentions using DIGLOG as a schematic frontend to produce XNF files, I suppose we should check out http://www.pcmp.caltech.edu/chipmunk/pickup/changes.html and its associated XNF file support. ftp://ftp.cs.indiana.edu/pub/goo/Chipmunk/netgen.tar.Z New tools for supporting Xilinx designs [Thanks to Ingo Cyliax (Indiana University)] I don't know much about this new version, as I said I only tried it a year ago.. let the list know if your using it. Regards from Ian McCrum, Lecturer in Digital Systems and ECAD ============================================================================ >From c43lyg@cc.dso.hac.com Sun May 26 09:35:14 1996 Subject: Re: XUMA Digest 1 (XNF -> VHDL tool) although i have not used it, i believe there is an XNF->VHDL model generator at ms-state's microsystems prototyping lab: http://WWW.ERC.MsState.Edu/mpl/vhdl/ i'd be interested in hearing how you like it. Lance Gin "off the keyboard ============================================================================ From: [anonymous] Subject: editlica picture --> Wfw // solution!! Hello World A little while ago I asked if somebody could tell me how to import pictures from "editlca" into Word-for-Windows. First of all my thanks to the several people who responded! For those of you who expressed interest in that procedure, here is the recipe: 1. In "editlca" type "help" on the command line. That brings up a 22-page meny of commands that can be typed in. One of which is "draw_hpplot-bw". 2. Still in "editlca" type (for example) "draw file.plt hpplot-bw world" this will generate file.plt in HP-plotter format. 3. You can also leave off "world" and "editlca" will then show a menu with two choices: "world" and "block". If you select "block" it will then ask to pick a block, which you do by either typing in its name or with the mouse in the usual way. 4. In WfW use "insert picture" and set the filter to "hp-plotter" (*.plt format). Go to the directory where file.plt lives and click on file.plt. 5. The picture will show up in the "-----.doc" and can there be stretched, shrunk, moved etc. It shows up with a rectangular empty box to the right, but by dragging the Southeast handle to the far right of the page just the picture, as it showed up in "editlca", will appear. 6. The "-----.doc" can then be printed even on just a dot-matrix printer. ======================================================================== From: Dean Fitzgerald <deanf@sqi.com> Subject: 5.1 Tools & Viewlogic Problem To the Xilinx community, Two particular difficulties with the 5.1 tools and Viewlogic have caused me grief. If anyone has insights, it would be appreciated. 1. I add a TNM property to a flip flop (say TNM = FUN). It is on a hierarchical schematic. I add a timespec of (TS04=FROM:FFS(FUN):TO:RAM=40) on the time spec symbol. (Note: On the schematic it is syntactically correct in case I missed it here.) The tools cannot find the TNM = FUN even though it is in the netlist as a property on the flip-flop symbol. The error states either that it cannot find it or you need a hierarchical path. I tried adding the path and it did not work either. Any Ideas? 2. After a clean design process I am ready to do an XNF2WIR. The Viewlogic symbol has both the pins used in the design "plus" the unused configuration pins (which are connected up for the board layout). XNF2WIR dies because those unused configuration pins are "not in the design". This worked fine in 4.X tools. XNF2WIR does work if there is no symbol. Any Ideas? Thanks in advance ... Dean Fitzgerald ========================================================================== From: [Anonymous] Subject: "tied" option WHY IS TIE AN OPTION? ==================== The primary reason that tie is an option is that it does take the MakeBits bitstream generator extra time to tie all the internal connections to a known value. During design debug, the extra time to tie a design is a nuisance. Tie is not required during a debug cycle unless you are building a power-critical application. All production designs should be tied. The MakeBits tie option defines all unused CLB and IOB inputs and consumes all available interconnect. This guarantees that all unused resources are at a know, non-floating, logic level. ============================================================================== XUMA is an independent mailing list for users of Xilinx devices and tools. To subscribe send an email to xuma_request@ecla.com To post an article, send an email to xuma@ecla.com The digests are archived at http://www.ecla.comArticle: 3491
Xilinx Users Mailing List Digest 3 6/10/96 1. Subject: win32s remove script 2. Subject: Specifying an editor in XACT 6.0 On wednesday 6/12/96, Xilinx and Marshall are sponsoring an on-line seminar on the 5200 family. Listen to live audio, and watch the presentation, as well as get any question you have answered. Go to www.marshall.com or www.xilinx.com for more details. ====================================================================== From: [anonymous] Subject: rmwin32s.bat script to remove win32s. @echo off @echo. @echo ****************************************************************** @echo. @echo Please make sure you are running this from native DOS. @echo. @echo If windows is running, please exit from windows and rerun. @echo. @echo ****************************************************************** @echo. @pause if "%1"=="" goto setName @set tmp_dir_name=%1 goto doIt :setName @set tmp_dir_name=c:\windows\system :doIt @echo Deleting win32s16.dll @del %tmp_dir_name%\win32s16.dll @echo Deleting w32sys.dll... @del %tmp_dir_name%\w32sys.dll @echo Deleting winmm16.dll... @del %tmp_dir_name%\winmm16.dll @echo Deleting win32s.ini... @del %tmp_dir_name%\win32s.ini @echo Deleting *.* in win32s directory... @del %tmp_dir_name%\win32s\*.* @echo Removing the win32s directory... @rmdir %tmp_dir_name%\win32s @echo. @echo **************************************************************** @echo. @echo You need to remove 'winmm16.dll' from the [boot] section @echo and 'device=...w32s.386' from the [368Enh] section of @echo \windows\system.ini @echo. @echo After pressing a key you will be in 'edit' to remove these @echo pieces of system.ini by hand... @echo. @echo **************************************************************** @echo. @pause @edit c:\windows\system.ini @echo. @echo Done! @echo. ============================================================================= From: [anonymous] Subject: Specifying your favorite text editor for Report Browser in XACT 6.0 I don't know how well documented this is, but I thought you might find this interesting / useful. It is possible to tell the Report Browser to use a different text editor than the default. (e.g. Word, epsilon etc.) To do this, simply place the following line in the Design Manager's .ini file. (dsgnmgr.ini) TEXT_EDITOR_PATH= <path to your favorite text editor> I don't believe the line is case sensitive, but I have not verified this. Also, this is not a formally supported feature. P.S. Design Manager must not be running when dsgnmgr.ini is modified. ============================================================================== XUMA is an independent mailing list for users of Xilinx devices and tools. To subscribe send an email to xuma_request@ecla.com To post an article, send an email to xuma@ecla.com The digests are archived at http://www.ecla.comArticle: 3492
FPGA'97: Call for Papers
1997 ACM/SIGDA Fifth International Symposium on
Field-Programmable Gate Arrays
Sponsored by ACM SIGDA, with support from Altera, Xilinx, and Actel
Monterey Beach Hotel, Monterey, California
February 9-11, 1997
(Web page: http://www.ece.nwu.edu/~hauck/fpga97)
The annual ACM/SIGDA International Symposium on Field-Programmable Gate Arrays
is the premier conference for presentation of advances in all areas
related to the FPGA technology. The topics of interest of this symposium
include, but are not limited to:
o Advances in FPGA architectures, including design of programmable logic blocks,
programmable interconnects, programmable I/Os, and development of new
FPGAs and field-configurable memories.
o New CAD algorithms and tools for FPGAs, including new algorithms for
sequential and combinational logic optimization, technology mapping,
partitioning, placement, routing, and development of new FPGA synthesis or
layout systems.
o Novel applications of FPGAs, including rapid prototyping, logic emulation,
reconfigurable custom computing, and dynamically reconfigurable
applications.
o Advances in field-programmable technology, including new process
and fabrication technologies, and field-programmable analog arrays.
Authors should submit 20 copies of their original work by September 27, 1996.
Each submission should include an 100-250 words abstract, and is limited
in length to 12 pages (including figures and tables, minimum point size 10).
Notification of acceptance will be sent by November 18, 1996.
A proceedings of accepted paper will be published by ACM.
Authors must assign copyright of their accepted papers to ACM as a condition
of publication. Final versions of accepted papers will be limited
to seven pages, and must be submitted by December 6, 1996.
All submissions should include the e.mail addresses of the authors, as all
correspondence with authors will be done via e.mail.
Submissions should be sent to:
Prof. Jason Cong
FPGA'97 Program Chair
UCLA Computer Science Department
4711 Boelter Hall
Los Angeles, CA 90095
Phone: (310) 206-2775, Fax: (310) 825-2273, E.mail: fpga97@cs.ucla.edu
Organizing Committee:
General Chair: Carl Ebeling, University of Washington
Program Chair: Jason Cong, UCLA
Publicity Chair: Scott Hauck, Northwestern University
Finance Chair: Jonathan Rose, University of Toronto
Local Chair: Pak Chan, UC Santa Cruz
Program Committee:
Michael Butts Quickturn
Pak Chan UCSC
Jason Cong UCLA
Carl Ebeling U. Washington
Masahiro Fujita Fujitsu Labs
Scott Hauck Northwestern Univ.
Dwight Hill Synopsys
Brad Hutchings BYU
Sinan Kaptanoglu Actel
David Lewis U. Toronto
Jonathan Rose U. Toronto
Richard Rudell Synopsys
Rob Rutenbar CMU
Gabriele Saucier Imag
Martine Schlag UCSC
Tim Southgate Altera
Steve Trimberger Xilinx
Martin Wong UT Austin
Nam-Sung Woo Lucent Technologies
+-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-+
| Scott A. Hauck, Assistant Professor |
| Dept. of EECS Voice: (847) 467-1849 |
| Northwestern University FAX: (847) 467-4144 |
| 2145 Sheridan Road Email: hauck@eecs.nwu.edu |
| Evanston, IL 60208 WWW: http://www.eecs.nwu.edu/~hauck |
+-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-+
Article: 3493We are developing a FPGA using Altera and one of the sub-systems is a simplied CD-ROM decoder. As it is quite standard a part, I think it may be found somewhere from the internet. Please email me if you have any idea of finding this item, commerical product referrals are also welcome. We have already designed one that's essentially a descrambler with sync detect, etc., but we want to reference to other design that uses less gate count. * Starry.Article: 3494
I need to build a UART into an Actel 1010. Ideally this should be 16450 or 16550A compatible. Can anyone help ?Article: 3495
Dear friends on the net,
I design with VHDL and use Exemplar to target Altera's
Flex10K family. I have successfully import the EDIF
file of each entity in hierarchy into ALTERA's development
tool -- MAX+PLUSII v.6.1.
In the phase of "LOGIC SYNTHESIZER" in MAX+PLUSII, however,
I get numerous warning messages that bother me very much.
Could anyone with similar experience teach me how to handle
them?
Most of them are related to instances in counter entities in
my design:
WARNING: Can not merge logic fed by CARRY primitive (an
instance name) into a single cell
INFO: Ignored 16 superfluous non-implementable CARRY or
CASCADE primitives
WARNING: CARRY primitive (an instance name) ignored
WARNING: CARRY primitive (an instance name) can not feed more
than one non-VARRY primitive
WARNING: CASCADE primitive (an instance name) cannot feed
primitive (an instance name) because it already
feeds primitive (another instance name)
WARNING: Multiple CARRY primitive feed (an instance name)
Best wishes,
Felix K.C. CHEN
--
---------------------------------
Felix, Kuan-chih CHEN (³¯ «a §Ó)
Associate Project Manager
System Product Division
D-Link Co., Hsin-chu, Taiwan
Email: flxchen@diig.dlink.com.tw
Machines and tools are only as
good as the people who use it.
---------------------------------
Article: 3496Is there anyone who had experience in constructing a crystal oscillator (1...10 MHz) at a XC31xxA similar to the description in the Xilinx Programmable Logic Data Book? My very special problem is I cannot use the dedicated IOs XTAL1/2 for that purpose. E-regards --------------------------- Rainer Scharnow (amigo@bintec.de) BinTec Commmunications GmbH ---------------------------Article: 3497
Hi, I'd like to hear comments from anybody using the Xilinx XC4013E LogiCore PCI target interface. How easy is to get a working PCI design? Is it possible to add other logic functions to the chip without it becoming unroutable? Etc, etc. Any comments at all would be greatly appreciated. I also got a quote on this chip from the distributor here in Australia of US$371 each (10 off quantities), which was quite a bit more than I expected, especially as a user of the XC3000 and XC3100 series chips. Does this price seem reasonable? Thanks in advance, Erik.Article: 3498
-- I can't find double port RAMS in thr XACT 4000 libary. How can I use this CLB facility if there is no symbol in the Libary ? Thanks in advance Manfred Aigner alias maigner@sbox.tu-graz.ac.atArticle: 3499
>I need to build a UART into an Actel 1010. >Ideally this should be 16450 or 16550A compatible. >Can anyone help ? I have never seen a complete schematic for the above. As with all marketable chips, it is a secret, and probably the only way you *might* get sight of it is by doing an ASIC design with a vendor who offers it as a macro, and even then you might get only a block. But various simple UART schematics have appeared from time to time. There is one in an old (c. 1989) Actel application note book which I have somewhere. I also remember seeing something in a Xilinx app note. These are all very basic UARTs. A 16550-compatible UART needs to have the 16-byte FIFOs; these will take up a lot of gates, in an FPGA anyway. I once just managed to fit a 20-byte FIFO into an XC3030. But I would approach this from the state machine route: state 0 waits for a +ve edge (the start of the start bit), then the transition to state 1 takes half a bit time (use a counter), then check for a 1 and return to state 0 if not present, else go to state 2 (the first data bit), then states 3,4,5,6,7,8,9 to retrieve the other 7 data bits (each delayed by 1 bit time, again done with a counter), then state 10 verifies the stop bit and flags a framing error if not a 0. Anyway, you get the idea. I normally do this with CUPL, then use a PALASM -> Xilinx translator. Then the data buffering is something else, but various FIFO schematics have been around, in FPGA app notes. But I would not try to *fully* emulate a PC UART, it is more work, and a lot of gates. Peter.
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