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FYI: There's a new book hot off the presses: Splash-2: FPGAs in a Custom Computing Machine, by D. Buell, J. Arnold, and W. Kleinfelder IEEE Computer Society Press, ISBN 0-8186-7413-X This book covers the key aspects of the Splash custom computing project born from the (formerly) Supercomputing Research Center (Bowie, MD). Splash-2 is a large experimental system consisting of (among other things) numerous XC4010s, crossbar networks, and an abundance of SRAM. The book covers the hardware, system software, and applications for the Splash machine. -P. Athanas Virginia TechArticle: 3426
First rule is to get some sleep. For instance, Xilinx position the mode pins in the sequence M1..M0..M2. It could be something really goofy! ft63@dial.pipex.com "Peter" writes: >> Hello, >> >> I have a board (a PC card) with 32 XC3064A (TQ144 package) devices, >> loaded serially (CCLK+DATA) and all 32 simultaneously. Each contains >> an identical circuit, basically a very slow but complex pulse counting >> function. Only a few pins on each FPGA are actually used; the rest are >> unconfigured so they use the internal pullup. <big snip> >> Any help is much appreciated. I have to deliver this by the 29th! >> >> Peter. >>Article: 3427
In article <4o1kfh$nv@serv.hinet.net>,
Felix K.C. CHEN <flxchen@diig.dlink.com.tw> wrote:
>Dear Friends,
>
>I might be wrong but I believe that no synthesizer can optimize
>finte state machine (in VHDL) today!
>
My first reaction when I read this post was RTFM! But, I will be
generous and assume that you don't have a good synthesis manual
available to you....
>
>The following statements are typical in a finite state machine
>VHDL code (of course we can write it in variation):
>
>-- state transition process
>
>if (CLK'event and CLK='1') then
> case state is
> when S0 =>
> if (some condition is true) then
> state <= S1;
> else
> state <= S3;
> end if;
> when S1 =>
>
Your coding style is your first mistake. Most synthesis tools
state that case statement are preferable to if else. if-else implies
priority. (This generates wasted logic in an FSM.) The second
mistake is your method of one-hot encoding. Example:
package pk is
type state is (S0, S1, S2, S3);--state can take one of these values.
attribute ENUM_ENCODING : STRING;
attribute ENUM_ENCODING of state : type is "00 10 11 01";
end pk;
library work;
use work.pk.all ; -- the default library in synopsys is work.
entity test is
port (X, clock : in bit;
Z : out bit);
end test;
architecture trial of test is
attribute STATE_VECTOR : string;
signal ST : state;
attribute STATE_VECTOR of trial : architecture is "ST";
begin
process
begin
wait until clock' event and clock = '1';
if X='0' then Z <= '0';
else
case ST is
when S0 => ST <= S1 ;
Z <= '0';
when S1 => ST <= S2 ;
Z <= '0';
when S2 => ST <= S3;
Z <= '0';
when S3 => ST <= S0 ;
Z <= '1';
end case;
end if;
end process;
end trial;
This is a "normal" state machine and this is one hot:
next_state = 8'b0 ;
case (1'b1)
// synopsys parallel_case full_case
state[START]:
if (in == 8'h3c)
next_state[SA] = 1'b1 ;
else
next_state[START] = 1'b1 ;
state[SB]:
if (in == 8'haa)
next_state[SE] = 1'b1 ;
else begin
next_state[SF] = 1'b1 ;
state[SC]:
next_state[SD] = 1'b1 ;
Mos synthesis tools have special compile modes for state machines. It is
best to use them.
//Celia Clause
Article: 3428Dear friends, although I have posted a correction for my earlier post, titled "impossible for Synthesizer to optimize FSM", many of you seem have not read the correction. I am not sure how good Synopsys is with FSM, though I have read its manual about extracting FSM from an entity. With Synopsys you have to specify the identifier of state vector you use so that it can extract the FSM. However, with Exemplar you can direct the synthesizer that how each enumeration type signal should be coded, one-hot, binary, gray and so on. I do not know which is better in result. But I think that for users' convinence, exemplar is better. In article <Ds45yu.B13@bri.hp.com> andrew@bri.hp.com <andrew@bri.hp.com> wrote: > > I have only experienced synthesis with synopsys. These are my thoughts. > > You can have all your state vectors encoded such that only 1 bit is set in any > state, thus: > > constant S0 : std_logic_vector(3 downto 0) := "0001"; > constant S1 : std_logic_vector(3 downto 0) := "0010"; > constant S2 : std_logic_vector(3 downto 0) := "0100"; > constant S3 : std_logic_vector(3 downto 0) := "1000"; > For one-hot encoding for FSM, I believe that VHDL synthesizers could reduce the comparison from a vector to a bit. According to Exemplar's Galileo reference manual, a state constant coded in one-hot is assigned a vector like "----1" or "---1-". It is not assigned "00001" or "00010". Therefore the statement like when state=state_name it implies when state="----1" rather then when state="00001". Since all logic operating on '-' are believed to be eliminated by synthesizer, there is no vector comparison at > With synopsys, it is possible to extract the FSM and then get synopsys to re- synthesys > with suitable directives to indicate that the state-vector should be decoded on a > per-bit basis and not on a per vector basis. This then does give you a true one-hot > encoded state-machine in that only 1 bit is used to decode the state. This methodology > is a pain because requires the FSM to be extracted from the design and resynthised. > I have seen it work but it just strikes me as being inefficient to have to synthesize > twice. Perhaps some others can comment on their experiences of fsm_extract. > I am not sure how good Synopsys is with FSM, though I have read its manual about extracting FSM from an entity. With Synopsys you have to specify the identifier of state vector you use so that it can extract the FSM. However, with Exemplar you can direct the synthesizer that how each enumeration type signal should be coded, one-hot, binary, gray and so on. I do not know which is better in result. But I think that for users' convinence, exemplar is better. Regards, Felix K.C. CHEN -- --------------------------------- Felix, Kuan-chih CHEN (³¯ «a §Ó) Associate Project Manager System Product Division D-Link Co., Hsin-chu, Taiwan Email: flxchen@diig.dlink.com.tw Machines and tools are only as good as the people who use it. ---------------------------------Article: 3429
Felix K.C. CHEN wrote: > [...] > For one-hot encoding for FSM, I believe that VHDL synthesizers > could reduce the comparison from a vector to a bit. According > to Exemplar's Galileo reference manual, a state constant coded > in one-hot is assigned a vector like "----1" or "---1-". It is > not assigned "00001" or "00010". > > Therefore the statement like > when state=state_name it implies when state="----1" rather then > when state="00001". Since all logic operating on '-' are believed > to be eliminated by synthesizer, there is no vector comparison at > [...] Felix, this will not work for synthesis, at least under Synopsys, and simulation results of this code will be different from your intention. A comparison of '0' to '-' (or '1' to '-', resp.) yields FALSE. Hence, if the state vector has the value "00001", and is compared to "----1", the result will be FALSE in simulation, and the particular state will not be recognized. As a rule of thumb, Don't Cares should be used only in assignments, and not in comparisons. If you want to hand-code one hot encoding, you will have to compare single bits of the state vector, like: if state(0) = '1' then ... elsif state(1) = '1' then ... ... I prefer using enumeration types for the state signal. The (Synopsys) FSM Compiler can be applied to encode the states one-hot or "auto" (which means that an optimized binary encoding is computed) and the results of the different encoding styles can be compared, whereas hand-coding requires changes in the VHDL code if you want to move from one-hot to binary or vice versa. Regards, Martin. ------------------------------------------------------------------------ Martin Radetzki e-mail: martin.radetzki@informatik.uni-oldenburg.de Carl v. Ossietzky University D-26111 Oldenburg, GermanyArticle: 3430
david@fpga.demon.co.uk wrote: > The "rough edges" referred to by recent reviewers here apply to any > newly released product. I hope you're right. Although many of my complaints seem to be designed in and, in fact, changes from the arguably better pro-series product. > I imagine that they looked at the first cut version (7.0) rather > than later versions with the rough edges smoothed. The current > release version of the Viewlogic product is, I believe, 7.11. I made my comments based on version 7.10. Based on my experience with Viewlogic, I'd be willing to bet large sums of money that no significant improvement will be made for at least a year.Article: 3431
In article <31a76353.204485@news.dial.pipex.com>
ft63@dial.pipex.com "Peter" writes:
"<snip>
"If one is using a part which can go into a socket on the *same* PCB
"footprint (e.g. DIP, or any of the PLCC devices) then the OTP parts
"are fine. One firm (Altera?) even offers to take back the first 100
"programmed parts for a 100% refund!
"
You can get QFP sockets that solder onto QFP pads. You can also get
logic analyzer adapters (i.e. fancy sockets with test points) that
solder straight onto QFP pads.
There are various sources, but the best-known is Emulation
Technology Inc. of Santa Clara.
--
David Pashley
Article: 3432Hello, is there any body there who uses Atmel Serie 6000 FPGAs and maybe even stores the configuration data in AT17C-series memory devices? If you do, you could help me a lot. I have developed a programmer that programs these little memory chips. The programming information is not very clear on the topic of the programmable reset polarity. I would like to have some sample files intended for AT17__ devices and I would like to know, what the reset polarity should be. In the documentation it says, that the reset polarity should be active low if the source file contains the data FF FF FF FF at location 04000h. This makes sence for the AT17C128, but what about the AT17C65 or AT17C256??? I would like to see the output files produced by some design package for these Atmel FPGAs so that I can adapt the programmer software to it. Thanks. Gruss, Paul. FIDO Paul Hoepping@2:2457/315.23 Internet Paul_Hoepping@citybox.fido.de Fax +49-271-3937339Article: 3433
In article <TB.96May28112333@vingmed.vingmed.no>, tb@vingmed.vingmed.no (Torbjoern Bakke) wrote: > >>>>> "P" == Peter <ft63@dial.pipex.com> writes: > > P> The odd thing I have just found is this: the 3030 "control device" is > P> visibly up and running (it is outputting various clocks which go to > P> the other 32 3064s) some 2ms before D/P gets released. This is even > P> though both /INIT and D/P are wire-ored between all 33 devices! One of > P> these clocks is 16MHz, and maybe this is interfering with the config. > P> I will work on this, but how can a FPGA be up & running while D/P is > P> still held low? > > This is odd, and should be looked into. But remember that you can > program the point were D/P changes - Before or After outputs go > active. This is all described in the databook. > > You said that the 3030 was the device driving CCLK. Thus - this > device has to start before the other devices, otherwise they will not > be configured (no CCLK). > > If you are using a serial PROM of some kind, make really sure it > doesn't start clocking out data before the devices are ready to > receive data. If this happens, you could lose the start of the > bitstream, and the devices would not configure properly. > > Hope this can be of help. > > -- > Torbjorn Bakke (tb@vingmed.no) Tel: +47 33 04 21 32 This gets interesting. Here is my analysis: The lead 3064 will go active on the second CCLK tick after it had received the amount of configuration data specified by the length count ( see page 2-29 in the Xilinx data book ). The fact that DONE was still held Low by other devices - that apparently did not receice enough CCLK ticks-, does *NOT* stop the 3030 from configuring and becoming active. ( You can wire DONE permanatly Low, and the chip will still configure properly. That is actually the recommended circuit for applications that don't have to look at DONE, and where a Low pulse on RESET must instigate reconfiguration.) I am certain that the 3030 cannot have active outputs and then spit out more than one rising CCLK edge after that. Check that CCLK stays parked High one tick after the 3030 outputs went active. So the question is: why does DONE mysteriously go High, about 2 ms later ? There is more to this circuit than we have been told. I would suggest counting or timing CCLK, to get at least a rough idea whether it has 22,216 rising edges, or 68,321, and preferrably a few more, as required for the concatenation of a 3030 and a 3064. The software generates the length-count value automatically. Check whether the preamble arrives at all DOUT outputs, and if possible analyze the length count. Has the length count been edited ? Are its bits in the right order? Remember, the value came from a parallel interface, but the chip is only interested in the bit-serial value that appears, MSB first, after the eight ones, followed by 0010 in the header. The next 24 bits are length-count, MSB first. Remember, it does not hurt to have a length-count value that is too large, it just takes longer to configure, but a length-count that is too short prevents configuration. My guess is still that there are double-transitions (reflections) on CCLK. That's why I suggest to lengthen the transition times drastically, e.g with a 50 Ohm series resistor and a 200 pF capacitor to ground, the usual dirty remedy when s signal causes reflections. I hate to make this sound complicated, it really is not. And we will fix this design, if we only get all the information. Peter Alfke. Xilinx Apps.Article: 3434
> If one is using a part which can go into a socket on the *same* PCB > footprint (e.g. DIP, or any of the PLCC devices) then the OTP parts > are fine. One firm (Altera?) even offers to take back the first 100 > programmed parts for a 100% refund! Altera makes some nifty development sockets for their PQFP-packaged devices. they require a bit more clearance around the part than if you just soldered the part to the board, but the socket is footprint-compatible with the PQFP. Works for me. rob rob.pfile@eng.sun.com standard disclaimer; not speaking for Sun, yadda yadda...Article: 3435
Newsgroups: comp.cad.synthesis,comp.lang.vhdl Subject: Re: VHDL synthesis & style questions: From: flxchen@diig.dlink.com.tw (Felix K.C. CHEN) Organization: D-Link Co., Hsin-chu, Taiwan References: <4oia3j$aqb@atheria.europa.com> X-NewsReader: Hi, You do not have to worry (or protect) the wrap around problem if you "add the std_logic_vector" rather than add the integer. The package ieee.std_logic_arith seems support addition on std_logic_vector. If not, please try synopsys's de-facto package std_logic_unsigned.all. The addition on std_logic_vector is very simple. In your case, you can code y <= y + "1"; -- but change the port direction from out to inout Best wishes, Felix K.C. CHEN In article <4oia3j$aqb@atheria.europa.com> Clifford E. Cummings <cliffc@europa.com> wrote: > VHDL synthesis & style questions: > > In VHDL, I could not add to the std_logic_vector output, I had to declare a > separate count register of type integer that I could add to, I had to compare > the integer to 15 because I could not allow the integer to wrap around (run > time syntax error), and I had to use a conversion function to re-assign the > integer to the std_logic_vector output (shown below): > > --------------------------------------------------------------------- > library IEEE; > use IEEE.std_logic_1164.all; > use IEEE.std_logic_arith.all; > > entity count4b is > port (y : out std_logic_vector(3 downto 0); > clk, rstN : in std_logic); > end count4b; > > architecture rtl of count4b is > signal count : integer range 0 to 15; > begin > process (clk, rstN) begin > if (rstN = '0') then > count <= 0; > elsif (clk = '1' and clk'EVENT) then > if (count = 15) then count <= 0; > else count <= count + 1; > end if; > end if; > end process; > > y <= CONV_STD_LOGIC_VECTOR(count, 4); > end rtl; > --------------------------------------------------------------------- > > When I synthesized the two models using Synopsys (Design Optimization>Map > Design>Medium), the Verilog model produced the 4-bit counter with wrap- around > as expected, but the VHDL model produced the same 4-bit counter with logic for > comparing the count to 15. I know about the new IEEE.numeric_std package for > synthesis which would help with the wrap-around problem, but Synopsys does not > seem to support it yet(?). How widely is it supported? > > I suppose I could have declared the output to be of type integer to avoid the > conversion function re-assignment(?) but that brings up a VHDL style question. > Is there a recommended I/O declaration style which makes porting and > instantiating VHDL models easier for other users of foreign models? > > I also ran into a case where it was more convenient to declare an output to be > of mode "buffer" so that I could read the output from within an architecture > that was checking for a full bit. I could not find an index reference in Doug > Perry's book for "buffer", and I only found one example in J. Bhasker's book > on "buffer" and it appears that whatever connects to an instantiated "buffer" > must also be of type "buffer", which again raises the question of I/O > declaration style recommendations? (I seem to recall that the VHDL > participants in John Cooley's "EDA Shootout" ran into problems > (type-mismatches which caused some re-coding delays) when "buffer"-mode was > used. > > Is there a better way to write my VHDL code for this 4-bit counter? > > Regards - Cliff Cummings > > //********************************************************************// > // Cliff Cummings E-mail: cliffc@europa.com // > // Sunburst Design Phone: 503-579-6362 / FAX: 503-579-7631 // > // 15870 SW Breccia Dr., Beaverton, OR 97007 // > // // > // Verilog & Synthesis Training / On-Site Training // > // Verilog, VHDL, Synopsys, LMG, FPGA, Consulting and Contracting // > //********************************************************************// > -- --------------------------------- Felix, Kuan-chih CHEN (³¯ «a §Ó) Associate Project Manager System Product Division D-Link Co., Hsin-chu, Taiwan Email: flxchen@diig.dlink.com.tw Machines and tools are only as good as the people who use it. ---------------------------------Article: 3436
!!! "It's not a BUG, jcooley@world.std.com
/o o\ / it's a FEATURE!" (508) 429-4357
( > )
\ - / INDUSTRY GADFLY: "Synopsys Redeemed; Summit Rises"
_] [_
by John Cooley, EE Times Columnist
Holliston Poor Farm, P.O. Box 6222, Holliston, MA 01746-6222
Roughly 5 years ago, Synopsys tried to sell a tool called FSM Compiler.
It was an add-on product to Design Compiler that was supposed to do great
things for state machines -- thus supposedly justifying its high price
at the time. Those who foolishly bought FSM Compiler found it full of
bugs plus it made their state machines far worse! Synopsys customers
took great joy in bashing FSM Compiler in the weekly E-mail Synopsys Users
Group (ESNUG) discussions. At first, Synopsys desperately tried to fix
all the bugs. But, eventually Synopsys backed off of trying to sell FSM
Compiler and quietly merged it into Design Compiler as a "free new
feature". Synopsys apps engineers and instructors practiced clever yet
discrete ways to warn customers to avoid FSM Compiler. Through the years
Synopsys quietly fixed the bugs in FSM Compiler -- but it still remained
a public embarrassment that Synopsys just wanted to forget.
Fast forward to the Great ESDA Shootout at the recent 1996 HP Design
SuperCon. Seventeen design teams (including five ESDA vendors) frantically
tried to create and synthesize a state machine with the fastest clock-to
-clock timing. The big question being asked was: Are ESDA tools up to snuff
compared to engineers doing hand coded Verilog or VHDL?
Among the ESDA companies, Summit Design did very well in the design entry
and ECO stages; for synthesis results, i-Logix and Speed Electronic got
second and third place with 2.09 nsec and 2.31 nsec respectively. Hoai Tran
of Symbios Logic, a hand coder using Verilog, won with a 1.77 nsec design.
All of the other hand coders ranged from 2.46 to 3.35 nsec. Even Bob
Painter, who learned basic Verilog, Design Compiler and "vi" from reading a
magazine article *during* the contest, got a 2.94 nsec design that easily
beat Mentor Graphic's last place 4.25 nsec!
Afterwards I was surprised to find out that the first and the third place
teams had both used FSM Compiler. This, plus one ESDA vendor's complaint
that everyone should have used the *same* Synopsys script to make all
non-ESDA things equal, prompted me to personally re-synthesize everything
using FSM Compiler. To my surprise, 8 out of 9 hand coded designs
synthesized down to 1.73 to 1.78 nsec! (Only newbie Bob Painter's design
came in at a slower 2.03 nsec.) Even Mentor's last place 4.25 nsec improved
to 2.08 nsec! All but one design got faster by about 50 percent with
FSM Compiler!
My congrats now go to Summit Design. Summit took third in design entry,
first in ECO, and first in synthesis (tying with John Gilbert of Motorola)
with a 1.73 nsec design. Gilbert used Verilog and Summit used VHDL.
Summit's Verilog also took second place in the synthesis category with
1.76 nsec. My sympathies now go to i-Logix because their contest design
data was lost and to Speed Electronic because their 2.30 nsec design now
ranks dead last out of the twelve contenders in the synthesis category.
I'd like to thank HP Design SuperCon for sponsoring the Great ESDA Shootout;
it has reintroduced us cynical engineers to FSM Compiler -- and 50 percent
faster state machines! (I'm sure Summit Design didn't mind this new
discovery, either!)
------
John Cooley runs the E-mail Synopsys Users Group (ESNUG), is president of the
User Society for Electronic Design Automation (USE/DA) & works as a contract
ASIC/FPGA designer. He loves hearing from fellow engineers at "jcooley
@world.std.com" or (508) 429-4357. [ Copyright 1996 CMP Publications ]
Article: 3437Felix, Kuan-chih CHEN (flxchen@diig.dlink.com.tw) wrote: : Newsgroups: comp.cad.synthesis,comp.lang.vhdl : Subject: Re: VHDL synthesis & style questions: : From: flxchen@diig.dlink.com.tw (Felix K.C. CHEN) : Organization: D-Link Co., Hsin-chu, Taiwan : References: <4oia3j$aqb@atheria.europa.com> : X-NewsReader: : Hi, : You do not have to worry (or protect) the wrap around problem if : you "add the std_logic_vector" rather than add the integer. : The package ieee.std_logic_arith seems support addition on : std_logic_vector. If not, please try synopsys's de-facto : package std_logic_unsigned.all. : The addition on std_logic_vector is very simple. In your case, : you can code : y <= y + "1"; -- but change the port direction from out to inout IMHO, the use of "inout" on a port which is really only an output is a nasty hack. We use "buffer" with very little grief and it reduces the risk of having multiple drives on a signal where we don't want it (these problems are found at analyse/elaborate time and not at run-time). Synopsys "design_compiler" has no problem with ports of mode buffer. There are a few complications in the use of "buffer"s when you wish to mix components with mode "out" with components which have "buffer"s. As long as one is aware of the restrictions then there is little overhead. If you want further clarification, I'd be pleased to help. Andrew library usual; use usual.disclaimers.all;Article: 3438
Rafiki Kim Hofmans (tw38966@vub.ac.be) wrote: : : Hi, : : I'm trying to create a ROM (2x32) with the memgen of Xact 6.0. : After inserting parttype 4010pq160-3 and editing the memorydata the : output states parttype 4005pg156, width 0 and depth0. : : And prosim doesn't recognize the created ROM symbol. : : Anyone experienced with the memgen ? : : Thanks in advance ! : : Kim : We wanted to use Memgen in combination with Mentor DA and had the problem that the automatic designed symbol interface was not created correctly, so we created a schematic out of the xnf file (created by memgen) and then we added the in and outports manually and designed a symbol for this.In the created schematic you can see a HEX-Value on the ROM symbols that represetates the data. For a 32*4 ROM we need about 10 minutes so its shorter than to find out a better way, but if anyone knows please tell me (thread memgen+mentor) -- Manfred Aigner alias maigner@sbox.tu-graz.ac.atArticle: 3439
>My guess is still that there are double-transitions (reflections) on CCLK. >That's why I suggest to lengthen the transition times drastically, e.g >with a 50 Ohm series resistor and a 200 pF capacitor to ground, the usual >dirty remedy when s signal causes reflections. This is probably what it was. I say "probably" because I can make it fail even when the waveform looks clean, on my 250MHz scope. I can make it reliably configure with either of: 1. the 3030's CCLK output driving the 32-off 3064s direct, with 220pF to GND; 2. the 3030's CCLK output driving a 74AC244 buffer, then 470pF to GND, then to the 3064s. I also find that with a very clean but slow edge it does not configure, around 30ns or slower. Any resistor in series makes things worse. The only conclusions I can reach are: that I had transmission line problems; that the edge must be faster than about 30ns; that the devices are sensitive to noise or glitches which are too fast to see on a 250MHz scope. >I hate to make this sound complicated, it really is not. And we will fix >this design, if we only get all the information. Short of posting the schematic and PCB layout, I did describe it as best as I could. But it is working now, so - THANKS TO EVERYONE FOR YOUR HELP. Peter.Article: 3440
I am trying to configure one FLEX81500 using PSS mode. Any one knows what kind of configuration file should I generate from MAXplus2? The "sequential .rbf" file or else? And what about the file format? Feng YunArticle: 3441
W A N T E D
ASIC/FPGA Engineers
Papillon Research Corporation
(formerly Chrysalis Research Corp.)
Due to continued growth, Papillon Research in Concord, MA is
seeking to expand its hardware engineering group.
We are looking for experienced Digital Hardware Engineers to
participate in leading edge ASIC, FPGA, and board-level designs using
the latest in HDL synthesis and simulation tools. If you desire to
work in a casual, startup atmosphere and have practical experience in
these areas, please contact us (PRINCIPALS ONLY):
Papillon Research Corporation
52 Domino Drive
Concord, MA 01742
jobs@chrysal.com
508-371-9175 (fax)
Chrysalis Research Corp. is not related to Chrysalis Symbolic Design.
Article: 3442In article <Ds7AIE.2ED@world.std.com>, John Cooley <jcooley@world.std.com> writes > >Among the ESDA companies, Summit Design did very well in the design entry >and ECO stages; for synthesis results, i-Logix and Speed Electronic got >second and third place with 2.09 nsec and 2.31 nsec respectively. Hoai Tran >of Symbios Logic, a hand coder using Verilog, won with a 1.77 nsec design. >All of the other hand coders ranged from 2.46 to 3.35 nsec. Even Bob >Painter, who learned basic Verilog, Design Compiler and "vi" from reading a >magazine article *during* the contest, got a 2.94 nsec design that easily >beat Mentor Graphic's last place 4.25 nsec! > >Afterwards I was surprised to find out that the first and the third place >teams had both used FSM Compiler. This, plus one ESDA vendor's complaint >that everyone should have used the *same* Synopsys script to make all >non-ESDA things equal, prompted me to personally re-synthesize everything >using FSM Compiler. To my surprise, 8 out of 9 hand coded designs >synthesized down to 1.73 to 1.78 nsec! (Only newbie Bob Painter's design >came in at a slower 2.03 nsec.) Even Mentor's last place 4.25 nsec improved >to 2.08 nsec! All but one design got faster by about 50 percent with >FSM Compiler! > >My congrats now go to Summit Design. Summit took third in design entry, >first in ECO, and first in synthesis (tying with John Gilbert of Motorola) >with a 1.73 nsec design. Gilbert used Verilog and Summit used VHDL. >Summit's Verilog also took second place in the synthesis category with >1.76 nsec. My sympathies now go to i-Logix because their contest design >data was lost and to Speed Electronic because their 2.30 nsec design now >ranks dead last out of the twelve contenders in the synthesis category. >I'd like to thank HP Design SuperCon for sponsoring the Great ESDA Shootout; >it has reintroduced us cynical engineers to FSM Compiler -- and 50 percent >faster state machines! (I'm sure Summit Design didn't mind this new >discovery, either!) > >------ IMHO the admission that contestants were not using the same synthesis tools makes the results highly suspect. Also you left out the changes in area! which is of course relevant. I'm not entirly sure what this exercise has proven maybe you could post a summary. ------------------------------------------------ Steven Bird VIZEF Limited Tel: 44 (0)1628 481571 Fax: 44 (0)1628 483902 ------------------------------------------------Article: 3443
landmarktrvl <landmarktrvl> wrote: >Dear Reader, >Are you running out of destinations for your VACATION LIST? >Are you interested in knowing more about history, culture and traditions? I will assume that you are new to the internet -- what you have done is known as spamming, and is most unwelcome. Do it if you want to non technical newsgroups (where this kind of thing is more popular), but this kind of posting to a technical newsgroup will just cause flames. I suggest you find out the meaning of the word "spam", and also "mail bomb" before doing this again -- we can fight back -- and the simple reaction is that because of the rudeness of this kind of advertising knowone ever reads what you are offering. -- Gavin Melville, gavin@cypher.co.nzArticle: 3444
[ Enclosed is a review of last year's (1995) DAC in San Francisco. If you
bump into me at DAC next week in Las Vegas, tell me what you think is hot
and what's not, so I can include it in this year's review! :^) - John ]
!!! "It's not a BUG, jcooley@world.std.com
/o o\ / it's a FEATURE!" (508) 429-4357
( > )
\ - / The Third Annual ESNUG/DAC Awards:
_] [_ "Sleep Deprivation, MacGyver & DAC '95"
- or -
"One Engineer's Review of DAC'95 in San Francisco, CA, June 12-16, 1995"
by John Cooley
Holliston Poor Farm, P.O. Box 6222, Holliston, MA 01746-6222
Legal Disclaimer: "As always, anything said here is only opinion."
[ Check out http://techweb.cmp.com/eet/docs/eetff.html (WWW EE Times)
for a photo of the DAC freebies & the awards they received! - John ]
It's amazing what the mildly hallucingenic effect five days worth of sleep
deprivation can do to the engineering mind. I remember in college psychology
there was some question as to whether humans actually dream in color or not.
By my fourth day of getting only 50% of my normal amount of sleep at DAC, not
only did the demos start breathing and exhibiting 3-D properties, I could now
personally attest that we do dream (or at least sleep walk) in color. It was
then I started pondering the big questions...
Why do engineers count by going "0, 1, 2..." instead of "1, 2, 3..."? Is
it possible to build a single pin chip with power, ground, input and output
all time multiplexed? Would "MacGyver", "Batman", "James Bond", and "Dr.Who"
suddenly all become glamorless technerds if they owned up to having an
engineering background? Instead of a circuit built on the assuption that
every question can be answered with a "yes" or a "no" (a binary system), what
would it look like if we based it on "yes", "no", or "no answer" (a trinary
system)? If engineers are so smart, why are they in the middle class? What
if there were no hypothetical questions?
Then I hit upon the one question that I could answer: "What were the ESNUG
User DAC awards this year?"
BIGGEST SURPRIZE AT DAC: Silerity. At first, I thought Alain Hanover (CEO
of ViewLogic) bought Silerity just as part of the deal to get Will Herman
back on board at ViewLogic. But after looking at the Silerity PathBlazer I
was surprized that there was real value there. What I saw was a datapath
compiler that, through brute force, went through all the datapath part and
layout permutations to produce an optimal final design. Cool! Runner up:
Mentor buying Exemplar. (Rumor was MGC might buy IST. IST is focused
primarily in VHDL and is still at the start-up stage. Exemplar is well known
in Verilog and VHDL in both the PC and UNIX worlds. Good choice Exemplar.)
WEIRDEST PRE-DAC IMAGE: Before DAC, ArcSys sent a postcard to customers with
pictures of six people in a "Name The Great Thinkers" contest. The odd thing
was that one "great thinker" appeared to be Lizzie Bordon, a famous ax
murderer from Massachusetts who killed her father and stepmother. Another
appeared to be Machiavelli, author of a book advocating gaining power via
cunning and ruthlessness with no regard to morality (and, incidentally, was
reputed to be the favorite bedside reader of Hitler, Stalin, and Mussolini!)
MOST TROUBLED HEIR APPARENT: SpeedSim. With high speed Chronologics falling
into disarray, Verilog vendors like Intergraph, Frontline, and Simucad have
been salivating at taking second place in the Verilog simulator market. It
appears that SpeedSim's super fast cycle based Verilog racehorse is the heir
apparent, but it's under a dark cloud. Synopsys has been heavily hinting
that they're working on a cycle based simulator of their own, but won't say
if it is Verilog, VHDL, or both.
BIGGEST CINDERELLA AT DAC: The IC place and route companies. With all the
engineering conferences chanting the mantra of "deeeeep suuuub miiiicroooon",
the usually ignored IC place and route companies like ArcSys, Cooper & Chyan,
ISS plus parts of Mentor and Cadence have suddenly come out of the closet
telling mainstream engineers: "Look at me! I'm hot technology!" The grand
pappy of all IC place and route, the once public domain TimberWolf, even made
its commercial debut at this year's DAC.
FIRST TO HACK DACNET AWARD: Unknown. An unidentified PCB EDA vendor managed
to hack DACnet's internal mailing list, get a partial listing of DACnet
account names and send junk e-mail every day promoting their wares. (I can't
get confirmation as to exactly which company did this, because most people
ignored the e-mail infomercial after the first day.) Despite this, a lot of
people enjoyed having the ability to check their secure home e-mail via
DACnet. Afterwards, the DACnet people forwarded the leftover e-mail in our
conference acounts to our home accounts. (A class act!)
BIGGEST LIE AT DAC: The NTT "Consortium." Angry attendees reported that
through Harmonix, Nippon Telegraph & Telephone (NTT), Japan's version of
AT&T, tried to create the image that there was a new "consortium" promoting
their NTT proprietary C-like SFL language as an industry standard in
reconfigurable computers. What angered the researchers at the meeting was
that they were indirectly told that the company with the money (NTT) would
control the "consortium." Also, all technical issues where handled in a hand
waving fashion. One researcher said: "Harmonix/NTT never mentioned the
problems of a reconfigurable logic operating system (the biggest sticking
point in the concept today) nor described how they were going to solve the
dynamic place and route problems, time-based partitioning, nor anything else.
These people were going to decide the industry standard for reconfigurable
computing?!?"
WHAT ENGINEERS TALKED ABOUT: This was the year for the fruity niche tool.
Other than GLOBEtrotter's licence management and admin tools, there was no
one hot EDA "toy" that everyone raved. What people saw was heavily
influenced by what they wanted to see.
The power junkies were seen shooting up around the Epic Design booth on their
'Mill products, Mentor for the Lsim Power Analyst, Systems Science for their
PowerSim and PowerFault, plus Synopsys for their rumored power tools.
The engineering Survivalists saw the world shortage of foundry capacity as a
bad sign and sought out the foundry-independent ASIC solutions offered by
SiArch, Mentor, Compass, Cascade, Sagantec, Aspec, and Meta-Software.
The I-don't-want-learn-another-damned-tool ASIC designers gravitated to the
tools made for them. Synplicity provided a simple, one button FPGA synthesis
tool that took all of 30 seconds to learn and run. Interconnectrix offered a
pricey PCB place and route tool that took in constraints in EE terms (instead
of geometric rules of thumb) to build PCB's that passed timing and signal
integrity specs. HLD Systems offered a general floorplanner that hooks
rather nicely into the Synopsys environment eliminating the need to learn the
25 or so ASIC specific floorplanners. Intellitech offered a general purpose
foundry/synthesis independent BSDL file generator.
Engineer members of the "Glowing Path Pure RTL Level Design" cult sought out
Synopsys HDL Advisor to help them write and analyze their RTL source code for
synthesis *before* synthesis, InterHDL for VeriLint (a killer Verilog syntax
checker) plus their V-to-V (a two way Verilog/VHDL translator) and Cadence's
newly announced RTL level floorplanner called SiliconQuest. Cultists also
noted that Leda pushed a universal VHDL source encrypter while Chronologics
pushed a universal Verilog model encrypter.
Pugilistic engineers said: "Looks like AT&T Design Automation is going to get
into some interesting fist fights with Chrysalis and Abstract Hardware in the
formal verification market, and LogicVision in the BIST market."
A few EDA vendors themselves happily noticed that although Microsoft had a
booth at DAC last year, they didn't this year. (They figured that a 2
billion dollar industry was chump change as far as Bill Gates was concerned.)
MOST CURIOUS NEW COMPANY AWARD: Savantage. These guys created a tool that
looks at a design as a bunch of raw dies and juggles partitioning through the
packaging, PCB, heat exchanger, connector, bonding, assembly, backplane and
enclosure issues with an eye on costs. A manufacturing engineer's dream.
BEST USE OF TERRAIN FOR A DAC PARTY: Synopsys took 400+ customers to
Fisherman's Warf in trolley cars to jump on a boat ride to Alcatraz. (After
having crashed three of Synopsys's DAC parties over the years, I was
personally kind of uneasy when, this time, they sent me an invitation to
visit a prison...) Anyway, we were given a great guided tour of the island
prison and then fed a yummy dinner on a evening cruise in San Francisco bay.
Even anticipating that the customers might get cold on the boat, Synopsys
gave us white sweaters tastefully embossed with a subdued "SYNOPSYS" in the
fabric! (The only down side was after dinner when the ferry was maneuvering
underneath the Golden Gate Bridge with a full moon and a fantastic view of
San Francisco at night. I really didn't want to be next to three engineers
from Data General plus two Synopsys R&D types. I wanted my girlfriend!)
Runner Up: Quickturn took customers for the best night view of the city, the
52nd floor of the Bank of America Building. The jazz band was excellent and
having their own home brew of HDL ICE beer was a hoot!
BEST CONGRESSIONAL JUNKETEER: Yatin Trivedi. Yatin, in a move that would
embarrass even the most corrupt congressman, managed to not only get himself
on the Design Acceleration sponsored harbor cruise, he got his wife, his kid,
his business partner and his business parter's wife on board!
WORST PLANNED DAC PARTY: The Official DAC "Cruise The Mediterranean" party.
Like a fool I thought we'd have a boat ride, but it just turned out to be one
HUGE room with food, beer and music. I did like seeing all the EDA vendors
and customers there, but thought it odd that at a conference which is 95%
male, they had a band playing slow dance music. Then I remembered: "Oh, yea!
That's right. We're in San Francisco!"
PANEL WITH THE MOST POLITICAL INTRIGUE: For a few months the Users Society
for Electronic Design Automation (USE/DA) has been surveying EDA customers
about proposed changes in the way EDA tools are sold. When USE/DA tried to
have a lunch panel on Monday at DAC to discuss the results with the CEOs of
the Big Four EDA companies, the DAC Committee nixed the idea for fear of
stealing from Ron Collett's panel on Tuesday. They wouldn't list the USE/DA
panel in any schedule and forbid the use of signs directing engineers to
where the USE/DA lunch panel was. Plus, they asked the CEOs not to attend!
At the last minute, Collett put an engineer from IBM to represent foundries
plus one of his unknown clients from Siemens to represent user views on his
Tuesday panel. (That is, no USE/DA people who have been working on these
issues were invited.) Despite the intrigue, the Monday USE/DA panel drew
CEOs Wally Rhines (of Mentor) and Aart De Geus (of Synopsys) along with 200
people as an audience. Interestingly, we found some real working data from
polling the audience; customers prefered a model of having all tools always
available to use as needed and to pay later on a per use basis (as opposed to
the PC shrink wrap sales model.)
WORST YET MOST ENTERTAINING DAC PANEL: Collett's five EDA CEOs DAC panel.
The panel consisted of Collett baiting each of the CEOs with embarrassing
issues they had dealt with throughout the year. At any moment I expected the
CEOs to pull out whiffle ball bats and start hitting each other. (Most
attendees voiced dual reactions of thinking the panel was a complete waste of
time, yet also very entertaining.) Richard Goering did a great write-up of
it on page 29 of the June 19th issue of EE Times. One fun quote left out,
though, was Alain Hanover (CEO of ViewLogic) on his rebellious Chronologic:
"Our founding forefathers guaranteed us the right to life, liberty, the
pursuit of happiness and the right to sue each other."
PANEL WITH THE MOST TECHNICAL PROBLEMS: The EE Times Forum. Although this
won best panel last year with its hand held electronic voter boxes that
engineers used to provide immediate feedback to the panelest's statements,
this year the voting boxes went haywire. The first indication was in the
supposed demographics of the audience. Polling indicated that they were
about 50% Synopsys, 50% Mentor, 50% Cadence, 50% Viewlogic and 58% Intergraph
users. (This is virtually impossible.) The second tip off was that no
matter what the panelists said they all got a 2.8 to 2.9 score. (Scoring
went from 1 for "lame" to 5 for "fantastic!".) "After seeing Penny Herscher
of Synopsys get a 2.9 for a great answer, I knew the voting boxes were
broken," said Cadence Marketing bigwig Tony Zingale, "I was tempted to
announce all Cadence software was now free." (I'm not sure whether Tony was
trying to get positive or negative responses from customers with this offer.)
Keeping in the spirit of technical difficulties on the EE Times DAC Forum,
attendees were given inadvertently defective pins that, when you pressed hard
while writing, the spring loaded guts would unexpectedly explode out the back
of the pin! (They make for great office joke pins!)
EDA SEGMENT WITH THE MOST SPYING: ESDA companies. My first impression of
Escalade was Michiel Ligthart whining: "Half of my demos today were given
to Synopsys employees." Yet, the very next day, I laughed finding Michiel
watching the demo of his competitor, Summit Design. (I'm sure he found out
that Summit was adding more pure Verilog features plus beefing up its test
tool.) I'm also sure that the Cadence and Synopsys employees watching the
i-Logix demo noted that i-Logix had added a Motiff style GUI, graphical
simulation that runs with vaguely defined descriptions, and how to generate
different styles of Verilog/VHDL/C code from one behavioral description
(useful for HW/SW codesign.) Runner up: the IC place and route companies.
MOST ENTERTAINING FLOOR SHOW: Compass Design hired a professional comedian
who told submicron jokes that were so corny they were good. Two were: "If a
clock tree falls alone in the woods, does it make a glitch?" and "When I was
young I got into some trouble. My father tied me to VSS. I was grounded
for life." Runner Up: Quickturn did a skit where an engineer was going
to leap off a building to his death because of design verification problems.
Even when the predictable Quickturn Man came to save the day, the customers
in the audience kept yelling: "Jump! Jump! Jump!"
MOST CONTENT-FREE FLOOR SHOW: Either Hewlett-Packard workstations or HP
Developers or HP EEsof (tells you how memorable the sales pitch was) managed
to continuously draw noticeably large crowds for their talks. Quietly asking
some of the crowd why this was such a draw, I got: "Shhh! We just want the
T-shirt!" (Later, I asked engineers what they remembered from the HP
presentation; no one could remember one quote or even what the talk was on!)
"WHERE'S THE BEEF?" AWARD: Cadence. They didn't have a customer party and
even though their exhibit booth was big, their demo suite was two cubicals in
size! Quite a few people were surprized how Cadence appeared to be backing
out of DAC, the various EDA committees like CFI, EDAC, VIUF, and OVI, and the
EDA industry in general. (I guess you don't need this presence to sell
design services instead of design products.)
MOST IMPROVED EDA COMPANY: Mentor Graphics. Watch out Cadence, Synopsys and
Viewlogic! Quite a few engineers noticed that Mentor Graphics now appeared
to be serious about mainstream EDA tools by offering a "real" VHDL simulator
plus adding full Verilog support for their simulation, synthesis and FPGA
synthesis offerings. Adding Verilog allows Mentor to sell to customers who
would have normally not given them the time of day. (Also, Mentor won the
Best Demo Suite Area award with their open tables, free food & soft drinks.)
MOST DISAPPOINTING DAC FREEBIE: ViewLogic's T-shirt. ViewLogic used to be so
hip and with the times with their DAC freebies. The year of the L.A. riots,
ViewLogic gave out baseball bats. The year that the U.S. sponsored the World
Cup in soccer, ViewLogic gave out soccer balls. This year, ViewLogic joined
the ranks of the mundane in giving out bland, white T-shirts. Blah.
BACK TO THE "REAL" WORLD: Checking my answering machine the morning after
DAC, I found out that my girlfriend had phoned the management of EE Times,
because she hadn't heard from me in a week and was worried. The front page
news in the San Francisco Chronicle that day was the mayor "blessing" the new
public toilets on Market street. In the weekend section, the "25th Annual
Lesbian, Gay, Bisexual and Transgender Pride" parade was scheduled on
Father's Day. I thought to myself: "Gosh, it's great to be back in the real
world!" and then happily daydreamed of what the freebies would be like at
next year's DAC in the notoriously decadent city of Las Vegas...
- John Cooley
part-time EDA industry gadfly
full-time contract ASIC/FPGA designer
P.S. If you thought this review was on-the-money or out-to-lunch, please tell
me. I love getting frank, honest feedback from fellow engineers.
P.P.S. In replying, *please* don't copy back this entire article; a 14,400
baud modem attached to a 386 on a sheep farm can handle only so much! :^)
===========================================================================
Trapped trying to figure out a Synopsys bug? Want to hear how 3567 other
users dealt with it ? Then join the E-Mail Synopsys Users Group (ESNUG)!
!!! "It's not a BUG, jcooley@world.std.com
/o o\ / it's a FEATURE!" (508) 429-4357
( > )
\ - / - John Cooley, EDA & ASIC Design Consultant in Synopsys,
_] [_ Verilog, VHDL and numerous Design Methodologies.
Holliston Poor Farm, P.O. Box 6222, Holliston, MA 01746-6222
Legal Disclaimer: "As always, anything said here is only opinion."
Article: 3445Hello, all! Some days ago we decided to use Xilinx FPGA in our PCMCIA design and found that our Cadence - Xilinx library is very old. Particularly we needs the latest files with packages description ($XACT/data/partlist.xct, $XACT/data/speeds.xct $XACT/data/*.pkg and may be some else). Who knows were I can get this information or send me this files through e-mail sol@elvis.msk.su? Help, please. Alex.Article: 3446
Yun Feng (yunfeng@cse.ucsc.edu) wrote: : I am trying to configure one FLEX81500 using PSS mode. Any one : knows what kind of configuration file should I generate from : MAXplus2? The "sequential .rbf" file or else? And what about the : file format? : Feng Yun There isn't a 'PSS' mode. You probably mean 'passive serial', 'PS'. (There is however a PPS mode, a parallel scheme). What file you need depends on whether you are using Bitblaster or a download cable from the PC Programmer. It's all in App Note 33. Try www.altera.com. -- Best Regards, Steve.Article: 3447
Hi, I'm a new Xilinx user. I work with Xact 6.0.0 and OrCAD 386+. Are there other Xilinx - OrCAD users? Thank you.Article: 3448
LAST MINUTE DAC NOTES:
- The Users Society for Electronic Design Automation (USE/DA) is
going to have its Birds of a Feather meeting on Wednesday,
June 5th, from 6:00 to 7:30 PM in the Hilton in Ballroom "D".
Come join us to install the new president, to swap industry dirt
and to set our agenda for next year. I hope to see ya'll there!
- Here's what we got for questions to put to the industry bigwigs
at this year's BIG DAC CEO panel on Tuesday. As the outgoing
president of USE/DA, I'll be moderating it. We'll have:
Mike Bosworth, CEO of OrCAD
Joe Costello, CEO of Cadence
Aart De Geus, CEO of Synopsys
Richard Goering, EE Times Technology Editor
Alain Hanover, CEO of ViewLogic
Wally Rhines, CEO of Mentor Graphics
Gary Smith, EDA Analyst from Dataquest
for 90 minutes of user-driven questioning! Feel free to slip
me any more last minute questions you may have by leaving them for
me at the Las Vegas Hilton front desk. See you at DAC!
- John Cooley
USE/DA President
--------------------------------------------------------------------------
To: All CEOs
I don't have a question, but a thank you note.
"By making your tools difficult to use, poorly integrated and full
of bugs, you have provide jobs for thousands of people like me to
support CAD tools within companies that buy them. Thank you very
much."
Ameesh Oza
Teradyne
To: Aart De Geus
Your in-Sync program has much higher entry requirements than Cadence
Connections, Mentor OpenDoor, or Viewlogic PowerPartner. Why is that?
Despite the positive image in the press, there still seems to be a
raging EDA Cold War. I've been trying to get into inSync for 12 months
and I just get stalled. (I been passed to three different people, they'd
lose the required customer references, claim the customers I reference
are unreachable yet when I pick up the phone the customer answers and/or
claimed to be on the road. They raised this stalling to an artform.)
Speed Electronic and Summit Design, my competitors, got into inSync
very quickly. Why can't Mentor?
- Daniel Payne
Mentor Graphics
To: Mike Bosworth
Was PC pricing a "cargo cult" belief for OrCad?; price it cheaply to sell
millions of copies in a market of only ~300,000 engineers?
- Sean Murphy
Leader-Murphy, Inc.
To: All
When will EDA providers finally realize PC platform support (Windows NT, in
particular) actually provides *more value* to users than UNIX support? The
typical shrink-wrapped PC software price structure need *not* apply. The
trick is how the EDA providers spin the value to customers in terms of
hardware price-performance, network support, integration with other office
tools, etc. etc. etc.
- Elliott Berger
Pixel Magic
To: All
I'm working on a mid-range sized design of around 200K gates, and my ASIC
vendor recommends 512MB of RAM; I also require several GB of disk for
storage. The cost of the underlying computer is not very significant at this
point. I don't think it will long before 200K will be considered a
relatively small design, so this isn't a problem likely to go away soon.
Windows is, to my mind, a plainly inferior development environment
when compared to the power and features of a Unix environment, so a really
strong incentive would be needed to get me to consider moving to a PC.
For the reason's given above I don't really see cost as being a good
reason, the Window's GUI has got to be the worst of the readily available
interfaces, and if anyone wants to they can run PC applications on
workstations via Wabi or emulators. Where is the driving force for the
change coming from ?
- Gavin Brebner
Tellabs
To: Joe Costello and Wally Rhines
In what design process areas do they see the on-site EDA consulting business
grow? In those areas where there are such high demand for EDA consulting,
is the on-site EDA consulting business induced by the complexity of the
EDA company's own tools?
Margaret Lee
Tandem Computers
To: Alain Hanover
The Viewlogic IC PowerTeam was formed to tightly integrate with back-end
IC tools from HLD Systems, Casacade, SVR, EPIC, and ISS/Avant! What
happened to the IC PowerTeam concept? I don't hear about it anymore.
- Daniel Payne
Mentor Graphics
To: Gary Smith
Firms like Dataquest, Collett International, and EDA Today all pretty much
make their money doing marketing research and selling specialized reports to
the commercial EDA vendors. As an EDA analyst often quoted in the industry
press how can you be objective about, say, Mentor Graphics, if Dataquest also
has a $200,000 market research contract with Mentor Graphics?
- John Cooley
Holliston Poor Farm
To: All
1. CAE CEOs talk about wanting to deliver value by helping customers
shorten design cycles. They also talk about guaranteeing results as
part of their consulting contracts. Yet customer design cycles are
lengthened when CAE companies slip software delivery schedules or ship
buggy code. (For example, I have not received Cadence's Q4 '95
maintenance upgrade as of 5/29/96.) Do the CEOs see this as a
problem? What are they doing to solve it? Are they willing to
guarantee delivery schedules in maintenance contracts?
2. Here's an audience question. Given a choice between buying either:
A. An integrated tool set from one vendor, or
B. High performance point tools with clean interfaces for user
integration from many vendors which would you choose?
3. When CAE companies merge, they often cite synergy as a motivation.
How often is synergy actually achieved? How often do mergers simply
create customer expectations for synergy and integration, which
are not technically feasible?
- Mike Murray
Acuson
To: Richard Goering
1.) How does the impact of a story effect whether or not it goes into
EE Times? That is, many times small start-ups have serious product or
staffing goofs that, if publically known, will kill the company. How
do you handle these situations?
2.) Have you ever known an advertiser in EE Times or other industry trade
publications try to use these ad dollars to influence what's reported
in that publication? How is this handled?
- John Cooley
Holliston Poor Farm
To: All
EDA Software patents. Most EDA software patents are held by IBM or by large
Japanese companies -- is this a potential problem for the industry? Is
patent protection a good idea for EDA software? If not, what's the
alternative?
Benchmarking. What do you think in general about independent benchmarks, and
why Viewlogic pulled out of the DA Solutions HDL simulation benchmark?
- Richard Goering
EE Times
To: All
I have been involved in the EDA industry for almost 17 years and somehow
we seem to keep solving the same problems. One of these problems is data
transfer between different EDA vendors. I believe the solution is for all
users of EDA/CAD/CAM products to demand one standard file format from
their vendors.
As a user since the most widely accepted standard is EDIF 2.0.0 and
EDIF 4.0.0 is coming out in July that is the format we need to rally
behind. The vendors I have talked to have agreed that they will supply
EDIF 4.0.0. interfaces it is just a matter of priorities as to when it
will be implemented. Is this the truth or so much hot air?
cathy_olsen@nt.com
To: All
Being from a PC company, I am extremely interested in EDA applications on
PC hardware. There have been several panels recently about "PC versus UNIX";
These panels tended to gravitate toward the cost issues related to the
software. What are the technical advantages/disadvantages of PC hardware
& OS versus traditional workstation hardware & OS you see as an EDA CEO??
Ben Buzonas
Compaq Computer Corporation
To: All
When will ALL the EDA tools talk to each other and work on standard file
formats? I see that some companies are trying to adapt to std
file formats but on the other hand, we spend many man years
solving those problems with TONs of inhouse scripts/wrappers/translators.
-Hiren Majmudar
Intel Corporation
To: Alain Hanover
Viewlogic - isn't a vital user group essential to developing a innovative
products?
- Sean Murphy
Leader-Murphy, Inc.
To: All
Q: How do the EDA vendors plan to resolve the business conflict of
supporting EDA standards needed to fuel the electronics and EDA industry
growth curve, while at the same time being concerned that offering their
technology for standardization may not give them the competitive
advantage?
Q: Given the results of the USE/DA Business Practices user survey, what
specific plans or commitments are the CEO's willing to make to the users
to address their users' concerns and needs?
- Steve Schulz
Texas Instruments
To: All
1. When I ask vendors what they are doing to ensure interoperability
between their tools and others' (sometimes even tools within the same
company), the most common reply I get is, "Our tools are really the most
interoperable. It is *their* tools that aren't". Can anyone care to
explain what that means?
2. The consulting pie seems to have given a significant boost to some
companies' revenues. What has it done to their long-term profitability?
Is "value-based" selling a myth or reality in the consulting world? Do
companies really expect to be profitable in consulting on "value based"
propositions during hard times? If so, don't the tool-less consulting
companies have an obvious edge over the conflict-of-interest'ing
companies? Or, are the vendors giving their tools away for *free*?
-Shankar Hemmady
Gurutech
To: All
One firm advertises a "make like" utility for managing design files. That
utility doesn't even monitor the date stamp of those files; the result is a
nightmare. Another case adds insult to injury when a tech support person
tells you that they will forward your "feature request" after you have just
phoned in a system crashing bug. After rushing a bug-filled product out to
market, exorbitant fees are charged for "maintenance".
Is predatory marketing practices, deceitful advertising, and poor product
quality going to be the EDA industry's continued future?
- Bill McGinley
Chisholm
To: Joe Costello
Last year Cadence had something like 7 to 9 major product announcements.
This year I can think of only one. Cadence has also pulled out of
EuroDAC this year. Is Cadence getting out of the EDA business?
- John Cooley
Holliston Poor Farm
To: Wally Rhines, Joe Costello, Aart De Geus
When are Mentor, Cadence and Synopsys going to deliver Windows products?
- Abbie Kendall
OrCAD
To: All
Q1: EDA companies are making it easier to create more and more complex
designs. How are your companies' products going to make it possible to
fully debug these complex designs before the heat death of the universe?
Q2: Datapath designs are really easy to design, yet control heavy designs
such as bus interfaces are notoriously difficult to design. Why are you
automating the easy Datapath designs, and not doing much to help those
of us with complex control heavy designs?
[ Anon @ Intel ]
To: All
I am evaluating whether use VHDL or Verilog HDL for high level design in a
situation where there is no prior baggage to carry. What are the
advantages/disadvantages comparing the two?
- Larry Sheu
AMD
To: All
In a developing countries like India, EDA vendors enjoy selling to and then
abandoning customers. With Cadence local support has been hopeless, since
we bought design tools in DEC 1994. Synopsys support in India is not that
bad and we are able to take out help from hotline. The main problem has been
their O/S compatibility and recent S/w releases. Viewlogic (thro' its local
representative ) always cribbs that PRO series of tools it sold to you thro'
some other vendor is a less powerful tool and you should use OFFICE version
of tools (obviously buy from us !). We do have Viewsynthesis on PC but
because of some technical problem it still is unoperational.
Why are developing countries EDA dumping grounds?
- TANAY KRISHNA
C-DOT, India
To: Aart De Geus
What's up with Synopsys and CCT and Synopsys and IBM and Synopsys and
Cadence? Aren't these eventually mutually exclusive P&R solutions?
Also, you've touted Behavioral Compiler for two years now, yet, from the
fact that I very rarely see anything about it from customers on the Internet
newsgroups tells me you just don't have many buyers. It behavioral
synthesis too early for its time, a flop, or what?
- John Cooley
Holliston Poor Farm
To: All
When, and how, will we have the interoperability issue solved. I.e. when
will be able to freely substitute one tool by the other, even from different
vendors without spending so much time on converting formats, libraries,
scripts, etc. As it seems today, it looks like some vendors prefer that to be
the old fashion way, so if you locked into their system, you will not be
able to try other systems.
Sometimes it is even worse. For Example, Cadence was pushing hard for Verilog
to be a standard, which finally came true, thru OVI. But Even Verilog
XL is "not" OVI compliant, i.e. it has additional features that are not
part of the OVI standard. So, even if we have a standard, it is not a real
one (Not talking about edif, ...)
- Erez Naory
IES Electronics Agencies Ltd.
To: Joe Costello
Will EDA Vendors (who are becoming merchants of on-site EDA consulting)
decide that their tools can give them a proprietary advantage over other
designers begin to keep their best tools in-house? (This naturally implies
that the tools they sell are out-house tools.)
-Martin Miller
Charles Stark Draper Laboratory
To: Richard Goering
Why are upgrades to EDA tools more a product of marketing departments, with
enhancements that reflect trendy GUIs and zippy ICONs? What kind of
statistics can a EDA manager take that give useful detailed information
about design times and might aid in comparing button pressing and Icon
grabbing versus quick key pressing?
The Design community is very diverse but selecting and upgrading EDA tools
is left more to touch and feel than to real measures for performance.
Hardware graphics vendors will quote screen redraw rates or zoom rates but
when have EDA vendors given us real numbers to compare? P.C. wholesalers
are frequently evaluated in magazines on how fast hot line calls are
answered and problems solved. Where are these numbers for the big
EDA companies?
- Marcus Larwill
larwill@fnal.gov
To: Gary Smith and All
Since commercial EDA tools are inadequate, large internal EDA groups exist
to meet corporate needs. As a result, commercial tools are of relatively
lower value to the dominant part of the semiconductor market. As examples,
DRC and schematic capture are essentially solved problems so they are viewed
as commodities. Do you see the semiconductor companies seeing their
specialized tool abilities as a key strategic advantage that they will not
give up?
- Doug Walker
Texas A&M University
To: All
1.) All EDA tools seem to be GUI-happy, with 413 levels of sub-menus,
organized in some seemingly arbitrary fashion, obviously driven by some
marketing guys that have never made a living at designing chips (i.e.
good demos, but poor productivity). What are you doing to measure
productivity of designers using your tools, and then increasing designer
productivity based on your research?
2.) We've all wasted a bunch of time with Verilog versus VHDL religious
wars - but really neither language is adequate and most designers don't
give a shit and understand that "the smaller the difference the larger
the war" (e.g. Pepsi vs. Coke) - otherwise it would be blatently obvious
which one is better. What are you doing to discourage the language
religion and to allow the desiger to concentrate on his design and
raising the likelyhood of success instead of letting the poor guy wallow
in the implementation and language details?
- Victor J. Duvanenko
Truevision
To: All
Migrating a toolset to a PC-based platform seems like it could be very
difficult if the target operating system is DOS/Windows. If the code
was originally written to work with Unix and X-Windows, it seems like
porting to DOS/Windows would require alot of work. Have you given
any thought to targetting low-cost PC-based Unix operating systems,
especially Linux? Linux is a solution that many people are using to
supplement Sun and HP workstations using lower cost PCs.
- Tom Mayo
General Electric
To: Wally Rhines and All
When are the EDA vending companies going to support PC's running
some kind of UNIX like Linux or SCO or something else?? That way
we could get the best of two worlds; cheap machines and a *real*
operating system. Linux is now so mature that you can get an officially
POSIX certified distribution (set of CD's). Digital is officially
backing Linux!
(When asked by Mentor what OS we'd like supported I answered Linux and
they just said 'What's that?' (what a nightmare!))
- Michael Dantzer-Sorensen
Nokia Mobile Phones
To: All
List the 3 things, in order, you have done that your customers feel
have improved your software quality the greatest. Given unlimited
resources, what one thing would you start doing NEW to improve software
quality even more?
I ask these questions because ECAD software is expensive, capabilities
are over-sold, and quality is lacking.
- John Swan
Motorola
To: All
1.) Could Car sales people do just as good a job at selling EDA tools as
the current staff? Will the EDA industry support a return policy like
CompUSA's or Software Etc?
2.) Why is Customer support so far down on the list of importance
within a company and yet they pay lip service to their importance?
(Internal negative attitudes to the ability of CAD/Customer Support
Engineers abounds.)
3.) Why does the EDA industry believe in infinite growth patterns and
infinite customer pockets?
- [ Anon @ an EDA vender ]
To: All
When will the quality of user documentation be improved? Almost all user
documents I have seen, and attempted to use, from the major EDA players are
basically reformatted reference documents. There are very few examples to
supplement syntax statements. The examples that exist frequently do not
match the shipped code. Common problems are not listed. Time spent
improving user documentation should not be considered time lost;
every constructive person-hour spent improving documentation will equal at
least that much time saved in hotline/AE hours.
- Erik Kusko
IBM
To: All
Why is it, that we could spend mega dollars for CAD-TOOLS, but we still have
to spend mega-labor on libraries?
Millions of Dollars of labor and Millions of hours of labor is wasted due a
not uniformly supported library.
- Robert Schultz
M/A-COM
To: Joe Costello
You claim your customers have over 10 million user written lines of
SKILL, yet TCL/TK seems to be a dominate command language and GUI builder
for both PC and UNIX environments. What's happening with your extension
language, SKILL? Is TCL/TK replacing it, or what?
- Daniel Payne
Mentor Graphics
To: All
While "deep-submicron" (0.35um) processing technology is available, tools
that enable designers to take advantage of the technology are, in my opinion,
not mature. (One indication of this is that the Cyrix's 6x86 implemented in
0.65um can still out-perform Intel's 0.35um-Pentium. Note: these are
full-custom designs, not even ASICs.) Concerning this Deep Submicron rush:
Do we need new tools & methodologies? If yes, what key characteristics do
they have? Have these approaches been tested?
What would be the indicator that tools/methodologies advocated by commercial
EDA vendors are mature enough for production use?
- Steven Leung
Tandem Computers
===========================================================================
Trapped trying to figure out a Synopsys bug? Want to hear how 4258 other
users dealt with it ? Then join the E-Mail Synopsys Users Group (ESNUG)!
!!! "It's not a BUG, jcooley@world.std.com
/o o\ / it's a FEATURE!" (508) 429-4357
( > )
\ - / - John Cooley, EDA & ASIC Design Consultant in Synopsys,
_] [_ Verilog, VHDL and numerous Design Methodologies.
Holliston Poor Farm, P.O. Box 6222, Holliston, MA 01746-6222
Legal Disclaimer: "As always, anything said here is only opinion."
Article: 3449husby@fnal.gov (Don Husby) wrote: > > david@fpga.demon.co.uk wrote: > > The "rough edges" referred to by recent reviewers here apply to any > > newly released product. > > I hope you're right. Although many of my complaints seem to be designed > in and, in fact, changes from the arguably better pro-series product. > > > I imagine that they looked at the first cut version (7.0) rather > > than later versions with the rough edges smoothed. The current > > release version of the Viewlogic product is, I believe, 7.11. > > I made my comments based on version 7.10. > Based on my experience with Viewlogic, I'd be willing to bet large > sums of money that no significant improvement will be made for at least > a year. > > The loss of the command line interface is a serious setback. I never realized how much I used it until I tried the new SW. I went back to my workview plus, partly because of shortcomings with 7.1 and partly because of win95 problems with some of my other tools. Hopefully some of this will be fixed by the time I am really ready to migrate to Win 95.
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