Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Threads Starting Apr 2000
21802: 00/04/01: J.R.: FPGA price vs Size
21805: 00/04/01: Peter Alfke: Re: FPGA price vs Size
22172: 00/04/28: Tim Forcer: Re: FPGA price vs Size
22213: 00/05/02: <kayrock@geocities.com>: Re: FPGA price vs Size
21814: 00/04/01: Gary Watson: Bitstream Format of Xilinx 4000 and Virtex Available for Download Here!
21823: 00/04/02: Eric GAUDET: Re: Bitstream Format of Xilinx 4000 and Virtex Available for Download
21815: 00/04/01: Greg Bezjak: Xilinx Foundation PAR hangs
22529: 00/05/10: Cory: Re: Xilinx Foundation PAR hangs
21817: 00/04/02: Steve Rencontre: Viewlogic ViewSim/Vwaves question
21820: 00/04/01: Anurag Tiwari: RISC/CISC Processor with Reconfigurable Logic
21824: 00/04/02: Jamil Khatib: Re: RISC/CISC Processor with Reconfigurable Logic
21825: 00/04/02: rk: Re: Shuttle Backup Computers and "Diverse Design" - Single Point Failures
21826: 00/04/02: rk: Re: Shuttle Backup Computers and "Diverse Design"
21828: 00/04/03: Tomasz Brychcy: Error during synthesis
21834: 00/04/03: Xanatos: Re: Error during synthesis
21830: 00/04/03: Virginia Horseman: HIPO - Hierarchy Input Process Output
21832: 00/04/03: Stuart J Adams: PCI test bench ??
21833: 00/04/03: Erik Lins: need FIFOs, urgent!
21836: 00/04/03: myself: Xilinx student edition, version 1.5
21837: 00/04/03: Luke Roth: Re: Xilinx student edition, version 1.5
21854: 00/04/04: myself: Re: Xilinx student edition, version 1.5
21838: 00/04/03: <elynum@my-deja.com>: Re: Xilinx student edition, version 1.5
21839: 00/04/03: Dave Vanden Bout: Re: Xilinx student edition, version 1.5
21847: 00/04/04: <elynum@my-deja.com>: Re: Xilinx student edition, version 1.5
21841: 00/04/03: Laurent Gauch: FPGA controlling S-7600A TCP/IP ...
21849: 00/04/04: Gary Watson: Re: FPGA controlling S-7600A TCP/IP ...
22042: 00/04/14: Steven K. Knapp: Re: FPGA controlling S-7600A TCP/IP ...
21846: 00/04/03: Liviu: Library of Parameterized Modules
21850: 00/04/04: Rickman: Re: Tired of paying your ISP?
21851: 00/04/04: Grzegorz: JTAG programming
21855: 00/04/04: Jean-Paul GOGLIO: Re: JTAG programming
21877: 00/04/05: Grzegorz: Re: JTAG programming
21880: 00/04/05: <rob_dickinson@my-deja.com>: Re: JTAG programming
21896: 00/04/06: Jean-Paul GOGLIO: Re: JTAG programming
21899: 00/04/06: <rob_dickinson@my-deja.com>: Re: JTAG programming
21903: 00/04/06: Jean-Paul GOGLIO: Re: JTAG programming
21904: 00/04/06: Grzegorz: Re: JTAG programming
21905: 00/04/06: Magnus Homann: Re: JTAG programming
21908: 00/04/06: Ray Andraka: Re: JTAG programming
21914: 00/04/06: Joel Kolstad: Re: JTAG programming
21915: 00/04/06: Etienne Racine: Re: JTAG programming
21906: 00/04/06: Etienne Racine: Re: JTAG programming
21970: 00/04/10: Alain Cloet: Re: JTAG programming
21853: 00/04/04: <e97bjli@thn.htu.se>: No net is connected....... ( xilinx)
21862: 00/04/04: Andy Peters: Re: No net is connected....... ( xilinx)
21857: 00/04/04: Vicente Marti: XCS05XL de Xilinx
21859: 00/04/04: Thomas Ekberg: Replication control in Xilinx P&R
21864: 00/04/04: Dan: Re: Replication control in Xilinx P&R
21874: 00/04/04: Bret Wade: Re: Replication control in Xilinx P&R
21861: 00/04/04: Michael García Lorenz: Curso gratuito de VHDL
21868: 00/04/04: Steve Casselman: Initialization of Ram in a marco
21889: 00/04/05: Steve Casselman: Re: Initialization of Ram in a marco
21871: 00/04/04: Chuck Carlson: Clocks and BUFGP
21872: 00/04/04: Andy Peters: Re: Clocks and BUFGP
21876: 00/04/05: Ray Andraka: Re: Clocks and BUFGP
21890: 00/04/05: Brian Philofsky: Re: Clocks and BUFGP
21891: 00/04/05: Brian Philofsky: Re: Clocks and BUFGP
21878: 00/04/05: Bingfeng Mei: Area ratio between routing resource and logic block
21882: 00/04/05: Utku Ozcan: PCI Bridge to Xilinx XCV*E
21894: 00/04/06: Keith R. Williams: Re: PCI Bridge to Xilinx XCV*E
21917: 00/04/06: John L. Smith: Re: PCI Bridge to Xilinx XCV*E
21921: 00/04/07: Keith R. Williams: Re: PCI Bridge to Xilinx XCV*E
21922: 00/04/07: Utku Ozcan: Re: PCI Bridge to Xilinx XCV*E
22115: 00/04/25: Rickman: Re: PCI Bridge to Xilinx XCV*E
21884: 00/04/05: Christof Paar: CHES 2000 deadline extended
21885: 00/04/05: Ron: Cheacksum implementation in VHDL
21887: 00/04/05: giuseppe giachella: ASIC synthesys using Leonardo Spectrum: any suggestion ?
21893: 00/04/06: Anshuman Sharma: JBits
21901: 00/04/06: Craig Slorach: Re: JBits
21897: 00/04/06: Joerg RiTTer: hwdebugr vs. jtag
21898: 00/04/06: <bjorn_lindegren@my-deja.com>: Spartan on chip oscillator
21909: 00/04/06: Ray Andraka: Re: Spartan on chip oscillator
21900: 00/04/06: Jamil Khatib: Power up set
21913: 00/04/06: Andy Peters: Re: Power up set
21924: 00/04/07: Klaus Falser: Re: Power up set
21902: 00/04/06: Tomasz Brychcy: Warnings during mapping
21910: 00/04/06: Ray Andraka: Re: Warnings during mapping
21912: 00/04/06: Graham Seaman: FPGA Openness/ Summary
21918: 00/04/06: Tom Burgess: Re: FPGA Openness/ Summary
21920: 00/04/07: Ray Andraka: Re: FPGA Openness/ Summary
21926: 00/04/07: Graham Seaman: Re: FPGA Openness/ Summary
21937: 00/04/07: Gary Watson: Re: FPGA Openness/ Summary
21916: 00/04/06: <grantb@ecn.ab.ca>: SpartanII BSDL file/JTAG Pgmr
21923: 00/04/07: Anshuman Sharma: EHW
21927: 00/04/07: Sigurd Urdahl: Re: EHW
21948: 00/04/08: Alex P.Martin: Re: EHW
21925: 00/04/07: Chih-Zong Lin: Any free design of 8051 in the net?
21929: 00/04/07: Mark A. Odell: Re: Any free design of 8051 in the net?
21931: 00/04/07: Edwin Naroska: Re: Any free design of 8051 in the net?
21934: 00/04/07: Dave Dunfield: Re: Any free design of 8051 in the net?
21938: 00/04/07: Cary Goltermann: Re: Any free design of 8051 in the net?
21941: 00/04/07: Lance Dannan Bresee: Re: Any free design of 8051 in the net?
21928: 00/04/07: Utku Ozcan: multiprocessor support of IC design tools
21930: 00/04/07: Jean-Paul GOGLIO: Re: multiprocessor support of IC design tools
21932: 00/04/07: Utku Ozcan: Re: multiprocessor support of IC design tools
21933: 00/04/07: Ray Andraka: Re: multiprocessor support of IC design tools
21936: 00/04/07: Jean-Paul GOGLIO: Re: multiprocessor support of IC design tools
21946: 00/04/07: Ray Andraka: Re: multiprocessor support of IC design tools
21959: 00/04/10: Jean-Paul GOGLIO: Re: multiprocessor support of IC design tools
21962: 00/04/10: Ray Andraka: Re: multiprocessor support of IC design tools
21939: 00/04/07: Jonas Rangell: Re: multiprocessor support of IC design tools
21944: 00/04/07: Brian Philofsky: Re: multiprocessor support of IC design tools
21947: 00/04/07: Bret Wade: Re: multiprocessor support of IC design tools
21954: 00/04/09: Utku Ozcan: Re: multiprocessor support of IC design tools
21955: 00/04/09: Ray Andraka: Re: multiprocessor support of IC design tools
21964: 00/04/10: Don Husby: Re: multiprocessor support of IC design tools
21960: 00/04/10: Jonas Rangell: Re: multiprocessor support of IC design tools
21935: 00/04/07: Steven Derrien: Retiming for Virtex FPGA with synopsys
21949: 00/04/08: Arrigo Benedetti: Re: Retiming for Virtex FPGA with synopsys
21940: 00/04/07: BJÖRN LINDEGREN: Port "IN2" has no net attached to it-on pad cells inserted at this port.
21942: 00/04/07: Brian Philofsky: Re: Port "IN2" has no net attached to it-on pad cells inserted at this
21945: 00/04/07: Brian Drummond: Re: Port "IN2" has no net attached to it-on pad cells inserted at this port.
21943: 00/04/07: <taetzsch@asic-alliance.com>: US - Engineering Opportunities in NH,MA,NJ,NY,CA
22030: 00/04/14: Reiner Hartenstein: Re: US - Engineering Opportunities in NH,MA,NJ,NY,CA
21950: 00/04/08: <karenwlead@my-deja.com>: CLKDLL stabilty state
22062: 00/04/17: Ed Mcgettigan: Re: CLKDLL stabilty state
21951: 00/04/08: Andreas Schmidt: Digital Design/Systems/CAD Engineer looking for position in California
21952: 00/04/08: The IRS: top50 keywords january - february - march...
21953: 00/04/09: adams: JTAG PROBLEM
21997: 00/04/11: Chris Dunlap: Re: JTAG PROBLEM
21956: 00/04/09: Greg Neff: Re: Shuttle Backup Computers and "Diverse Design"
21957: 00/04/10: Kevin T. Mortimer: Virtex Trivia
21965: 00/04/10: Peter Alfke: Re: Virtex Trivia
21967: 00/04/10: Peter Alfke: Re: Virtex Trivia
21958: 00/04/10: Reiner Hartenstein: FPL 2000 -- Call for Exhibitors
21961: 00/04/10: Ian Miller: Java to HDL compiler, Free Beta
22029: 00/04/14: Reiner Hartenstein: Re: Java to HDL compiler, Free Beta
22092: 00/04/20: glen herrmannsfeldt: Re: Java to HDL compiler, Free Beta
21963: 00/04/10: Jamil Khatib: Distributed Arithmetic
21966: 00/04/10: Peter Alfke: Re: Distributed Arithmetic
21971: 00/04/10: Thomas Loftus: Re: Distributed Arithmetic
21974: 00/04/10: Ray Andraka: Re: Distributed Arithmetic
21968: 00/04/10: <redbens@my-deja.com>: setup and hold time violation
21973: 00/04/10: Christian Mautner: Re: setup and hold time violation
21975: 00/04/10: Ray Andraka: Re: setup and hold time violation
21977: 00/04/10: Andy Peters: Re: setup and hold time violation
21981: 00/04/11: Klaus Falser: Re: setup and hold time violation
21969: 00/04/10: Steven Sanders: Xilinx Foundation 2.1 error
21972: 00/04/10: Christian Mautner: Re: Xilinx Foundation 2.1 error
21984: 00/04/11: Jon Harrison: Re: Xilinx Foundation 2.1 error
21982: 00/04/11: Klaus Falser: Re: Xilinx Foundation 2.1 error
23261: 00/06/19: Bryan Jones: Re: Xilinx Foundation 2.1 error
23309: 00/06/22: <bkk411@hotmail.com>: Re: Xilinx Foundation 2.1 error
23273: 00/06/20: Bryan Jones: Re: Xilinx Foundation 2.1 error
21976: 00/04/10: sriley: creating a bit stream
21978: 00/04/11: MK Yap: Re: Multiple Clock design, setup & hold time violation
21979: 00/04/11: Tomasz Brychcy: Programator for xilinx
21980: 00/04/11: Ray Andraka: Re: Programator for xilinx
22013: 00/04/12: Leon Heller: Re: Programator for xilinx
21983: 00/04/11: Tomasz Brychcy: Errors during synthesis
21996: 00/04/11: Chris Dunlap: Re: Errors during synthesis
21986: 00/04/11: Tomasz Brychcy: Errors during translation
21987: 00/04/11: Jean-Paul GOGLIO: Virtex E Pads Output Impedance
21992: 00/04/11: Peter Alfke: Re: Virtex E Pads Output Impedance
21995: 00/04/11: Bob Perlman: Re: Virtex E Pads Output Impedance
22006: 00/04/12: Bob Perlman: Re: Virtex E Pads Output Impedance
22078: 00/04/19: Austin Lesea: Re: Virtex E Pads Output Impedance
21988: 00/04/11: Jamil Khatib: LUT
21989: 00/04/11: Jamil Khatib: LUT
21990: 00/04/11: Jamil Khatib: LUT
21993: 00/04/11: Nicolas Matringe: Re: LUT
21991: 00/04/11: Jamil Khatib: LUT
21994: 00/04/11: Peter Alfke: Re: LUT
21998: 00/04/11: Tom McLaughlin: Specifying PCI buffer for Xilinx 4000XLA
22001: 00/04/11: Tom McLaughlin: Re: Specifying PCI buffer for Xilinx 4000XLA
22005: 00/04/11: Mike Peattie: Re: Specifying PCI buffer for Xilinx 4000XLA
22015: 00/04/12: Tom McLaughlin: Re: Specifying PCI buffer for Xilinx 4000XLA
21999: 00/04/11: Xanatos: Clock Dividers
22003: 00/04/11: Ray Andraka: Re: Clock Dividers
22007: 00/04/12: Allan Herriman: Re: Clock Dividers
22010: 00/04/12: Allan Herriman: Re: Clock Dividers
22000: 00/04/11: Jack D. Ma: Is there any DSP and FPGA based board suitable to motor drive control?
22002: 00/04/11: Ray Andraka: Re: Is there any DSP and FPGA based board suitable to motor drive
22004: 00/04/11: Ian Yellowley: Re: Is there any DSP and FPGA based board suitable to motor drive
22117: 00/04/25: Rickman: Re: Is there any DSP and FPGA based board suitable to motor drive
22130: 00/04/26: Komatose: Re: Is there any DSP and FPGA based board suitable to motor drive
22158: 00/04/27: Rickman: Re: Is there any DSP and FPGA based board suitable to motor
22008: 00/04/12: MK Yap: Re: Multiple Clock design, setup & hold time violation
22009: 00/04/12: Ray Andraka: Re: Multiple Clock design, setup & hold time violation
22018: 00/04/12: <iglasner@zumanetworks.com>: Re: Multiple Clock design, setup & hold time violation
22059: 00/04/17: MK Yap: Re: Multiple Clock design, setup & hold time violation
22019: 00/04/12: Christian Mautner: Re: Multiple Clock design, setup & hold time violation
22011: 00/04/12: Oliver Diessel: CFP: PART2000 - Seventh Australasian Parallel and Real-Time Systems
22012: 00/04/12: jok: pci bus, critical path
22014: 00/04/12: Thomas Zipper: parity - block ram
22016: 00/04/12: Thomas Rinder: Modeltech Error
22017: 00/04/12: Andy Peters: Re: Modeltech Error
22020: 00/04/12: deviant: Word up
22021: 00/04/13: Gerhard Griessnig: DSP - FPGA
22022: 00/04/13: Philipp: Demo - board
22036: 00/04/14: Markus Wannemacher: Re: Demo - board
22037: 00/04/14: Gary Watson: Re: Demo - board
22039: 00/04/14: Laurent Gauch: Re: Demo - board
22023: 00/04/13: Jamil Khatib: Parallel to serial
22025: 00/04/13: Allan Herriman: Re: Parallel to serial
22079: 00/04/19: stefaan: Re: Parallel to serial
22024: 00/04/13: <marko.udvanc@trilus-spe.si>: Re: jtag/jtagprog and fpga-demo-board
22027: 00/04/13: Robert Binkley: Re: jtag/jtagprog and fpga-demo-board
22026: 00/04/13: Ricardo Matias Moreno Moll: XCHECKER 3V adapter
22031: 00/04/14: Tom Burgess: Re: XCHECKER 3V adapter
22041: 00/04/14: Andy Peters: Re: XCHECKER 3V adapter
22045: 00/04/14: Tom Burgess: Re: XCHECKER 3V adapter
22038: 00/04/14: Ricardo Matias Moreno Moll: Re: XCHECKER 3V adapter
22028: 00/04/13: Gary Spivey: Re: A Question on Verilog
22032: 00/04/14: Rick Filipkiewicz: Virtex readback
22033: 00/04/14: Alex Flitwick: Re: Virtex readback
22034: 00/04/14: Alex Flitwick: PCMCIA Intellectual Property
22040: 00/04/14: Jan Gray: XSOC news: articles, Verilog, talk
22046: 00/04/15: Taras Zima: synchronous FIFO
22048: 00/04/15: Peter Alfke: Re: synchronous FIFO
22053: 00/04/16: Taras Zima: Re: synchronous FIFO
22070: 00/04/18: Jamil Khatib: Re: synchronous FIFO
22047: 00/04/15: Vasant Ram: FPGA/PLD design tools?
22049: 00/04/16: Ray Andraka: Re: FPGA/PLD design tools?
22050: 00/04/16: Eric GAUDET: Re: FPGA/PLD design tools?
22051: 00/04/15: Joel Kolstad: Re: FPGA/PLD design tools?
22054: 00/04/16: Laurent Gauch: Re: FPGA/PLD design tools?
22055: 00/04/17: Keith R. Williams: Re: FPGA/PLD design tools?
22065: 00/04/17: John Doe: Re: FPGA/PLD design tools?
22067: 00/04/17: <iglasner@my-deja.com>: Re: FPGA/PLD design tools?
22052: 00/04/16: rk: Announcement and Second CFP: 2000 MAPLD International Conference
22056: 00/04/17: Steve Daphne Martindell: Virtex-EM speed files
22057: 00/04/17: David A Hand: Handshaking in Xilinx Foundation Express ???
22058: 00/04/17: Joel Kolstad: Re: Handshaking in Xilinx Foundation Express ???
22068: 00/04/17: David A Hand: Re: Handshaking in Xilinx Foundation Express ???
22074: 00/04/18: Andy Peters: Re: Handshaking in Xilinx Foundation Express ???
22060: 00/04/17: Jens Hildebrandt: PULL-UPs on Xilinx-FPGA pads
22061: 00/04/17: Rémi SEGLIE: Re: PULL-UPs on Xilinx-FPGA pads
22072: 00/04/18: Jens Hildebrandt: Re: PULL-UPs on Xilinx-FPGA pads
22077: 00/04/19: Rémi SEGLIE: Re: PULL-UPs on Xilinx-FPGA pads
22083: 00/04/20: Jens Hildebrandt: Re: PULL-UPs on Xilinx-FPGA pads
22088: 00/04/20: Christian Mautner: Re: PULL-UPs on Xilinx-FPGA pads
22069: 00/04/18: Matt Billenstein: Re: PULL-UPs on Xilinx-FPGA pads
22063: 00/04/17: Robert Posey: Does anyone have a modern reference for the Failure Modes of FPGA's
22064: 00/04/17: Ed Mcgettigan: Re: OE in hierachial ABEL design
22066: 00/04/17: Nestor: Errors when synthesizing using generics but not during synthessi
22071: 00/04/18: Russell Brinkmann: Scripting Xilinx Foundation's hitop
22073: 00/04/18: Brian Philofsky: Re: Scripting Xilinx Foundation's hitop
22075: 00/04/18: ECruz68007: Modification on Pioneer DV-525 dvd player inquiery
22076: 00/04/18: Brian Kane: Boston SNUG 2000 -- Call For Papers
22080: 00/04/19: test: Test : Please ignore...
22081: 00/04/20: ¾ç¼¼¾ç: A New FPGA Board Capable of HW/SW Co-debugging
22082: 00/04/20: MK Yap: Interface with Altera's LPM_RAM_IO && Multiple cycle instruction with Synplify??
22099: 00/04/22: <rajkumar@gdatech.com>: Re: Interface with Altera's LPM_RAM_IO && Multiple cycle instruction with Synplify??
22145: 00/04/27: MK Yap: Re: Interface with Altera's LPM_RAM_IO && Multiple cycle instruction with Synplify??
22179: 00/04/28: David Bishop: Re: Interface with Altera's LPM_RAM_IO && Multiple cycle instruction
22084: 00/04/20: Pete Dudley: PLD Timing, Tco?
22085: 00/04/20: Xanatos: Re: PLD Timing, Tco?
22090: 00/04/20: Pete Dudley: Re: PLD Timing, Tco?
22091: 00/04/20: Pete Dudley: Answer Found, thank you.
22087: 00/04/20: Marc Battyani: Fast (> 100Mb) serial link to PC
22093: 00/04/21: Greg Neff: Re: Fast (> 100Mb) serial link to PC
22094: 00/04/21: Yacine EL KOLLI: Re: Fast (> 100Mb) serial link to PC
24443: 00/08/08: Fred SKalka: Re: Fast (> 100Mb) serial link to PC
24538: 00/08/12: Joel Kolstad: Re: Fast (> 100Mb) serial link to PC
22089: 00/04/20: Rathna Rao: jobs
22096: 00/04/21: <steve@sk-tech.com>: Virtex-E and LVDS
22100: 00/04/22: Greg Neff: Re: Virtex-E and LVDS
22105: 00/04/24: Gary Watson: Re: Virtex-E and LVDS
22106: 00/04/24: <steve@sk-tech.com>: Re: Virtex-E and LVDS
22107: 00/04/24: Greg Neff: Re: Virtex-E and LVDS
22097: 00/04/21: Frederic Magniette: which pci board?
22114: 00/04/25: Nikolay Rognlien: Re: which pci board?
23727: 00/07/06: John Newton: Re: which pci board?
22098: 00/04/21: Robert Posey: RAM BIST Tests In VHDL (esp March II)
22101: 00/04/22: louis-zhang: High Speed LVDS or HSTL
22102: 00/04/23: rudy munguia: Please Help with SBC's
22103: 00/04/23: Sreedhar Sampath: CLKDLL
22104: 00/04/24: JWKIM: Re: CLKDLL
22108: 00/04/24: Chris Plachta: Any good third-party place and route tools?
22127: 00/04/26: Jamil Khatib: Re: Any good third-party place and route tools?
22109: 00/04/24: Tobin Fricke: xilinx --> altera vhdl
22116: 00/04/25: <mench@mench.com>: Re: xilinx --> altera vhdl
22126: 00/04/26: Egbert Molenkamp: Re: xilinx --> altera vhdl
22110: 00/04/24: qaz: Quartus "clock skew excedes data delay" error
22181: 00/04/28: David Bishop: Re: Quartus "clock skew excedes data delay" error
22111: 00/04/25: #YEO WEE KWONG#: Segregation between synthesis code and simulation code
22118: 00/04/25: Brian Philofsky: Re: Segregation between synthesis code and simulation code
22119: 00/04/25: Don Husby: Re: Segregation between synthesis code and simulation code
22112: 00/04/25: Jeff Piper: ****Easy Money****
22113: 00/04/25: David: Any free design of 80C186 ??
22120: 00/04/26: Florindo Santoro: Buy FPGA
22148: 00/04/27: <rotemg@mysticom.com>: Re: Buy FPGA
22121: 00/04/25: Dan Kuechle: Xilinx Virtex problem (schematic)
22123: 00/04/25: Johnny: Re: Xilinx Virtex problem (schematic)
22134: 00/04/26: Philip Freidin: Re: Xilinx Virtex problem (schematic)
22137: 00/04/26: Greg Neff: Re: Xilinx Virtex problem (schematic)
22139: 00/04/26: Greg Neff: Re: Xilinx Virtex problem (schematic)
22133: 00/04/26: Philip Freidin: Re: Xilinx Virtex problem (schematic)
22136: 00/04/26: Bill Blyth: Re: Xilinx Virtex problem (schematic)
22122: 00/04/25: Paul S. Graham: Running the Xilinx Alliance Tools under Linux
22125: 00/04/26: Jamil Khatib: Foundation 2.1i
22128: 00/04/26: rja3: High Gate count?
22129: 00/04/26: John Ireland: Re: High Gate count?
22131: 00/04/26: Komatose: PID on FPGA
22138: 00/04/26: Andy Peters: Re: PID on FPGA
22147: 00/04/27: Komatose: Re: PID on FPGA
22132: 00/04/26: Dan: How to Prevent theft of FPGA design
22135: 00/04/26: Philip Freidin: Re: How to Prevent theft of FPGA design
22140: 00/04/26: bob elkind: Re: How to Prevent theft of FPGA design
22180: 00/04/28: David Bishop: Re: How to Prevent theft of FPGA design
22184: 00/04/30: Rickman: Re: How to Prevent theft of FPGA design
22187: 00/04/30: Joel Kolstad: Re: How to Prevent theft of FPGA design
22188: 00/04/30: Nicholas C. Weaver: Re: How to Prevent theft of FPGA design
22189: 00/04/30: Nicholas C. Weaver: Re: How to Prevent theft of FPGA design
22190: 00/04/30: Rickman: Re: How to Prevent theft of FPGA design
22194: 00/05/01: Jim Granville: Re: How to Prevent theft of FPGA design
22195: 00/04/30: Joel Kolstad: Re: How to Prevent theft of FPGA design
22217: 00/05/02: Andreas Doering: Re: How to Prevent theft of FPGA design
22230: 00/05/02: James Horn: Re: How to Prevent theft of FPGA design
22234: 00/05/02: Greg Neff: Re: How to Prevent theft of FPGA design
22243: 00/05/02: Robert Posey: Re: How to Prevent theft of FPGA design
22244: 00/05/02: Greg Neff: Re: How to Prevent theft of FPGA design
22257: 00/05/03: <csjacobs@my-deja.com>: Re: How to Prevent theft of FPGA design
22264: 00/05/03: Greg Neff: Re: How to Prevent theft of FPGA design
22273: 00/05/03: Jon Elson: Re: How to Prevent theft of FPGA design
22258: 00/05/03: <csjacobs@my-deja.com>: Re: How to Prevent theft of FPGA design
22260: 00/05/03: Robert Posey: Re: How to Prevent theft of FPGA design
22263: 00/05/03: Rickman: Re: How to Prevent theft of FPGA design
22267: 00/05/03: Rick Filipkiewicz: Re: How to Prevent theft of FPGA design
22277: 00/05/03: Rickman: Re: How to Prevent theft of FPGA design
22278: 00/05/04: Nicholas C. Weaver: Re: How to Prevent theft of FPGA design
22280: 00/05/04: Jim Granville: Re: How to Prevent theft of FPGA design
22292: 00/05/04: Rickman: Re: How to Prevent theft of FPGA design
22299: 00/05/04: Nicholas C. Weaver: Re: How to Prevent theft of FPGA design
22325: 00/05/05: David Bishop: Re: How to Prevent theft of FPGA design
22342: 00/05/05: Hal Murray: Re: How to Prevent theft of FPGA design
22383: 00/05/07: David Bishop: Re: How to Prevent theft of FPGA design
22279: 00/05/04: Ray Andraka: Re: How to Prevent theft of FPGA design
22282: 00/05/04: Hal Murray: Re: How to Prevent theft of FPGA design
22291: 00/05/04: Rickman: Re: How to Prevent theft of FPGA design
22275: 00/05/04: Ray Andraka: Re: How to Prevent theft of FPGA design
22298: 00/05/04: David Kessner: Re: How to Prevent theft of FPGA design
22301: 00/05/04: Nicholas C. Weaver: Re: How to Prevent theft of FPGA design
22303: 00/05/04: David Kessner: Re: How to Prevent theft of FPGA design
22327: 00/05/05: Ray Andraka: Re: How to Prevent theft of FPGA design
22333: 00/05/05: Nicholas C. Weaver: Re: How to Prevent theft of FPGA design
22353: 00/05/05: Ray Andraka: Re: How to Prevent theft of FPGA design
22355: 00/05/05: Nicholas C. Weaver: Re: How to Prevent theft of FPGA design
22338: 00/05/05: <david_kessner@my-deja.com>: Re: How to Prevent theft of FPGA design
22340: 00/05/05: Rickman: Re: How to Prevent theft of FPGA design
22348: 00/05/05: David Kessner: Re: How to Prevent theft of FPGA design
22379: 00/05/06: Rickman: Re: How to Prevent theft of FPGA design
22354: 00/05/05: Ray Andraka: Re: How to Prevent theft of FPGA design
22378: 00/05/06: Rickman: Re: How to Prevent theft of FPGA design
22382: 00/05/07: Ray Andraka: Re: How to Prevent theft of FPGA design
22385: 00/05/06: Rickman: Re: How to Prevent theft of FPGA design
22400: 00/05/08: David Kessner: Re: How to Prevent theft of FPGA design
22304: 00/05/04: Rickman: Re: How to Prevent theft of FPGA design
22306: 00/05/04: Nicholas C. Weaver: Re: How to Prevent theft of FPGA design
22321: 00/05/04: Robert Posey: Re: How to Prevent theft of FPGA design
22332: 00/05/05: Catalin Baetoniu: Re: How to Prevent theft of FPGA design
22334: 00/05/04: Rickman: Re: How to Prevent theft of FPGA design
22307: 00/05/04: David Kessner: Re: How to Prevent theft of FPGA design
22309: 00/05/04: Nicholas C. Weaver: Re: How to Prevent theft of FPGA design
22310: 00/05/04: David Kessner: Re: How to Prevent theft of FPGA design
22313: 00/05/04: Nicholas C. Weaver: Re: How to Prevent theft of FPGA design
22318: 00/05/04: Rickman: Re: How to Prevent theft of FPGA design
22320: 00/05/04: Nicholas C. Weaver: Re: How to Prevent theft of FPGA design
22322: 00/05/04: Rickman: Re: How to Prevent theft of FPGA design
22314: 00/05/04: <a@z.com>: Re: How to Prevent theft of FPGA design
22319: 00/05/04: Rickman: Re: How to Prevent theft of FPGA design
22329: 00/05/05: Catalin Baetoniu: Re: How to Prevent theft of FPGA design
22335: 00/05/05: Rickman: Re: How to Prevent theft of FPGA design
22324: 00/05/05: Jim Granville: Re: How to Prevent theft of FPGA design
22331: 00/05/05: Catalin Baetoniu: Re: How to Prevent theft of FPGA design
22336: 00/05/05: Rickman: Re: How to Prevent theft of FPGA design
22337: 00/05/05: Nicholas C. Weaver: Re: How to Prevent theft of FPGA design
22395: 00/05/08: Rick Filipkiewicz: Re: How to Prevent theft of FPGA design
22366: 00/05/06: Jim Granville: Re: How to Prevent theft of FPGA design
22368: 00/05/06: Catalin Baetoniu: Re: How to Prevent theft of FPGA design
22417: 00/05/09: Jim Granville: Re: How to Prevent theft of FPGA design
22431: 00/05/09: Rick Filipkiewicz: Re: How to Prevent theft of FPGA design
22246: 00/05/03: Zoltan Kocsi: Re: How to Prevent theft of FPGA design
22272: 00/05/03: Jon Elson: Re: How to Prevent theft of FPGA design
22316: 00/05/04: Steve Dewey: Re: How to Prevent theft of FPGA design
22141: 00/04/26: MikeJ: Help! going from ACTmap to Synplicity
22142: 00/04/26: $: Looking for contract/consulting help
22143: 00/04/27: Dan: ? economical SPROM programmer for Xilinx
22146: 00/04/27: <felix_bertram@my-deja.com>: Re: ? economical SPROM programmer for Xilinx
22149: 00/04/27: Mike H.: Re: ? economical SPROM programmer for Xilinx
22192: 00/05/01: Rick Filipkiewicz: Re: ? economical SPROM programmer for Xilinx
22497: 00/05/10: Emmanuel Lecomte: Re: ? economical SPROM programmer for Xilinx
22502: 00/05/10: Ray Andraka: Re: ? economical SPROM programmer for Xilinx
22638: 00/05/15: Marc K.: Re: ? economical SPROM programmer for Xilinx
22501: 00/05/10: Hernan Sanchez: Re: ? economical SPROM programmer for Xilinx
22144: 00/04/26: Richard B. Katz: Design Study
22150: 00/04/27: Kevin Klopfenstein: Xilinx "length count" question
22152: 00/04/27: Tom Fischaber: Re: Xilinx "length count" question
22157: 00/04/27: Peter Alfke: Re: Xilinx "length count" question
22159: 00/04/28: Rickman: Re: Xilinx "length count" question
22198: 00/05/01: Ed McCauley: Re: Xilinx "length count" question
22151: 00/04/27: Jerry English: AHDL to Verilog
22153: 00/04/27: Nestor: Instantiating and Compiling Altera LPM Macros with Synplify
22178: 00/04/28: David Bishop: Re: Instantiating and Compiling Altera LPM Macros with Synplify
22209: 00/05/01: Nestor: Re: Instantiating and Compiling Altera LPM Macros with Synplify
22211: 00/05/02: David Bishop: Re: Instantiating and Compiling Altera LPM Macros with Synplify
22154: 00/04/27: khoi ha: testing
22155: 00/04/27: Anton Erasmus: Verilog Compiler ?
22166: 00/04/28: JPC: Re: Verilog Compiler ?
22206: 00/05/01: Christian Mautner: Re: Verilog Compiler ?
22238: 00/05/02: Simon Greaves: VHDL / Verilog Consultant
22221: 00/05/02: Nikolay Rognlien: Re: Verilog Compiler ?
22156: 00/04/27: Rick Milado: FPGA + DSP24 = Super Performance DSP
22160: 00/04/28: sduduma: maxplus2 lpm in renoir
22219: 00/05/02: <antonin@my-deja.com>: Re: maxplus2 lpm in renoir
22161: 00/04/28: Ben: A Question on Virtex Configuration
22163: 00/04/28: Peter Schulz: Re: A Question on Virtex Configuration
22164: 00/04/28: Ben: Re: A Question on Virtex Configuration
22218: 00/05/02: Daryl Bradley: Re: A Question on Virtex Configuration
22237: 00/05/02: Rick Filipkiewicz: Re: A Question on Virtex Configuration
22169: 00/04/28: Tom Fischaber: Re: A Question on Virtex Configuration
22174: 00/04/28: Ben: Re: A Question on Virtex Configuration
22193: 00/05/01: Rick Filipkiewicz: Re: A Question on Virtex Configuration
25807: 00/09/21: Stephen Ingram: Re: A Question on Virtex Configuration
25808: 00/09/21: K. Orthner: Re: A Question on Virtex Configuration
25840: 00/09/22: Carl Rohrer: Re: A Question on Virtex Configuration
22162: 00/04/28: Nak: [HELP] - Express Mode for XC5000
22175: 00/04/28: Rickman: Re: [HELP] - Express Mode for XC5000
22183: 00/04/29: Nak: Re: [HELP] - Express Mode for XC5000
22165: 00/04/28: Márcio Longaray: DSP (FPGA) description
22168: 00/04/28: Craig Slorach: Re: DSP (FPGA) description
22167: 00/04/28: giuseppe: xilinx prom 2nd source.
22170: 00/04/28: <felix_bertram@my-deja.com>: Re: xilinx prom 2nd source.
22171: 00/04/28: Greg Neff: Re: xilinx prom 2nd source.
22173: 00/04/28: Theron Hicks: Re: xilinx prom 2nd source.
22176: 00/04/28: Reiner Hartenstein: which Conference Calendars on the web .... (FPL 2000)
22222: 00/05/02: Daniel Kroening: Re: which Conference Calendars on the web .... (FPL 2000)
22177: 00/04/28: Steven Derrien: Initial DFF value for Virtex in VHDL
22200: 00/05/01: Jamie Sanderson: Re: Initial DFF value for Virtex in VHDL
22182: 00/04/29: Peter: Why are there no "cheap" FPGAs?
22185: 00/04/30: Rickman: Re: Why are there no "cheap" FPGAs?
22197: 00/05/01: Theron Hicks: Re: Why are there no "cheap" FPGAs?
22207: 00/05/01: Ray Andraka: Re: Why are there no "cheap" FPGAs?
22223: 00/05/02: Theron Hicks: Re: Why are there no "cheap" FPGAs?
22226: 00/05/02: Uwe Bonnes: Re: Why are there no "cheap" FPGAs?
22233: 00/05/02: Ray Andraka: Re: Why are there no "cheap" FPGAs?
22259: 00/05/03: Nicholas C. Weaver: Re: Why are there no "cheap" FPGAs?
22204: 00/05/01: Peter Alfke: Re: Why are there no "cheap" FPGAs?
22261: 00/05/03: Rickman: Re: Why are there no "cheap" FPGAs?
22281: 00/05/04: Jim Granville: Re: Why are there no "cheap" FPGAs?
22375: 00/05/06: Peter: Re: Why are there no "cheap" FPGAs?
22236: 00/05/02: Paul Walker: Re: Why are there no "cheap" FPGAs?
22249: 00/05/03: Rickman: Re: Why are there no "cheap" FPGAs?
22274: 00/05/04: Ray Andraka: Re: Why are there no "cheap" FPGAs?
22733: 00/05/21: Richard Erlacher: Re: Why are there no "cheap" FPGAs?
22734: 00/05/21: Ray Andraka: Re: Why are there no "cheap" FPGAs?
22186: 00/04/30: George: Help!
22241: 00/05/02: Dan: DCT vs. FFT Are these ideas correct ?
22191: 00/04/30: Russ Magee: Bi-dir pass-thru w/switch in MAX+Plus II?
22269: 00/05/03: Steve Dewey: Re: Bi-dir pass-thru w/switch in MAX+Plus II?
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
