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Is there any free 8051 design ? MillerArticle: 21926
Ray Andraka (randraka@ids.net) wrote: : Nice summary. : : One nit on your conclusion though, You mention that several tools generate : the XNF format, which is true enough. What is implied though is that that : gets you closer to the bitstream. XNF is the netlist that goes into the : front end of the tool- it is basically a textual netlist of your schematic : or HDL design. In the M1 and M2 tools, EDIF format is preferred by xilinx, : and they've made noises about getting rid of XNF altogether (which us users : have asked them not to do). As I mentioned fairly early in the thread, you : can get pretty detailed in your description of the design at the XNF level : in that you can direct placement as well as lock the pins on the CLBs to : force a particular routing. The fact is though, that XNF is the file : format to get into the front end of the tools, not a shortcut to the : backend. : Of course. If that's the way it came over, I'll change the wording. All I meant was that open-source EDA tools have currently progressed to the stage where they can output XNF (EDIF might be better, but there are problems with the price of the specs for people writing free software!) The next stage is presumably working on place and route; the group in the University of Toronto who produced vpr (now part of MaxPlus) have shown that this is something that can be done without necessarily being the size of Xilinx.. After that, the bitstream problem will become more urgent for open-source developers. But all this is at a bit of a tangent to Greg Alexander's original thread - he had a particular task in mind, and was not (IMO) intending to replace the whole Xilinx toolset with homebrewed one-man developed software, as some people seemed to assume... GrahamArticle: 21927
Anshuman Sharma <gte600f@prism.gatech.edu> writes: > > > can anyone guide me to the EHW conference website? Which of them? There's one in Edinburgh this spring (ICES2000), but I believe there is one scheduled for this summer in Las Vegas (or something) too. <url:http://www.dcs.napier.ac.uk/evol/ices2000.htm> -sig -- sigurd urdahlArticle: 21928
In a past thread, "SpartanXL route and place", I had sent a posting in which I stated that it is impossible to speed up Xilinx tools by using more than one processor on the same UNIX workstation. After a quick search, I have learned, that there is no IC design tool in the world today that supports more than one processor on both the PC and UNIX platform. This result covers everything (simulator, synthesizer, router software, ASIC and FPGA). Utku -- I feel better than James Brown.Article: 21929
It's so easy, I would suspect so. What do you want to attach to the 8051? On 7 Apr 2000 07:23:24 GMT, dcp79807@pdp.csie.nctu.edu.tw (Chih-Zong Lin) wrote: >Is there any free 8051 design ? >Miller - Mark A. Odell (remove thisisnotvalid. to reply via email)Article: 21930
Utku Ozcan wrote in <38EDC317.21528CD0@netas.com.tr>... >In a past thread, "SpartanXL route and place", I had sent a >posting in which I stated that it is impossible to speed up >Xilinx tools by using more than one processor on the same >UNIX workstation. > >After a quick search, I have learned, that there is no >IC design tool in the world today that supports more than one >processor on both the PC and UNIX platform. This result covers >everything (simulator, synthesizer, router software, ASIC >and FPGA). > >Utku > >-- >I feel better than James Brown. I use FPGA Express (synopsys) on a Bi Pentium III Win NT PC and during synthesis, the 2 processors work. A few months a go, i have tested the FPGA Booster option of Aldec Active HDL 3.6 and if i remember well, the 2 processors worked together when simulating a multi-FPGA post-implemented design (as i couldn't buy this option, i'm still not sure of that, if someone could confirm ). All my other tools (Xilinx Implementation tools or Active HDL 3.6 without booster) use only a single processor. -- J-P GOGLIO GETRIS S.A. 13 Chemin des Prés 38240 Meylan Tel : (+33) 4 76 18 52 10 E-mail : goglio@getris.com Fax : (+33) 4 76 18 52 01Article: 21931
Hi, Chih-Zong Lin wrote: > Is there any free 8051 design ? > Miller You may take a look at section 4.9 (part 1) of the FAQ (http://www.vhdl.org/comp.lang.vhdl/). -- EdwinArticle: 21932
> [snip] > > I use FPGA Express (synopsys) on a Bi Pentium III Win NT PC and during > synthesis, the 2 processors work. > > [snip] then ok, so it means they support two processors. Surprising... Have you set up anything specific for FPGA Express, in both the tool options and operating system? Utku -- I feel better than James Brown.Article: 21933
True, the xilinx tools don't use two processors, but I do use a 2 processor machine so that I can stay productive when a place and route is in progress. I haven't seen any single application yet that truely uses both processors at once. It can appear that both processors are being used, as each thread gets assigned to the most available processor when it comes up. Utku Ozcan wrote: > > [snip] > > > > I use FPGA Express (synopsys) on a Bi Pentium III Win NT PC and during > > synthesis, the 2 processors work. > > > > [snip] > > then ok, so it means they support two processors. Surprising... > Have you set up anything specific for FPGA Express, in both > the tool options and operating system? > > Utku > > -- > I feel better than James Brown. -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 21934
>Is there any free 8051 design ? >Miller There are a few available in the download area of my web page: http://www.dunfield.com 8031DESI.ZIP Several 8031 designs showing different menory schemes 8051ICE.ZIP LOW COST In-Circuit Emulator for 8051 DBOXKIT.ZIP Control VCR with CTRL-L (LANC) port via RS-232 IR232KIT.ZIP Serial Infared Controller (RS-232 learning remote) RINGSWKT.ZIP Telephone "distinctive ring" switcher. DARC.ZIP Amateur Radio/Repeater Controller HTX242.ZIP Computer control HTX242 ham radio via mike jack All of these use an 8051/8031, and include schematic drawings. You should also take EMBEDRAW.ZIP, which has the drawing editor you will need to see the schematics. Regards, ----------------------------------------------------------------------- dave@ Dave Dunfield - Dunfield Development Systems dunfield Box 31044 Nepean Ontario Canada K2B 8S8 FAX:613-256-5821 .com Low $ embedded SW development tools http://www.dunfield.com -----------------------------------------------------------------------Article: 21935
Hello, I'm trying to implement a heavily pipelined SP floating point adder with sysnopsys. To do so, i've trying to take advantadge of the "retiming" feature provided by the FC2 compiler. My vhdl design had 7 registers at each input port (65 input) and one register at each output port (32 output), and the floating point addition is performed in a pure combinatorial fashion. With all this register available I expect FC2 to be able to dramatically reduce the critical path by moving the registers with retiming. However, whenever I try to retime this circuit, my FC2 sessions crashes, and I get the following error message : Abort at 401 Fatal: Internal system error, cannot recover. Anyone knows about this ? I was thinking it might be because Fc2 infers some SRL16 primitive (LUT configured as shift register) for all my input registers and then gets lost in the retiming step ? StevenArticle: 21936
Utku Ozcan wrote in message <38EDDEEE.9D4C4C5E@netas.com.tr>... > then ok, so it means they support two processors. Surprising... > Have you set up anything specific for FPGA Express, in both > the tool options and operating system? > Absolutely nothing for the synthesizer, i have just run the Foundation installation CD. For Win NT, you just have to check if the multiprocessing is enabled (when booting), if not i don't know how to enable it, but i suppose that this info is easy to find. -- J-P GOGLIO GETRIS S.A. 13 Chemin des Prés 38240 Meylan Tel : (+33) 4 76 18 52 10 E-mail : goglio@getris.com Fax : (+33) 4 76 18 52 01Article: 21937
Graham Seaman <seamang@westminster.ac.uk> wrote in message news:38ec9144@ant.wmin.ac.uk... > After the recent thread on FPGA openness (ie. the bitstream formats) > I decided to put together a more permanent summary before the > thread vanished from newservers. > You can see it at: http://collector.hscs.wmin.ac.uk/news/ > It's a biased summary, in the sense that I agree with the > 'bitstream should be open' side of the argument. But I've > tried to be careful not to quote the people on the other side > of the argument out of context. If anyone does feel I've misrepresented > them by taking statements out of context, let me know. Excellent summary, particularly as it makes my postings seem more well-reasoned than they actually were! -- Gary Watson gary@nexsan.sex (Change dot sex to dot com to reply!!!) Nexsan Technologies Ltd. Derby DE21 7BF ENGLAND http://www.nexsan.comArticle: 21938
Chih-Zong Lin wrote: > Is there any free 8051 design ? > Miller Look at http://tech-www.informatik.uni-hamburg.de/vhdl/vhdl.html There are links to two 8051 designs in vhdlArticle: 21939
Utku Ozcan wrote: > > In a past thread, "SpartanXL route and place", I had sent a > posting in which I stated that it is impossible to speed up > Xilinx tools by using more than one processor on the same > UNIX workstation. I just tried to use the multi-CPU feature on Xilinx P&R and got this message.... WARNING:baspw:122 - Multi-task PAR is not needed for this job. The -m (Multi-Tasking) switch will not be used. Apparently the software and I disagree about what is needed and not :-( (Using M1.5i, PAR: Xilinx Place And Route M1.5.25.) As long as one can't pursuade the software it is impossible to use multi CPU support. /JonasArticle: 21940
Hi
Im a newbie in FPGA design, and I have problem whith my inport in the
entity.
When I synthesis my code I recive an error message:
Port "IN2" has no net attached to it-on pad cells inserted at this port
(FPGA -padmap-2).
I tried an exemle from Xilinx home page, It works good, but when i trie to
add my own IN port 'IN2', the error occure.
If I compare IN1 and IN2 in my code, I can't see the difference between
them.
My code at the bottom:
Thankful for help:
Björn
library IEEE;
use IEEE.std_logic_1164.all;
entity USE_GSR is
port (RESET, IN1,IN2, CLK: in std_logic;
--IN2: in std_logic; --_vector(7 downto 0);
OUT1: out std_logic);
end USE_GSR;
architecture TEST of USE_GSR is
signal sampel1: std_logic; --_vector(7 downto 0);
component STARTUP
port (GSR: in std_logic);
end component;
begin
--Instantiate STARTUP, and map RESET to the Global Reset net
U1: STARTUP port map (GSR => RESET);
process (CLK, RESET)
begin
if RESET='1' then
OUT1 <= '0';
elsif rising_edge (CLK) then
OUT1 <= IN1;
sampel1<=IN2;
end if;
end process;
end TEST;
Article: 21941dcp79807@pdp.csie.nctu.edu.tw (Chih-Zong Lin) wrote: > Is there any free 8051 design ? > Miller > http://www.ucolick.org/~lance/home.html has a link to some 8051 schematics in acrobat format. Sent via Deja.com http://www.deja.com/ Before you buy.Article: 21942
This is a multi-part message in MIME format. --------------1D06B27C18B870C0CDF7B218 Content-Type: text/plain; charset=iso-8859-1 Content-Transfer-Encoding: 8bit It doesn't look like the signal sampel1 is connected to anything. Floating signals get optimized out and therefore IN2 will not be connected to anything. try completeing this connection and I'll bet that message will go away. -- Brian "BJÖRN LINDEGREN" wrote: > Hi > > Im a newbie in FPGA design, and I have problem whith my inport in the > entity. > > When I synthesis my code I recive an error message: > Port "IN2" has no net attached to it-on pad cells inserted at this port > (FPGA -padmap-2). > > I tried an exemle from Xilinx home page, It works good, but when i trie to > add my own IN port 'IN2', the error occure. > If I compare IN1 and IN2 in my code, I can't see the difference between > them. > > My code at the bottom: > > Thankful for help: > > Björn > > library IEEE; > use IEEE.std_logic_1164.all; > > entity USE_GSR is > port (RESET, IN1,IN2, CLK: in std_logic; > --IN2: in std_logic; --_vector(7 downto 0); > OUT1: out std_logic); > > end USE_GSR; > > architecture TEST of USE_GSR is > > signal sampel1: std_logic; --_vector(7 downto 0); > > component STARTUP > port (GSR: in std_logic); > end component; > > begin > > --Instantiate STARTUP, and map RESET to the Global Reset net > U1: STARTUP port map (GSR => RESET); > > process (CLK, RESET) > begin > if RESET='1' then > OUT1 <= '0'; > elsif rising_edge (CLK) then > OUT1 <= IN1; > sampel1<=IN2; > end if; > end process; > > end TEST; --------------1D06B27C18B870C0CDF7B218 Content-Type: text/x-vcard; charset=us-ascii; name="brianp.vcf" Content-Transfer-Encoding: 7bit Content-Description: Card for Brian Philofsky Content-Disposition: attachment; filename="brianp.vcf" begin:vcard n:Philofsky;Brian tel;work:1-800-255-7778 x-mozilla-html:TRUE url:http://www.xilinx.com org:Xilinx, Inc.;Software Marketing adr:;;2100 Logic Dr.;San Jose;CA;95124;USA version:2.1 email;internet:brianp@xilinx.com title:Technical Marketing Engineer fn:Brian Philofsky end:vcard --------------1D06B27C18B870C0CDF7B218--Article: 21943
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This is a multi-part message in MIME format. --------------E7FB1520A2D00B8E708AC0BA Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit The -m switch is not supported for Windows PCs. Are you executing this on a PC or UNIX (Solaris or HP-UX) workstation? -- Brian Jonas Rangell wrote: > Utku Ozcan wrote: > > > > In a past thread, "SpartanXL route and place", I had sent a > > posting in which I stated that it is impossible to speed up > > Xilinx tools by using more than one processor on the same > > UNIX workstation. > > I just tried to use the multi-CPU feature on Xilinx P&R > and got this message.... > > > WARNING:baspw:122 - Multi-task PAR is not needed for this job. The -m > (Multi-Tasking) switch will not be used. > > > > Apparently the software and I disagree about what is needed and not :-( > (Using M1.5i, PAR: Xilinx Place And Route M1.5.25.) > > As long as one can't pursuade the software it is impossible > to use multi CPU support. > > > > /Jonas --------------E7FB1520A2D00B8E708AC0BA Content-Type: text/x-vcard; charset=us-ascii; name="brianp.vcf" Content-Transfer-Encoding: 7bit Content-Description: Card for Brian Philofsky Content-Disposition: attachment; filename="brianp.vcf" begin:vcard n:Philofsky;Brian tel;work:1-800-255-7778 x-mozilla-html:TRUE url:http://www.xilinx.com org:Xilinx, Inc.;Software Marketing adr:;;2100 Logic Dr.;San Jose;CA;95124;USA version:2.1 email;internet:brianp@xilinx.com title:Technical Marketing Engineer fn:Brian Philofsky end:vcard --------------E7FB1520A2D00B8E708AC0BA--Article: 21945
On Fri, 7 Apr 2000 17:55:54 +0200, "BJÖRN LINDEGREN" <b.j.l@swipnet.se> wrote: >Hi > >Im a newbie in FPGA design, and I have problem whith my inport in the >entity. > >When I synthesis my code I recive an error message: >Port "IN2" has no net attached to it-on pad cells inserted at this port >(FPGA -padmap-2). You connect IN2 to a signal, but that signal goes nowhere and does nothing ... therefore it's a target for optimisation. If you connected it to a second OUT port or used it for something constructive then the "problem" would go away. - BrianArticle: 21946
If you go to a dos pox and run par without arguments you get the help screen.
From there I quote:
"-m = Multi task par run. File <node list file> ",
contains a list of node names on which to run the jobs.
(This option is not currently supported on WIN NT/WIN 95
systems)."
Also, I have not seen any evidence that Aldec 3.6c supports multiple processors
either (if you know different, then please educate me on how to set it up to do
so). I know that synplicity and modelsim also run just one processor. Note: If
you have a two processor system, the tasks will be spread out to the two
processors, but the combined processor load while running just synplicity or
xilinx (or substitute other EDA package) under NT only totals 50%, indicating
that teh programs are single threaded. The advantage two processors gets you is
that you can run two things at once even if they are both processor intensive
(where it slows down is on disk access).
Jean-Paul GOGLIO wrote:
> Utku Ozcan wrote in message <38EDDEEE.9D4C4C5E@netas.com.tr>...
> > then ok, so it means they support two processors. Surprising...
> > Have you set up anything specific for FPGA Express, in both
> > the tool options and operating system?
> >
>
> Absolutely nothing for the synthesizer, i have just run the Foundation
> installation CD.
> For Win NT, you just have to check if the multiprocessing is enabled (when
> booting), if not i don't know how to enable it, but i suppose that this info
> is easy to find.
>
> --
> J-P GOGLIO
> GETRIS S.A.
> 13 Chemin des Prés
> 38240 Meylan
> Tel : (+33) 4 76 18 52 10
> E-mail : goglio@getris.com
> Fax : (+33) 4 76 18 52 01
--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email randraka@ids.net
http://users.ids.net/~randraka
Article: 21947Hello Jonus, The "-m node_list" option of PAR is related to the Multi-Pass Place & Route feature which farms out multiple PAR runs to the various machines in your node list file, to be run concurrently. Each pass gets a different placement seed. If your PAR command uses the -m switch but does not specify multiple passes using the "-n #" switch, then you will see the message "Multi-task PAR is not needed for this job", because you have only specified a single pass. This has nothing to do with using multiple processors on a single machine, and as others have said, it's only supported on Solaris and HP-UX machines. Regards, Bret Wade Xilinx Product Applications Jonas Rangell wrote: > Utku Ozcan wrote: > > > > In a past thread, "SpartanXL route and place", I had sent a > > posting in which I stated that it is impossible to speed up > > Xilinx tools by using more than one processor on the same > > UNIX workstation. > > I just tried to use the multi-CPU feature on Xilinx P&R > and got this message.... > > > WARNING:baspw:122 - Multi-task PAR is not needed for this job. The -m > (Multi-Tasking) switch will not be used. > > > > Apparently the software and I disagree about what is needed and not :-( > (Using M1.5i, PAR: Xilinx Place And Route M1.5.25.) > > As long as one can't pursuade the software it is impossible > to use multi CPU support. > > > > /JonasArticle: 21948
http://ic.arc.nasa.gov/ic/eh2000Article: 21949
Steven Derrien <sderrien@irisa.fr> writes: > Hello, > > I'm trying to implement a heavily pipelined SP floating point adder with > sysnopsys. To do so, i've trying to take advantadge of the "retiming" > feature provided by the FC2 compiler. My vhdl design had 7 registers at > each input port (65 input) and one register at each output port (32 > output), and the floating point addition is performed in a pure > combinatorial fashion. > With all this register available I expect FC2 to be able to dramatically > reduce the critical path by moving the registers with retiming. > > However, whenever I try to retime this circuit, my FC2 sessions crashes, > and I get the following error message : > > Abort at 401 > Fatal: Internal system error, cannot recover. > > Anyone knows about this ? > > I was thinking it might be because Fc2 infers some SRL16 primitive (LUT > configured as shift register) for all my input registers and then gets > lost in the retiming step ? > > Steven I had the very same problem with a design here. I contacted Synopsys tech support, and they filed a STAR (Synopsys Technical Action Request). STAR number is 99705. I have not checked if FC2 v. 3.4.0, that was released a few days ago, still has this problem. -Arrigo -- Dr. Arrigo Benedetti e-mail: arrigo@vision.caltech.edu Caltech, MS 136-93 phone: (626) 395-3695 Pasadena, CA 91125 fax: (626) 795-8649
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