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a@z.com wrote: > Hi, > > You may want to take a look at the Parallel III cable - same > functionality but contains just some buffers. It can also double as a > JTAG download cable too. > well, not exactly. Same purpose, but not as much functionality. You can't do readback with a parallel III for example. > > Regards, > Catalin > > Ray Andraka wrote: > > > It's not a trivial design. It's got an XC3042 FPGA in it among other > > things. > > > > Fuzesi Arnold wrote: > > > > > Hi All! > > > > > > I want to make my own xchecker cable. > > > > > > Is it possible ? > > > > > > Can I copy an original cable? > > > > > > Thanks, > > > Arnold > > > /Electrical Engineer Student/ > > > > -- > > -Ray Andraka, P.E. > > President, the Andraka Consulting Group, Inc. > > 401/884-7930 Fax 401/884-7950 > > email randraka@ids.net > > http://users.ids.net/~randraka -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 20851
Fred Marshall wrote: > > Rickman, > > Saying QuickBooks (which is what I use) and MRP / integrated capabilities > seems quite a stretch when you consider the price of the packages. If > you're just starting out, what's really wrong with simply buying in two > categories: > 1) reeled parts that come in relatively large quantities but aren't cost > drivers. > 2) all the others that you'll probably buy for each production lot. > > Just buy them off the BOM. It's not that big a deal. > > If you really want to be prepared to be a much bigger company then you'll > probably be investing in all sorts of infrastructure around the MRP system. > > It all revolves around how much you're willing to invest in software and > infrastructure. I'll be interested to see if someone recommends an > inexpensive MRP package here as well. > > I had a survey article that I may be able to retrieve. email me if you're > interested. > > Regards, You make it sound so simple. I have found that the parts procurement process is the single most difficult part of running a company. I am planning on bringing an assitant on board to perform the office duties and will train for procurement. But this is not an easy process. The big problem has to do with the multiple part numbers and suppliers for each line item we need. Then all of the orders have to be tracked and with lead times of up to 12 weeks for some parts, it becomes a lot of work to make sure that all the parts will be in by the scheduled manufacturing start date. For just three small boards, I have 100 different passive components and 50 active ones. This also includes mechanical components and the PCBs. I am not trying to be rude, but if you don't see the difficulty of procurement, it is likely that you are not doing it. Or maybe I am just not doing it right... I know that I have a new found respect for buyers! If you have some info on this process, I would love to read it. Let me know! -- Rick Collins rick.collins@XYarius.com remove the XY to email me. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design Arius 4 King Ave Frederick, MD 21701-3110 301-682-7772 Voice 301-682-7666 FAX Internet URL http://www.arius.comArticle: 20852
Maybe you should consider finding a turnkey manufacturer. Rickman wrote: > > Fred Marshall wrote: > > > > Rickman, > > > > Saying QuickBooks (which is what I use) and MRP / integrated capabilities > > seems quite a stretch when you consider the price of the packages. If > > you're just starting out, what's really wrong with simply buying in two > > categories: > > 1) reeled parts that come in relatively large quantities but aren't cost > > drivers. > > 2) all the others that you'll probably buy for each production lot. > > > > Just buy them off the BOM. It's not that big a deal. > > > > If you really want to be prepared to be a much bigger company then you'll > > probably be investing in all sorts of infrastructure around the MRP system. > > > > It all revolves around how much you're willing to invest in software and > > infrastructure. I'll be interested to see if someone recommends an > > inexpensive MRP package here as well. > > > > I had a survey article that I may be able to retrieve. email me if you're > > interested. > > > > Regards, > > You make it sound so simple. I have found that the parts procurement > process is the single most difficult part of running a company. I am > planning on bringing an assitant on board to perform the office duties > and will train for procurement. But this is not an easy process. The big > problem has to do with the multiple part numbers and suppliers for each > line item we need. Then all of the orders have to be tracked and with > lead times of up to 12 weeks for some parts, it becomes a lot of work to > make sure that all the parts will be in by the scheduled manufacturing > start date. For just three small boards, I have 100 different passive > components and 50 active ones. This also includes mechanical components > and the PCBs. > > I am not trying to be rude, but if you don't see the difficulty of > procurement, it is likely that you are not doing it. Or maybe I am just > not doing it right... I know that I have a new found respect for buyers! > > If you have some info on this process, I would love to read it. Let me > know! > > -- > > Rick Collins > > rick.collins@XYarius.com > > remove the XY to email me. > > Arius - A Signal Processing Solutions Company > Specializing in DSP and FPGA design > > Arius > 4 King Ave > Frederick, MD 21701-3110 > 301-682-7772 Voice > 301-682-7666 FAX > > Internet URL http://www.arius.comArticle: 20853
Buy a Z80 core and program both it and the code into a Flash-based FPGA with security features. Note that Zilog is now pushing the EZ80, a new super-fast core with Z80 compatibility, so that might be a good fit for your app. imcneill@mccomp.demon.co.uk (Ian McNeill) wrote in <ibbras88m6covvsp67f48u1kp3s5kg93en@4ax.com>: >I'm in the market for a 16 bit micro, with 64k+ on chip eeprom or flash, >where the on-board memory has excellent security, i.e. it cannot be read >by a programmer, but more importantly, it can not be read by a program >residing in external rom. Ideally the processor would only run program >that resides on the on-chip memory, and external memory would be >restricted to Ram or Code data. >We are migrating from a Z80 code base, so if there was something >Z80-like then so much the better, but if not, I'd settle for something >that has plenty of registers and operates the Flags register in a >similar way to a Z80, in particular the Carry flag on adds and >subtracts. This rules on the Intel mircocontrollers cause it does >things a LOT differently with the flags. >Any other builtin periperhals would be a bonus, but not essential.Article: 20854
On Wed, 26 Jan 2000 15:11:21 -0500, +Pablo+ <anon@vapor.net> wrote: >On Fri, 31 Dec 1999 11:20:44 -0600, "Larry Edington" ><larryeSpam.Me.Not@centuryinter.net> wrote: > >>I'm looking at an FPGA for project I'm working on and am concerned about >>security. CPLD's and ASIC's I'm familiar with but FPGA's are a new trick for >>me. >> >>I'm looking at Altera and Xilinx. >> >>It appears that most FPGA's are programmed with a serial eeprom. I'm >>concerned about the security the data in the eeprom. What keeps someone from >>simply copying your eeprom to duplicate your FPGA's programming? > >You can also load from a microprocessor or part of a parallel eprom >elsewhere in the system. It would take a lot more work for someone to >reverse engineer if done this way. > Isn't is still dirt-simple to capture the bistream or parallel-loaded data during boot? > >In an extreme case, a missile containing these devices is loaded at >boot time from the launcher. Once launched, the hard configuration >data is no longer part of the system. Once power is lost, the >configuration is also lost. Failed missiles cannot be reverse >engineered by the enemy. > >> >>Maybe this is a stupid question but I'm still learning about FPGA's. Since I >>will have some encryption / decryption functions in the FPGA, this is a big >>concern for me. What do you need to do to protect your design when using >>FPGA's ? >> >>thanks, >>Larry E. >>Remove Spam_me_not to reply via email. >> >> >> >Article: 20855
Tim Forcer wrote: > > ... > I can't find a specific reference to someone doing ... > configure using master serial mode from an EEPROM as > per standard, but, optionally, use the JTAG port > to reconfigure. > > ... > > It's not that I don't believe it can be done, just > that I'd like to hear that it _HAS_ been done! ... And nobody has claimed that dubious honour. So I assume it hasn't ever been done on a "real" product. Shame, really. Also implies that JTAG isn't used that much? (Yes, I know it's sad, replying to my own posts. But information is contained in nulls, and I felt like commenting on that fact.) -- Tim Forcer tmf@ecs.soton.ac.uk The University of Southampton, UK The University is not responsible for my opinionsArticle: 20856
Jerry Avins wrote: > "E. Robert Tisdale" wrote: > > > > ... > > > > Thanks Ray, > > > > I just thought that you might have meant "on-line" arithmetic > > when you said "bit-serial" arithmetic. > > But, apparently, that is not the case. > > I'll bite. What's "on-line" arithmetic? You owe me one. "On-Line" arithmetic is a new form of arithmetic being tested at MIT I believe ... instead of writing complex and space consuming algorithms within FPGAs for functions such as sin/cos etc., the FPGA has a state machine that is programmed to generate ethernet packets that can be transmitted over the internet. They are sent, through an internet connection that the FPGA has access to, to a server somewhere that has enough grunts to be able to perform the requested arithmetic function very very quickly ... the result is returned back to the FPGA within a maximum time, but which is significantly less than the time it would have taken the fpga to perform it. In this way it is easy to envisage even more complex arithmetic functions being implemented, that have a deterministic response time. Of course, the server will typically only be performing arithmetic tasks, but if it's powerful enough it could serve many FPGA's thoeretically anywhere in the world ... even from space! It is possible, however, that due to internet congestion or packet misdirection, that the result that the FPGA is returned is not the expected arithmetic result, but the 1-800 telephone number of Delicous Debby Daring to Dabble in Delightful Doings .. rather confusing for the poor FPGA I wager .... ... at least that's what I read in Electronics Times.... Gary.Article: 20857
Nicolas Matringe wrote: > > "Jaime Andrés Aranguren Cardona" a écrit : > > > > Hi, guys. > > > > I hope you help me with this. I am trying to install Xilinx Foundation 2.1i > > on my PC, but a message wich stands it can not "inflate PCFJars" appears on > > the screen, and cancells the installation. > > Looks like you don't have enough space in your temporary directory. > > Nicolas MATRINGE DotCom S.A. > Conception electronique 16 rue du Moulin des Bruyeres > Tel 00 33 1 46 67 51 11 92400 COURBEVOIE > Fax 00 33 1 46 67 51 01 FRANCE I had the same error when trying to upgrade Fondation and it was because the design manager was running. Hope this help Yacine. -- ===================================================== EL KOLLI Yacine | e-mail:elkolli@crf.canon.fr Canon C.R.F. | Phone: +33.(0)2.99.87.68.79 http://www.crf.canon.fr | FAX: +33.(0)2.99.84.11.30 ====================================================Article: 20858
PC is too slow for readback debug infomarton without hw acceleration. Take a look at databook. XChecker is recomended for readback, but the schematic... Arnold <a@z.com> wrote in message 38B418B6.98E0D6A7@z.com... >Hi, > >You may want to take a look at the Parallel III cable - same >functionality but contains just some buffers. It can also double as a >JTAG download cable too. > >Regards, >Catalin > >Ray Andraka wrote: > >> It's not a trivial design. It's got an XC3042 FPGA in it among other >> things. >> >> Fuzesi Arnold wrote: >> >> > Hi All! >> > >> > I want to make my own xchecker cable. >> > >> > Is it possible ? >> > >> > Can I copy an original cable? >> > >> > Thanks, >> > Arnold >> > /Electrical Engineer Student/ >> >> -- >> -Ray Andraka, P.E. >> President, the Andraka Consulting Group, Inc. >> 401/884-7930 Fax 401/884-7950 >> email randraka@ids.net >> http://users.ids.net/~randraka >Article: 20859
This is a multi-part message in MIME format. --------------480FF297E6A14FB08E25806B Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit does anybody out there know where to get PC-motherboards which support PCI 64 bit / 66 MHz ??? (or PCI 32 bit / 66 MHz, or PCI 64 bit / 33 MHz) --------------480FF297E6A14FB08E25806B Content-Type: text/x-vcard; charset=us-ascii; name="mmichel.vcf" Content-Transfer-Encoding: 7bit Content-Description: Card for Markus Michel Content-Disposition: attachment; filename="mmichel.vcf" begin:vcard n:Michel;Markus tel;fax:+41 (0)61 336 22 00 tel;work:+41 (0)61 336 22 22 x-mozilla-html:FALSE org:Kontron Medical AG version:2.1 email;internet:mmichel@kontronmedical.ch title:dipl. El'Ing. ETH adr;quoted-printable:;;Reinacherstr. 131=0D=0AP.O. Box;CH- 4002 Basel;;;Switzerland x-mozilla-cpt:;5808 fn:Markus Michel end:vcard --------------480FF297E6A14FB08E25806B--Article: 20860
Weren't there some early ibm machines with revolving drum that doubled as main storage and main 'ram'? Jerry Avins wrote: > > I want to add that ENIAC's serial architecture was well suited to the > mercury delay line that constituted its main memory. (Disks are serial > too, bit we don't use them for main memory.) > > Jerry > -- > Engineering is the art of making what you want from things you can get. > ----------------------------------------------------------------------- -- ******************************************* * Russell Shaw, B.Eng, M.Eng(Research) * * Electronics Consultant * * email: russell@webaxs.net * * Australia * *******************************************Article: 20861
Markus Michel wrote: > does anybody out there know where to get PC-motherboards which support > PCI 64 bit / 66 MHz ??? > (or PCI 32 bit / 66 MHz, or PCI 64 bit / 33 MHz) Hi, I saw some x86 server configuration by Intel with PCI 66/64 capabilities, you should be able to find them on Intel WebSite. Also I think that most recent alpha based motherboard have 66/64 slots. Hope this helps StevenArticle: 20862
russell shaw wrote: > > Weren't there some early ibm machines with revolving drum that doubled > as main storage and main 'ram'? Yes, EG the IBM 650 I think. But I don't think we use them much these days. http://www.spawned.com/jargon/jargon_49.htmlArticle: 20863
Richard Erlacher wrote: > On Wed, 26 Jan 2000 15:11:21 -0500, +Pablo+ <anon@vapor.net> wrote: > > >On Fri, 31 Dec 1999 11:20:44 -0600, "Larry Edington" > ><larryeSpam.Me.Not@centuryinter.net> wrote: > > > >>I'm looking at an FPGA for project I'm working on and am concerned about > >>security. CPLD's and ASIC's I'm familiar with but FPGA's are a new trick for > >>me. > >> > >>I'm looking at Altera and Xilinx. > >> > >>It appears that most FPGA's are programmed with a serial eeprom. I'm > >>concerned about the security the data in the eeprom. What keeps someone from > >>simply copying your eeprom to duplicate your FPGA's programming? > > > >You can also load from a microprocessor or part of a parallel eprom > >elsewhere in the system. It would take a lot more work for someone to > >reverse engineer if done this way. > > > > Isn't is still dirt-simple to capture the bistream or parallel-loaded > data during boot? > Capture yes, reverse engineer no. If someone uses your FPGA bit stream it would be a trivial to show they stole your design....That is once you catch them. -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 20864
Hi Ray, Correct, I forgot about readback - but does anybody really use it? Catalin Ray Andraka wrote: > a@z.com wrote: > > > Hi, > > > > You may want to take a look at the Parallel III cable - same > > functionality but contains just some buffers. It can also double as a > > JTAG download cable too. > > > > well, not exactly. Same purpose, but not as much functionality. You can't > do readback with a parallel III for example. > > > > > Regards, > > CatalinArticle: 20865
I went down this road about three years ago. You might try "parts and vendors" but I don't know where from. It will pull BOMs from (eg)ORCAD into itself if your prepared to bother, and tries fairly hard to give you what you want. I say "prepared to bother" because it will cost you less than £200 which is not too much to waste, the holy grail does not exist at any price, mainly because they can't cope with multiple vendors with different part numbers which can only sometimes be used instead of others. It is often best to get your pcb's panelled up to the largest size that will go through a local companies pick & place and let them stuff the boards with the descretes. This works out cheaper than doing it by hand yourself and then keeping your stocks to the few expensive parts to solder on as you sell them. Note that as soon as your selling in surprisingly small volumes then getting your third party to buy and stuff the expensive parts as well becomes competitive due to their overall buying volumes. Rob In article <38B2F23D.C424DE1E@yahoo.com>, Rickman <spamgoeshere4@yahoo.com> wrote: > I have started a company to make several DSP boards and I am looking for > a program to manage the parts procurement and tracking for manufacturing > these boards. As it turns out, I am spending more time dealing with the > management of the process than I am the engineering. A good MRP program > would help me enormously. > > It would also be good if it included or interfaced to an accounting > package. I have considered using Quick Books for accounting simply > because that is recommended by my accountant. > > Anyone involved in the support of manufacturing that can offer some > advice? > > -- > > Rick Collins > > rick.collins@XYarius.com > > remove the XY to email me. > > Arius - A Signal Processing Solutions Company > Specializing in DSP and FPGA design > > Arius > 4 King Ave > Frederick, MD 21701-3110 > 301-682-7772 Voice > 301-682-7666 FAX > > Internet URL http://www.arius.com > Sent via Deja.com http://www.deja.com/ Before you buy.Article: 20866
Hi I plan to buy a Xilinx PCI Core for a SpartanII device but I can't find any information about the core pinout. I'd like to start working on the PCB layout as soon as possible. The planned device is an XC2S50-FG256. Any help, link... is greatly appreciated Thanks in advance, Nicolas MATRINGE DotCom S.A. Conception electronique 16 rue du Moulin des Bruyeres Tel 00 33 1 46 67 51 11 92400 COURBEVOIE Fax 00 33 1 46 67 51 01 FRANCEArticle: 20867
Hello,
a@z.com wrote:
> Correct, I forgot about readback - but does anybody really use it?
I do, but given the time some of my questions take to be answered, I'd bet we're
just a minority...
Some questions I've been trying to get a definitive answer:
I've been told that a DLL output will follow its input when driven by the
boundary-scan cell. Given that Virtex can perform the optional 1149.1 instruction
INTEST:
How "clean" is the DLL output when switching to INTEST? I mean, is it gracefully
stopping or if garbage can be seen when the DLL looses its lock? Also, how do you
deal with the fact that the lock will become inactive but you still want to
single step the internal logic? And if you use the 2x DLL output, how do you keep
that clock tree synchronized to other 1x global clocks, I suppose you need to
pulse it twice? That wouldn't work if using both 1x and 2x outputs...
Etienne.
--
______ ______
*****/ ____// _ \_\*************************************************
* / /_/_ / /_/ / / Etienne Racine, Hardware Designer *
* / ____// __ /_/ Visual Systems Engineering *
* / /_/_ / / /\ \ \ CAE Electronics Ltd. *
*/_____//_/_/**\_\_\*************************************************
Article: 20868Dear all, I'm trying to use automatic retiming with a VHDL design that I'm synthesizing with the command line version of FPGA Express 3.3.1. Automatic retiming is supposed to redistribute a number of pipeline registers instantiated at the inputs of a combinational block evenly across the logic so that timing will be easier to meet. This is a fragment of the compilation script that I'm using: create_chip -target VIRTEX -device V800HQ240 -speed -6 -progress -target $target -name $chip -keep_pads -eliminate $top set_chip_retiming -enable current_chip $chip Has anyone got this to work? When I look at the edif netlist I see that the pipeline registers are not distributed at all, but are all stacked up at the inputs. By the way, does anyone know is Synplicity has this feature too? (I'm thinking to switch soon...) Thanks much, -Arrigo -- Dr. Arrigo Benedetti e-mail: arrigo@vision.caltech.edu Caltech, MS 136-93 phone: (626) 395-3695 Pasadena, CA 91125 fax: (626) 795-8649Article: 20869
Hil Balaji, "Balaji Rangaswamy" <karapampuchi@yahoo.com> schrieb im Newsbeitrag news:891nql$178s@r02n01.cac.psu.edu... > Can anyone direct me to a design example for implementating a pulse width > modulation (PWM) circuit in an Altera Flex 10K? Design handbooks, > tutorials, > appnotes? > I just don't have any of these things, but I already have implemented some PWM code for a 3 phase Power Stage for 3~ brushless Servomotors. It's quite simple. Assuming You have the pulse-width value as a 8Bit, signed (two's complement) vector, you just have to start a counter (8Bit) that is incremented with each clock pulse. It will permanently count from $00 to $FF and you just need to reload the comparison register with the pulse- width value, every time the counter changes from $7F to $80. The Pulse-width modulated Bit is generated as follows: * when the counter changes from $7F to $80, you reset the bit * every time the counter is increased, you compare the counter if it's greater than the loaded pulse-width value. If it is, just toggle the Bit. The result is a PWM Signal with Duty Cycles of 0..100%. The frequency is 1/255 of the Counter Clock. Hope this would help you to solve the problem, CU, CarlhermannArticle: 20870
russell shaw wrote: > > Weren't there some early ibm machines with revolving drum that doubled > as main storage and main 'ram'? > > Jerry Avins wrote: > > > > I want to add that ENIAC's serial architecture was well suited to the > > mercury delay line that constituted its main memory. (Disks are serial > > too, bit we don't use them for main memory.) > > > > Jerry > > -- > > Engineering is the art of making what you want from things you can get. > > ----------------------------------------------------------------------- > > -- > ******************************************* > * Russell Shaw, B.Eng, M.Eng(Research) * > * Electronics Consultant * > * email: russell@webaxs.net * > * Australia * > ******************************************* Maybe, but the only drum machine I had direct experience with was a timeshare PDP-10, and that had core for main memory. The OS command to run one of our programs from the TTY was RUN DRUM PREP; PREP was the name of the program. Jerry -- Engineering is the art of making what you want from things you can get. -----------------------------------------------------------------------Article: 20871
russell shaw wrote:
> Weren't there some early IBM machines with revolving drum
> that doubled as main storage and main 'ram'?
The very first electronic digital computer was invented
by Professor John Atanasoff in 1939 and built
by one of his Graduate Students -- Clifford Berry --
at Iowa State University. Berry had completed
the computer by 1942 -- long before the ENIAC.
http://www.cs.iastate.edu/jva/jva-archive.shtml
The ABC stored electrical charge on a rotating drum
for memory -- sort of a DRAM.
Article: 20872I made some progress and found that set_chip_retiming has to be issued after current_chip, not before. Now, however, FPGA Express is blowing up: 81.0% 82.0% Creating retiming model for design ... Abort at 401 Fatal: Internal system error, cannot recover. Time to call synopsys tech support again ... -Arrigo Arrigo Benedetti <arrigo@vision.caltech.edu> writes: > Dear all, > > I'm trying to use automatic retiming with a VHDL design that > I'm synthesizing with the command line version of FPGA Express > 3.3.1. Automatic retiming is supposed to redistribute a number > of pipeline registers instantiated at the inputs of a combinational > block evenly across the logic so that timing will be easier to meet. > This is a fragment of the compilation script that I'm using: > > create_chip -target VIRTEX -device V800HQ240 -speed -6 -progress > -target $target -name $chip -keep_pads -eliminate $top > > set_chip_retiming -enable > > current_chip $chip > > Has anyone got this to work? When I look at the edif netlist I see that > the pipeline registers are not distributed at all, but are all stacked > up at the inputs. > By the way, does anyone know is Synplicity has this feature too? > (I'm thinking to switch soon...) > > Thanks much, > > -ArrigoArticle: 20873
Some vendors of RAM based devices will try to pitch design security to you, but there is no way to truly secure a design that uses a bit-stream to program it. If you really need security, look at anti-fuse based devices from either Actel or Quicklogic. Also, Xilinx Coolrunner lines are ram based, but programmed from an internal EEPROM, so they may be secure as well. Good luck! -- Keith F. Jasinski, Jr. kfjasins@execpc.com Richard Erlacher <edick@hotmail.com> wrote in message news:38b4d365.57336553@mindmeld.idcomm.com... > > > On Wed, 26 Jan 2000 15:11:21 -0500, +Pablo+ <anon@vapor.net> wrote: > > >On Fri, 31 Dec 1999 11:20:44 -0600, "Larry Edington" > ><larryeSpam.Me.Not@centuryinter.net> wrote: > > > >>I'm looking at an FPGA for project I'm working on and am concerned about > >>security. CPLD's and ASIC's I'm familiar with but FPGA's are a new trick for > >>me. > >> > >>I'm looking at Altera and Xilinx. > >> > >>It appears that most FPGA's are programmed with a serial eeprom. I'm > >>concerned about the security the data in the eeprom. What keeps someone from > >>simply copying your eeprom to duplicate your FPGA's programming? > > > >You can also load from a microprocessor or part of a parallel eprom > >elsewhere in the system. It would take a lot more work for someone to > >reverse engineer if done this way. > > > > Isn't is still dirt-simple to capture the bistream or parallel-loaded > data during boot? > > > > >In an extreme case, a missile containing these devices is loaded at > >boot time from the launcher. Once launched, the hard configuration > >data is no longer part of the system. Once power is lost, the > >configuration is also lost. Failed missiles cannot be reverse > >engineered by the enemy. > > > >> > >>Maybe this is a stupid question but I'm still learning about FPGA's. Since I > >>will have some encryption / decryption functions in the FPGA, this is a big > >>concern for me. What do you need to do to protect your design when using > >>FPGA's ? > >> > >>thanks, > >>Larry E. > >>Remove Spam_me_not to reply via email. > >> > >> > >> > > >Article: 20874
The first "home computer" that I know of was built by Don Hitt of IBM in
the early sixties out of a recirculating acoustic delay line with a
discrete component one bit ALU. The architecture was ingeniously simple
and it was at least a Turing. Programming it so that the data and
instruction you needed next was always close upstream was quite a
challenge though.
I think I've mentioned Don before in the context of the first working,
productized, embedded microprocessor which was his next effort in the
mid sixties along with Bob Wasserman. I think that Don was the Seymore
Cray (sp.?) of minimalist architecture.
Bob
russell shaw wrote:
>
> Weren't there some early ibm machines with revolving drum that doubled
> as main storage and main 'ram'?
>
> Jerry Avins wrote:
> >
> > I want to add that ENIAC's serial architecture was well suited to the
> > mercury delay line that constituted its main memory. (Disks are serial
> > too, bit we don't use them for main memory.)
> >
> > Jerry
> > --
> > Engineering is the art of making what you want from things you can get.
> > -----------------------------------------------------------------------
>
> --
> *******************************************
> * Russell Shaw, B.Eng, M.Eng(Research) *
> * Electronics Consultant *
> * email: russell@webaxs.net *
> * Australia *
> *******************************************
--
"Things should be described as simply as possible, but no simpler."
A. Einstein
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