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Jerry Avins wrote:
> "E. Robert Tisdale" wrote:
> >
> > What the heck is bit serial arithmetic?
>
> Try to find documentation on the PDP8S. That was a bit serial machine.
> Some old IC logic books have spec sheets for bit serial adders.
WARNING: WORTHLESS TRIVIA IN THIS POST
From a historical point of view, there are some rather famous machines and
applications that were serial. The ENIAC, for instance, was a serial
machine, operating one decimal digit at a time. Each decimal digit
consisted of a ring of 10 flip-flops. Many of the early aerospace designs
were bit serial, as the need to minimize mass and power were important.
Just like in many Computer Science algorithms, there's a space-time
trade-off. Of course, the simplified hardware can go really fast with
respect to clock rate. It's possible to perhaps win on speed, too, with a
serial architecture, as other sections of the FPGA, not used by a parallel
adder, can be dedicated to performing some other useful computational
function in parallel.
> Jerry
> --
> Engineering is the art of making what you want from things you can get.
Excellent quote.
"There's nothing like real data to f' up a great theory."
rk
Article: 20826rk wrote: ... > > WARNING: WORTHLESS TRIVIA IN THIS POST > > From a historical point of view, there are some rather famous machines and > applications that were serial. The ENIAC, for instance, was a serial > machine, operating one decimal digit at a time. Each decimal digit > consisted of a ring of 10 flip-flops. Many of the early aerospace designs > were bit serial, as the need to minimize mass and power were important. > > Just like in many Computer Science algorithms, there's a space-time > trade-off. Of course, the simplified hardware can go really fast with > respect to clock rate. It's possible to perhaps win on speed, too, with a > serial architecture, as other sections of the FPGA, not used by a parallel > adder, can be dedicated to performing some other useful computational > function in parallel. > Worthless trivia are what will make this NG worth following even after I've learned all the answers. (Ahem!) I want to add that ENIAC's serial architecture was well suited to the mercury delay line that constituted its main memory. (Disks are serial too, bit we don't use them for main memory.) Jerry -- Engineering is the art of making what you want from things you can get. -----------------------------------------------------------------------Article: 20827
HELLO TO ALL I have to write syntesisable models (verilog) with are according with IEC 1131-3. Could you tell me where could I find this standard. And what "according with IEC 1131-3" mean. my adrss: rgasiore@veri.iie.pz.zgora.plArticle: 20828
Ray Andraka wrote: > The arithmetic is performed one bit per clock cycle, > so that it takes N clock cycles to perform an N bit wide operation. > For straight arithmetic operations, > it is usually done LSB first since arithmetic operations are left transitive. > Occasionally there are times > when an MSB first bit serial operation is desirable, > such as priority encodes, compares and first one's detections. > > True it takes more clock cycles to perform an operation, > but you get the advantage of a much smaller circuit > (1/Nth the size in the general case, and often even smaller). > For example, a bit-serial adder is a 3 input XOR gate, > a majority-3 gate and two flip-flops. > That can be done in a pair of FPGA logic elements. > Since you don't have wide fanout controls or long carries, > the clock rate can be quite a bit higher than the clock > for more conventional bit-parallel arithmetic. > In many cases, the time-hardware product for a bit serial design > is smaller than the equivalent bit-parallel design > (meaning you get the same performance in a smaller area). > > Modern FPGAs are capable of clock rates of well over 100MHz, > which is much higher than the data rates on typical applications > slated for FPGAs in today's market. > If you do a parallel design for a relatively low data rate, say 10 MHz, > you leave a lot of the FPGA's capability on the table > so you might be passing up an opportunity for a much smaller device. Thanks Ray, I just thought that you might have meant "on-line" arithmetic when you said "bit-serial" arithmetic. But, apparently, that is not the case.Article: 20829
Hi Jaime, If you are running WinNT 4.0 you need at least Service Pack 3 for the installation process to work. Regards, Catalin "Jaime Andrés Aranguren Cardona" wrote: > Hi, guys. > > I hope you help me with this. I am trying to install Xilinx Foundation 2.1i > on my PC, but a message wich stands it can not "inflate PCFJars" appears on > the screen, and cancells the installation. > > I have a Pentium Celeron 333MHz w/ 64Mb RAM. > > So I tried to install it from the hard disk, but it didn´t help. > > Please, any help to jaac@pregrado.upb.edu.co > > Thanks in advance > > -- > Please confirm recieving. > Favor confirmar recibimento. > > Jaime Andrés Aranguren Cardona > jaac@pregrado.upb.edu.coArticle: 20830
Hi, You may want to take a look at the Parallel III cable - same functionality but contains just some buffers. It can also double as a JTAG download cable too. Regards, Catalin Ray Andraka wrote: > It's not a trivial design. It's got an XC3042 FPGA in it among other > things. > > Fuzesi Arnold wrote: > > > Hi All! > > > > I want to make my own xchecker cable. > > > > Is it possible ? > > > > Can I copy an original cable? > > > > Thanks, > > Arnold > > /Electrical Engineer Student/ > > -- > -Ray Andraka, P.E. > President, the Andraka Consulting Group, Inc. > 401/884-7930 Fax 401/884-7950 > email randraka@ids.net > http://users.ids.net/~randrakaArticle: 20831
Info on cables (and schematic for parallel 3) here: http://www.xilinx.com/support/programr/cables.htm a@z.com wrote: > > Hi, > > You may want to take a look at the Parallel III cable - same > functionality but contains just some buffers. It can also double as a > JTAG download cable too. > > Regards, > Catalin > Regards, Tom BurgessArticle: 20832
That is cool. An excellent description...I know because I didn't know
it before, and now I do! (obviously there are a lot of fine points).
but when I think about combining bit serial arithmetic with something
like SP/DIF (also serial format easily handled by FPGA's) the possibilities
are endless...
In article <38B36BB4.EA4DDCD2@ids.net>, Ray Andraka wrote:
>The arithmetic is performed one bit per clock cycle, so that it takes N
>clock cycles to perform an N bit wide operation. For straight
>arithmetic operations, it is usually done LSB first since arithmetic
>operations are left transitive. Occasionally there are times when an
>MSB first bit serial operation is desirable, such as priority encodes,
>compares and first one's detections.
--
DSP Audio Effects! http://gweep.net/~shifty
. . . . . . . . ... . . . . . .
"La la la laaa laaa laaa " | Niente
La la la laaa laaa laaa." -Stereolab | shifty@gweep.net
Article: 20833
...snip...
> ENTITY count1 is
> PORT
> (
> clock : IN STD_LOGIC;
> enable : IN STD_LOGIC;
> qa : OUT STD_LOGIC_VECTOR (0 to 7)
> );
> END count1;
>
> ARCHITECTURE Count1Arch of count1 is
> BEGIN
> VAR: PROCESS (clock)
> VARIABLE count : INTEGER RANGE 0 TO 255;
>
> BEGIN
> IF (clock'EVENT AND clock = '1') THEN
> IF enable = '1' THEN
> count := count + 1;
> END IF;
> END IF;
> qa <= CONV_STD_LOGIC_VECTOR(count,8);
> END PROCESS;
> END Count1Arch;
Try changing above line to:
qa <= CONV_STD_LOGIC_VECTOR( CONV_UNSIGNED( count, 9 ), 8 );
I think Synopsis is complaining because its trying to convert _signed_
value to a slv, and that takes one more bit.
WoodyJ
Sent via Deja.com http://www.deja.com/
Before you buy.
Article: 20834
Now that I understand it a little bit better, what techniques do you
use to handle unsynchronized input streams, e.g. two sp/dif streams?
And how do you handle incoming streams with varying data rates?
or is bit serial arithmetic only usually used within the chip, once
data is been clocked in parallel fashion?
again, thanks.
-Noah
In article <890g88$kd1$1@nnrp1.deja.com>, Lasse Langwadt Christensen wrote:
>it is doing a calculation one bit at a time. It's more less
>the same as doing e.g. a 32 bit addition on an 8 bit cpu,
>using 4, 8 bit adds (with a carry in and out), it's just done
>with 1 bit adds, it can save HW but will cost on clockcycles
>needed to do a calculation.
>
>-Lasse
>
>
>Sent via Deja.com http://www.deja.com/
>Before you buy.
--
DSP Audio Effects! http://gweep.net/~shifty
. . . . . . . . ... . . . . . .
"La la la laaa laaa laaa " | Niente
La la la laaa laaa laaa." -Stereolab | shifty@gweep.net
Article: 20835"E. Robert Tisdale" wrote: > > ... > > Thanks Ray, > > I just thought that you might have meant "on-line" arithmetic > when you said "bit-serial" arithmetic. > But, apparently, that is not the case. I'll bite. What's "on-line" arithmetic? You owe me one. Jerry -- Engineering is the art of making what you want from things you can get. -----------------------------------------------------------------------Article: 20836
wannarat <ksuwanna@kmitl.ac.th> wrote: : Dear All : Why do we have noise in the bus between FPGA to RAM(external )? : I tested with my design synthesize with RAM onto FPGA , the result : hasn't have noise. : Why is it like that? Missing decoupling and bad layout are possible causes, Glitches,Races etc are more reasons. Bye -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 20837
Crackpot wrote: > > Now that I understand it a little bit better, what techniques do you > use to handle unsynchronized input streams, e.g. two sp/dif streams? > And how do you handle incoming streams with varying data rates? > > or is bit serial arithmetic only usually used within the chip, once > data is been clocked in parallel fashion? > > again, thanks. > > -Noah > > In article <890g88$kd1$1@nnrp1.deja.com>, Lasse Langwadt Christensen wrote: > >it is doing a calculation one bit at a time. It's more less > >the same as doing e.g. a 32 bit addition on an 8 bit cpu, > >using 4, 8 bit adds (with a carry in and out), it's just done > >with 1 bit adds, it can save HW but will cost on clockcycles > >needed to do a calculation. > > > >-Lasse > > > > > >Sent via Deja.com http://www.deja.com/ > >Before you buy. > > -- > DSP Audio Effects! http://gweep.net/~shifty > . . . . . . . . ... . . . . . . > "La la la laaa laaa laaa " | Niente > La la la laaa laaa laaa." -Stereolab | shifty@gweep.net That's a hardware question, of course. Depending on what you want to do, and on the resources you have, you can use parallel or serial data busses. A rate converter can be a shift register clocked in at one rate and out at another, a parallel transfer from one shift register to another (UART to UART for communication rate conversion) or anything else that works. Jerry -- Engineering is the art of making what you want from things you can get. -----------------------------------------------------------------------Article: 20838
Hi, Check the Setup.log file that is in the Temp directory of the PC. This will give you more info on why it failed the install Common problems are that there is not enough disk space for the installer. The user has no USER Path defined which causes a 'snippet 700' failure. Make sure that you have admin privilages. Cheers, Dave Hawke Xilinx UK a@z.com wrote in message <38B417E8.FE543C83@z.com>... >Hi Jaime, > >If you are running WinNT 4.0 you need at least Service Pack 3 for the >installation process to work. > >Regards, >Catalin > >"Jaime Andrés Aranguren Cardona" wrote: > >> Hi, guys. >> >> I hope you help me with this. I am trying to install Xilinx Foundation 2.1i >> on my PC, but a message wich stands it can not "inflate PCFJars" appears on >> the screen, and cancells the installation. >> >> I have a Pentium Celeron 333MHz w/ 64Mb RAM. >> >> So I tried to install it from the hard disk, but it didn´t help. >> >> Please, any help to jaac@pregrado.upb.edu.co >> >> Thanks in advance >> >> -- >> Please confirm recieving. >> Favor confirmar recibimento. >> >> Jaime Andrés Aranguren Cardona >> jaac@pregrado.upb.edu.co >Article: 20839
Fabrice Hoffmann wrote: > i want to load an ALTERA EPC2 configuration Eeperom from an embedded > controller which has an RS232. I plan to use the free ALTERA Jam Player > running on a PC. So i have to emulate the BitBlaster functionality in my > controller firmware. Does anybody have information about the bitblaster > (schematics !!! ...). I just don't understand the task. Is the configuration Eprom on your board or separate? Do you want to program the Eprom regularly or only for upgrades? The last I would use are BitBlaster and JamPlayer. You can interface the Altera CPLD directly to you microcontroller bus and program it with 4 lines C code. (You can write me in German if that helps you...) ArminArticle: 20840
Nicholas C Weaver writes: > It is under the LGPL, so you can use this in a commercial product. A core for FPGAs under LGPL. Now that has some interesting implications. Like, you can't just give someone a bitmap for your commercial product. You have to give them the source to the LGPL'd core _and_ files which allow the recipient to change the LGPL'd core and reconstruct the FPGA program. E.g., a netlist EDIF for the application part. have a nice day, -- JamieArticle: 20841
In article <m2aekrtvrt.fsf@pcep-jamie.cern.ch>, Jamie Lokier <spamfilter.feb2000@tantalophile.demon.co.uk> wrote: >Nicholas C Weaver writes: >> It is under the LGPL, so you can use this in a commercial product. > >A core for FPGAs under LGPL. Now that has some interesting >implications. Like, you can't just give someone a bitmap for your >commercial product. > >You have to give them the source to the LGPL'd core _and_ files which >allow the recipient to change the LGPL'd core and reconstruct the FPGA >program. E.g., a netlist EDIF for the application part. The important part about it being under the LGPL instead of the GPL is that you ONLY need to release the source for the core itself, not your whole design. The LGPL, unlike the GPL, removes the viral nature or firewalling necessary to use GPL code in a larger project. -- Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 20842
Are your base address registers for your memory mapped registers marked as non-prefetchable? Also, why are you trying to relocate the memory? My understanding is they are set to sane values during the bios boot process and should not move. Bruce ajit_madhekar@my-deja.com wrote: > > 3) My card driver reads the config space and come to know the memory > region > of interest. > 4) Using ioremap_nocache in Linux and NdisMMapIoSpace in NDIS 3.0, I > remap > the memory into another region ( physical to virtual memory mapping, as > they > call it in NDIS) > 5) I acess the memory address from the remapped locations thereonwords. > > Problem faced > ---------------- > > Now the problem faced many times in Linux and sometimes in WinNT is > that the > base address is found to be changed in the middle of operation.( > randomly , > sometimes after half hour run and sometimes even in minutes ). When the > driver reads any register from the remapped location , it finds all > "FFFFF... ". Upon this when I read the PCI space for base address 0 , I > found it changed.Article: 20843
I think this problem caused from function overload .Some FPGA tools can not detect it. You should not declear unsigned package and arithmetic package simultaneously.(It already declared inside unsigned package) It would be fine if you remove unsigned package from use statement. Good Luck. Satoru Takemoto CyberLabo Limited Homepade: http://www.cyber-labo.co.jp/ > ************* > library IEEE; > use IEEE.std_logic_1164.all; > use IEEE.STD_LOGIC_UNSIGNED.all; > use IEEE.STD_LOGIC_ARITH.all; > > ENTITY count1 is > PORT > ( > clock : IN STD_LOGIC; > enable : IN STD_LOGIC; > qa : OUT STD_LOGIC_VECTOR (0 to 7) > ); > END count1; > > ARCHITECTURE Count1Arch of count1 is > BEGIN > VAR: PROCESS (clock) > VARIABLE count : INTEGER RANGE 0 TO 255; > > BEGIN > IF (clock'EVENT AND clock = '1') THEN > IF enable = '1' THEN > count := count + 1; > END IF; > END IF; > qa <= CONV_STD_LOGIC_VECTOR(count,8); -- This line produces an error > message on synthesis > END PROCESS; > END Count1Arch; > > ************* > > -- > Holger Kleinert > Development / Support > > IBP Instruments GmbH > Sutelstrasse 7a > D-30659 Hannover, Germany > > http://www.ibpmt.com > Fon : +49-511-652286 > Fax : +49-511-652283Article: 20844
try this. www.pjrc.com/tech/xdownloader/ Fuzesi Arnold wrote: > Hi All! > > I want to make my own xchecker cable. > > Is it possible ? > > Can I copy an original cable? > > Thanks, > Arnold > /Electrical Engineer Student/Article: 20845
--
*******************************************************************
Balaji Rangaswamy
Residence Office
445, Waupelani Drive, Apt F26 303, Electrical Engg West,
State College, PA 16801. University Park, PA 16802.
Ph: (814) 235 9472 Ph: (814) 863 0082
EMail: brangasw@cse.psu.edu
*******************************************************************
Article: 20846
Can anyone direct me to a design example for implementating a pulse width
modulation (PWM) circuit in an Altera Flex 10K? Design handbooks,
tutorials,
appnotes?
Thank you
Balaji.
--
*******************************************************************
Balaji Rangaswamy
Residence Office
445, Waupelani Drive, Apt F26 303, Electrical Engg West,
State College, PA 16801. University Park, PA 16802.
Ph: (814) 235 9472 Ph: (814) 863 0082
EMail: brangasw@cse.psu.edu
*******************************************************************
Article: 20847I am planning on using the Xilinx PCI32 soft-core PCI interface in one of their Virtex devices. I have been looking over their data and literature and have not been able to find timing and interface specifications on the local side of the PCI Core. By local side, I am referring to the PCI core signals that will interface with a FIFO either within the Virtex device, or in my case interface with an external Synchronous Dual-Port SRAM. Ideally, it would be great if Xylinx provided a Glue-Logic VHDL module that would seamlessly interface their PCI core with a synchronous Dual-Port SRAM (64K x 16). I would appreciate any leads. Thanks! Sent via Deja.com http://www.deja.com/ Before you buy.Article: 20848
Radoslaw Gasiorek wrote: > > HELLO TO ALL > > I have to write syntesisable models (verilog) with are according with IEC > 1131-3. > Could you tell me where could I find this standard. And what "according > with IEC 1131-3" mean. Hmmm, strange requirement - ask the client for an example! IEC1131-3 is a Standards Spec, relating mainly to Programmable Logic Controllers (PLC's). It has 5 language 'legs' SFC : Sequential Function Chart ~ Flow Charts ST : Structured Text ~ Modula-2/Pascal/ ( and so VHDL-ish) LD : Ladder Diagram ~ old PLC standard FBD : Function Block Diagram - ~ Schematic Diagram IL : Instruction List - A bit like reverse polish (HP calculators ) Assembller So while the Structured Text language is a solid, type safe high level language, ( better suited to enbedded control than C, and we make a 8051 compiler using this Std), verilog it is NOT. You could maybe use FBD techniques for the top level description ? There is some WEB info at http://www.ISaGRAF.com/ There is also a book, ISBN 2-9511585-0-5 : IEC1131 Programming Methodology - jg -- ======= Manufacturers of Design Tools for uC and PLD ===== * IceP2051 - Full Speed ICE, for 1K,2K,4K 20 Pin FLASH controllers * OptoISP - Safe, fast In System Program of 89S, 90S, 17C devices => http://www.DesignTools.co.nz/winner51.htm for highlightsArticle: 20849
On-line arithmetic is basically doing arithmetic with signed digits. It was originally developed to accelerate addition and subtraction by eliminating the carry propagation, but has found better application in dividers and multipliers. It is kind of messy, and a real pain to convert to and from binary number systems. Jerry Avins wrote: > "E. Robert Tisdale" wrote: > > > > ... > > > > Thanks Ray, > > > > I just thought that you might have meant "on-line" arithmetic > > when you said "bit-serial" arithmetic. > > But, apparently, that is not the case. > > I'll bite. What's "on-line" arithmetic? You owe me one. > > Jerry > -- > Engineering is the art of making what you want from things you can get. > ----------------------------------------------------------------------- -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randraka
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