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Threads Starting Dec 1999
19129: 99/12/01: Nicolas Matringe: Timing constraint not met
19130: 99/12/01: Bonio Lopez: Re: Timing constraint not met
19132: 99/12/01: Nicolas Matringe: Re: Timing constraint not met
19134: 99/12/01: Ray Andraka: Re: Timing constraint not met
19131: 99/12/01: Manfred Kraus: data serializer/decoder FPGA solution
19135: 99/12/01: Ray Andraka: Re: data serializer/decoder FPGA solution
19148: 99/12/02: Manfred Kraus: Re: data serializer/decoder FPGA solution
19139: 99/12/02: Magnus Homann: Re: data serializer/decoder FPGA solution
19145: 99/12/02: Mark Summerfield: Re: data serializer/decoder FPGA solution
19146: 99/12/02: Klaus Falser: Re: data serializer/decoder FPGA solution
19163: 99/12/02: Holger Kleinert: Re: data serializer/decoder FPGA solution
19208: 99/12/06: Hal Murray: Re: data serializer/decoder FPGA solution
19140: 99/12/01: Spatel: Free Data Management Software
19142: 99/12/02: <rajesh52@hotmail.com>: Verilog FAQ
19147: 99/12/02: Mark van de Belt: Command line for FPGA Express
19153: 99/12/02: Andy Peters: Re: Command line for FPGA Express
19167: 99/12/03: Austin Franklin: Re: Command line for FPGA Express
19172: 99/12/03: Mark van de Belt: Re: Command line for FPGA Express
19186: 99/12/03: Dave Vanden Bout: Re: Command line for FPGA Express
19191: 99/12/04: Austin Franklin: Re: Command line for FPGA Express
19197: 99/12/05: Dave Vanden Bout: Re: Command line for FPGA Express
19150: 99/12/02: Davide Falchieri: Tristate bidirectional pads with Xilinx
19152: 99/12/02: Andy Peters: Re: Tristate bidirectional pads with Xilinx
19157: 99/12/02: Jamie Sanderson: Re: Tristate bidirectional pads with Xilinx
19161: 99/12/02: Dragon: Re: Tristate bidirectional pads with Xilinx
19162: 99/12/02: Dragon: Re: Tristate bidirectional pads with Xilinx
19165: 99/12/02: Peter Alfke: Re: Tristate bidirectional pads with Xilinx
19166: 99/12/02: Dragon: Re: Tristate bidirectional pads with Xilinx
19169: 99/12/03: Ray Andraka: Re: Tristate bidirectional pads with Xilinx
19177: 99/12/03: Davide Falchieri: Re: Tristate bidirectional pads with Xilinx
19179: 99/12/03: Andy Peters: Re: Tristate bidirectional pads with Xilinx
19184: 99/12/03: Rickman: Re: Tristate bidirectional pads with Xilinx
19151: 99/12/02: Bonio Lopez: Question to synplicity users and other not Leonardo users,
19175: 99/12/03: Jonas Thor: Re: Question to synplicity users and other not Leonardo users,
19154: 99/12/02: Nicolas Matringe: Virtex and JTAG configuration
19171: 99/12/03: Nicolas Matringe: Re: Virtex and JTAG configuration
19155: 99/12/02: Bonio Lopez: Connection of light diode and FPGA
19156: 99/12/02: Jamie Sanderson: Re: Connection of light diode and FPGA
19170: 99/12/03: Olaf: Re: Connection of light diode and FPGA
19158: 99/12/02: Jonathan Bromley: CAN testing - Any CANbus cores out there?
19192: 99/12/04: <tryggvem@my-deja.com>: Re: CAN testing - Any CANbus cores out there?
19193: 99/12/04: Joseph Hlebasko: Re: CAN testing - Any CANbus cores out there?
19270: 99/12/09: F.Rodriguez: Re: CAN testing - Any CANbus cores out there?
19277: 99/12/09: Jonathan Bromley: Re: CAN testing - Any CANbus cores out there?
19160: 99/12/02: SMiOUxrH: <!-- To use a different cobrand, make sure you have a template for it in /parts/cobrand/ -->
19164: 99/12/02: OxbIEcum: <!-- To use a different cobrand, make sure you have a template for it in /parts/cobrand/ -->
19173: 99/12/03: Johan Ditmar: Problems with routing Virtex device
19174: 99/12/03: Ray Andraka: Re: Problems with routing Virtex device
19176: 99/12/03: Ray Andraka: Re: Problems with routing Virtex device
19209: 99/12/06: Bonio Lopez: Re: Problems with routing Virtex device
19210: 99/12/06: Don Husby: Re: Problems with routing Virtex device
19178: 99/12/03: Jamie Sanderson: Help with ROM in Xilinx Virtex
19180: 99/12/03: Ray Andraka: Re: Help with ROM in Xilinx Virtex
19181: 99/12/03: Ernesto Guevara: Re: Help with ROM in Xilinx Virtex
19182: 99/12/03: Jamie Sanderson: Solution: ROM in Xilinx Virtex
19183: 99/12/03: Ray Andraka: Re: Solution: ROM in Xilinx Virtex
19206: 99/12/06: Samer EL HAJJ: Re: Help with ROM in Xilinx Virtex
19207: 99/12/06: Samer EL HAJJ: Re: Help with ROM in Xilinx Virtex
19211: 99/12/06: Jamie Sanderson: Re: Help with ROM in Xilinx Virtex
19187: 99/12/03: Volker Kalms: ALTERA EPC2 configuration problem
19188: 99/12/04: Andrew Buckin: Simple programmator for EP910
19212: 99/12/06: News_food: Re: Simple programmator for EP910
19302: 99/12/11: Richard Erlacher: Re: Simple programmator for EP910
19199: 99/12/05: Dan Rymarz: hobbyist friendly pld?
19200: 99/12/05: Pascal Dornier: Re: hobbyist friendly pld?
19202: 99/12/05: Dave Vanden Bout: Re: hobbyist friendly pld?
19301: 99/12/11: Richard Erlacher: Re: hobbyist friendly pld?
19204: 99/12/06: Leon Heller: Re: hobbyist friendly pld?
19265: 99/12/09: Nigel Orr: Re: hobbyist friendly pld?
19321: 99/12/14: Leon Heller: Re: hobbyist friendly pld?
19369: 99/12/16: David Gesswein: Re: hobbyist friendly pld?
19348: 99/12/15: Tim Forcer: Re: hobbyist friendly pld?
19357: 99/12/15: Dave Vanden Bout: Re: hobbyist friendly pld?
19365: 99/12/16: Leon Heller: Re: hobbyist friendly pld?
19352: 99/12/15: amigabill: Re: hobbyist friendly pld?
19353: 99/12/15: amigabill: Re: hobbyist friendly pld?
19213: 99/12/06: Steve Dewey: Re: hobbyist friendly pld?
19241: 99/12/08: Hans: Re: hobbyist friendly pld?
19225: 99/12/07: Tim Forcer: Re: hobbyist friendly pld?
19581: 00/01/02: Richard Erlacher: Re: hobbyist friendly pld?
19754: 00/01/11: Stewart, Nial [HAL02:HH00:EXCH]: Re: hobbyist friendly pld?
19308: 99/12/13: Grant Sargent: Re: hobbyist friendly pld?
19411: 99/12/20: <jcurren@my-deja.com>: Re: hobbyist friendly pld?
19666: 00/01/07: PaulTB: Re: hobbyist friendly pld?
19201: 99/12/06: Gabry: NOT PCI TO PCI BUS....how it is possible with FPGA?
19203: 99/12/05: Arch^Mage: Schematic Help Please....
19205: 99/12/06: Dave Decker: Re: Schematic Help Please....
19215: 99/12/06: Xanatos: JTAG use after FPGA configuration on board
19296: 99/12/11: Andrew Cannon: Re: JTAG use after FPGA configuration on board
19216: 99/12/06: Moussa Ba: TIme Delay 1us-100ms
19218: 99/12/06: Ray Andraka: Re: TIme Delay 1us-100ms
19231: 99/12/07: muzo: Re: TIme Delay 1us-100ms
19235: 99/12/07: Ray Andraka: Re: TIme Delay 1us-100ms
19255: 99/12/08: Peter Alfke: Re: TIme Delay 1us-100ms
19217: 99/12/06: IEC5: Actel Programming Information Sought
19219: 99/12/06: rk: Re: Actel Programming Information Sought
19234: 99/12/07: Erich Wagner: Re: Actel Programming Information Sought
19222: 99/12/06: rk: test, please ignore
19223: 99/12/07: Bernard Esteban: PCI RESET with FPGA
19224: 99/12/07: Bernard Esteban: JTAG on PCI slot
19233: 99/12/07: Holger Kleinert: Re: JTAG on PCI slot
19243: 99/12/08: Pete Dudley: Re: JTAG on PCI slot
19250: 99/12/08: Holger Kleinert: Re: JTAG on PCI slot
19254: 99/12/09: Hal Murray: Re: JTAG on PCI slot
19256: 99/12/09: Joseph H Allen: Re: JTAG on PCI slot
19264: 99/12/09: Ray Andraka: Re: JTAG on PCI slot
19268: 99/12/09: Joseph H Allen: Re: JTAG on PCI slot
19226: 99/12/07: Thorsten Neumann: Problems with Leonardo Spectrum
19229: 99/12/07: Stuart Clubb: Re: Problems with Leonardo Spectrum
19227: 99/12/07: Mike: AM2901 bit slice processor
19232: 99/12/07: B. Joshua Rosen: Re: AM2901 bit slice processor
19236: 99/12/08: glen herrmannsfeldt: Re: AM2901 bit slice processor
19237: 99/12/07: rk: Re: AM2901 bit slice processor
19239: 99/12/08: Bob Doyle: Re: AM2901 bit slice processor
19300: 99/12/11: Richard Erlacher: Re: AM2901 bit slice processor
19228: 99/12/07: <raderrl@my-deja.com>: tool command language (TCL)
19230: 99/12/07: Stuart Clubb: Re: tool command language (TCL)
19240: 99/12/08: Sharif: Autologic II Xilinx Library
19242: 99/12/08: anonymous: Is there two-read one-write asynchronous SRAM in FPGA?
19244: 99/12/08: Utku Ozcan: Re: Is there two-read one-write asynchronous SRAM in FPGA?
19246: 99/12/08: Jan Gray: Re: Is there two-read one-write asynchronous SRAM in FPGA?
19274: 99/12/09: Ray Andraka: Re: Is there two-read one-write asynchronous SRAM in FPGA?
19280: 99/12/09: John L. Smith: Re: Is there two-read one-write asynchronous SRAM in FPGA?
19284: 99/12/09: John L. Smith: Re: Is there two-read one-write asynchronous SRAM in FPGA?
19248: 99/12/08: Jamie Sanderson: Re: Is there two-read one-write asynchronous SRAM in FPGA?
19304: 99/12/11: jan coombs: Re: Is there two-read one-write asynchronous SRAM in FPGA?
19245: 99/12/08: <eml@riverside-machines.com.NOSPAM>: Re: Xilinx FPGA Map report question
19247: 99/12/08: Utku Ozcan: constraints between clock domains: can't advance
19249: 99/12/08: Ray Andraka: Re: constraints between clock domains: can't advance
19251: 99/12/08: Don Husby: Re: constraints between clock domains: can't advance
19252: 99/12/08: Bob Perlman: Re: constraints between clock domains: can't advance
19261: 99/12/09: Bonio Lopez: Re: constraints between clock domains: can't advance
19294: 99/12/10: Utku Ozcan: Re: constraints between clock domains: can't advance
19260: 99/12/09: jim granville: Re: constraints between clock domains: can't advance
19253: 99/12/08: OC team: press release
19259: 99/12/09: <please@dont.mail.me.com>: Re: press release
19257: 99/12/09: Jeff Smith: Lattice ispLSI Security
19306: 99/12/12: Luigi Funes: Re: Lattice ispLSI Security
19307: 99/12/12: Ray Andraka: Re: Lattice ispLSI Security
19332: 99/12/14: <luigi_funes@my-deja.com>: Re: Lattice ispLSI Security
19335: 99/12/14: Ray Andraka: Re: Lattice ispLSI Security
19315: 99/12/13: Armin Mueller: Re: Lattice ispLSI Security
19258: 99/12/09: Andrew Reddig: JTAG programming problem with multiple Altera MAX7000A devices
19262: 99/12/09: Dan Rymarz: Re: JTAG programming problem with multiple Altera MAX7000A devices
19281: 99/12/10: Free Spirit: Re: JTAG programming problem with multiple Altera MAX7000A devices
19297: 99/12/10: Andrew Reddig: Re: JTAG programming problem with multiple Altera MAX7000A devices
19263: 99/12/09: Matthieu Liger: Passing attributes from VHDL with FPGA Express for Xilinx
19266: 99/12/09: Ray Andraka: Re: Passing attributes from VHDL with FPGA Express for Xilinx
19267: 99/12/09: Rich Walker: Vantis MACH ISP
19269: 99/12/09: Theron Hicks: EEPROM for spartan xl series FPGA?
19275: 99/12/09: Holger Kleinert: Re: EEPROM for spartan xl series FPGA?
19278: 99/12/10: David Hawke: Re: EEPROM for spartan xl series FPGA?
19283: 99/12/09: Luc Nantel: Re: EEPROM for spartan xl series FPGA?
19272: 99/12/09: Walter Soto Encinas Junior: Synopsys backannotation
19273: 99/12/09: Andy Peters: Re: Synopsys backannotation
19276: 99/12/09: Walter Soto Encinas Junior: Re: Synopsys backannotation
19282: 99/12/09: Andy Peters: Re: Synopsys backannotation
19286: 99/12/10: Daniel K. Elftmann: Re: Synopsys backannotation
19290: 99/12/10: David Robinson: Re: Synopsys backannotation
19360: 99/12/16: Chandramohan Sateesh: Re: Synopsys backannotation
19371: 99/12/16: Paulo Dutra: Re: Synopsys backannotation
19279: 99/12/09: Thomas W. Fry: FPGA Benchmarks
19299: 99/12/11: Brian Dipert: Re: FPGA Benchmarks
19285: 99/12/10: ydHeVVur: <!-- To use a different cobrand, make sure you have a template for it in /parts/cobrand/ -->
19287: 99/12/10: Lourens Geldenhuys: MAX7256A dies during ICP
19323: 99/12/14: <deroberts@my-deja.com>: Re: MAX7256A dies during ICP
19326: 99/12/14: Lourens Geldenhuys: Re: MAX7256A dies during ICP
19533: 99/12/29: bob elkind: Re: MAX7256A dies during ICP
19288: 99/12/10: Nicolas Matringe: Xilinx COREgen memory initialization files
19291: 99/12/10: Rémi SEGLIE: Re: Xilinx COREgen memory initialization files
19289: 99/12/10: <smithers12@my-deja.com>: Virtex boards
19311: 99/12/13: Daryl Bradley: Re: Virtex boards
19324: 99/12/14: <cartman_sspi@my-deja.com>: Re: Virtex boards
19333: 99/12/14: Tim Tyler: Re: Virtex boards
19359: 99/12/16: Oh Sheau Pyng: Virtex boards
19361: 99/12/16: Bill Blyth: Re: Virtex boards
19390: 99/12/18: Oh Sheau Pyng: Virtex boards
19364: 99/12/16: Image Simulation: Re: Virtex boards
20241: 00/02/02: david gilchrist: Re: Virtex boards
19292: 99/12/10: Richard B. Katz: test message
19293: 99/12/10: Richard B. Katz: test message
19295: 99/12/10: Xanatos: Altera APEX lpm modules in Synplify
19303: 99/12/11: Magnus Homann: Re: Altera APEX lpm modules in Synplify
19298: 99/12/11: Milliwave: FPGA to ASIC Conversion?
19305: 99/12/11: rk: Announcement and First Call for Papers - 2000 MAPLD Conference
19309: 99/12/13: Mark Harvey: R: Command line for FPGA Express
19310: 99/12/13: Peter Heidrich: Silicon instead of FPGA for Ethernet-to-Ethernet MAC Switch?
19312: 99/12/13: <uj101@my-deja.com>: Re: Silicon instead of FPGA for Ethernet-to-Ethernet MAC Switch?
19313: 99/12/13: Thomas Rathgen: power on reset with FLEX 10K
19316: 99/12/13: aitan ameti: Re: power on reset with FLEX 10K
19314: 99/12/13: Nicolas Matringe: Virtex hard macro
19328: 99/12/14: Graeme Durant: Re: Virtex hard macro
19317: 99/12/13: Walter Soto Encinas Jr: Velab and VSS simulation
19318: 99/12/13: jeffrey j cook: VirtexE availability?
19336: 99/12/14: <kulak@my-deja.com>: Re: VirtexE availability?
19339: 99/12/15: Isabelle Gonthier: Re: VirtexE availability?
19344: 99/12/15: jeffrey j cook: Re: VirtexE availability?
19381: 99/12/17: Rick Filipkiewicz: Re: VirtexE availability?
19319: 99/12/14: Marc Battyani: State machine ok with binary encoding but unstable with one hot encoding
19320: 99/12/14: David Murray: Re: State machine ok with binary encoding but unstable with one hot encoding
19325: 99/12/14: <micheal_thompson@my-deja.com>: Re: State machine ok with binary encoding but unstable with one hot encoding
19327: 99/12/14: David Murray: Re: State machine ok with binary encoding but unstable with one hot encoding
19329: 99/12/14: Chris Squires: Re: State machine ok with binary encoding but unstable with one hot encoding
19330: 99/12/14: Marc Battyani: Re: State machine ok with binary encoding but unstable with one hot encoding
19341: 99/12/15: Austin Franklin: Re: State machine ok with binary encoding but unstable with one hot encoding
19343: 99/12/14: Robert Sefton: Re: State machine ok with binary encoding but unstable with one hot
19345: 99/12/15: Ken McElvain: Re: State machine ok with binary encoding but unstable with one hot
19347: 99/12/15: Chris Squires: Re: State machine ok with binary encoding but unstable with one hot encoding
19349: 99/12/15: <mench@mench.com>: Re: State machine ok with binary encoding but unstable with one hot encoding
19350: 99/12/15: Austin Franklin: Re: State machine ok with binary encoding but unstable with one hot encoding
19354: 99/12/15: Mike Treseler: Re: State machine ok with binary encoding but unstable with one hot
19340: 99/12/15: Austin Franklin: Re: State machine ok with binary encoding but unstable with one hot encoding
19351: 99/12/15: David Murray: Re: State machine ok with binary encoding but unstable with one hot encoding
19355: 99/12/15: Austin Franklin: Re: State machine ok with binary encoding but unstable with one hot encoding
19342: 99/12/15: Matt Billenstein: Re: State machine ok with binary encoding but unstable with one hot encoding
19363: 99/12/16: Johan Van Dyck: Re: State machine ok with binary encoding but unstable with one hot encoding
19451: 99/12/22: <eml@riverside-machines.com.NOSPAM>: Re: State machine ok with binary encoding but unstable with one hot encoding
19463: 99/12/22: Marc Battyani: Re: State machine ok with binary encoding but unstable with one hot encoding
19322: 99/12/14: Eduardo Augusto Bezerra: CORE-2000 - Reconfigurable Computing Workshop
19331: 99/12/14: Oliver Huang: How to probe internal signals of P&R-ed Xilinx device with Verilog timing simulation ?
19334: 99/12/14: Eileen Haldeman: System Engineering positions
19338: 99/12/14: Steve Martindell: memory init file format for Foundation simulator ?
19346: 99/12/15: Nicolas Matringe: Re: memory init file format for Foundation simulator ?
19356: 99/12/15: J.R.: Speed grade
19358: 99/12/15: Peter Alfke: Re: Speed grade
19375: 99/12/17: Davide Falchieri: Re: Speed grade
19384: 99/12/17: Peter Alfke: Re: Speed grade
19387: 99/12/17: Ray Andraka: Re: Speed grade
19398: 99/12/19: Luigi Funes: Re: Speed grade
19402: 99/12/19: Ray Andraka: Re: Speed grade
19412: 99/12/20: Jonas Thor: Re: Speed grade
19419: 99/12/20: Ray Andraka: Re: Speed grade
19421: 99/12/20: rk: Re: Speed grade
19423: 99/12/21: Hal Murray: Re: Speed grade
19424: 99/12/20: rk: Re: Speed grade
19458: 99/12/22: Keith Jasinski, Jr.: Re: Speed grade
19435: 99/12/21: Joel Kolstad: Re: Speed grade
19442: 99/12/21: rk: Re: Speed grade
19444: 99/12/21: Ray Andraka: Re: Speed grade
19469: 99/12/23: Ray Andraka: Crossing clock domain boundaries[ was Speed grade]
19459: 99/12/22: Keith Jasinski, Jr.: Re: Speed grade
19436: 99/12/21: Bob Perlman: Re: Speed grade
19443: 99/12/22: Jamie Lokier: Re: Speed grade
19376: 99/12/17: Andreas Doering: Re: Speed grade
19362: 99/12/16: Vladimir Trosin: We work for you to have a rest!!!
19366: 99/12/16: Peter A Dudley: Virtex Configuration Trouble
19368: 99/12/16: Nicolas Matringe: Re: Virtex Configuration Trouble
19370: 99/12/16: Peter A Dudley: Re: Virtex Configuration Trouble
19367: 99/12/16: Pier Paolo: Foundation 2.1 GTS problem
19372: 99/12/17: giuseppe giachella: R: constraints between clock domains: can't advance
19373: 99/12/17: Ono noriaki: Question:Logic change with Quartus
19374: 99/12/17: Søren Lambæk: How to include SpartanXL code in C souce code?
19382: 99/12/17: John Janusson: Re: How to include SpartanXL code in C souce code?
19405: 99/12/20: Mark van de Belt: Re: How to include SpartanXL code in C souce code?
19417: 99/12/20: Joel Kolstad: Re: How to include SpartanXL code in C souce code?
19377: 99/12/17: //members.home.nl/stoelie: Http://members.home.nl/stoelie
19380: 99/12/17: Bonio Lopez: JEDEC
19383: 99/12/17: Andy Peters: Re: JEDEC
19385: 99/12/17: Matt Gavin: Global buffer insertion (Synplify/Flex10K)
19471: 99/12/23: Thomas Rathgen: Re: Global buffer insertion (Synplify/Flex10K)
19477: 99/12/23: Ying C.: Re: Global buffer insertion (Synplify/Flex10K)
19386: 99/12/17: Mark Hillers: Simulation of Virtex-XDW
19388: 99/12/17: Michael Helduser: Altera Quartus 99.10
19389: 99/12/17: Xanatos: Re: Altera Quartus 99.10
19777: 00/01/12: <pengyun@my-deja.com>: Re: Altera Quartus 99.10
19391: 99/12/17: Dann Corbit: Dumb question springing from a discussion about chess on a chip...
19392: 99/12/18: Ray Andraka: Re: Dumb question springing from a discussion about chess on a chip...
19393: 99/12/17: Dann Corbit: Re: Dumb question springing from a discussion about chess on a chip...
19394: 99/12/18: Simon Bacon: Re: Dumb question springing from a discussion about chess on a chip...
19396: 99/12/18: Dave Decker: Re: Dumb question springing from a discussion about chess on a chip...
19397: 99/12/19: <geronimojones@my-deja.com>: Re: Dumb question springing from a discussion about chess on a chip...
19413: 99/12/20: Simon Bacon: Re: Dumb question springing from a discussion about chess on a chip...
19415: 99/12/20: John L. Smith: Re: Dumb question springing from a discussion about chess on a chip...
19416: 99/12/20: Joel Kolstad: Re: Dumb question springing from a discussion about chess on a chip...
19420: 99/12/20: Ray Andraka: Re: Dumb question springing from a discussion about chess on a chip...
19395: 99/12/18: Ray Andraka: Re: Dumb question springing from a discussion about chess on a chip...
19400: 99/12/19: Vincent Diepeveen: Re: Dumb question springing from a discussion about chess on a chip...
19410: 99/12/20: Ray Andraka: Re: Dumb question springing from a discussion about chess on a chip...
19430: 99/12/21: Vincent Diepeveen: Re: Dumb question springing from a discussion about chess on a chip...
19433: 99/12/21: Ray Andraka: Re: Dumb question springing from a discussion about chess on a chip...
19455: 99/12/22: Vincent Diepeveen: Re: Dumb question springing from a discussion about chess on a chip...
19440: 99/12/21: Don Husby: Re: Dumb question springing from a discussion about chess on a chip...
19454: 99/12/22: Vincent Diepeveen: Re: Dumb question springing from a discussion about chess on a chip...
19464: 99/12/22: <ahuramazda@my-deja.com>: Re: Dumb question springing from a discussion about chess on a chip...
19468: 99/12/23: Dave Decker: Re: Dumb question springing from a discussion about chess on a chip...
19473: 99/12/23: Vincent Diepeveen: Re: Dumb question springing from a discussion about chess on a chip...
19475: 99/12/23: <ahuramazda@my-deja.com>: Re: Dumb question springing from a discussion about chess on a chip...
19476: 99/12/23: Ray Andraka: Re: Dumb question springing from a discussion about chess on a chip...
19479: 99/12/24: <ahuramazda@my-deja.com>: Re: Dumb question springing from a discussion about chess on a chip...
19480: 99/12/24: Ray Andraka: Re: Dumb question springing from a discussion about chess on a chip...
19485: 99/12/25: <ahuramazda@my-deja.com>: Re: Dumb question springing from a discussion about chess on a chip...
19488: 99/12/24: Dave Vanden Bout: Re: Dumb question springing from a discussion about chess on a chip...
19489: 99/12/24: Dave Vanden Bout: Re: Dumb question springing from a discussion about chess on a ch
19519: 99/12/29: Keith R. Williams: Re: Dumb question springing from a discussion about chess on a chip...
19483: 99/12/24: Jan Gray: regular expression matching and parsing in FPGAs (was chess...)
19486: 99/12/25: <ahuramazda@my-deja.com>: Re: regular expression matching and parsing in FPGAs (was chess...)
19472: 99/12/23: Vincent Diepeveen: Re: Dumb question springing from a discussion about chess on a chip...
19399: 99/12/19: Thomas Bornhaupt: JamPlayer and 10K10
19401: 99/12/20: Michael Stanton: Re: JamPlayer and 10K10
19403: 99/12/20: Thomas Bornhaupt: Re: JamPlayer and 10K10
19418: 99/12/21: Michael Stanton: Re: JamPlayer and 10K10
19426: 99/12/21: Thomas Bornhaupt: Re: JamPlayer and 10K10
19448: 99/12/22: Steve Rencontre: Re: JamPlayer and 10K10
19404: 99/12/20: <micheal_thompson@my-deja.com>: Necessary to 'synchronise' an asynchronous FSM reset?
19407: 99/12/20: Bob Perlman: Re: Necessary to 'synchronise' an asynchronous FSM reset?
19428: 99/12/21: <micheal_thompson@my-deja.com>: Re: Necessary to 'synchronise' an asynchronous FSM reset?
19438: 99/12/21: Bob Perlman: Re: Necessary to 'synchronise' an asynchronous FSM reset?
19409: 99/12/20: Ray Andraka: Re: Necessary to 'synchronise' an asynchronous FSM reset?
19414: 99/12/20: Simon Bacon: Re: Necessary to 'synchronise' an asynchronous FSM reset?
19406: 99/12/20: Vincent Diepeveen: Making a chessprogram in FPGA?
19408: 99/12/20: Steven K. Knapp: ANN: The Industry's Largest Independent Information Source of FPGAs and CPLDs (www.optimagic.com)
19422: 99/12/21: #YEO WEE KWONG#: automated testbench
19425: 99/12/21: <elynum@my-deja.com>: fpga cost
19427: 99/12/21: rk: Re: fpga cost
19429: 99/12/21: Ray Andraka: Re: fpga cost
19441: 99/12/21: rk: Re: fpga cost
19446: 99/12/21: Ray Andraka: Re: fpga cost
19450: 99/12/21: rk: Re: fpga cost
19460: 99/12/22: Steen Larsen: Re: fpga cost
19474: 99/12/23: rk: Re: fpga cost
19629: 00/01/05: Steen Larsen: Re: fpga cost
19633: 00/01/04: Ray Andraka: Re: fpga cost
19630: 00/01/04: John Cain: Re: fpga cost
19637: 00/01/05: rk: Re: fpga cost
19437: 99/12/21: Joel Kolstad: Re: fpga cost
19431: 99/12/21: Bonio Lopez: AMD FLASH ?
19432: 99/12/21: Lutz Kleberhoff: Re: AMD FLASH ?
19434: 99/12/21: Bonio Lopez: Re: AMD FLASH ?
19439: 99/12/21: Christof Paar: M1 timings
19445: 99/12/21: Phil Hays: Re: M1 timings
19447: 99/12/21: Ray Andraka: Re: M1 timings
19449: 99/12/21: Ray Andraka: Re: M1 timings
19452: 99/12/22: <eml@riverside-machines.com.NOSPAM>: Re: M1 timings
19611: 00/01/04: Rick Filipkiewicz: Re: M1 timings
19619: 00/01/04: Peter Alfke: Re: M1 timings
19453: 99/12/22: Walter Soto Encinas Jr: EDIF and VITAL
19456: 99/12/22: <elynum@my-deja.com>: XC4000E
19457: 99/12/22: Etienne Racine: Re: XC4000E
19461: 99/12/22: Ray Andraka: Re: XC4000E
19462: 99/12/22: Danesh Tavana: JOBS: Open Positions at Triscend: The Configurable System-on-Chip Company
19465: 99/12/22: Xanatos: Working @ Home
19466: 99/12/23: khKim: Bi-directional 3-State Buffer
19470: 99/12/23: Mark van de Belt: Re: Bi-directional 3-State Buffer
19467: 99/12/23: Mahboob Ahmed: PCI slot 3.3V pins.
19482: 99/12/24: peter dudley: Re: PCI slot 3.3V pins.
19545: 99/12/30: Austin Franklin: Re: PCI slot 3.3V pins.
19548: 99/12/30: Magnus Homann: Re: PCI slot 3.3V pins.
19556: 99/12/30: Austin Franklin: Re: PCI slot 3.3V pins.
19562: 99/12/31: Magnus Homann: Re: PCI slot 3.3V pins.
19587: 00/01/03: Free Spirit: Re: PCI slot 3.3V pins.
19572: 00/01/01: Joel Kolstad: Re: PCI slot 3.3V pins.
19478: 99/12/23: James Yeh: viewlogic problem
19481: 99/12/24: Ray Andraka: Re: viewlogic problem
19484: 99/12/24: James Yeh: Re: viewlogic problem
19487: 99/12/25: <Santa@TheNorthPole.Org>: * * * M E R R Y C H R I S T M A S * * *
19490: 99/12/25: <krishnam@nital.stpp.soft.net>: Re: EDIF and VITAL
19491: 99/12/25: Luc Nantel: Is Actel antifuse FPGA realy secure ?
19492: 99/12/26: Jamil Khaib: FIFO design
19495: 99/12/27: Andy Peters: Re: FIFO design
19493: 99/12/27: David Geng: status during ISP
19513: 99/12/28: Bibico Cando: Re: status during ISP
19544: 99/12/30: David Geng: Re: status during ISP
19517: 99/12/29: Steve Rencontre: Re: status during ISP
19542: 99/12/30: Keith R. Williams: Re: status during ISP
19494: 99/12/27: Bonio Lopez: How can I preset /prereset some Latches
19498: 99/12/27: Dave Vanden Bout: Re: How can I preset /prereset some Latches
19509: 99/12/28: <eml@riverside-machines.com.NOSPAM>: Re: How can I preset /prereset some Latches
19496: 99/12/27: Legista: Schematics for ISP
19612: 00/01/04: Wolfgang Freiberger: Re: Schematics for ISP
19613: 00/01/04: Wolfgang Freiberger: Re: Schematics for ISP
19497: 99/12/28: Susan Deike: xilinx help *desperately* needed
19499: 99/12/28: Susan Deike: Re: xilinx help *desperately* needed
19505: 99/12/28: Bonio Lopez: Re: xilinx help *desperately* needed
19525: 99/12/29: Bonio Lopez: Re: xilinx help *desperately* needed
19501: 99/12/28: Matt Billenstein: Re: xilinx help *desperately* needed
19504: 99/12/28: Susan Deike: Re: xilinx help *desperately* needed
19507: 99/12/28: <a@z.com>: Re: xilinx help *desperately* needed
19516: 99/12/28: Matt Billenstein: Re: xilinx help *desperately* needed
19510: 99/12/28: Andy Peters: Re: xilinx help *desperately* needed
19500: 99/12/28: #YEO WEE KWONG#: HDL to graphic conversion
19506: 99/12/28: Edwin Naroska: Re: HDL to graphic conversion
19518: 99/12/28: peter dudley: Re: HDL to graphic conversion
19618: 00/01/05: goodkook: Re: HDL to graphic conversion
19502: 99/12/28: Matt Billenstein: Specifying Virtex CLKDLL CLKDV_DIVIDE property in VHDL
19503: 99/12/27: Simon Bacon: Re: Specifying Virtex CLKDLL CLKDV_DIVIDE property in VHDL
19508: 99/12/28: Larry Edington: VGA controller in FPGA
19511: 99/12/28: Joseph H Allen: Re: VGA controller in FPGA
19512: 99/12/28: Joseph H Allen: Re: VGA controller in FPGA
19514: 99/12/28: Dave Vanden Bout: Re: VGA controller in FPGA
19515: 99/12/28: Dave Vanden Bout: Re: VGA controller in FPGA
19596: 00/01/03: Steve Dewey: Re: VGA controller in FPGA
19520: 99/12/29: Jamil Khaib: USB2 core call for Volunteers
19523: 99/12/29: <mcjy@my-deja.com>: Re: USB2 core call for Volunteers
19524: 99/12/29: <mcjy@my-deja.com>: Re: USB2 core call for Volunteers
19531: 99/12/29: Andy Peters: Re: USB2 core call for Volunteers
19534: 99/12/29: Magnus Homann: Re: USB2 core call for Volunteers
19541: 99/12/29: Andy Peters: Re: USB2 core call for Volunteers
19552: 99/12/30: <mcjy@my-deja.com>: Re: USB2 core call for Volunteers
19553: 99/12/30: Magnus Homann: Re: USB2 core call for Volunteers
19536: 99/12/29: Steen Larsen: Re: USB2 core call for Volunteers
19551: 99/12/30: <mcjy@my-deja.com>: Re: USB2 core call for Volunteers
19538: 99/12/29: Joe: Re: USB2 core call for Volunteers
19547: 99/12/30: Jamil Khaib: Re: USB2 core call for Volunteers
19521: 99/12/29: Jamil Khaib: OpenIPCore call for examples
19522: 99/12/29: Jamil Khaib: sim error & webfitter
19526: 99/12/29: Timothy Miller: Virtex Config Help
19529: 99/12/29: Nicolas Matringe: Re: Virtex Config Help
19532: 99/12/29: Timothy Miller: Re: Virtex Config Help
19539: 99/12/29: peter dudley: Re: Virtex Config Help
19555: 99/12/30: Timothy Miller: Re: Virtex Config Help
19589: 00/01/03: Ray Andraka: Re: Virtex Config Help
19527: 99/12/29: Walter Soto Encinas Jr: VITAL timing parameter
19528: 99/12/29: J.R.: An online division unit with constant divisor
19530: 99/12/29: Kelly Hall: Re: An online division unit with constant divisor
19535: 99/12/29: Terje Mathisen: Re: An online division unit with constant divisor
19569: 00/01/01: Russell Coggrave: Re: An online division unit with constant divisor
20211: 00/02/01: LuisGomezMelis: RE: INTERNET CONSULTANT NEEDED
19593: 00/01/03: Douglas W. Jones,201H MLH,3193350740,3193382879: Re: An online division unit with constant divisor
19604: 00/01/04: Kelly Hall: Re: An online division unit with constant divisor
19605: 00/01/04: Peter L. Montgomery: Re: An online division unit with constant divisor
19608: 00/01/04: Terje Mathisen: Re: An online division unit with constant divisor
19624: 00/01/05: Christer Ericson: Re: An online division unit with constant divisor
19635: 00/01/05: Terje Mathisen: Re: An online division unit with constant divisor
19615: 00/01/04: Douglas W. Jones,201H MLH,3193350740,3193382879: Re: An online division unit with constant divisor
19537: 99/12/29: <elynum@my-deja.com>: xess board
19557: 99/12/31: IC-BOOK: Bad ALTERA data
19540: 99/12/29: peter dudley: IRDY/TRDY Dedicated or Special Pin Name
19546: 99/12/30: Magnus Homann: Re: IRDY/TRDY Dedicated or Special Pin Name
19590: 00/01/03: Ray Andraka: Re: IRDY/TRDY Dedicated or Special Pin Name
19543: 99/12/30: wannarat: FG and H function in Xilinx FPGA
19591: 00/01/03: Ray Andraka: Re: FG and H function in Xilinx FPGA
19549: 99/12/30: Bonio Lopez: License of Atmel free CD ROM Software
19554: 99/12/30: dmac: Re: License of Atmel free CD ROM Software
19550: 99/12/30: Genio Kronauer: XC9500 0,5u Mask: Errors?
20051: 00/01/25: +Pablo+: XC9500 0,5u Mask: Errors?
20123: 00/01/27: Andrew M. Dyer: Re: XC9500 0,5u Mask: Errors?
19558: 99/12/30: Matt Billenstein: Foundation 2.1i Synthesis->Options One-Hot/Zero-Hot state machine encoding
19559: 99/12/31: MK Yap: Using internal RAM in Altera Flex 10KE
19560: 99/12/31: <mcjy@my-deja.com>: Re: Using internal RAM in Altera Flex 10KE
19568: 00/01/01: Michael Vincze: Re: Using internal RAM in Altera Flex 10KE
19602: 00/01/04: MK Yap: Re: Using internal RAM in Altera Flex 10KE
19586: 00/01/03: <andy_ash@my-deja.com>: Re: Using internal RAM in Altera Flex 10KE
19594: 00/01/03: David Kessner: Re: Using internal RAM in Altera Flex 10KE
19606: 00/01/04: goodkook: Re: Using internal RAM in Altera Flex 10KE
19657: 00/01/07: <rob_dickinson@my-deja.com>: Re: Using internal RAM in Altera Flex 10KE
19561: 99/12/31: Mariotto: code error in active vhdl
19573: 00/01/01: Joel Kolstad: Re: code error in active vhdl
19563: 99/12/31: Larry Edington: Design security
19564: 99/12/31: Nicholas C. Weaver: Re: Design security
19567: 99/12/31: Peter Alfke: Re: Design security
19575: 00/01/01: Keith R. Williams: Re: Design security
19566: 99/12/31: Phil Hays: Re: Design security
19570: 00/01/01: Larry Edington: Re: Design security
19571: 00/01/01: Jonathan Bromley: Re: Design security
19574: 00/01/01: Number Cruncher: Re: Design security
19576: 00/01/01: John Cain: Re: Design security
19577: 00/01/01: Larry Edington: Re: Design security
19580: 00/01/02: Hal Murray: Re: Design security
19582: 00/01/02: Joel Kolstad: Re: Design security
19584: 00/01/02: Larry Edington: Re: Design security
19585: 00/01/02: Joel Kolstad: Re: Design security
19641: 00/01/05: <randombit@my-deja.com>: Re: Design security
19643: 00/01/05: Ray Andraka: Re: Design security
19578: 00/01/02: Richard Erlacher: Re: Design security
19579: 00/01/01: Larry Edington: Re: Design security
19583: 00/01/02: John Cain: Re: Design security
19588: 00/01/03: Ray Andraka: Re: Design security
19597: 00/01/03: Hal Murray: Re: Design security
19713: 00/01/09: jim granville: Re: Design security
19714: 00/01/09: Hal Murray: Re: Design security
19778: 00/01/12: Steve Rencontre: Re: Design security
19800: 00/01/12: Peter Alfke: Re: Design security
19831: 00/01/13: rk: Re: Design security
19842: 00/01/14: Steve Rencontre: Re: Design security
19844: 00/01/14: Keith R. Williams: Re: Design security
19856: 00/01/14: <eml@riverside-machines.com.NOSPAM>: Re: Design security
19877: 00/01/15: Hal Murray: Re: Design security
19817: 00/01/13: <satish_me@hotmail.com>: Re: Design security
19825: 00/01/13: Ray Andraka: Re: Design security
19599: 00/01/03: John Cain: Re: Design security
19600: 00/01/03: Ray Andraka: Re: Design security
19671: 00/01/07: Richard Erlacher: Re: Design security
19682: 00/01/07: Michael Lee: Re: Design security
19592: 00/01/03: <eml@riverside-machines.com.NOSPAM>: Re: Design security
19598: 00/01/03: Stuart Clubb: Re: Design security
19609: 00/01/04: Armin Mueller: Re: Design security
19620: 00/01/05: jim granville: Re: Design security
19670: 00/01/07: Richard Erlacher: Re: Design security
19677: 00/01/07: Ed Mcgettigan: Re: Design security
19690: 00/01/08: Allan Herriman: Re: Design security
19647: 00/01/06: Stuart Clubb: Re: Design security
19642: 00/01/05: <randombit@my-deja.com>: Re: Design security
19648: 00/01/06: Stuart Clubb: Re: Design security
19661: 00/01/07: rk: Re: Design security
19731: 00/01/10: rk: Re: Design security
19672: 00/01/07: Richard Erlacher: Re: Design security
19678: 00/01/07: Magnus Homann: Re: Design security
19689: 00/01/08: jim granville: Re: Design security
19640: 00/01/05: <randombit@my-deja.com>: Re: Design security
19595: 00/01/03: Steve Dewey: Re: Design security
19603: 00/01/03: John Cain: Re: Design security
19610: 00/01/04: rk: Re: Design security
19750: 00/01/11: Pat: Re: Design security
20082: 00/01/26: +Pablo+: Design security
20854: 00/02/24: Richard Erlacher: Re: Design security
20863: 00/02/24: Ray Andraka: Re: Design security
20873: 00/02/24: Keith Jasinski, Jr.: Re: Design security
20877: 00/02/24: Peter Alfke: Re: Design security
20885: 00/02/25: Andreas Heiner: Re: Design security
20901: 00/02/25: Rickman: Re: Design security
20902: 00/02/26: <imclaren@california.com>: Re: Design security
21101: 00/03/06: John Larkin: Re: Design security
21135: 00/03/08: Keith R. Williams: Re: Design security
20889: 00/02/25: Keith Jasinski, Jr.: Re: Design security
20894: 00/02/25: Tom Burgess: Re: Design security
20912: 00/02/27: Keith R. Williams: Re: Design security
21081: 00/03/06: Richard Erlacher: Re: Design security
21095: 00/03/07: Keith R. Williams: Re: Design security
21107: 00/03/06: Joel Kolstad: Re: Design security
19565: 99/12/31: Number Cruncher: Design security
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