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The way to do this is to synchronize your independent inputs to the global clock then use the synchronized inputs to enable counters working on the global clock. You'll need a synchronizer circuit that generates a one clock wide pulse for each 0 to 1 transition of the input clocks. Your local clock will have to be at least as fast as the fastest incoming clock, and if you can do 2x it makes the synchronizing a whole lot easier. The whole local counter doesn't have to work at 2x, only the first few bits. For that matter, you could prescale the input clocks using small counters and then synchronize the prescaled clocks to the global clock. The prescalers should not be more than 2 bits (in the same slice or CLB) so that you can run them with a clock that is routed on the general routing rather than on a global clock net. If you are careful about it, you can run the prescaler at a considerably higher frequency than the global clock tree is capable of. I think Peter Alfke did an app note to this effect for a 400MHz freq counter a couple years ago (before virtex). "Kresten Nørgaard" wrote: > Andy Peters skrev i meddelelsen <85d9lj$18d7$1@noao.edu>... > >Kresten Nørgaard wrote in message <857h4h$96j$1@news.inet.tele.dk>... > >>Hi group! > >>I'm looking into a new design, consisting of 4 pcs. of 32-bit 100 MHz > >>asynchronous counters. When stopped, the counters are emptied into a FIFO > >>(common to all counters - 32 kbyte size total). The FIFO's will be read > >>through an ordinary 8 MHz CPU interface. > > > >Question: why an async counter? Especially at 100 MHz? you'd better off > >with a synchronous counter and some logic that generates count enables. > > Quite right, but I figured, that I would need 4 "global" clocks to make 4 > counters, and not all FPGA families features so many distributed clocks. > > Another issue is power consumption. I reckoned, to lower the power > dissipation, if a chose a ripple counter, but I might be wrong on that? > > Kresten -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 19776
I have seen these on PowerPCs also. They are typically not very accurate, like about 4 degrees C was the spec in the PowerPC, but for many applications this is adequate. They utilize a temp to junction voltage characteristic that is linear and does not require a look up table common to thermistors which are non-linear. "Ray Andraka" <randraka@ids.net> wrote in message news:387A3996.F4830073@ids.net... > Haven't used them. They work based on the stong temperature dependence > of the junction voltage. > > Matt Billenstein wrote: > > > Has anyone used these or even know how they work? > > > > thx > > > > m > > > > Matt Billenstein > > http://w3.one.net/~mbillens/ > > mbillens@one.net > > -- > -Ray Andraka, P.E. > President, the Andraka Consulting Group, Inc. > 401/884-7930 Fax 401/884-7950 > email randraka@ids.net > http://users.ids.net/~randraka > >Article: 19777
hi, I also encounter such problem. Quartus occurs internal error when fitting 20% typically in case I tune some clique, location & options. even when I do such kind of thing in tcl following Xanatos's suggestion. do u have any solution? in my design, return to 9906sp2 or 9910 is of no help. Regards, Peng Yun In article <%cy64.1320$ak.3586@news20.bellglobal.com>, "Xanatos" <deletemeaoe_londonfog@hotmail.com> wrote: > > Is anyone else running Altera's Quartus 99.10 SP1 under Windows NT 4.0 SP4 > > and having miserable problems? If I try tweaking any design options I > > consistently get internal errors during compiles . Tech Support doesn't > say > > much except that "it" will be fixed in the next release? > > > > I reverted back to 99.06 SP 2 and am having none of the problems I had > using > > 99.10. > > I just took a crap, and it spelt Q U A R T U S. > > No, all joking aside here, I have had ENDLESS problems with it crashing > using > 99.10 SP1 under NT 4.0 SP4. I turfed the SP1 and went back to old 99.10. I > only had 2 crashes today....a new record. > > Trust me my friend...those internal errors arn't going anywhere fast.... > > My other tip for you....I was talking with Tech support, and they said the > best thing is to run the tool with TCL scripts. I figured that was the route > I was going to have to take anyway - that Timing Wizard does not nearly > constrain the stuff I need, etc. > > If your problems were "solved" using 99.06 SP2, then I might have to give > that a try. Thanks for the tip. > > Regards, > Xanatos > > Sent via Deja.com http://www.deja.com/ Before you buy.Article: 19778
In article <3878359A.69D0@DesignTools.co.nz>, jim.granville@DesignTools.co.nz (jim granville) wrote: > Hal Murray wrote: > > > > In article <3870B679.D84288FD@ids.net>, > > Ray Andraka <randraka@ids.net> writes: > > > The problem with putting an OTP key in the device, is that the > > > non-volatile > > > cells can't be fabricated without additional process steps. The > > > FPGA > > > process is essentially the same as DRAM, which lets it be done with > > > bleeding > > > edge process. Put PROM cells on there, and you lose the speed. > > > > I'm not a silicon guru. This case is different from a normal > > PROM in that we don't need a lot of bits. > > But you do - the whole config memory needs to go on chip, not just the > security bit(s), and you'll want the config memory re-writable as well, > otherwise the anitfuse devices are equivalent. > > A few bits of write-once is not a big problem - you just arrange a > kill-able element. > > Gatefield/Actel have FLASH FPGA, but the very leading edge will always > be > RAM based. I've just received an info sheet on the Cypress Delta39k family. Guess what? An SRAM CPLD and a flash memory in a 2-dice-per-chip package! This still isn't going to stop the bad guy with lots of money to spend on disassembling the chip, but it's got to be a good thing for intermediate security. -- Steve Rencontre, Design Consultant http://www.rsn-tech.demon.co.ukArticle: 19779
Make money faster than you could ever beleive! Here's how I started. I found this site while searching the web that told me what i'm about to tell you. you gonna think that this is a scam but tell me why you can't afford to take six dollars and turn it into thousands : The program goes as follows(follow these directions or it will not work): : 1) Take 6 separate envelopes and pieces of paper. On the paper, write : “Please put me on your mailing list and then place your name with : address.” : Now get 6 US $1.00 bills and place one in each of the envelopes with the : paper so wrapped around the bill so the bill can not be seen through the : envelope. This will prevent thievery. You should now have 6 sealed : envelopes, each with a piece of paper stating the above phrase, your name : and address, and a $1.00 bill. By providing a $1.00 in each envelope, you : are paying for their services. This is how it becomes legal. : 2) Mail the 6 envelopes to the following addresses: : : 1)Liam PO Box 90 Federal, NSW 2480 Australia : 2)Oliver PO Box 1032 Mullumbimby, NSW 2482 Australia : 3)Matt PO Box 260127 Boston, MA 02126 : 4)Paula 4763 N. Thorne Ave. Fresno, CA 93704 : 6) Durant Davis Jr. 2418 Rio Vista St. Chester Va. 23831 : 5)Durant Davis Jr. 2418 RioVista St. Chester VA 23831 : 6) Eric PO Box 536 Raymond NH 03077 : 3) Now take the #1 name off the list that you see above, move the other : names up (6 becomes 5, 5 becomes 4, etc...) and add YOUR Name as : number 6 on the list. : 4) Change anything you need in this letter you would like,but try to keep : it as close to original as possible. : 5) Now, post your amended article to at least 200 newsgroups. (I think : there are close to 24,000 groups) All you need is 200, but remember, the : more you post, and the more money you make! : -----HOW TO POST TO NEWSGROUPS------------ : 1) You do not need to re-type this entire letter to do your own posting. : Simply put your cursor at the beginning of this letter and drag your cursor : to the bottom of this document, then select 'copy' from the edit menu. This : will copy the entire letter into the computers memory. : 2) Open a blank 'notepad' file, and place your cursor at the top of the : blank page. From the 'edit' menu select 'paste'. This will paste a copy of : the letter into notepad so that you can add your name to the list. : 3) Save your new notepad file as a .txt file. If you want to do your : postings in different sittings, you'll always have this file to go back to. : 4) Use Netscape or Internet explorer and try searching for various : newsgroups (on-line : forums, message boards, chat sites, discussions.) : 5) Visit these message boards and post this article as a new message by : highlighting the text of this letter and selecting paste from the edit : menu. Fill in the Subject, this will be the header that everyone sees as : they scroll through the list of postings in a particular group, click the : post message button. You're done with your first one!. : So after thinking it over, and talking to a few people first, I thought : about trying it. I figured what have I got to lose except 6 stamps and : $6.00, right? Like most of us I was a little skeptical and a little worried : about the legal aspects of it, put I am a paralegal so I did some checking, : as well as, called the U.S. Post Office (1-800-725-2161) and they confirmed : that it is legal! Then I invested the $6.00. I am very glad I did.... : within 7 days, I started getting money in the mail! I was shocked! I : figured it would end soon, but the money just kept coming in. In my first : week, I made about $25.00. By the end of the second week I had made a : total : of over $1,000.00! In the third week I had over $10,000.00 and it's still : growing. This is now my fourth week and I have made a total of just over : $42,000.00 and it's still coming in rapidly. It's certainly worth $6.00, : and 6 stamps, I have spent more than that on the lottery!! : Let me tell you how this works and most importantly, why it works....also, : make sure you print a : copy of this article NOW, so you can get the information off of it as you : need it. : Congratulations...THAT'S IT! All you have to do is jump to different : newsgroups and post away : after you get the hang of it, and it will take about 30 seconds for : each newsgroup! : **REMEMBER, THE MORE NEWSGROUPS YOU POST IN, THE MORE : MONEY YOU : WILL MAKE!! BUT YOU HAVE TO POST A MINIMUM OF 200** That's : it! You will : begin receiving money from around the world within days! You may : eventually : want to rent a P.O. Box due to the large amount of mail you will receive. : If you wish to stay anonymous, you can invent a name to use, as long as the : postman will deliver it. **JUST MAKE SURE ALL THE ADDRESSES ARE : CORRECT.** Now the WHY part: Out of 200 postings, say I receive only 5 : replies (a very low example). So then I made $5.00 with my name at #6 on : the letter. Now, each of the 5 persons who just sent me $1.00 make the : MINIMUM 200 postings, each with my name at #5 and only 5 persons : respond to each of the original 5, that is another $25.00 for me, now those : 25 each make 200 MINIMUM posts with my name at #4 and only 5 replies : each, : I will bring in an additional : $125.00! Now, those 125 persons turn around and post the MINIMUM 200 : with : my name at #3 : and only receive 5 replies each, I will make an additional $626.00! OK, now : here is the fun part, : each of those 625 persons post a MINIMUM 200 letters with my name at #2 : and : they each only : receive 5 replies, that just made me $3,125.00!!! Those 3,125 persons will : all deliver this message to 200 newsgroups with my name at #1 and if still : 5 persons per 200 newsgroups react I will receive $15,625,00! With an : original investment of only $6.00! AMAZING! When your name is no : longer on : the list, you just take the latest posting in the newsgroups, and send out : another $6.00 to names on the list, putting your name at number 6 again. : And start posting again. The thing to remember is, do you realize that : thousands of people all over the world are joining the internet and reading : these articles everyday, JUST LIKE YOU are now!! So can you afford $6.00 : and see if it really works?? I think so... People have said, "what if the : plan is played out and no one sends you the money? So what! What are the : chances of that happening when there are tons of new honest users and new : honest people who are joining the internet and newsgroups everyday and : are willing to give it a try? Estimates are at 20,000 to 50,000 new users, : every day, with thousands of those joining the Internet.Besides if you don' t follow these simple instructions than chances are it won't work Remember, : play FAIRLY and HONESTLY and this will work : : : : : :Article: 19780
Make money faster than you could ever beleive! Here's how I started. I found this site while searching the web that told me what i'm about to tell you. you gonna think that this is a scam but tell me why you can't afford to take six dollars and turn it into thousands : The program goes as follows(follow these directions or it will not work): : 1) Take 6 separate envelopes and pieces of paper. On the paper, write : “Please put me on your mailing list and then place your name with : address.” : Now get 6 US $1.00 bills and place one in each of the envelopes with the : paper so wrapped around the bill so the bill can not be seen through the : envelope. This will prevent thievery. You should now have 6 sealed : envelopes, each with a piece of paper stating the above phrase, your name : and address, and a $1.00 bill. By providing a $1.00 in each envelope, you : are paying for their services. This is how it becomes legal. : 2) Mail the 6 envelopes to the following addresses: : : 1)Liam PO Box 90 Federal, NSW 2480 Australia : 2)Oliver PO Box 1032 Mullumbimby, NSW 2482 Australia : 3)Matt PO Box 260127 Boston, MA 02126 : 4)Paula 4763 N. Thorne Ave. Fresno, CA 93704 : 6) Durant Davis Jr. 2418 Rio Vista St. Chester Va. 23831 : 5)Durant Davis Jr. 2418 RioVista St. Chester VA 23831 : 6) Eric PO Box 536 Raymond NH 03077 : 3) Now take the #1 name off the list that you see above, move the other : names up (6 becomes 5, 5 becomes 4, etc...) and add YOUR Name as : number 6 on the list. : 4) Change anything you need in this letter you would like,but try to keep : it as close to original as possible. : 5) Now, post your amended article to at least 200 newsgroups. (I think : there are close to 24,000 groups) All you need is 200, but remember, the : more you post, and the more money you make! : -----HOW TO POST TO NEWSGROUPS------------ : 1) You do not need to re-type this entire letter to do your own posting. : Simply put your cursor at the beginning of this letter and drag your cursor : to the bottom of this document, then select 'copy' from the edit menu. This : will copy the entire letter into the computers memory. : 2) Open a blank 'notepad' file, and place your cursor at the top of the : blank page. From the 'edit' menu select 'paste'. This will paste a copy of : the letter into notepad so that you can add your name to the list. : 3) Save your new notepad file as a .txt file. If you want to do your : postings in different sittings, you'll always have this file to go back to. : 4) Use Netscape or Internet explorer and try searching for various : newsgroups (on-line : forums, message boards, chat sites, discussions.) : 5) Visit these message boards and post this article as a new message by : highlighting the text of this letter and selecting paste from the edit : menu. Fill in the Subject, this will be the header that everyone sees as : they scroll through the list of postings in a particular group, click the : post message button. You're done with your first one!. : So after thinking it over, and talking to a few people first, I thought : about trying it. I figured what have I got to lose except 6 stamps and : $6.00, right? Like most of us I was a little skeptical and a little worried : about the legal aspects of it, put I am a paralegal so I did some checking, : as well as, called the U.S. Post Office (1-800-725-2161) and they confirmed : that it is legal! Then I invested the $6.00. I am very glad I did.... : within 7 days, I started getting money in the mail! I was shocked! I : figured it would end soon, but the money just kept coming in. In my first : week, I made about $25.00. By the end of the second week I had made a : total : of over $1,000.00! In the third week I had over $10,000.00 and it's still : growing. This is now my fourth week and I have made a total of just over : $42,000.00 and it's still coming in rapidly. It's certainly worth $6.00, : and 6 stamps, I have spent more than that on the lottery!! : Let me tell you how this works and most importantly, why it works....also, : make sure you print a : copy of this article NOW, so you can get the information off of it as you : need it. : Congratulations...THAT'S IT! All you have to do is jump to different : newsgroups and post away : after you get the hang of it, and it will take about 30 seconds for : each newsgroup! : **REMEMBER, THE MORE NEWSGROUPS YOU POST IN, THE MORE : MONEY YOU : WILL MAKE!! BUT YOU HAVE TO POST A MINIMUM OF 200** That's : it! You will : begin receiving money from around the world within days! You may : eventually : want to rent a P.O. Box due to the large amount of mail you will receive. : If you wish to stay anonymous, you can invent a name to use, as long as the : postman will deliver it. **JUST MAKE SURE ALL THE ADDRESSES ARE : CORRECT.** Now the WHY part: Out of 200 postings, say I receive only 5 : replies (a very low example). So then I made $5.00 with my name at #6 on : the letter. Now, each of the 5 persons who just sent me $1.00 make the : MINIMUM 200 postings, each with my name at #5 and only 5 persons : respond to each of the original 5, that is another $25.00 for me, now those : 25 each make 200 MINIMUM posts with my name at #4 and only 5 replies : each, : I will bring in an additional : $125.00! Now, those 125 persons turn around and post the MINIMUM 200 : with : my name at #3 : and only receive 5 replies each, I will make an additional $626.00! OK, now : here is the fun part, : each of those 625 persons post a MINIMUM 200 letters with my name at #2 : and : they each only : receive 5 replies, that just made me $3,125.00!!! Those 3,125 persons will : all deliver this message to 200 newsgroups with my name at #1 and if still : 5 persons per 200 newsgroups react I will receive $15,625,00! With an : original investment of only $6.00! AMAZING! When your name is no : longer on : the list, you just take the latest posting in the newsgroups, and send out : another $6.00 to names on the list, putting your name at number 6 again. : And start posting again. The thing to remember is, do you realize that : thousands of people all over the world are joining the internet and reading : these articles everyday, JUST LIKE YOU are now!! So can you afford $6.00 : and see if it really works?? I think so... People have said, "what if the : plan is played out and no one sends you the money? So what! What are the : chances of that happening when there are tons of new honest users and new : honest people who are joining the internet and newsgroups everyday and : are willing to give it a try? Estimates are at 20,000 to 50,000 new users, : every day, with thousands of those joining the Internet.Besides if you don' t follow these simple instructions than chances are it won't work Remember, : play FAIRLY and HONESTLY and this will work : : : : : :Article: 19781
Are there any users of big parts that care to share a better way to assign pins? In the past, I handled pin assignments in the three ways listed below. These ways were not completely exclusive, in that they can all be back annotated to a text constraint file, which can be cleaned up and documented. I am not sure that any of these are a realistic plan for these large parts. I would like to hear any discussion as to better ideas of how to do a pinout. 1) Let the place and route tools assign the pins, and then back annotate to a text constraint file (.ucf). This has the advantage of a small amount of human effort, and produces an "ok" pinout from the point of the FPGA design. It isn't a real good pinout, as often the speed and density of the design can be noticeably improved by even a little amount of hand assignment. Also, it may not be very good from the board design point of view. Regardless of the past, this doesn't seem to be an option with the new large parts (Xilinx Virtex for example), as the place and route tools refuse to assign pins on designs with different Vcco or Vref supply voltages. 2) Type in a text constraint file. This has the advantage of allowing a complete documentation for all pins, including the pins I can't constrain, like power and ground pins, allows prohibiting of unused pins (another good thing), and allows for a knowledgeable user to produce a better pinout from both the FPGA and board point of view, with a fair amount of manual labor needed for a PQ240 package. This is still do-able, but I shudder at the task of producing such a document for a ball grid part with over 1000 pins, different signal types so need to check the banking rules, and the lack of a computer and/or human readable pin list with all the needed information to start with. (Perhaps the last complaint can be cured by some nice person telling me where such a pin list can be found?) But the user needs to try to put all the pins into the correct banks, and then run the translate, map and place and route tools to find out if it was a legal pinout. Repeat until good. 3) Use the Xilinx graphical floorplanner. This has the advantages of having some of the key information in graphical form and allows for a knowledgeable user to produce a better pinout with somewhat less effort than writing the text file, but the Xilinx floorplanner isn't documentable, can't be used with text constraint placement files and doesn't know about the banking rules and other special rules. The size of the first fault depends on how much you value correct documentation. The second fault is deadly for some, and no issue at all for others. The last of these faults is perhaps the worst, as it requires that the user try to put all the pins into the correct banks, and then run the translate, map and place and route tools to find out if it was a legal pinout. Repeat until good. -- Phil Hays 26.2 ns! Where in heck did that number come from? Maybe next time it would be a good idea for the designer to document how the designer produced the timing constraints! What an idea!Article: 19782
Jamil Khaib <Khatib@ieee.org> wrote in message news:387AD481.58C40A0C@ieee.org... > > Hi, > In the last few years the hardware resources for ASIC, FPGA, and CPLD > designers was improved in the manner of hw size, speed and fabrication > delay. And cost. > SW programmers now also have high speed processors, large memories > advanced compilers and visual tools. although all these resources are > available for programmers, but -as I see- they do not improve their sw > _in_the_same_ratio_as_the improvements_of_the_resources. For example all > new sw versions need larger memories and faster processors without the > increase of the functionality of the new version. This is because they > always think that they will have larger memory and faster processors and > they do not have time to optimize their code nor to calculate how much > resources they need as they did in the past. To a certain extent you are correct IMHO. If you are developing on a fast machine, then you simply do not know how your program performs on a slower machine. There is no incentive for a programmer to test/compile his code on a slower machine. After all when was the last time you heard of someone asking for a slower machine to do their work on? Software is compounded by the fact of it now being layered. Part of this is due to object oriented programming, but it imposes several layers of code that can not be optimized out. You can see this from compiling Charles Petzold's "hello" program in C. (Charles Petzold wrote the bible on Windows 3.x programming.) If you compile this in Visual C++ then you will see an increase in code size. It gets even more chaotic when you are allowed to dynamically link code (ie: DLLs.) What this does is slow down program performance, however compiles quicker (since you don't have to recompile the DLLs all the time.) Programmers are paid to develop their programs, not run them. Things would be different in my world, however... > Since the hardware technology becomes to offer to HW designers more than > what they need I think they will start doing the same as what SW > programmers doing now. I think you are correct, however for hardware it is somewhat different. You are limited to a more finite resource. If you need a bigger/faster chip, you typically have to shell out extra money. If you are developing software, the resources are virtually free. For example a 2x256 array cost just as much as a 2x32 array. In hardware I'd be more concerned about "behavioral" synthesis and object oriented VHDL. I believe there are more pressing problems than design and waste for hardware. Simulation speed and lack of models is more important to me. Again in my world if I was producing off the shelf components, I'd be damned sure to provide simulatable models with full timing, for free! Of course the models would be behavioral and not provide any information useful for some other component producer. > Do you think like me? Do you know how can we prevent this? > I think this can be prevented by following the Open Source and open > Hardware design concepts in the design. You can read more about this > idea in OpenIPCore Project at http://www.openip.org/oc Nice plug for the OpenIPCore Project. But I don't think your scare tactic works. Don't get me wrong I believe in a project such as yours. The more open things are, the better. But I think the OpenIPCore Project addresses other issues. Not efficiency in code/synthesis, but efficiency in development time. Everything should be plug and chug. Best Regards, Michael Vincze > Thanks > Jamil Khatib > OpenIP Organization http://www.openip.org > OpenIPCore Project http://www.openip.org/oc > OpenCores Porject http://www.opencores.orgArticle: 19783
Peter A Dudley wrote: > Hello Marc > > We are using a 3M/TexTool BGA Socket that works pretty well. It clamps > on the side above the centerline of the balls so that they can be > soldered down later. We're using the sockets for an ASIC not an FPGA but > its the same Amkor Super BGA package that the Virtex uses. > > We wanted to use the same board layout with the socket as we did with > the soldered down part as you are doing. We accomplished this even > though the socket is a through hole device by putting a via for each BGA > pad and opening up the via hole size a little. The pins on the socket > are very slim so we can solder the socket into the vias or we can solder > the BGA directly onto the BGA pads. > > In this configuration, I believe this 3M/TexTool BGA Socket should work > well above 100MHz. We're hoping to do above 500MHz because the ASIC is > GaAs. > > Good Luck > > Pete yum yum !!!! AsGa for the F-CPU project would be ... cool ! :-) WHYGEE ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ SHARCPAGE: http://www.mime.univ-paris8.fr/~whygee/sharcpage.htmlArticle: 19784
Peter A Dudley wrote: > Hello Marc > > We are using a 3M/TexTool BGA Socket that works pretty well. It clamps > on the side above the centerline of the balls so that they can be > soldered down later. We're using the sockets for an ASIC not an FPGA but > its the same Amkor Super BGA package that the Virtex uses. > > We wanted to use the same board layout with the socket as we did with > the soldered down part as you are doing. We accomplished this even > though the socket is a through hole device by putting a via for each BGA > pad and opening up the via hole size a little. The pins on the socket > are very slim so we can solder the socket into the vias or we can solder > the BGA directly onto the BGA pads. > > In this configuration, I believe this 3M/TexTool BGA Socket should work > well above 100MHz. We're hoping to do above 500MHz because the ASIC is > GaAs. > > Good Luck > > Pete yum yum !!!! GaAs for the F-CPU project would be ... cool ! :-) WHYGEE ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ SHARCPAGE: http://www.mime.univ-paris8.fr/~whygee/sharcpage.htmlArticle: 19785
Phil Hays wrote:
>
> Are there any users of big parts that care to share a better way to assign pins?
>
> In the past, I handled pin assignments in the three ways listed below.
>
> 1) Let the place and route tools assign the pins, and then back annotate to a
> text constraint file (.ucf).
> 2) Type in a text constraint file.
> 3) Use the Xilinx graphical floorplanner.
When using such a high number of pins you usually have some busses,
say 32 or 64 bits wide.
This imlies regularities for your design internally and externally (on
the PCB).
Therefore, I propose (and used) a modification of 2)
4) Generate a constraint file with a script (perl or whatever).
In our current design (a router) there are several busses but
the busses are connected to the core in "bit-neighbouring" fashion,
i.e. the ith bits of all busses are next to each other.
This reduces the usage of routing resources because the router
essentially
connects the corresponding bits via a crossbar.
Dependent what your design does (DSP, graphics, etc.)
this can be good way.
I think that 1) is not very good, because the optimization problem the
P&R-tools
have to solve is NP-complete and they therefore can only find some
not-worst
solution for suc large problems.
Furthermore, if you start designing the PCB when the digital design is
only known roughly the wrong problem is optimized.
To generate the input for the scriptsa correlation between the pin name
and the position of the PAD is needed. I got this by copy-and-paste from
the
data sheet text: the table with the pin names (for xc4kxv bg560) is in
exactly
the same sequence as the pads running (counter-?) clockwise around the
die.
Check this in the FPGA-Editor or floorplanner.
Another way to get this correspondence is the BSDL-file. Since the
BSCAN-chain
also runs once around the chip the sequence of the pads corresponds to
the
index of the according BSCAN-cell.
If you are interested in the perl-scripts, let me know.
Regards,
Andreas
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Andreas C. Doering
Medizinische Universitaet zu Luebeck
Institut fuer Technische Informatik
Email: doering@iti.mu-luebeck.de
Home: http://www.iti.mu-luebeck.de/~doering
quiz, papers, VHDL, music
"The fear of the LORD is the beginning of ... science" (Proverbs 1.7)
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Article: 19786<mcjy@my-deja.com> wrote in message news:85g98k$op6$1@nnrp1.deja.com... > Hi! [cut] > > Then we will need two month at least to > develop the block and then combine them > and carry out testing in simulation. > At this moment I still wonder how we > can test our design. I believe that the > prototyping board from Altera should be PCI card featuring two Virtex chips is under development. See http://www.opencores.org/cores/sfpga/. > very useful but if we want to do the > test in real circuit we will also need > to develop device driver. > Device drivers are not a problem (I have experience with PCI drivers for Linux and for NT). regards, DamjanArticle: 19787
Subject: Re: PCI/USB Date: Mon, 10 Jan 2000 14:05:28 From: " " <mcjy@my-deja.com> To: khatib@ieee.org CC: Hi! Thanks for your email. For the PCI core project, I would expect it take six months to get a basic model. (Depending on how many people. My estimation is 5 people) It sounds like a very long time but organising a project on the internet is very different from normal project. All of us have a full time job so we can only spend around 6 to 10 hours each week. ============================================== First we do not have to count anyone in the project to work as full time job or even as part time but as "spare time". Also we have no time restriction although it is good idea to have a fixed time schedule. =============================================== I guess we can use one month to develop the block diagrams and configuration of the project (as you know, we will need sometime for people to feedback) and several generation of the block diagrams would be developed in this month. Then we will focus on the detail spec of each block. We might need to think of some of the interaction between block in the early planning stage, but it really depends on situation. Then we will need two month at least to develop the block and then combine them and carry out testing in simulation. At this moment I still wonder how we can test our design. I believe that the prototyping board from Altera ============================== Or even we can do a board for us ================================= should be very useful but if we want to do the test in real circuit we will also need to develop device driver. ====================================== I agree the device driver should be an important part of our project. ====================================== About the PCI specification : I think we will work on PCI 2.2 64 bit extension is only one of the feature support in PCI 2.x, but it is ok to develop 32 bit core for PCI 2.2 (and I think it would be much easier to start with). ======================================================= Iagree the first block should be PCI2.2 32bit controller ========================================================= PCI specification said a device should be able to run from 66MHz to 0MHz. But the hardware performance requirment of 66MHz system maybe too high (difficult to prototype), so maybe we need to work on 33MHz design first. PCI-X is 133MHz PCI. I don't know if its specification is released yet. It is develop by Compag, and a few other PC companies. WIth current performance in FPGA, I guess it is almost impossible for us to prototype. Compact PCI is based of PCI 2.x and it support hot swap. It have extra requirment on the pins implementation (the pins must be tristate during the hot swap process). ============================== I have a good link about PCI core at http://www.tkt.cs.tut.fi/~havu/pci/models.html ==================================== Thanks Jamil Khatib OpenIP Organization http://www.openip.org OpenIPCore Project http://www.openip.org/oc OpenCores Project http://www.opencores.org I haven't look at USB yet. Write to you again later. Have a nice day. from Joe -- On 10 Jan 00 09:33:15 Asia/T jamil khatib wrote: >Hi Joe, >I am so sorry but my email does not send emails but it receives I have to >check it. >Anyhow I have some suggestions and I am going to send it to all PCI members, >news group and opencores mailing list > >Please if you want to replay my email is khatib@ieee.org >Thanks > >============================================================================= >Hi, >Before we start the work in the cores design we have to define few things. >We should get information about PCI and USB standards and design tips ( I >posted few links the last time and I still looking for more) I hope once we >proved that we are able to develop a good system may be we can get some >support from the PCI or USB groups and I'll try to contact them so as to get >the specs or test suits. >Documentation: text files is the most portable format or latex can be used to >write our design documentation instead of the MS stuff that are not portable. >The project should be divided into small subprojects for example we could have >: the main controller, the optional blocks, the arbiter and test suite. >Development platform: we need to make our platform as much as possible generic >and platform independent and it will be excellent if we port it to many >platforms. >Project schedule: ?. defining the spec and the subprojects. ?. defining the functionality of the main blocks. > ?. defining the blocks interfaces. ?. defining the archs, the states and timing of the blocks ?. selecting some tools and platforms ?. design implementation. ?. verification ?. testing on real system >could you please comment on the schedule >as a first step we have to understand the diff between the available bus >standards (e.g. PCI64/66MHz, PCI-X, CompactPCI- USB v1 & USB v2) and all >optional and required features of the busses. > >Thanks >Jamil Khatib >OpenIP Organization http://www.openip.org >OpenIPCore Project http://www.openip.org/oc >OpenCores Project http://www.opencores.org > > >____________________________________________________________________ >Get your own FREE, personal Netscape WebMail account today at http://webmail.netscape.com. > --== Sent via Deja.com http://www.deja.com/ ==-- Share what you know. Learn what you don't.Article: 19788
ian@five-d.com (Ian Kemmish) writes: > smaller programs do get fewer cache misses and TLB misses, and > depending on what you're running, this can make a perceptible > difference to performance. Also, I suspect smaller programs generally have fewer bugs. > Compact, fast and robust code is produced by Real Programmers, who > either work alone, or, as described in The Mythical Man Month, with > a co-pilot. Ideally, the Real Programmer develops on the slowest > machine in the building and the co-pilot tracks down bugs on the > fastest machine in the building:-) Of course, CFR code released by the RP as OS will get reused into other systems or application, and when the RP has stressed CF at the expense of R, there are a lot of testers who can help pinpoint the error. > Activities like Open Source, on the other hand, have a cast of > thousands, I think few OS projects have a thousand primary developers, not even the Linux kernel. Thousands eyeballing the code, and submitting small patches to the primary developers for integration, yes. > and a strong economic incentive Huh? What economic incentive? Even the packagers like Red Hat, which is where I perceived most of the economic perspective, are hurting pretty bad from their rushing out unfinished products - gnome 1.0 and glibc 2.0 for instance. > to ship many flakey new versions and fix them on a time and > materials basis later on. So you can get hold of unfinished code, so what? If you want things to *work*, use e.g. Debian's "stable" distribution, where everything has been tested pretty well. If you want to live on the cutting edge, use "unstable", and deal with it. -kzm -- If I haven't seen further, it is by standing in the footprints of giantsArticle: 19789
In article <387C16FC.9DD85B57@sprynet.com>, Phil Hays
<Spampostmaster@sprynet.com> writes
>Are there any users of big parts that care to share a better way to assign pins?
[...]
>1) Let the place and route tools assign the pins, and then back annotate to a
>text constraint file (.ucf).
[...]
>2) Type in a text constraint file.
[...]
>3) Use the Xilinx graphical floorplanner.
[...]
Not sure I'd really recommend this long-winded method, but it might be
useful.
A modification on 2):
Get the acrobat version of the data book and device-specific pin tables;
Extract the text of the table into the clipboard;
Paste said text into Word;
Convert the text back into a table;
Replace IO pins in the table with your signal names (preferably by
moving them from a list rather than by retyping them);
Global edit the columns into the syntax of the UCF file, including
adding the quotes and terminating semi-colon;
Remove the columns for all the packages except the one you are using;
Convert table to text, using a valid separator consistent with UCF
syntax;
Copy the text via the clipboard to the rest of the UCF file.
The intermediate table can be kept as a file so that if you need to
change package size, half the work of producing the new UCF file has
already been done. It is not actually even necessary to recompile --
just use the alternative pins of the new package.
Maybe better would be to let the P&R tools produce a pad listing in .pcf
format and then edit this into .ucf format and change the pin numbers.
Does anyone else understand why it is the .pcf format that the tools
produce an example of (in the .pad file) rather than the .ucf format?
Paul
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Article: 19790Hi everyone, I am a newbie for FPGA design ,and I has encountered the following problem in these days: The edif files exported from workview office7.53 cannot be accepted as the input of Xilinx foundation series2.1i,that is ,I launched the Schematic Editor ,clicked the "generate schematic from netlist..." item, and selected the edif file created by WVO753,eg,test.edn ,then I pressed OK,after some seconds,the Schematic Editor poped up a message box saying "pin *** not found",and exited. Would anyone help? Sent via Deja.com http://www.deja.com/ Before you buy.Article: 19791
Sure, after you correct problem with your provider/server/pages: Microsoft OLE DB Provider for ODBC Drivers error '80040e14' [Microsoft][ODBC SQL Server Driver][SQL Server]Line 1: Incorrect syntax near '='. /ViewProduct.asp, line 12 <puttqj@kasee.com> wrote in message news:Tdge4.9615$2x3.189890@newscontent-01.sprint.ca... > Hello all, > > if you are interested in hardware/software related questions or in the newest about computers and games, please visit my site. It*s free, by the way. > > http://www.geocities.com/linkalike/ > > Richard > > edffdiqvegxgnunxhjqjvfuztevmvpwkerwzurfhovmiygvylzelztwpwjsfovzodowfrrcbgzqv msjmjrvekyjcliqewnbhpdzjvgniqdgjdclrounfbqoqcliyvogsdvxfghugjpzpwhirosxgxsul hdohlwwcgdnkxrhywvsfvfhrwxwyediqotfusjgmlinnxjequgeuzsqucseystkjluyetxqchvth hftlpfeckuqerpnxqoiunoqbomicheyjbdjnuelschpzfxumzjkchozbdwpoypyjgbf >Article: 19792
There are different levels (or content types) that can be in an EDIF file. In the Workview Office edif interface menu, you should be selecting the EDIF Netlist writer tab, and in the Input box entering the name of the top page of your schematic hierarchy. The LEVEL box MUST be set to "xilinx" to generate a valid netlist for place and route. This netlist is brought into the Foundation tools using the Design manager, not the Project manager (although there may be a way to make that work too). The netlist you got from Viewlogic is specfied in the new-project popup as the input design file. The Foundation schematic program should not even be involved. What you are trying to do (and failing) is to bring the viewlogic netlist into the Foundation schematic package (made by Aldec), and this wont work, because the netlist does not have the info needed for Aldec to create a schematic view. On the bright side, this probably isn't some thing you should need to do, since you have a perfectly fine viewer for your schematics, ViewDraw. There is an import facility in the Aldec software to directly read the Viewlogic schematics, but every time I have tried it it crashed. It is also uni-directional, which makes its use problematic at best, even if it didnt crash. Although the core tools are identical, typically the Viewlogic tools are use with the Xilinx Alliance software, rather that the Foundation software. While the core software is the same, you are missing some tutorial documentation that covers the integration of the Viewlogic software with the core tools. You may be able to find this info at their web site. Philip In article <85hisi$ma1$1@nnrp1.deja.com>, <himalayas@my-deja.com> wrote: >Hi everyone, > I am a newbie for FPGA design ,and I has encountered the following >problem in these days: > The edif files exported from workview office7.53 cannot be accepted >as the input of Xilinx foundation series2.1i,that is ,I launched the >Schematic Editor ,clicked the "generate schematic from netlist..." item, >and selected the edif file created by WVO753,eg,test.edn ,then I pressed >OK,after some seconds,the Schematic Editor poped up a message box >saying "pin *** not found",and exited. > Would anyone help? > > >Sent via Deja.com http://www.deja.com/ >Before you buy.Article: 19793
Thanks Philip,
in fact the true problem I am facing is that ,
my design project(XC3000) is based on a design someone developed
years ago using workview office 4.3(under dos),now my box runs on
win98,and I can only open the design project using WVO7.53(just as
you have said,xilinx foundation 2.1i cannot import the project),and to
implementation the design I have to use Foundation 2.1i.During the
implemetation(yes,the target netlist file is exported from WVO753 with
the "level" property set to "Xilinx"),the software(flow engine) window
shows "Writing the design to ....ngo",then "Reading ....ngo",then
"Reading component libraries for design expansion...",then it
stops,after some minutes,it bursts out lots of error messages such as
"ERROR:NgdHelpers:312 - logical block "$1I1\$1I1\$1I1\$1I1" of type
"DFF" is unexpanded." ,
"ERROR:NgdHelpers:312 - logical block "$1I1\$1I1\$1I2\$1I17\$1I1" of
type "DFF" is unexpanded.",etc. of course the software exits.
It seems that Foundation 2.1i doesn't recognize the component libraries
(builtin,mx3000,x3000,xblox,xpal,xttl..)used in the design with WVO 4.3
under DOS?And how can I port the project onto the current EDA
environment?
Would anyone help me?:-)
Thanks again,
Jimmy
Sent via Deja.com http://www.deja.com/
Before you buy.
Article: 19794
In article <s7n6l7b9oj814@corp.supernews.com>,
Paul Butler <c_paul_butler@yahoo.com> wrote:
> I admit I'm used to living with bugs. EDA software is so buggy it's
> unbelievable - it's like a soap bubble always on the verge of collapse. My
> OS is comparitively stable and I hardly blink when I have to reboot. What
> else am I going to do? Grin and bear it.
I think this makes my case better than I possibly could.
I just checked around my net and while most systems were rebooted the weekend
of 1/1/00 for political reasons, there's a few who escaped. I haven't found
a UNIX box with an uptime below 10 days, and most are 50-150 days including
some that are 10 year old 386 boxes.
--
In hoc signo hack, Peter da Silva <peter@baileynm.com>
`-_-' Ar rug tú barróg ar do mhactíre inniu?
'U`
"I *am* $PHB" -- Skud.
Article: 19795Hi I have a system that uses a motorola hc11 micro Does enyone have a cpld or fpga built around a hc11 micro? cost?Article: 19796
"Ketil Z Malde" <ketil@ii.uib.no> wrote in message news:KETIL-vk1n1qb7ijq.fsf@eris.bgo.nera.no... > ian@five-d.com (Ian Kemmish) writes: > > > > Activities like Open Source, on the other hand, have a cast of > > thousands, > > I think few OS projects have a thousand primary developers, not even > the Linux kernel. Thousands eyeballing the code, and submitting small > patches to the primary developers for integration, yes. > > > and a strong economic incentive > > Huh? What economic incentive? Even the packagers like Red Hat, which > is where I perceived most of the economic perspective, are hurting > pretty bad from their rushing out unfinished products - gnome 1.0 and > glibc 2.0 for instance. I think you just answered your own question. If Redhat et al "are hurting pretty bad from their rushing out unfinished products," then they've got a real incentive to be more conservative and do it right next time, don't they? Well, maybe not. Microsoft and a lot of others do this all the time. > > to ship many flakey new versions and fix them on a time and > > materials basis later on. > > So you can get hold of unfinished code, so what? If you want things > to *work*, use e.g. Debian's "stable" distribution, where everything has > been tested pretty well. If you want to live on the cutting edge, use > "unstable", and deal with it. Like the first two versions of almost any MS product... LarryArticle: 19797
Hi to everybody Does somebody know a library of FPGA benchmarks used for research? I would be pleased if I got to know where to look for it. Thanks. MichaelArticle: 19798
Peter Alfke wrote: > Spartan2 was officially announced today, Jan 10. Getting the Virtex features, especially the 4K block RAMs, in a small, lower cost form is great. You can put a whole CPU and its memory inside a Spartan2. This will be very desirable for students and teachers of CPU design. Also for anyone who wants an easily programmed controller inside their FPGA design. So, Peter, when will Spartan2 be supported by the Student Edition software? The whole family, as with Spartan, right? Thanks! --Mike ButtsArticle: 19799
Different people, different views... I would use 4 individual clocks, and even use ripple counters, since they offer highest frequency resolution ( if needed ) and lowest power consuumption. Obviously, you have to accomodate the ripple delay when the counter stops, but that seems to be easily done in this design that looks like an event or frequency counter. I am a fan of global clocks and synchronous design, but that's not the best method for everything. Once a year I may disagree with Ray. Would become boring otherwise. Peter Alfke, Xilinx Applications ================================ Ray Andraka wrote: > The way to do this is to synchronize your independent inputs to the global > clock then use the synchronized inputs to enable counters working on the global > clock. You'll need a synchronizer circuit that generates a one clock wide > pulse for each 0 to 1 transition of the input clocks. Your local clock will > have to be at least as fast as the fastest incoming clock, and if you can do 2x > it makes the synchronizing a whole lot easier. The whole local counter doesn't > have to work at 2x, only the first few bits. For that matter, you could > prescale the input clocks using small counters and then synchronize the > prescaled clocks to the global clock. The prescalers should not be more than 2 > bits (in the same slice or CLB) so that you can run them with a clock that is > routed on the general routing rather than on a global clock net. If you are > careful about it, you can run the prescaler at a considerably higher frequency > than the global clock tree is capable of. I think Peter Alfke did an app note > to this effect for a 400MHz freq counter a couple years ago (before virtex). > > "Kresten Nørgaard" wrote: > > > Andy Peters skrev i meddelelsen <85d9lj$18d7$1@noao.edu>... > > >Kresten Nørgaard wrote in message <857h4h$96j$1@news.inet.tele.dk>... > > >>Hi group! > > >>I'm looking into a new design, consisting of 4 pcs. of 32-bit 100 MHz > > >>asynchronous counters. When stopped, the counters are emptied into a FIFO > > >>(common to all counters - 32 kbyte size total). The FIFO's will be read > > >>through an ordinary 8 MHz CPU interface. > > > > > >Question: why an async counter? Especially at 100 MHz? you'd better off > > >with a synchronous counter and some logic that generates count enables. > > > > Quite right, but I figured, that I would need 4 "global" clocks to make 4 > > counters, and not all FPGA families features so many distributed clocks. > > > > Another issue is power consumption. I reckoned, to lower the power > > dissipation, if a chose a ripple counter, but I might be wrong on that? > > > > Kresten > > -- > -Ray Andraka, P.E. > President, the Andraka Consulting Group, Inc. > 401/884-7930 Fax 401/884-7950 > email randraka@ids.net > http://users.ids.net/~randraka
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