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Hi all, I want to assess the feasibility of using an FPGA to manage multiple analog to digital converters (ADC) which provide input and output via Motorola SPI protocol. The SPI is a standard 3-wire synchronous serial protocol which can be emulated with code and bit-level instructions on single lines (SCLK, SDATA, GND and a chip select). I want to clock 32 ADC devices and capture their output at 20K samples per second (2 bytes per sample) simultaneously and continuously. My idea is to feed the output of each ADC into a pin on a FPGA and clock the data into internal registers which then line up the data in channel order (with some FIFO buffering) for parallel removal. Then, my embedded processor will receive an interrupt when it is time to unload the FIFO and will be able to pull the data out and place it in system memory. I can generate the sample and data clocks with the FPGA or externally. Is an FPGA the right tool for this job? If not, is anyone aware of a serial buffering device that will hold the data until the micro can get around to all 32 ADCs within the 50 uS between samples? TIA, Tim Kippen ____________________________________________________________ Tim Kippen Diversified Technical Systems, Inc. Senior Engineer 909 Electric Avenue, Suite 206B mailto:timk@dtsweb.com Seal Beach, CA 90740 http://www.dtsweb.com/ 562.493.0158 Fax: 562.493.3158Article: 20026
This is a periodic posting to let readers of these newsgroups know
about several online resources that may be relevant:
[1] Embedded Systems Glossary
http://www.netrino.com/Publications/Glossary/
[2] Embedded Systems Bibliography
http://www.netrino.com/Publications/Bibliography/
These are online versions of the Glossary and Bibliography from my
book, "Programming Embedded Systems in C and C++" (O'Reilly and
Associates, ISBN 1-56592-354-5).
It is my intention to make occasional changes and updates to these
online versions. I would very much like to hear your constructive
feedback. Please send your suggestions to <webmaster@netrino.com>.
I have put a lot of work into writing the book and creating and
maintaining these online resources. I hope that they will be a
valuable contribution to the community of embedded systems hard-
ware and software designers.
Sincerely,
Michael Barr
Article: 20027In article <3887666C.6E66F592@ids.net>, Ray Andraka <randraka@ids.net> wrote: <snip> >For DSP, you really need an effective carry chain architecture, and the ability >to efficiently realize delay queues. Altera's carry chain structure is crippled >for all but the most basic arithmetic functions, and delay queues chew up an >awful lot of resource. > A slightly off-topic question: Are there any sources to find out more about how to access the carry chain in the Xilinx FPGA's? I haven't found much on their site or in their documentation. Tyrone -- -------------- thompson@eecis.udel.edu University of Delaware Tyrone Thompson EE Graduate StudentArticle: 20028
Yes. There are bit of a design sprinkled through some of the xilinx appnotes. Look up under memory functions. IIRC, there was one on large fifos using an FPGA and DRAM which touched on the controller issue. I'm pretty sure there are others. Thomas Sitt wrote: > Hello, > I want to use standard sdram ( 64 MByte ) with FPGA. > Is it possible and where are examples to find ? > > Greetings > Thomas Sitt -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 20029
You need to be more specific. PYD wrote: > Does anyone knows how to make polynomial calculation on FPGA ? > > Do you have any experience or do you know an homepage which is talking about > ??? > > Best regards, -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 20030
In the older software, you had to instantiate the pieces and put RLOCs on it. See the libraries guide for the details. The newest PAR software supposedly will construct the carry chains correctly if there are either no RLOCs or everything is RLOCed, which helps out the synthesis crowd. If you are using synthesis, it will basically infer the carry chain for basic mathematic and counter functions. sometimes you may have to be creative about how you state the function to get it to see the arithmetic through extra muxing functions or whatnot. I've only really had problems with it not recognizing the arithmetic when I manipulate individual bits of the input. Tyrone Thompson wrote: > In article <3887666C.6E66F592@ids.net>, Ray Andraka <randraka@ids.net> wrote: > <snip> > >For DSP, you really need an effective carry chain architecture, and the ability > >to efficiently realize delay queues. Altera's carry chain structure is crippled > >for all but the most basic arithmetic functions, and delay queues chew up an > >awful lot of resource. > > > > A slightly off-topic question: > > Are there any sources to find out more about how to access the carry chain in > the Xilinx FPGA's? I haven't found much on their site or in their documentation. > > Tyrone > > -- > -------------- > thompson@eecis.udel.edu University of Delaware > Tyrone Thompson EE Graduate Student Tyrone Thompson wrote: > In article <3887666C.6E66F592@ids.net>, Ray Andraka <randraka@ids.net> wrote: > <snip> > >For DSP, you really need an effective carry chain architecture, and the ability > >to efficiently realize delay queues. Altera's carry chain structure is crippled > >for all but the most basic arithmetic functions, and delay queues chew up an > >awful lot of resource. > > > > A slightly off-topic question: > > Are there any sources to find out more about how to access the carry chain in > the Xilinx FPGA's? I haven't found much on their site or in their documentation. > > Tyrone > > -- > -------------- > thompson@eecis.udel.edu University of Delaware > Tyrone Thompson EE Graduate Student -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 20031
An FPGA should work just fine for that. You might even consider sharing the shift register between multiple ADCs to save some area. If the SCLK limits you in that respect, then you can bring in the data from all 32 at a convienent rate, storing them serially in xilinx CLB RAM or SRL16's at only a LUT or two per channel, then unload/load the serial memories inside the FPGA to a single serial-parallel shift register to save on the number of CLBs needed to implement it. Tim Kippen wrote: > Hi all, > > I want to assess the feasibility of using an FPGA to manage multiple analog > to digital converters (ADC) which provide input and output via Motorola SPI > protocol. The SPI is a standard 3-wire synchronous serial protocol which > can be emulated with code and bit-level instructions on single lines (SCLK, > SDATA, GND and a chip select). I want to clock 32 ADC devices and capture > their output at 20K samples per second (2 bytes per sample) simultaneously > and continuously. My idea is to feed the output of each ADC into a pin on a > FPGA and clock the data into internal registers which then line up the data > in channel order (with some FIFO buffering) for parallel removal. Then, my > embedded processor will receive an interrupt when it is time to unload the > FIFO and will be able to pull the data out and place it in system memory. I > can generate the sample and data clocks with the FPGA or externally. > > Is an FPGA the right tool for this job? > > If not, is anyone aware of a serial buffering device that will hold the data > until the micro can get around to all 32 ADCs within the 50 uS between > samples? > > TIA, > > Tim Kippen > > ____________________________________________________________ > Tim Kippen Diversified Technical Systems, Inc. > Senior Engineer 909 Electric Avenue, Suite 206B > mailto:timk@dtsweb.com Seal Beach, CA 90740 > http://www.dtsweb.com/ 562.493.0158 Fax: 562.493.3158 -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 20032
Tyrone Thompson wrote: > In article <3887666C.6E66F592@ids.net>, Ray Andraka <randraka@ids.net> wrote: > <snip> > > Altera's carry chain structure is crippled > >for all but the most basic arithmetic functions, and delay queues chew up an > >awful lot of resource. > > > > A slightly off-topic question: > > Are there any sources to find out more about how to access the carry chain in > the Xilinx FPGA's? I haven't found much on their site or in their documentation. > Go to xilinx.com, click on "search" ( in the top bar ), enter carry, and you get a few hundred hits, the first 50 of which are all sorts of detailed descriptions of the Xilinx carry structures, their capabilities and limitations. Maybe more than you ever wanted to know.. :-) Peter Alfke, Xilinx ApplicationsArticle: 20033
In article <jYKKOL3KHdqtzU8E0YzfNDf8DPD0@4ax.com>,
John Larkin <jjlarkin@highlandSnipSniptechnology.com> wrote:
>Interestingly, on one board I put a bunch of Hirose coax connector
>pads so I could TDR the power planes and the little 3.3v island. As
>far as I could tell, a plane behaves like an ideal capacitor of the
>expected value. Adding bypass caps - anywhere - then makes it look
>like a *bigger* ideal capacitor. If your power and ground planes are
>close, all you need is a few scattered bypass caps, but nothing like
>one per chip. Some brave souls build BIG digital boards with no bypass
>caps at all!
This is probably fine. There is a case where large capacitance is actually
needed: analog boards where you care about low frequencies. In this case
the traditional 10uF - 15uF electrolytic bypass capacitor where the power
enters the board is critical.
If you have a high speed signal which crosses planes which are not close,
insert a ground return via near the crossing via. Of course your
power/ground planes should be close :-)
--
/* jhallen@world.std.com (192.74.137.5) */ /* Joseph H. Allen */
int a[1817];main(z,p,q,r){for(p=80;q+p-80;p-=2*a[p])for(z=9;z--;)q=3&(r=time(0)
+r*57)/7,q=q?q-1?q-2?1-p%79?-1:0:p%79-77?1:0:p<1659?79:0:p>158?-79:0,q?!a[p+q*2
]?a[p+=a[p+=q]=q]=q:0:0;for(;q++-1817;)printf(q%79?"%c":"%c\n"," #"[!a[q-1]]);}
Article: 20034
In article <5Jah4.5117$uI1.73580@typhoon2.kc.rr.com>,
Matt Billenstein <mbillens@one.net> wrote:
>All,
>
>I've not seen (or cannot find) an appropriate appnote or reference design
>for laying down these fine pitch BGA parts (say FG256 for example) There
>doesn't seem to be a lot of room between BGA solder pads (0.400 millimeters
>nominal) to route out or drop vias of any substantial size... I can route
>out two rows around the whole part with very little trouble, but I think I
>have to dogbone anything further inside the part. How are you folks here
>doing it?
Lots of planes :-)
I'm guessing that you can half merge the via's anular ring with the BGA pad-
just as long as solder mask fully surrounds the via's hole. I haven't done
my first BGA card yet, so I'm just starting to think about this.
--
/* jhallen@world.std.com (192.74.137.5) */ /* Joseph H. Allen */
int a[1817];main(z,p,q,r){for(p=80;q+p-80;p-=2*a[p])for(z=9;z--;)q=3&(r=time(0)
+r*57)/7,q=q?q-1?q-2?1-p%79?-1:0:p%79-77?1:0:p<1659?79:0:p>158?-79:0,q?!a[p+q*2
]?a[p+=a[p+=q]=q]=q:0:0;for(;q++-1817;)printf(q%79?"%c":"%c\n"," #"[!a[q-1]]);}
Article: 20035Cheers for any help.Article: 20036
On Thu, 1 Jan 1970 02:59:59, John Larkin <jjlarkin@highlandSnipSniptechnology.com> wrote: > > Keith, > > Hirose makes some itty bitty surface-mount coax connectors (the H.FL > series) you can buy from Digikey. We often plop a few here and there > on multilayer boards. The three gnd pins go to vias to the nearest > ground plane, and the center pin goes through a via to whatever we're > interested in: a test trace, a power plane, a power island, stuff like > that. We then solder the connectors onto a bare board, TDR things, and > see how close our theory came to real life. We often find that the PCB > fab houses aren't too religious about the dielectric stackups! It's > good to know this before you populate a mess of boards. I looked at DigiKey today. What a horrible site. I did finally find what your were talking about. I then went to Hirose to get some real information. What a mess of a site they have. It took forever to get any meaningful information. They may have great product but they can't sell it! > The next time you buy boards, ask for a 'solder sample'. All board > houses make 10-50% extras to make up for yield problems, and don't > usually mind giving rejects or extras away. They'll sometimes punch a > hole on it to ensure it's not usable! I'll ask. I don't care if I have to buy a good one. The board manufacturer is doing the engineering, fab, and assembly. I don't think they'd be worried about me getting ahold a "reject" whether it is or not. > Keep in mind that a 30 ps TDR magnifies trace discontinuities greatly > in most cases. You have to mentally (or mathematically!) lowpass > filter the TDR display to make it consistant with your actual > risetimes. Sure. Been there. > We usually use four ceramic caps per Xilinx chip, near the corners of > a 3.3 volt island. Seems to work fine. On Virtex/VirtexE? That's not what Xilinx is saying. That's not my experience either. Our product is a BGA and we're having all sorts of problems supplying the power to the part (note that this is on testers with their inherent problems, so far). > > 460 is a LOT of caps! Not really. I have lots more space for them. ;-) In fact I'm using *many* 470uF SMT caps in parallel instead of PTH bulk capacitors. Parallel is an advantage. Putting them on the back-side is an advantage. I gotta buy the things in reels anyway so it doesn't matter much if I need one or use a hundred. Remember, on this particular project the cost of a reel of capacitors means next to nothing. The FPGAs alone are $1300 each and the *socket* for the "golden" chip is about $3000 (per copy). Add $50K for ten populated boards (PD thru assembly), a few thousand for ancillary parts, and my time (and the cost of the failure "using" that other FPGA), you find that a liberal dose of capacitors is chump-change. Again, there is no intention of sending this widget to production. If there were, I wouldn't be a one-man-band and the boards would be thouroughly modeled. This doesn't change the fact that I want to understand what's going on and I do appreciate your comments. In light of this 460 caps isn't a lot. In fact after looking over the design agin, I see where some more might be needed (I get another pass ;-). ---- KeithArticle: 20037
That is a very easy solution. You can also use ispLSI2032's which are 32 macrocell devices (3x the size of 22V10). It's the same cable and software. The 2032 gives you do an address decoder easily. The cable and software are very user friendly. Synario schematic capture and ABEL HDL. The 6 month license is renewable at no charge. Mike Roberts "Shawn D'Alimonte" <sdalimon@www.ee.ryerson.ca> wrote in message news:86gmtj$bvg$1@ns2.ryerson.ca... > I am working on my final project in EE which involves improving a > single board computer used in several classes. Students usually build > their own board (from a kit) for one class and many use the board in > their projects. I am hoping to replace the GAL16V8 used for address > decoding with something easier to program. > > So far all I have found is Lattice's ispGAL22V10. I found a schematic > of the programmer cable and can get the software with a free 6 month > license. > > I was wondering if anyone has any suggestions. It should easily > replace a GAL device. Small size, low cost and ease of soldering (DIP > or PLCC package) are important. The programmer must be simple and > easy to build and software should be available for free. > > Thanks in advance for any suggestions. > > -- > Shawn D'Alimonte - sdalimon@ee.ryerson.ca > "Faster processors are nice, but they are not truly revolutionary. And > neither are colors." - Jim Collas, Amiga Inc.Article: 20038
The read and write are pretty easy, but I had to use a lot of states to properly initialize the darn things. The fancy stuff like row/bank activation and tagging will eat up a lot of gates, The row address comparators usually take three levels of logic, slowing the system. I did one in an Altera Max7128A-6, it runs to 75MHZ (pushing it) I did the DQM decode with an external GAL22lv10-4 part On Mon, 24 Jan 2000 19:56:25 GMT, Ray Andraka <randraka@ids.net> wrote: >Yes. > >There are bit of a design sprinkled through some of the xilinx >appnotes. Look up under memory functions. IIRC, there was one on large >fifos using an FPGA and DRAM which touched on the controller issue. I'm >pretty sure there are others. > >Thomas Sitt wrote: > >> Hello, >> I want to use standard sdram ( 64 MByte ) with FPGA. >> Is it possible and where are examples to find ? >> >> Greetings >> Thomas SittArticle: 20039
This is a multi-part message in MIME format. --------------31FA5B6B8599ADEFB01E26C7 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit i was involved in designing the sram fpga architecture . i am almost in the final stage of development . i have designed the chip using vhdl , in that how can i decribe the global clock distribution . there should only one clock input to all the logic cells in the sram fpga . how this can be achieved by vhdl or in general i need help in this thanks in advance kamal --------------31FA5B6B8599ADEFB01E26C7 Content-Type: text/x-vcard; charset=us-ascii; name="raja.vcf" Content-Transfer-Encoding: 7bit Content-Description: Card for raja Content-Disposition: attachment; filename="raja.vcf" begin:vcard n:kamalanathan;Raja tel;home:07 38761962 tel;work:07 33658849 x-mozilla-html:FALSE adr:;;;;;; version:2.1 email;internet:raja@elec.uq.edu.au fn:Raja kamalanathan end:vcard --------------31FA5B6B8599ADEFB01E26C7--Article: 20040
On 25 Jan 2000 00:47:04 GMT, krw@attglobal.net (Keith R. Williams) wrote: <stuff snipped> >On Virtex/VirtexE? That's not what Xilinx is saying. That's not >my experience either. Our product is a BGA and we're having all >sorts of problems supplying the power to the part (note that this >is on testers with their inherent problems, so far). >> >> 460 is a LOT of caps! > >Not really. I have lots more space for them. ;-) In fact I'm >using *many* 470uF SMT caps in parallel instead of PTH bulk >capacitors. Parallel is an advantage. Putting them on the >back-side is an advantage. I gotta buy the things in reels >anyway so it doesn't matter much if I need one or use a hundred. <more stuff snipped> One of the best how-many-and-what-kind-of-bypass-capacitors-do-I-need articles I've seen is by some signal integrity engineers at Sun, titled, "Power Distribution System Design Methodology and Capacitor Selection for Modern CMOS Technology." You can find it online at: http://www.qsl.net/wb6tpu/si_documents/docs.html One comment about capacitor placement: if you have a 500ps risetime (as more than a few modern devices do) and the bypass capacitor is more than an inch or so away from the device's power pins, that cap isn't helping source current for that edge, except to replenish plane charge after the fact. Placement does matter, at least for the smaller, high-frequency bypass caps (the larger, lower-frequency bulk capacitors are another matter). The plane-to-plane capacitance is nice, being low-inductance, but there isn't much of it, particularly if you have lots of stuff switching. CMOS-based designs can have rather astonishing dI/dt requirements; I'd think a long time before trying to build a board without high-frequency bypass caps. Take care, Bob Perlman ----------------------------------------------------- Bob Perlman Cambrian Design Works Digital Design, Signal Integrity http://www.best.com/~bobperl/cdw.htm Send e-mail replies to best<dot>com, username bobperl -----------------------------------------------------Article: 20041
On Sun, 25 Jan 3900 01:57:53, bobperl@best_no_spam_thanks.com (Bob Perlman) wrote: > On 25 Jan 2000 00:47:04 GMT, krw@attglobal.net (Keith R. Williams) > wrote: > > <stuff snipped> > >On Virtex/VirtexE? That's not what Xilinx is saying. That's not > >my experience either. Our product is a BGA and we're having all > >sorts of problems supplying the power to the part (note that this > >is on testers with their inherent problems, so far). > >> > >> 460 is a LOT of caps! > > > >Not really. I have lots more space for them. ;-) In fact I'm > >using *many* 470uF SMT caps in parallel instead of PTH bulk > >capacitors. Parallel is an advantage. Putting them on the > >back-side is an advantage. I gotta buy the things in reels > >anyway so it doesn't matter much if I need one or use a hundred. > <more stuff snipped> > > One of the best how-many-and-what-kind-of-bypass-capacitors-do-I-need > articles I've seen is by some signal integrity engineers at Sun, > titled, "Power Distribution System Design Methodology and Capacitor > Selection for Modern CMOS Technology." You can find it online at: > > http://www.qsl.net/wb6tpu/si_documents/docs.html Thanks. That'll be on tomorrow's reading list. > One comment about capacitor placement: if you have a 500ps risetime > (as more than a few modern devices do) and the bypass capacitor is > more than an inch or so away from the device's power pins, that cap > isn't helping source current for that edge, except to replenish plane > charge after the fact. Placement does matter, at least for the > smaller, high-frequency bypass caps (the larger, lower-frequency bulk > capacitors are another matter). The plane-to-plane capacitance is > nice, being low-inductance, but there isn't much of it, particularly > if you have lots of stuff switching. CMOS-based designs can have > rather astonishing dI/dt requirements; I'd think a long time before > trying to build a board without high-frequency bypass caps. I couldn't agree more. That's why I was astonished to hear of people "going naked". I'm not a newbie (I've been an engineer for 26 years) to high speed design, and I've always treated decoupling with respect. I can remember a wire-wrapped proto board I did years ago. The design had the VCC and GND "nailed" down to the planes with little spring clips (anyone remember Augat WW boards ;-). with 8.2uF and .1uF caps at each VCC. Well, the technician didn't see any puropose in these clips that could almost be seen (and one PITA to work with), so he decided to daisy-chain all VCCs and grounds. What a trip figuring that out! He damned near wore that board (pointy side t'wards the head), which represented a *months* work (IIRC 4000 wires- all hand done). Well, we all have to learn (some electronics, some temper ;-). The board in question here *should* be pretty good (he prays every night). We'll see in a week or so. Like I said above, I tried to follow Xilinx' guidelines. I have 10nF or .1uF at every pair of VCCint and VCCO pins (can't get them closer than that given three pairs-each at 1mm spacing per octant on a FG680). These caps are within .1" of the balls on the back side, inside the I/O ring. I also have a pair of 15uF at each octant right behind the 10nF caps. Over to the side (maybe an inch away) is a 470uF cap for each voltage for some bulk. Has anyone else noticed that tantalum caps are impossible to find?? ---- KeithArticle: 20042
Tim, your application looks like a project I was involved in about two years ago. The board we designed had 32 ADCs and ran at 100kS/s (if I remember correctly) via SPI. All 32 channels were handled by an Altera FLEX10K which also included control logic and memory interfacing. So it definitely can be done. I'd say an FPGA is an ideal solution for your problem. If you are interested I can give you a contact where you might be able to obtain (example) AHDL source code. Ulrich Stauss Engineering Manager Hills Industries Limited Email: ustauss@hills.com.au Ray Andraka <randraka@ids.net> wrote in message news:388CB20D.407C36D@ids.net... > An FPGA should work just fine for that. You might even consider sharing the > shift register between multiple ADCs to save some area. If the SCLK limits you > in that respect, then you can bring in the data from all 32 at a convienent > rate, storing them serially in xilinx CLB RAM or SRL16's at only a LUT or two > per channel, then unload/load the serial memories inside the FPGA to a single > serial-parallel shift register to save on the number of CLBs needed to implement > it. > > Tim Kippen wrote: > > > Hi all, > > > > I want to assess the feasibility of using an FPGA to manage multiple analog > > to digital converters (ADC) which provide input and output via Motorola SPI > > protocol. The SPI is a standard 3-wire synchronous serial protocol which > > can be emulated with code and bit-level instructions on single lines (SCLK, > > SDATA, GND and a chip select). I want to clock 32 ADC devices and capture > > their output at 20K samples per second (2 bytes per sample) simultaneously > > and continuously. My idea is to feed the output of each ADC into a pin on a > > FPGA and clock the data into internal registers which then line up the data > > in channel order (with some FIFO buffering) for parallel removal. Then, my > > embedded processor will receive an interrupt when it is time to unload the > > FIFO and will be able to pull the data out and place it in system memory. I > > can generate the sample and data clocks with the FPGA or externally. > > > > Is an FPGA the right tool for this job? > > > > If not, is anyone aware of a serial buffering device that will hold the data > > until the micro can get around to all 32 ADCs within the 50 uS between > > samples? > > > > TIA, > > > > Tim Kippen > > > > ____________________________________________________________ > > Tim Kippen Diversified Technical Systems, Inc. > > Senior Engineer 909 Electric Avenue, Suite 206B > > mailto:timk@dtsweb.com Seal Beach, CA 90740 > > http://www.dtsweb.com/ 562.493.0158 Fax: 562.493.3158 > > -- > -Ray Andraka, P.E. > President, the Andraka Consulting Group, Inc. > 401/884-7930 Fax 401/884-7950 > email randraka@ids.net > http://users.ids.net/~randraka > >Article: 20043
Phil Endecott wrote:
>
> Andreas Doering wrote:
> > I am interested in the implementation of indexing memory in hardware
> > (custom or FPGA).
> > The problem is the following:
> > say we have inputs a0,a1
> > and a0 (a 5-bit-vector) can have 19 different values and
> > a1 (also 5-bit) can have 21 different values.
> > We need to address a memory with binary addresses.
> > Hence we could concatenate both vectors and needed 1K memory words.
>
Thank you to all who participated in the problem.
I might have been misunderstood:
I am interested in the general problem not just in the example given.
The apporach of Andreas Gieriet is an intersting starting point,
but as he points it out only works in some cases.
The pragmatic approach with a CAM or "let the synthesis" do might
be valuable but does not reveal much for the general case.
A CAM means that I need A0*A1*B*(log A0 + log A1) many memeory cells
even in a CAM that allows don't cares.
I had expected that there is something already known, but could not find
anything in the bibliography data bases I know.
Again thanks to all.
Andreas
--
---------------------------------------------------------------
Andreas C. Doering
Medizinische Universitaet zu Luebeck
Institut fuer Technische Informatik
Email: doering@iti.mu-luebeck.de
Home: http://www.iti.mu-luebeck.de/~doering
quiz, papers, VHDL, music
"The fear of the LORD is the beginning of ... science" (Proverbs 1.7)
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Article: 20044My first experience with HDL or programmed logic design was to modify a test pattern generator implemented in an Altera 10K device. The original was written in AHDL, and after picking up that everything happens concurrently and the syntax of the AHDL commands it was pretty easy. Then came using the Altera tolls to compile, place and route and produce a ROM file for downloading the FPGA it self. This part was very intuitive and I had no trouble at all with it. Later I used several different types of smaller Altera parts to do some simple test fixture type devices and thought that I would never need to learn another vendor's tools. When I first looked into using the Xilinx parts was when we began development on a PCI board in a system that we knew would be bound by PCI I/O before it was done. I started looking for a 64 bit / 66 MHz PCI controller but all the ASICs available at the time were targeted to interfacing to a particular processor, either MIPS or 68K. That is when I decided to look into getting a PCI core to drop into the FPGA that I knew would be on the board gluing the PCI controller to the rest of the logic. That was when I discovered the Virtex line (I had heard of them, but never really bothered to look at the spec because I didn't need a device that big.) They are far superior to the current Altera devices in many ways (Altera still holds some niches). At the time I looked at the tools, which we had at my company but that I had never played with. I thought at the time that they were much less intuitive and harder to use, but I found that I picked it up easily. I also found them to be much more powerful than Max+IIplus (haven't tried quartus yet, only installed it when the update came). Now that I have more experience and some rather large, high speed FPGA design experience, I really prefer the Xilinx tools, and I still think they have the best million gate size FPGAs on the market. Any way, to finally answer your question, I think you should go for Xilinx for sure. Some of the other vendors also have devices that work well in certain applications, but overall, for SRAM based FPGAs, Xilinx rules! Support is good too. Peter A. and other folk in the know even take the time to talk to students attending the Xilinx courses (in SJ) at the lunch break. It was a valuable extra in the course, I learned almost as much at lunch as in class. Haven't taken any Altera courses, they offered us some free ones but we had to take them beginning at the newbie level. My schedule doesn't permit that waste of time, so I couldn't take that advantage. Ben Sanchez Nancy Montanez wrote: > > This is very true. I was involved in a summer long project to build a > CPU using digital design software. I was told that I had to use Altera > because a) it was very economical and b) the professors did not know > of any other option. Now, after working with the software for a year, > I'm very eager to try something new. Should I go for Xilinx? Or does > anyone have any other options? > > - Nancy Montanez > nmontane@cs.usfca.edu > Ray Andraka wrote: > > > I think a large part of it may be 1) what users are used to, and 2) > > percieved > > ease of use. Altera has a very aggressive university program which > > puts the > > altera devices and tools into student's hands at virtually no cost. > > Xilinx > > isn't nearly so forthcoming on that front. Altera's tools are more > > 'push the > > big green button and let it go' than xilinx, which is fine when you > > are doing > > designs that don't effectively use the FPGA's capability. Altera > > tools lack the > > controllability needed to tweak the design compilation, which may > > make the tool > > less onerous to learn but more frustrating for the accomplished > > user. > > > >Article: 20045
A bit off topic but has anyone tried a Double Data Rate (DDR) SDRAM controller in an an FPGA ? There's a Xilinx Virtex apps note on this topic but I haven't really studied it yet.Article: 20046
Please advise: Can Atmel AT17c256 be used in place of Xilinx XC17s20 config PROM? Regards Peter FennArticle: 20047
Dies ist eine mehrteilige Nachricht im MIME-Format.
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Hi,
I am looking for publications and other informations about the following
quesitions:
1. The concept of a DSP-System with a FPGA as coprozessor - what
functions are normally realized in the FPGA?
2. What kind of methods exists to split up algorithms on a System with a
FPGA- and a DSP-Device ? The aim is to get a shorter runtime as in the
DSP-only case and to become more flexibility as in the FPGA-only case.
Additional information: The algorithms come from digital image
processing.
3. What is the best (if possible) or a good hardware-structure in a FPGA
& DSP-System, especially then BUS- and RAM-conception?
Many thanks and best regards,
Gunter Foettinger
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Article: 20048Hello, I`m a newbie to the Xilinx Foundation Series. I have 5 VHDL files (describing 5 components) and I want to link these in a top file, but graphical! How do I make symbols out of my VHDL code? Thanx Steven.Article: 20049
I have not used Foundation for about a year, but I seem to remember that in the VHDL Editor/Compiler Window there is an option to create a Macro. The Macro option will generate a symbol in your project directory that can be used in the schematic editor. Good luck, -- Shane Tow Nortel Networks stow@nortelnetworks.com Steven Sanders wrote: > > Hello, > > I`m a newbie to the Xilinx Foundation Series. I have 5 VHDL files > (describing 5 components) > and I want to link these in a top file, but graphical! How do I make > symbols out of my VHDL code? > > Thanx > > Steven.
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