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Xilinx has an app note on line on implementing a plug and play ISA interface. It has all the details you'll need. Robert Morse wrote: > Hi, > I am looking for a ISA PnP core, for an FPGA. We are currently > using a commercial ISA PnP chip but they require another EPLD to > interface into fix up the signals so we can use them. So any > news on a ISA PnP core, either commercial or Free. > > Thanks in advance. > > Robert Morse > > -- > ++++++++++++++++++++++++++++++++++++++++ > + Robert Morse + > + rmorse@rmsun.linxnet.com + > ++++++++++++++++++++++++++++++++++++++++ -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 17251
Hi, I have used OSC4 of XC40003E in Verilog. Verilog simulation library of OSC4 is in $XILINX/verilog/src/UNI4000E/OSC4.v. I think VHDL version will be $XILINX/vhdl/src/unisims/unisim_VITAL.vhd.Article: 17252
This is a periodic posting to let readers of these newsgroups know
about several online resources that may be relevant:
[1] Embedded Systems Glossary
http://www.netrino.com/Publications/Glossary/
[2] Embedded Systems Bibliography
http://www.netrino.com/Publications/Bibliography/
These are online versions of the Glossary and Bibliography from my
book, "Programming Embedded Systems in C and C++" (O'Reilly and
Associates, ISBN 1-56592-354-5).
It is my intention to make occasional changes and updates to these
online versions. I would very much like to hear your constructive
feedback. Please send your suggestions to <webmaster@netrino.com>.
I have put a lot of work into writing the book and creating and
maintaining these online resources. I hope that they will be a
valuable contribution to the community of embedded systems hard-
ware and software designers.
Sincerely,
Michael Barr
Article: 17253pw@panix.com (Paul Wallich) writes: >In article <K1Mg3.12$4H4.1291@paloalto-snr1.gtei.net>, "Jan Gray" ><jsgray@acm.org.nospam> wrote: >>Paul Wallich wrote in message ... >>>It's a little amusing to note that the emulator, the thread executing the >>user's >>>program, was actually the lowest-priority thread. (Also amusing to >>>think that Alto micromachine was something like 1600 gates -- you >>>could build dozens of them on a single FPGA). >> >>Perhaps, but if you count the register files and constant and microcode >>memory it was much larger than 1600 gates. >But should you? One of the things that's pretty clear is that the >micromachine remained relatively constant while the register >files and control stores got mucked around. Given the bandwidth >requirements (60 MHz by essentially 3 x 32 bits) you could put >everything offchip easily enough. And at the time (MSI) the >partitioning seemed clear... >(I'm only sort of kidding -- the question of what the CPU is goes >right along with the question of what language it "directly >executes".) Actually, if you're willing to take the Alto one step higher and build a wilflower-class D-machine with the MESA instruction set, this might have the ideal instruction set for a massively parallel FPGA processor. The code density of this machine was something like 2-3 byte-opcodes per high-level language statement. In other words, it was probably the code density champ of all time. That's why Xerox kept it secret and shot itself in the foot. Of course, I'm only sort of kidding - MESA was sort of icky with one foot in the 16-bit world and one foot in the 32-bit world. LONG POINTERs were no fun... Don Gillies - t_dgilli.x@qualcomm.x.com - Planetwide Software, Inc. (consultant) / Globalstar Satellite CDMA Project, Qualcomm Inc., 6455 Lusk Blvd San Diego, California 92121 - phone: 619-651-2326. Adjunct Professor of EE, UBC, Vancouver BC Canada V6T 1Z4 http://www.ee.ubc.ca/home/staff/faculty/gillies/etc/www/index.html (remove x's to reply by email)Article: 17254
Hi, Andy Peters <apeters@noao.edu.NOSPAM> schrieb in im Newsbeitrag: 7mihna$1cg4$1@noao.edu... ... > Change your declaration of angle_output to STD_LOGIC_VECTOR(7 downto 0). > Now you'll have eight obvious ports you can use to map to the pins you > desire. That's exactly how to do it. > > Of course, you'll have to tweak your code. you can have a signal internal > to your architecture called angle that's declared as integer range 0 to 255 > and do all operations on the integer, and you need to convert it to > STD_LOGIC_VECTOR only when driving the output: > > angle_output <= ConversionToSLV(angle); > Okay, the Altera Compiler uses angle_output <= CONV_STD_LOGIC_VECTOR(angle,width) where angle is the integer value and width the number of bit to represent this integer value (in your case: 8 Bit, such width is 8).. CU, CSArticle: 17255
In article <7mjge5$pqt$1@cascade.cs.ubc.ca>, gillies@cs.ubc.ca (Donald Gillies) wrote: > Actually, if you're willing to take the Alto one step higher and build > a wilflower-class D-machine with the MESA instruction set, this might > have the ideal instruction set for a massively parallel FPGA > processor. The code density of this machine was something like 2-3 > byte-opcodes per high-level language statement. In other words, it > was probably the code density champ of all time. That's why Xerox > kept it secret and shot itself in the foot. > > Of course, I'm only sort of kidding - MESA was sort of icky with one > foot in the 16-bit world and one foot in the 32-bit world. LONG > POINTERs were no fun... > > > Don Gillies - t_dgilli.x@qualcomm.x.com - Planetwide Software, Inc. > (consultant) / Globalstar Satellite CDMA Project, Qualcomm Inc., > 6455 Lusk Blvd San Diego, California 92121 - phone: 619-651-2326. > Adjunct Professor of EE, UBC, Vancouver BC Canada V6T 1Z4 > http://www.ee.ubc.ca/home/staff/faculty/gillies/etc/www/index.html > (remove x's to reply by email) Actually Xerox built multiprocessor D-class machines. The first version I knew of was done by the printer people in El Segundo, CA -- around 1986. Interpress the precursor to Postscript was defined so that one (printed) page was described completely independent from the others -- unlike Postscript where you can describe an image and then use multiple (Print? it's been too long since I wrote Postscript) to blast the image. Thus, it was possible and desirable to have multiple Mesa processors, so each one could be creating the raster image for another page. That's one reason why Interpress printers were (are?) so much faster than Postscript ones. (Also, Interpress was always binary, unlike Postscript 1 which was ASCII that had to be interpreted.) Anyway, the printer people took the 6085 (second generation Xerox Star hardware) and made a 4(?) processor system. They also modified the Pilot operating system. This design was used for many years -- in fact, I was recently told that some Xerox printers still use Mesa. (When Xerox was pulling the plug on the final support of Star, they got some cries of protest from a group that needed some compiler fixes!!! for their project. This was a 6 pass compiler written in before '82.) In 1987-ish, PARC was working on the Dragon processor -- a multiprocessor version of the Dorado box. (Dorado was an ECL processor that was I think 4 times faster than the Dlion, or 8010/6085 design.) Then Xerox did a deal with Sun -- licensing the Star user interface to Sun for OpenLook, doing some kind of deal so Sun got the Dragon design and even the design team (temporarily) while Xerox got the right to resale Sun SPARC systems with a Xerox nameplate. Xerox also agreed to port Star to the Sun (SunOS) platform -- this was known internally as the Salient project. I've been told that the Dragon project was the precursor to Sun's current very successful clustering technology. Dave Curbow (I wrote a lot of Mesa) Xerox '83-'90Article: 17256
Hi ALL, Today, I signed up for a membership at what appears to be one of the most amazing sites on the Net. It's basically a vast consumer community service, which will soon be offering its members substantial discounts on consumer merchandise as well as other various community services (like forums, on-line shopping malls and a targeted internet consumer index). They seem to be pretty serious! Besides, they're offering a referral program that gives out cash bonuses of up to $1000 which could also be applied to the purchase of the company's shares (if they complete an IPO). IT'S REALLY TRUE ! They provide on-line stats, and I'd like you to help me run up my bonus. It's easy to sign up, but their offer is limited, so try and do it as soon as you can. Simply register at http://www.targetshop.com/users/level1.asp?refId=294432, (my referral number is 294432) and tell your friends as well! Thanks, and good luck with the bonuses! Take care and Good luck !Article: 17257
In article <7mjge5$pqt$1@cascade.cs.ubc.ca>, gillies@cs.ubc.ca (Donald Gillies) wrote: > a wilflower-class D-machine with the MESA instruction set, this might > have the ideal instruction set for a massively parallel FPGA > processor. The code density of this machine was something like 2-3 > byte-opcodes per high-level language statement. In other words, it > was probably the code density champ of all time. I'm not sure that that follows. What do you call a typical "high-level language statement"? I'd say that a = b and a += b and a = b + c are pretty typical. Assuming that everything is in registers (a good bet with VAX or 68K with 16 registers, almost certain with a typical RISC with 32) then those take 3/3/4 bytes on VAX, 2/2/4 bytes on 68K and 4/4/4 on most any RISC. Oh, and 2/3/4 bytes on Java VM. On x86 they are 1/1/2 bytes if everything is in registers, but that's reasonably unlikely in general, in which case I think it devolves to rather more than the RISCs (result/first operand in register and 2nd operand in memory are quite likely on x86, which gives numbers comparable to 68K or Java). -- BruceArticle: 17258
In article <curbow-1407992127380001@dynamic45.pm07.san-jose.best.com>, curbow@best.com (Dave Curbow) wrote: > Interpress the precursor to Postscript was defined so that one (printed) > page was described completely independent from the others -- > unlike Postscript where you can describe an image and then use > multiple (Print? it's been too long since I wrote Postscript) to blast > the image. copypage/showpage. PostScript also carries state from one page to the next, unless you explicitly use save/restore around each page's contents -- which much machine-generated code, and anything following the DSC (Document Structuring Conventions), does. -- BruceArticle: 17259
Ray Andraka wrote: > > Let's see. Aldec, modelsim, synplicity, viewlogic and altera all use dongles. I guess > you must be doing all your work on Foundation? Unfortunately, in this business, > dongles are a fact of life. I've currently got a string of 9 of them on my system :-( You're assuming that I am working with Xilinx parts ;) But, yes, I have been using Foundation. Before that I was using Orcad Express, but they have gone to a dongle for their latest release. But then I gave up trying to design FPGAs with their software for other reasons. I am working with the Lucent tools and parts now. The free tools don't come with a dongle (or support). I am not sure what happens when I buy a supported version of the tools. -- Rick Collins rick.collins@XYarius.com remove the XY to email me. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design Arius 4 King Ave Frederick, MD 21701-3110 301-682-7772 Voice 301-682-7666 FAX Internet URL http://www.arius.comArticle: 17260
In article <378CFC93.29652CB9@ids.net>,
Ray Andraka <randraka@ids.net> writes:
> Xilinx has an app note on line on implementing a plug and play ISA
> interface. It has all the details you'll need.
>
Ya, know about that one, I should of made clear that I need one that
does memory address decoding and IO decoding. The Xilinx Tech Note only
handles IO Decoding.
Thanks again.
Robert Morse
ORIG POST:::
Hi,
I am looking for a ISA PnP core, for an FPGA. We are currently
using a commercial ISA PnP chip but they require another EPLD to
interface into fix up the signals so we can use them. So any
news on a ISA PnP core, either commercial or Free.
Thanks in advance.
Robert Morse
--
++++++++++++++++++++++++++++++++++++++++
+ Robert Morse +
+ rmorse@rmsun.linxnet.com +
++++++++++++++++++++++++++++++++++++++++
Article: 17261No, it is more that I surmised that you were, since foundation is the only one of the major players that doesn't need a dongle either for design entry or place and route or both...that is with the exception of the cheap seats which I got the impression over the years that you were well beyond. I did forget about ORcad entry, I never really considered it up to FPGA entry because historically it handled hierarchy so awfully. I haven't looked at it in a while now, but I think it is also dongled. Rickman wrote: > Ray Andraka wrote: > > > > Let's see. Aldec, modelsim, synplicity, viewlogic and altera all use dongles. I guess > > you must be doing all your work on Foundation? Unfortunately, in this business, > > dongles are a fact of life. I've currently got a string of 9 of them on my system :-( > > You're assuming that I am working with Xilinx parts ;) > > But, yes, I have been using Foundation. Before that I was using Orcad > Express, but they have gone to a dongle for their latest release. But > then I gave up trying to design FPGAs with their software for other > reasons. > > I am working with the Lucent tools and parts now. The free tools don't > come with a dongle (or support). I am not sure what happens when I buy a > supported version of the tools. > > -- > > Rick Collins > > rick.collins@XYarius.com > > remove the XY to email me. > > Arius - A Signal Processing Solutions Company > Specializing in DSP and FPGA design > > Arius > 4 King Ave > Frederick, MD 21701-3110 > 301-682-7772 Voice > 301-682-7666 FAX > > Internet URL http://www.arius.com -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 17262
In article <curbow-1407992127380001@dynamic45.pm07.san-jose.best.com>, curbow@best.com (Dave Curbow) writes:
>I was recently told that some Xerox printers still use Mesa. (When Xerox
AFAIK, DocuTech still does. I'm pretty sure that the UI reuses a lot
of XPIW (although this is from observation, rather than from seeing the
code).
(I left 6 years ago, and this true then...)
>Dave Curbow (I wrote a lot of Mesa)
>Xerox '83-'90
Hugh.
(I worked on Internationalisation of the Docutech UI, in InterLISP, on
1186s, and spent a lot of time waiting for 6085s to reboot. Xerox
'81-`93)
--
"The road to Paradise is through Intercourse."
The uk.transport FAQ; http://www.axalotl.demon.co.uk/transport/FAQ.html
[Substitute "axalotl" for "nospam" to email me]
Article: 17263Damn, I bet the bastards sell Amway too. NPK wrote: > Hi ALL, > > Today, I signed up for a membership at what appears to be one of the most > amazing sites on the Net. It's basically a vast consumer community service, > which will soon be offering its members substantial discounts on consumer > merchandise as well as other various community services (like forums, > on-line shopping malls and a targeted internet consumer index). They seem to > be pretty serious! > > Besides, they're offering a referral program that gives out cash bonuses of > up to $1000 which could also be applied to the purchase of the company's > shares (if they complete an IPO). IT'S REALLY TRUE ! > > They provide on-line stats, and I'd like you to help me run up my bonus. > It's easy to sign up, but their offer is limited, so try and do it as soon > as you can. > > Simply register at http://www.targetshop.com/users/level1.asp?refId=294432, > (my referral number is 294432) and tell your friends as well! > > Thanks, and good luck with the bonuses! > > Take care and Good luck !Article: 17264
Hi I was wondering if anyone could help.. I'm looking to hardware implement a neural network, using a fpga plugin board for my PC and using VHDL to configure it. As I'm a total beginner to this field I was wondering if anyone could help with a few questions. The network I want to construct is going to be big. (the smallest would contain many tens of thousands of nodes ) the training sets is also BIG (many many MB's). If I were to use just a "standard" backprop algorithm, what would be the best implement this.. Also If the training sets, weights etc.. were stored in the main memory of the PC host, a driver program would be need to send the training data, weights etc.. to the fpga, this would be written in C++ say ( I'm only guessing here ) So would a possible bottleneck occur here..?, Is there any way the PC memory could be accessed directly thought VHDL. JamesArticle: 17265
Why don't you use floating licenses with Flex License Manager? Wouldn't that solve your problem?? (Aldec, Modelim, Synplicity do support floating licenses...) Ray Andraka wrote: > > Let's see. Aldec, modelsim, synplicity, viewlogic and altera all use dongles. I guess > you must be doing all your work on Foundation? Unfortunately, in this business, > dongles are a fact of life. I've currently got a string of 9 of them on my system :-( > > > -- > -Ray Andraka, P.E. > President, the Andraka Consulting Group, Inc. > 401/884-7930 Fax 401/884-7950 > email randraka@ids.net > http://users.ids.net/~randraka -- ---------------------------------------------------------- Martin Guibert Email: mailto:guibert@cae.ca Hardware Designer Phone: (514) 341-2000 x3629 Visual System Engineering Addr: 8585 Cote de Liesse Dept. 72 C.P. 1800 H4L 4X4 CAE Electronics Ltd. Quebec, Canada ----------------------------------------------------------Article: 17266
I have used VCPU for about 6 months on an ARM based project. We brought it into the design flow late in the cycle and have been very pleased with the results. We are a small team on a very complex chip and VCPU has improved our productivity in two ways: 1. It reduces our simulation overhead because the ARM is not using up cycles in our verilog simulator. 2. It removed a step in our simulation process by allowing us to run code on a code debugger directly against the verilog (which the sw guys like), instead of converting it to a binary image for loading to a verilog memory model for simulation. Perhaps more importantly, our customer (software developers) likes it because they can develop code on their own tools in another state and run it on our verilog with minimal interference from us (sensitive IP issues). In my opinion, VCPU contributed significantly to our ability to deliver functional prototype silicon to our customer ahead of their expectation. VCPU is not perfect, it has some inherent timing quirks because the code is not executed on the simulation clock (bus cycles are). However, we are aware of those issues and have not seen any problem related to them so far. Dorian Snell In article <7mi9on$j0p$1@nnrp1.deja.com>, yorams70@my-deja.com wrote: > Hi. > I would like to read the impression of people who used Virtual CPU of > SUMMIT design. > > ThankX, > Yoram Stern. > > Sent via Deja.com http://www.deja.com/ > Share what you know. Learn what you don't. > Sent via Deja.com http://www.deja.com/ Share what you know. Learn what you don't.Article: 17267
Hi, I just recently became interested in FPGAs, and was wondering if anyone knew of a good website or book that would help out a beginner? Most of the info I have found has been to high-level for me just yet. Thanks in advance. yonoArticle: 17268
On Wed, 14 Jul 1999 17:07:58 -0400, Ray Andraka <randraka@ids.net> wrote: >Some software won't work with the latest sentinel driver...notably viewlogic WVO 7.5 eek! Thanks Ray. I din't know that. I wonder what the issue is? Any news from VL? Cheers Stuart For Email remove "NOSPAM" from the addressArticle: 17269
The floating licenses come at a substantial premium. Martin Guibert wrote: > Why don't you use floating licenses with Flex License Manager? Wouldn't > that solve your problem?? > > (Aldec, Modelim, Synplicity do support floating licenses...) > > Ray Andraka wrote: > > > > Let's see. Aldec, modelsim, synplicity, viewlogic and altera all use dongles. I guess > > you must be doing all your work on Foundation? Unfortunately, in this business, > > dongles are a fact of life. I've currently got a string of 9 of them on my system :-( > > > > > > -- > > -Ray Andraka, P.E. > > President, the Andraka Consulting Group, Inc. > > 401/884-7930 Fax 401/884-7950 > > email randraka@ids.net > > http://users.ids.net/~randraka > > -- > ---------------------------------------------------------- > Martin Guibert Email: mailto:guibert@cae.ca > Hardware Designer Phone: (514) 341-2000 x3629 > Visual System Engineering Addr: 8585 Cote de Liesse > Dept. 72 C.P. 1800 H4L 4X4 > CAE Electronics Ltd. Quebec, Canada > ---------------------------------------------------------- -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 17270
Nothing more than, yup it's a problem and an offer for a temporary license locked to the c: drive serial number. Stuart Clubb wrote: > On Wed, 14 Jul 1999 17:07:58 -0400, Ray Andraka <randraka@ids.net> > wrote: > > >Some software won't work with the latest sentinel driver...notably viewlogic WVO 7.5 > > eek! > > Thanks Ray. I din't know that. I wonder what the issue is? Any news > from VL? > > Cheers > Stuart > > For Email remove "NOSPAM" from the address -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 17271
If I recall correctly, the memory decoding is essentially the same except you use the memory controls. Robert Morse wrote: > In article <378CFC93.29652CB9@ids.net>, > Ray Andraka <randraka@ids.net> writes: > > Xilinx has an app note on line on implementing a plug and play ISA > > interface. It has all the details you'll need. > > > > Ya, know about that one, I should of made clear that I need one that > does memory address decoding and IO decoding. The Xilinx Tech Note only > handles IO Decoding. > > Thanks again. > > Robert Morse > > ORIG POST::: > > Hi, > I am looking for a ISA PnP core, for an FPGA. We are currently > using a commercial ISA PnP chip but they require another EPLD to > interface into fix up the signals so we can use them. So any > news on a ISA PnP core, either commercial or Free. > > Thanks in advance. > > Robert Morse > > -- > ++++++++++++++++++++++++++++++++++++++++ > + Robert Morse + > + rmorse@rmsun.linxnet.com + > ++++++++++++++++++++++++++++++++++++++++ -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 17272
Orcad 9+ can be locked to a NIC or a hard drive or a dongle, or can float (FlexLM). -- Bob Elkind Martin Guibert wrote: > > Why don't you use floating licenses with Flex License Manager? Wouldn't > that solve your problem?? > > (Aldec, Modelim, Synplicity do support floating licenses...) > > Ray Andraka wrote: > > > > Let's see. Aldec, modelsim, synplicity, viewlogic and altera all use dongles. I guess > > you must be doing all your work on Foundation? Unfortunately, in this business, > > dongles are a fact of life. I've currently got a string of 9 of them on my system :-( > > > > > > -- > > -Ray Andraka, P.E. > > President, the Andraka Consulting Group, Inc. > > 401/884-7930 Fax 401/884-7950 > > email randraka@ids.net > > http://users.ids.net/~randraka > > -- > ---------------------------------------------------------- > Martin Guibert Email: mailto:guibert@cae.ca > Hardware Designer Phone: (514) 341-2000 x3629 > Visual System Engineering Addr: 8585 Cote de Liesse > Dept. 72 C.P. 1800 H4L 4X4 > CAE Electronics Ltd. Quebec, Canada > ----------------------------------------------------------Article: 17273
That's the same as ieee1184. Carlhermann Schlehaus wrote: > > and do all operations on the integer, and you need to convert it to > > STD_LOGIC_VECTOR only when driving the output: > > > > angle_output <= ConversionToSLV(angle); > > > > Okay, the Altera Compiler uses angle_output <= > CONV_STD_LOGIC_VECTOR(angle,width) > > where angle is the integer value and width the number of bit to represent > this integer value (in your case: 8 Bit, such width is 8).. > > CU, CS -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 17274
In comp.arch Bruce Hoult <bruce@hoult.actrix.gen.nz> wrote: : In article <curbow-1407992127380001@dynamic45.pm07.san-jose.best.com>, [Comments on "page independence" of Interpress and PostScript document descriptions.] Adobe's highend printing technology (Supra?) has a front end which converts PostScript to PDF, splits the PDF into page batches and submits the page batches to parallel printing subsystems. One of the motiviations of this is the page independence of PDF. From my point of view, this is about as elegant as translating of Java byte code to x86 code so it can be fed to an out of order front end and finally be executed by a pipelined datapath. But hey, elegance is pretty worthless as a metric of technology success. I also heard from someone outside Adobe who tried to use this technology that it had lots and lots of implementation problems. I'm not sure if there are shipping products based on it even now. (A few years after it was announced.) I thought Xerox was supposed to have one though. -Z-
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