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Threads Starting Jul 2001
32583: 01/07/01: Paul Taylor: Closest Xilinx equivalent to Altera EPF10KE?
32609: 01/07/02: Falk Brunner: Re: Closest Xilinx equivalent to Altera EPF10KE?
32637: 01/07/03: Paul Taylor: Re: Closest Xilinx equivalent to Altera EPF10KE?
32584: 01/07/01: Nir Dahan: DLL/PLL inside
32585: 01/07/01: Dean: Xilink WebPACK keeps removing a pin I want to keep.
32588: 01/07/01: pete dudley: Re: Xilink WebPACK keeps removing a pin I want to keep.
32607: 01/07/02: Caleb Hess: Re: Xilink WebPACK keeps removing a pin I want to keep.
32610: 01/07/02: Dean Malandris: Re: Xilink WebPACK keeps removing a pin I want to keep.
32802: 01/07/09: Mark Ng: Re: Xilink WebPACK keeps removing a pin I want to keep.
32586: 01/07/01: Leon Heller: Xillinx WebPack PAR problem
32602: 01/07/02: Petter Gustad: Re: Xillinx WebPack PAR problem
32589: 01/07/01: pete dudley: Virtex II Block RAM's - Is the second port free?
32590: 01/07/01: Mike Butts: Re: Virtex II Block RAM's - Is the second port free?
32596: 01/07/02: Peter Alfke: Re: Virtex II Block RAM's - Is the second port free?
32648: 01/07/03: Yanick Viens: Re: Virtex II Block RAM's - Is the second port free?
32594: 01/07/01: Fabio: About evolutionary circuit design
32595: 01/07/01: Daniel Morelli: Intel 82380 DMA Controller in Xilinx 300
32597: 01/07/01: Rajesh Bawankule: FAQ: Verilog FAQ : July 1, 2001
32604: 01/07/02: Andrew Bridger: Xilinx Foundation vs Foundation ISE?
32615: 01/07/02: Tom Fischaber: Re: Xilinx Foundation vs Foundation ISE?
32613: 01/07/02: Heather Cooper: High Speed Logic Board Designer needed
32614: 01/07/02: Heather Cooper: FPGA Design
32619: 01/07/02: Steve Casselman: Undocumemted Xilinx Tools
32810: 01/07/09: Dennis McCrohan: Re: Undocumemted Xilinx Tools
32620: 01/07/02: Don Husby: IPAD primitive is broken in exemplar xilinx verilog libraries?
32622: 01/07/02: David Pariseau: poor man's floating point...
32624: 01/07/03: Muzaffer Kal: Re: poor man's floating point...
32633: 01/07/03: David Pariseau: Re: poor man's floating point...
32634: 01/07/03: Steve Casselman: Re: poor man's floating point...
32638: 01/07/03: Philip Freidin: Re: poor man's floating point...
32650: 01/07/04: Ray Andraka: Re: poor man's floating point...
32711: 01/07/05: glen herrmannsfeldt: Re: poor man's floating point...
32625: 01/07/03: Royan Ong: Nets with more than one driver
32630: 01/07/03: Nicolas Matringe: Re: Nets with more than one driver
32631: 01/07/03: Jonathan Bromley: Re: Nets with more than one driver
32662: 01/07/04: Royan Ong: Re: Nets with more than one driver
32663: 01/07/04: Jonathan Bromley: Re: Nets with more than one driver
32664: 01/07/04: Royan Ong: Re: Nets with more than one driver
32628: 01/07/03: Tran Cong So: XC4010 ! help please
33403: 01/07/25: Joe: Re: XC4010 ! help please
33447: 01/07/26: Werner Dreher: Re: XC4010 ! help please
33482: 01/07/27: Joe: Re: XC4010 ! help please
33543: 01/07/30: Seth Kintigh: Re: XC4010 ! help please
32632: 01/07/03: Ruediger Dehmel: xilinx timing analyser gives strange errors
32635: 01/07/03: Gonzalo Arana: uart rs232? (for free)
32644: 01/07/04: Russell Shaw: Re: uart rs232? (for free)
32659: 01/07/04: Edwin Naroska: Re: uart rs232? (for free)
32660: 01/07/04: Michael Strothjohann: Re: uart rs232? (for free)
32682: 01/07/04: VhdlCohen: Re: uart rs232? (for free)
32636: 01/07/03: vhdl: Jtag programmer, and the WinNT Parallel port
32641: 01/07/04: Rick Filipkiewicz: Re: Jtag programmer, and the WinNT Parallel port
32642: 01/07/03: VhdlCohen: Re: 'Initial' opinions...
32655: 01/07/04: Rick Filipkiewicz: Re: 'Initial' opinions...
32643: 01/07/04: David Nyarko: Are these typical VirtexE timing values?
32646: 01/07/04: Phil Hays: Re: Are these typical VirtexE timing values?
32652: 01/07/04: Ray Andraka: Re: Are these typical VirtexE timing values?
32647: 01/07/03: Yanick Viens: Re: Driven clocks balancing
32658: 01/07/04: Rajesh Bawankule: Third issue of Chip-Guru is ready: July 2001
32661: 01/07/04: Wojciech Zabolotny: How to read(verify) configuration from SRAM configured (ACEX) Altera
32665: 01/07/04: M.B.: FPGA projects
32666: 01/07/04: Sven Blankenberg: Problem with resolution functions
32672: 01/07/04: Kuan Zhou: Re: Problem with resolution functions
32699: 01/07/05: Sven Blankenberg: Re: Problem with resolution functions
32679: 01/07/04: Tim: Re: Problem with resolution functions
32697: 01/07/05: Sven Blankenberg: Re: Problem with resolution functions
32761: 01/07/08: Tim: Re: Problem with resolution functions
32834: 01/07/10: Abhijit K. Deb: Re: Problem with resolution functions
32667: 01/07/04: SN: 8031 microcontroller on FPGA development board :-(
32668: 01/07/04: Allan Herriman: Re: 8031 microcontroller on FPGA development board :-(
32669: 01/07/04: Keith R. Williams: Re: 8031 microcontroller on FPGA development board :-(
32698: 01/07/05: Niki Steenkamp: Re: 8031 microcontroller on FPGA development board :-(
32702: 01/07/05: Keith R. Williams: Re: 8031 microcontroller on FPGA development board :-(
32705: 01/07/05: Dave Vanden Bout: Re: 8031 microcontroller on FPGA development board :-(
32720: 01/07/06: Jim Granville: Re: 8031 microcontroller on FPGA development board :-)
32839: 01/07/10: Steven K. Knapp: Re: 8031 microcontroller on FPGA development board :-)
32906: 01/07/11: Steven J. Ackerman: Re: 8031 microcontroller on FPGA development board :-)
32908: 01/07/11: emanuel stiebler: Re: 8031 microcontroller on FPGA development board :-)
32712: 01/07/05: Spehro Pefhany: Re: 8031 microcontroller on FPGA development board :-(
32671: 01/07/04: Spehro Pefhany: Re: 8031 microcontroller on FPGA development board :-(
32688: 01/07/05: Tony Burch: Re: 8031 microcontroller on FPGA development board :-(
32673: 01/07/04: Manfred Kraus: clock frequency synthesizer for FPGA
32685: 01/07/05: Kolja Sulimma: Re: clock frequency synthesizer for FPGA
32674: 01/07/04: Subodh Nijsure: Downloading FPGA (XBN) bitstream to XCV50E
32677: 01/07/04: Tim: Re: Downloading FPGA (XBN) bitstream to XCV50E
32693: 01/07/05: Felix Bertram: Re: Downloading FPGA (XBN) bitstream to XCV50E
32745: 01/07/06: Jon Elson: Re: Downloading FPGA (XBN) bitstream to XCV50E
32757: 01/07/07: Subodh Nijsure: Re: Downloading FPGA (XBN) bitstream to XCV50E
32675: 01/07/04: vhdl: How to estimate the number of CLBs ?
32678: 01/07/04: Kuan Zhou: Re: How to estimate the number of CLBs ?
32687: 01/07/05: Ray Andraka: Re: How to estimate the number of CLBs ?
32696: 01/07/05: Alan Fitch: Re: How to estimate the number of CLBs ?
32704: 01/07/05: Jamie Sanderson: Re: How to estimate the number of CLBs ?
32709: 01/07/05: Ray Andraka: Re: How to estimate the number of CLBs ?
32680: 01/07/04: vhdl: RE: How to estimate the number of CLBs ?
32686: 01/07/04: Ben Franchuk: Glitch hunting.
32736: 01/07/06: Falk Brunner: Re: Glitch hunting.
32689: 01/07/05: Cameron Watt: Xilinx J Drive
32690: 01/07/05: Mike Hicks: Tcl/Tk VHDL Automatic Testbench Generator - tb_gen.tcl (0/1)
32703: 01/07/05: Dave Colson: Aldec Active-HDL 4.2 Windows 2000 Verilog back anno Xilinx problems
32706: 01/07/05: Nial Stewart: Re: Tcl/Tk VHDL Automatic Testbench Generator - tb_gen.tcl (0/1)
32707: 01/07/05: Nial Stewart: Re: Tcl/Tk VHDL Automatic Testbench Generator - tb_gen.tcl (0/1)
32729: 01/07/06: =?iso-8859-1?Q?Torbj=F6rn?= Stabo: Re: Tcl/Tk VHDL Automatic Testbench Generator - tb_gen.tcl (0/1)
32730: 01/07/06: Nial Stewart: Re: Tcl/Tk VHDL Automatic Testbench Generator - tb_gen.tcl (0/1)
32691: 01/07/05: Mike Hicks: Tcl/Tk VHDL Automatic Testbench Generator - tb_gen.tcl (1/1)
32701: 01/07/05: Dave Colson: Re: Tcl/Tk VHDL Automatic Testbench Generator - tb_gen.tcl (1/1)
32723: 01/07/06: Richard Erlacher: Re: Tcl/Tk VHDL Automatic Testbench Generator - tb_gen.tcl (1/1)
32692: 01/07/05: Marco: Altera ACEX
32695: 01/07/05: <martin.j.thompson@trw.com>: Re: Altera ACEX
32732: 01/07/06: Dmitry Kuznetsov: Re: Altera ACEX
32744: 01/07/06: Peter Ormsby: Re: Altera ACEX
32770: 01/07/08: Rick Collins: Re: Altera ACEX
32773: 01/07/08: bob elkind: Re: Altera ACEX
32775: 01/07/08: bob elkind: Max+2 and multi-cycle timing analysis WAS: Altera ACEX
32780: 01/07/09: Rick Collins: Re: Max+2 and multi-cycle timing analysis WAS: Altera ACEX
32782: 01/07/09: bob elkind: Re: Max+2 and multi-cycle timing analysis WAS: Altera ACEX
32793: 01/07/09: Rick Collins: Re: Max+2 and multi-cycle timing analysis WAS: Altera ACEX
32798: 01/07/09: Mike Treseler: Re: Max+2 and multi-cycle timing analysis WAS: Altera ACEX
32825: 01/07/10: Marco: Re: Max+2 and multi-cycle timing analysis WAS: Altera ACEX
32694: 01/07/05: Rotem Gazit: Driven clocks balancing
32700: 01/07/05: Tim: Re: Driven clocks balancing
32708: 01/07/05: Subodh Nijsure: Downloading file to Xilinx (Vertex_E) FPGA.
32735: 01/07/06: Werner Dreher: Re: Downloading file to Xilinx (Vertex_E) FPGA.
32931: 01/07/12: Oliver Amft: Re: Downloading file to Xilinx (Vertex_E) FPGA.
32994: 01/07/14: John Larkin: Re: Downloading file to Xilinx (Vertex_E) FPGA.
33016: 01/07/15: Subodh Nijsure: Re: Downloading file to Xilinx (Vertex_E) FPGA.
33042: 01/07/16: Werner Dreher: Re: Downloading file to Xilinx (Vertex_E) FPGA.
32710: 01/07/05: Fredj Rouatbi: Arc Tangente and Square Root algorithms
32715: 01/07/05: Ray Andraka: Re: Arc Tangente and Square Root algorithms
32713: 01/07/05: Sandra Nielsen: AMS Wildstar Board
32716: 01/07/05: Ray Andraka: Re: AMS Wildstar Board
32737: 01/07/06: Sandra Nielsen: Re: AMS Wildstar Board
32714: 01/07/05: tiderh: low skew in vertex II
32719: 01/07/05: Alex Rast: Best JTAG H/W, S/W for most meaningful debug info?
32722: 01/07/05: Daniel J. Morelli: Re: Best JTAG H/W, S/W for most meaningful debug info?
32830: 01/07/10: Alex Rast: Problems with JTAG on XC95144 was:Best JTAG H/W,...
32866: 01/07/10: Philip Freidin: Re: Problems with JTAG on XC95144 was:Best JTAG H/W,...
32914: 01/07/11: Alex Rast: Re: Problems with JTAG on XC95144 was:Best JTAG H/W,...
32724: 01/07/06: <donald7@dreamwiz.com>: Spartan-II (XC2S200) Configuration Help~ DONE doesn't go HIGH
32726: 01/07/06: Manfred Kraus: Re: Spartan-II (XC2S200) Configuration Help~ DONE doesn't go HIGH
32725: 01/07/05: Antonio: Core Generator IQ NCO
32739: 01/07/06: Clark Pope: Re: Core Generator IQ NCO
32727: 01/07/06: Steven Sanders: Xilinx PCI development board
32728: 01/07/06: Harjo Otten: Re: Xilinx PCI development board
32734: 01/07/06: Manfred Kraus: Re: Xilinx PCI development board
33025: 01/07/15: Dave Feustel: Re: Xilinx PCI development board
32733: 01/07/07: Ivan Vernot: WTB:50 Mhz 24 CHANNEL LOGIC ANALYZER only $199
32740: 01/07/06: Mike Treseler: Re: WTB:50 Mhz 24 CHANNEL LOGIC ANALYZER only $199
32784: 01/07/09: Ulf Samuelsson: Re: WTB:50 Mhz 24 CHANNEL LOGIC ANALYZER only $199
32984: 01/07/14: Ivan Vernot: Re: WTB:50 Mhz 24 CHANNEL LOGIC ANALYZER only $199
32997: 01/07/14: Wally: Re: WTB:50 Mhz 24 CHANNEL LOGIC ANALYZER only $199
32738: 01/07/06: chris: Problems with Virtex Block Ram Propagation Delay
32754: 01/07/07: Kevin Neilson: Re: Problems with Virtex Block Ram Propagation Delay
32756: 01/07/07: Ray Andraka: Re: Problems with Virtex Block Ram Propagation Delay
32741: 01/07/06: VhdlCohen: white paper: MINIMIZING DESIGN ERRORS.
32742: 01/07/06: Joey Oravec: FPGA Express search path
32988: 01/07/14: Anil: Re: FPGA Express search path
33030: 01/07/15: Srinivasan Venkataramanan: Re: FPGA Express search path
32743: 01/07/06: jdiaz_pr: Floating Point SQRT
32747: 01/07/06: Ray Andraka: Re: Floating Point SQRT
32746: 01/07/06: finish: retiming possible with Schematic Entry
32749: 01/07/06: Mike Lowey: 3.1 on Win2000 with restricted (student) user?
32875: 01/07/10: Mike Lowey: Re: 3.1 on Win2000 with restricted (student) user?
32755: 01/07/07: Peter Lang: Large Power up Current on Spartan2
32758: 01/07/07: Gerald B: Re: Large Power up Current on Spartan2
32759: 01/07/07: Philip Freidin: Re: Large Power up Current on Spartan2
32769: 01/07/08: Rick Collins: Re: Large Power up Current on Spartan2
32877: 01/07/10: Austin Lesea: Re: Large Power up Current on Spartan2
32881: 01/07/10: Eric Smith: Re: Large Power up Current on Spartan2
32885: 01/07/10: Gerald B: Re: Large Power up Current on Spartan2
32760: 01/07/07: chris: maintaining net names after synthesis and place and route... synthesis tool: synplicity
32762: 01/07/07: Richard B. Katz: 2001 MAPLD Conference: Program Announced, Registration Open, and Last
32765: 01/07/08: Pat McGuirk: Shift and Add Multiplier With Signed Numbers
32766: 01/07/08: Alan Nishioka: Re: Shift and Add Multiplier With Signed Numbers
32767: 01/07/08: Philip Freidin: Re: Shift and Add Multiplier With Signed Numbers
32847: 01/07/10: Santiago de Pablo: Re: Shift and Add Multiplier With Signed Numbers
32771: 01/07/09: Ray Andraka: Re: Shift and Add Multiplier With Signed Numbers
32795: 01/07/09: John_H: Re: Shift and Add Multiplier With Signed Numbers
32809: 01/07/09: John_H: Re: Shift and Add Multiplier With Signed Numbers - just a bit more
32928: 01/07/12: Rob Finch: Re: Shift and Add Multiplier With Signed Numbers
32960: 01/07/13: Ray Andraka: Re: Shift and Add Multiplier With Signed Numbers
32998: 01/07/14: Steve Casselman: Re: Shift and Add Multiplier With Signed Numbers
33019: 01/07/15: John_H: Re: Shift and Add Multiplier With Signed Numbers
33024: 01/07/15: Ray Andraka: Re: Shift and Add Multiplier With Signed Numbers
32768: 01/07/08: chris: Need some help using Synplify ... and also considering Xilinx Modular Flow
32772: 01/07/09: Ray Andraka: Re: Need some help using Synplify ... and also considering Xilinx
32776: 01/07/09: Muzaffer Kal: Re: Need some help using Synplify ... and also considering Xilinx Modular Flow
32779: 01/07/09: Rick Filipkiewicz: Re: Need some help using Synplify ... and also considering Xilinx
32794: 01/07/09: Kevin Neilson: Re: Need some help using Synplify ... and also considering Xilinx Modular Flow
32797: 01/07/09: Jason T. Wright: Re: Need some help using Synplify ... and also considering Xilinx
32807: 01/07/09: chris: Re: Need some help using Synplify ... and also considering Xilinx Modular Flow
32774: 01/07/08: Jack: Offer: Extra Xilinx PCI development kit (HOT 2)
32777: 01/07/08: Jure Oblak: Simulation problems with BlockRAM's INIT values !
32778: 01/07/09: Allan Herriman: Re: Simulation problems with BlockRAM's INIT values !
32811: 01/07/09: Mike Treseler: Re: Simulation problems with BlockRAM's INIT values !
32817: 01/07/10: Phil Hays: Re: Simulation problems with BlockRAM's INIT values !
32858: 01/07/10: Ray Andraka: Re: Simulation problems with BlockRAM's INIT values !
32911: 01/07/11: s cote: Re: Simulation problems with BlockRAM's INIT values !
32781: 01/07/09: Noddy: Clock buffers
32796: 01/07/09: Falk Brunner: Re: Clock buffers
32783: 01/07/09: Noddy: Online threshold limit counter
32792: 01/07/09: John_H: Re: Online threshold limit counter
32804: 01/07/09: John_H: oops
32835: 01/07/10: Noddy: Re: Online threshold limit counter
32838: 01/07/10: Keith R. Williams: Re: Online threshold limit counter
32857: 01/07/10: Ray Andraka: Re: Online threshold limit counter
32863: 01/07/10: Keith R. Williams: Re: Online threshold limit counter
32880: 01/07/11: Ray Andraka: Re: Online threshold limit counter
32861: 01/07/10: Andy Peters <andy [@] exponentmedia: Re: Online threshold limit counter
32864: 01/07/10: John_H: Re: Online threshold limit counter
32883: 01/07/11: Ray Andraka: Re: Online threshold limit counter
32905: 01/07/11: John_H: Re: Online threshold limit counter
32882: 01/07/11: Ray Andraka: Re: Online threshold limit counter
32786: 01/07/09: Martin Melzer: Metastability constants for Altera FPGAs?
32787: 01/07/09: Thomas Reinemann: Vitrtex selectram
32789: 01/07/09: Keith R. Williams: Re: Vitrtex selectram
32790: 01/07/09: Abhimanyu Rastogi: FLEX EPF8452A
32791: 01/07/09: Wamsi Mohan: Virtexe Config problem
32800: 01/07/09: Steve Casselman: Re: Virtexe Config problem
32889: 01/07/10: Vikram Pasham: Re: Virtexe Config problem
32801: 01/07/09: James Wang: Spartan-II implementation woes
32850: 01/07/10: Falk Brunner: Re: Spartan-II implementation woes
32803: 01/07/09: cyber_spook: What chip!?
32806: 01/07/09: Eric Smith: Re: What chip!?
32816: 01/07/10: Kolja Sulimma: Re: What chip!?
32870: 01/07/10: Eric Smith: Re: What chip!?
32846: 01/07/10: Niki Steenkamp: Re: What chip!?
32855: 01/07/10: bob elkind: Altera synthesis tools WAS: What chip!?
32865: 01/07/10: cyber_spook: Re: Altera synthesis tools WAS: What chip!?
32888: 01/07/11: Peter Ormsby: Re: Altera synthesis tools WAS: What chip!?
32913: 01/07/11: cyber_spook: Re: Altera synthesis tools WAS: What chip!?
32808: 01/07/09: John_H: Re: What chip!?
32813: 01/07/10: Rick Filipkiewicz: Re: What chip!?
32818: 01/07/09: bob elkind: Re: What chip!?
32822: 01/07/10: Rick Filipkiewicz: Re: What chip!?
32829: 01/07/10: bob elkind: Re: What chip!?
32867: 01/07/10: cyber_spook: Re: What chip!?
32874: 01/07/10: Rick Filipkiewicz: Re: What chip!?
33413: 01/07/25: Peter Alfke: Re: What chip!?
33414: 01/07/25: Rick Filipkiewicz: Re: What chip!?
33421: 01/07/25: bob elkind: Re: What chip!?
33440: 01/07/26: Austin Lesea: He is back from vacation, and he has a tan, too!
32814: 01/07/09: Ben Franchuk: Re: What chip!?
32815: 01/07/09: Steve Casselman: Re: What chip!?
32819: 01/07/09: bob elkind: Re: What chip!?
32868: 01/07/10: cyber_spook: Re: What chip!?
32869: 01/07/10: cyber_spook: Re: What chip!?
32805: 01/07/09: <gsinfo@gefen.com>: DVI to ADC Conversion Box 8968
32821: 01/07/09: Antonio: Two's complement to binary translation problem
32836: 01/07/10: Noddy: Re: Two's complement to binary translation problem
32845: 01/07/10: John_H: Re: Two's complement to binary translation problem
32831: 01/07/10: Lionel DORIS: Pins state on Spartan XL before config.
32851: 01/07/10: Falk Brunner: Re: Pins state on Spartan XL before config.
32995: 01/07/14: John Larkin: Re: Pins state on Spartan XL before config.
33551: 01/07/30: Yury: Re: Pins state on Spartan XL before config.
32833: 01/07/10: Michael Johnen: assigning signals with Altera Max+PlusII vhdl
32840: 01/07/10: Tim O'Connell: Re: assigning signals with Altera Max+PlusII vhdl
32871: 01/07/10: cyber_spook: Re: assigning signals with Altera Max+PlusII vhdl
33228: 01/07/19: Tim O'Connell: Re: assigning signals with Altera Max+PlusII vhdl
32841: 01/07/10: Anno: FPGA on flex?
32843: 01/07/10: <jschneider@cix.ceeowe.ewekay>: Re: FPGA on flex?
32872: 01/07/10: cyber_spook: Re: FPGA on flex?
32842: 01/07/10: Noddy: Adder/Subtracter Core???
32853: 01/07/10: John_H: Re: Adder/Subtracter Core???
32859: 01/07/10: Ray Andraka: Re: Adder/Subtracter Core???
32873: 01/07/10: John_H: Re: Adder/Subtracter Core???
32844: 01/07/10: Jason Daughenbaugh: XC17S00XL vs XC17S00A
32849: 01/07/10: =?ISO-8859-1?Q?Beno=EEt?=: ATMCAM & UTOPIA Bus in VHDL
32852: 01/07/10: Kolja Sulimma: How do I distribute cores?
32860: 01/07/10: Ray Andraka: Re: How do I distribute cores?
32862: 01/07/10: Kolja Sulimma: Re: How do I distribute cores?
32879: 01/07/11: Ray Andraka: Re: How do I distribute cores?
32890: 01/07/11: Francisco Camarero: Re: How do I distribute cores?
32894: 01/07/11: Kolja Sulimma: Re: How do I distribute cores?
32930: 01/07/12: Rob Finch: Re: How do I distribute cores?
32974: 01/07/13: Steve Casselman: Re: How do I distribute cores?
32980: 01/07/13: Ray Andraka: Re: How do I distribute cores?
32876: 01/07/10: Don Husby: Virtex2: Is it possible to place distributed DPRAM
32878: 01/07/10: Steve Casselman: Re: Virtex2: Is it possible to place distributed DPRAM
32884: 01/07/11: Ray Andraka: Re: Virtex2: Is it possible to place distributed DPRAM
32893: 01/07/11: Philip Freidin: Re: Virtex2: Is it possible to place distributed DPRAM
32899: 01/07/11: Ray Andraka: Re: Virtex2: Is it possible to place distributed DPRAM
32900: 01/07/11: Goran Bilski: Re: Virtex2: Is it possible to place distributed DPRAM
32938: 01/07/12: Chris Mc Clements: Re: Virtex2: Is it possible to place distributed DPRAM
32944: 01/07/12: Goran Bilski: Re: Virtex2: Is it possible to place distributed DPRAM
32903: 01/07/11: Don Husby: Re: Virtex2: Is it possible to place distributed DPRAM
32891: 01/07/11: Antonio: Need to speed up VHDL accumulator on Xilinx
32895: 01/07/11: Francisco Camarero: Re: Need to speed up VHDL accumulator on Xilinx
32897: 01/07/11: Ray Andraka: Re: Need to speed up VHDL accumulator on Xilinx
32898: 01/07/11: fred: Re: Need to speed up VHDL accumulator on Xilinx
32901: 01/07/11: Goran Bilski: Re: Need to speed up VHDL accumulator on Xilinx
32904: 01/07/11: John_H: Re: Need to speed up VHDL accumulator on Xilinx
32910: 01/07/11: Kevin Neilson: Re: Need to speed up VHDL accumulator on Xilinx
32896: 01/07/11: Steven Derrien: file flush in VHLD for synopsys VSS
32939: 01/07/12: Michael Paar: Re: file flush in VHLD for synopsys VSS
32941: 01/07/12: Steven Derrien: Re: file flush in VHLD for synopsys VSS
32902: 01/07/11: C. Gyselinck: emergency consumption reduction for Spartan II
32909: 01/07/11: Austin Lesea: Re: emergency consumption reduction for Spartan II
32912: 01/07/11: Ben Franchuk: Re: FPGA-based board vs bigger FPGA
32915: 01/07/11: Philip Freidin: Re: need help implementing state diagram of a 2input mealy machine!
32917: 01/07/11: Rick Filipkiewicz: Re: need help implementing state diagram of a 2input mealy machine!
32918: 01/07/11: Kolja Sulimma: Re: need help implementing state diagram of a 2input mealy machine!
32921: 01/07/11: Chez: Re: need help implementing state diagram of a 2input mealy machine!
32916: 01/07/11: Gonzalo Arana: WebPACK problem
32919: 01/07/11: Jennifer Jenkins: Re: WebPACK problem
32922: 01/07/11: Gonzalo Arana: Re: WebPACK problem
32920: 01/07/11: Chez: need help implementing state diagram of a 2input mealy machine!
32923: 01/07/11: James Baker: Erasing Altera EPC-1441?
32942: 01/07/12: Peter Ormsby: Re: Erasing Altera EPC-1441?
32924: 01/07/12: Clyde R. Visser: Xilinx makefile under RedHat
32955: 01/07/12: frank bergmann: Re: Xilinx makefile under RedHat
32957: 01/07/12: Duane Clark: Re: Xilinx makefile under RedHat
32925: 01/07/11: fczhao: How to view BlockRam contents generated by Xilinx Coregenerator in Active Hdl 4.2 ?
32926: 01/07/11: fczhao: View Blockram content generated by Xilinx Coregenerator
32927: 01/07/11: jdiaz_pr: FPGA-based board vs bigger FPGA
32929: 01/07/12: Noddy: Design entry
32973: 01/07/13: VhdlCohen: Re: Design entry
32975: 01/07/13: Ben Franchuk: Re: Design entry
33018: 01/07/15: John_H: Re: Design entry
33020: 01/07/15: Ben Franchuk: Re: Design entry
33028: 01/07/15: Keith R. Williams: Re: Design entry
33038: 01/07/16: Rick Filipkiewicz: Re: Design entry
32977: 01/07/13: John_H: Re: Design entry
32978: 01/07/13: Magnus Homann: Re: Design entry
32979: 01/07/13: Ray Andraka: Re: Design entry
33060: 01/07/16: Don Husby: Re: Design entry
32982: 01/07/13: Alex Rast: Re: Design entry
32983: 01/07/13: Muzaffer Kal: Re: Design entry
32996: 01/07/14: Neil Franklin: Re: Design entry
32993: 01/07/14: emanuel stiebler: Re: Design entry
33045: 01/07/16: Keith R. Williams: Re: Design entry
33050: 01/07/16: Ken McElvain: Re: Design entry
33051: 01/07/16: Keith R. Williams: Re: Design entry
33066: 01/07/16: Ken McElvain: Re: Design entry
32999: 01/07/14: Mike Treseler: Re: Design entry
33399: 01/07/25: Joe: Re: Design entry
32932: 01/07/12: Chris Stephens: How to get " The Embedded Newsletter "
32933: 01/07/12: Daniel =?iso-8859-1?Q?Ha=F1czewski?=: Xilinx FPGA density estimation
32940: 01/07/12: Peter Ormsby: Re: Xilinx FPGA density estimation
32934: 01/07/12: Russell Shaw: Byteblasting an ACEX in running system?
33039: 01/07/16: Martin Schoeberl: Re: Byteblasting an ACEX in running system?
33065: 01/07/17: Russell Shaw: Re: Byteblasting an ACEX in running system?
32935: 01/07/12: Andrej: ModelSim v5.5
32936: 01/07/12: Peter Lang: Problems: Xilinx 3.1i Service Pack 8
32961: 01/07/13: Stephan Neuhold: Re: Problems: Xilinx 3.1i Service Pack 8
32965: 01/07/13: qlyus: Re: Problems: Xilinx 3.1i Service Pack 8
32937: 01/07/12: Abhimanyu Rastogi: ne one knows wat this AHDL code is doing??
32959: 01/07/13: Russell Shaw: Re: ne one knows wat this AHDL code is doing??
32943: 01/07/12: Utku Ozcan: *.SDC - *.UCF conversion table?
32946: 01/07/12: Kevin Neilson: Re: *.SDC - *.UCF conversion table?
32947: 01/07/12: Kevin Neilson: DLL Phase Locking in Division Mode
32948: 01/07/12: Austin Lesea: Re: DLL Phase Locking in Division Mode
32953: 01/07/12: John_H: Re: DLL Phase Locking in Division Mode
33112: 01/07/17: Austin Lesea: Re: DLL Phase Locking in Division Mode
32949: 01/07/12: Achlys: Xilinx BRAM failures
32952: 01/07/12: Mike Treseler: Re: Xilinx BRAM failures
32967: 01/07/13: Achlys: Re: Xilinx BRAM failures
32971: 01/07/13: Jamie Sanderson: Re: Xilinx BRAM failures
32976: 01/07/13: Magnus Homann: Re: Xilinx BRAM failures
32981: 01/07/14: Rick Filipkiewicz: Re: Xilinx BRAM failures
32964: 01/07/13: Kevin Neilson: Re: Xilinx BRAM failures
32985: 01/07/14: Bob Perlman: Re: Xilinx BRAM failures
33152: 01/07/18: Achlys: Re: Xilinx BRAM failures
33177: 01/07/18: Rick Filipkiewicz: Re: Xilinx BRAM failures
33223: 01/07/19: Bob Perlman: Re: Xilinx BRAM failures
32954: 01/07/12: Magnus Homann: Re: PCI arbiter core
32951: 01/07/12: Sebastien: PCI arbiter core
33400: 01/07/25: Joe: Re: PCI arbiter core
32956: 01/07/12: Alex Rast: How to fan out signals to bus lines in Xilinx Foundation Schematic Editor?
33026: 01/07/15: Hong: Re: How to fan out signals to bus lines in Xilinx Foundation Schematic Editor?
33034: 01/07/16: Alex Rast: Re: How to fan out signals to bus lines in Xilinx Foundation Schematic Editor?
33069: 01/07/16: Hong: Re: How to fan out signals to bus lines in Xilinx Foundation Schematic Editor?
32958: 01/07/12: chris: reading a vcd file into verilog xl
32962: 01/07/13: Dean: Help needed: why am I getting device programming errors on Webpack.
32972: 01/07/13: Mikeandmax: Re: Help needed: why am I getting device programming errors on Webpack.
32987: 01/07/14: Dean: Re: Help needed: why am I getting device programming errors on Webpack.
32990: 01/07/14: Rick Filipkiewicz: Re: Help needed: why am I getting device programming errors on Webpack.
33007: 01/07/15: Dean Malandris: Re: Help needed: why am I getting device programming errors on Webpack.
33011: 01/07/15: Dean: Re: Help needed: why am I getting device programming errors on Webpack.
32963: 01/07/13: T.Dattuprasad: Foundation2.1i
33012: 01/07/15: Falk Brunner: Re: Foundation2.1i
32989: 01/07/14: Russell Shaw: Re: Altera's ByteBlasterMV cable resistor values (2.2 ohms) ?
33001: 01/07/14: Rodo: Re: Altera's ByteBlasterMV cable resistor values (2.2 ohms) ?
33004: 01/07/15: Russell Shaw: Re: Altera's ByteBlasterMV cable resistor values (2.2 ohms) ?
33008: 01/07/15: C.Schlehaus: Re: Altera's ByteBlasterMV cable resistor values (2.2 ohms) ?
33009: 01/07/15: Russell Shaw: Re: Altera's ByteBlasterMV cable resistor values (2.2 ohms) ?
33036: 01/07/16: PYD: Re: Altera's ByteBlasterMV cable resistor values (2.2 ohms) ?
33041: 01/07/17: Russell Shaw: Re: Altera's ByteBlasterMV cable resistor values (2.2 ohms) ?
32991: 01/07/14: SAF: Which Chip Family?
33000: 01/07/14: Mike Treseler: Re: Which Chip Family?
33002: 01/07/14: SAF: Re: Which Chip Family?
33005: 01/07/15: Tony Burch: Re: Which Chip Family?
33010: 01/07/15: SAF: Re: Which Chip Family?
33014: 01/07/15: Falk Brunner: Re: Which Chip Family?
33017: 01/07/15: John_H: Re: Which Chip Family?
33021: 01/07/15: SAF: Re: Which Chip Family?
33022: 01/07/15: SAF: Re: Which Chip Family?
33027: 01/07/15: chris: Re: Which Chip Family?
33029: 01/07/16: Tony Burch: Re: Which Chip Family?
33013: 01/07/15: Falk Brunner: Re: Which Chip Family?
33023: 01/07/15: Ray Andraka: Re: Which Chip Family?
33046: 01/07/16: Falk Brunner: Re: Which Chip Family?
33055: 01/07/16: Ray Andraka: Re: Which Chip Family?
33116: 01/07/17: Ray Andraka: Re: Which Chip Family?
33158: 01/07/18: Falk Brunner: Re: Which Chip Family?
32992: 01/07/14: Pascal Lacroix: Real beginner
33003: 01/07/14: SAF: WebPack or Foundation?
33006: 01/07/15: Russell Shaw: Re: WebPack or Foundation?
33015: 01/07/15: Falk Brunner: Re: WebPack or Foundation?
33031: 01/07/15: Antonio: Polyphase filter question
33033: 01/07/16: Antonio: DDS Xilinx Core
33127: 01/07/17: Hong: Re: DDS Xilinx Core
33208: 01/07/19: Ciaran McGloin: Re: DDS Xilinx Core
33035: 01/07/16: =?ISO-8859-1?Q?Beno=EEt?=: can not create a distributed Memory
33037: 01/07/16: SAF: Book Recommendation (bit different)
33047: 01/07/16: chris: Re: Book Recommendation (bit different)
33061: 01/07/16: SAF: Re: Book Recommendation (bit different)
33064: 01/07/16: Gonzalo Arana: Re: Book Recommendation (bit different)
33075: 01/07/17: Vladimir Dergachev: Re: Book Recommendation (bit different)
33484: 01/07/28: mulp: Re: Book Recommendation (bit different)
33076: 01/07/17: SAF: Re: Book Recommendation (bit different)
33205: 01/07/19: Gonzalo Arana: Re: Book Recommendation (bit different)
33493: 01/07/28: Steven K. Knapp: Re: Book Recommendation (bit different)
33040: 01/07/16: Abhimanyu Rastogi: How to set an AHDL query pattern
33043: 01/07/16: bugbear: conditional expression optimization
33044: 01/07/16: Jon: Re: conditional expression optimization
33079: 01/07/17: bugbear: Re: conditional expression optimization
33120: 01/07/18: Jim Granville: Re: conditional expression optimization
33136: 01/07/18: bugbear: Re: conditional expression optimization
33048: 01/07/16: Rotem Gazit: Fixing routing in a Virtex FPGA
33052: 01/07/16: Jeffrey Vallier: Re: Fixing routing in a Virtex FPGA
33132: 01/07/18: Rotem Gazit: Re: Fixing routing in a Virtex FPGA
33053: 01/07/16: Ray Andraka: Re: Fixing routing in a Virtex FPGA
33059: 01/07/16: John_H: Re: Fixing routing in a Virtex FPGA
33133: 01/07/18: Rotem Gazit: Re: Fixing routing in a Virtex FPGA
33054: 01/07/16: Eric Crabill: Re: Fixing routing in a Virtex FPGA
33049: 01/07/16: Dave Brown: Xilinx .bit file format
33081: 01/07/17: Stephan Neuhold: Re: Xilinx .bit file format
33102: 01/07/17: Neil Franklin: Re: Xilinx .bit file format
33058: 01/07/16: Morgan Kaufmann Publishers: New Book: Readings in Hardware/Software Co-design
33063: 01/07/16: Yoram Rovner: I NEED XILINX FOUNDATION PROFESSIONAL
33067: 01/07/16: Eric Smith: Re: I NEED XILINX FOUNDATION PROFESSIONAL
33077: 01/07/17: Antonio: Re: I NEED XILINX FOUNDATION PROFESSIONAL
33115: 01/07/17: Anna Acevedo: Re: I NEED XILINX FOUNDATION PROFESSIONAL
33070: 01/07/17: Tomek: PROBLEM!!!
33078: 01/07/17: Stefaan Vanheesbeke: Re: PROBLEM!!!
33093: 01/07/17: Brian Philofsky: Re: PROBLEM!!!
33091: 01/07/17: Dave Colson: Re: PROBLEM!!!
33096: 01/07/17: Dave Colson: Re: PROBLEM!!!
33071: 01/07/17: Craig Abramson: Utopia Interface
33073: 01/07/17: Ben Franchuk: Re: processor core
33074: 01/07/17: Vladimir Dergachev: clock versus just a pad
33080: 01/07/17: John Smith: processor core
33088: 01/07/17: Martin Schoeberl: Re: processor core
33094: 01/07/17: Veronica Merryfield: Re: processor core
33095: 01/07/17: Brian Philofsky: Re: processor core
33124: 01/07/18: Tony Burch: Re: processor core
33159: 01/07/18: Falk Brunner: Re: processor core
33166: 01/07/18: John Smith: Re: processor core
33191: 01/07/18: Steven K. Knapp: Re: processor core
33268: 01/07/21: Rob Finch: Re: processor core
33084: 01/07/17: Martin Rice: Coolrunner: availability
33098: 01/07/17: Richard Dungan: Re: Coolrunner: availability
33119: 01/07/18: Jim Granville: Re: Coolrunner: availability
33170: 01/07/18: Patrick Kane: Re: Coolrunner: availability
33085: 01/07/17: Noddy: Unconnected nets
33089: 01/07/17: Stephan Neuhold: Re: Unconnected nets
33086: 01/07/17: Antonio: Interpolating Filter question
33087: 01/07/17: Paul Graham: Using the Xilinx Alliance 3.1i/3.3i Tools under Linux
33101: 01/07/17: Tom Dillon: Re: Using the Xilinx Alliance 3.1i/3.3i Tools under Linux
33105: 01/07/17: Paul Graham: Re: Using the Xilinx Alliance 3.1i/3.3i Tools under Linux
33090: 01/07/17: <kodtest99@yahoo.com>: Help me please in one test.
33092: 01/07/17: Dave Brown: MCS file format
33109: 01/07/17: Philip Freidin: Re: MCS file format
33097: 01/07/17: JianYong Niu: Xilinx System Generator V1.0 question
33099: 01/07/17: Larry Doolittle: Drive strength of Xilinx DONE pin
33113: 01/07/17: Austin Lesea: Re: Drive strength of Xilinx DONE pin
33100: 01/07/17: sandeep: regarding the constraints while writing VHDL code
33106: 01/07/17: John_H: Re: regarding the constraints while writing VHDL code
33110: 01/07/17: Kevin Neilson: Re: regarding the constraints while writing VHDL code
33173: 01/07/18: Falk Brunner: Re: regarding the constraints while writing VHDL code
33253: 01/07/20: Andy Peters <andy [@] exponentmedia: Re: regarding the constraints while writing VHDL code
33260: 01/07/21: Russell Shaw: Re: regarding the constraints while writing VHDL code
33263: 01/07/21: Ray Andraka: Re: regarding the constraints while writing VHDL code
33103: 01/07/17: David Wright: Working Design - Anyone
33104: 01/07/17: Dave Vanden Bout: Re: Working Design - Anyone
33108: 01/07/17: Kevin Neilson: Re: Working Design - Anyone
33111: 01/07/17: Ray Andraka: Re: Working Design - Anyone
33125: 01/07/17: Ben Franchuk: Re: Working Design - Anyone
33169: 01/07/18: Ray Andraka: Re: Working Design - Anyone
33151: 01/07/18: Nial Stewart: Re: Working Design - Anyone
33117: 01/07/17: Mike Treseler: Re: Working Design - Anyone
33118: 01/07/18: Jim Granville: Re: Working Design - Anyone
33128: 01/07/18: Russell Shaw: Re: Working Design - Anyone
33155: 01/07/18: Nial Stewart: Re: Working Design - Anyone
33179: 01/07/19: Jim Granville: Re: Working Design - Anyone
33192: 01/07/19: Russell Shaw: Re: Working Design - Anyone
33193: 01/07/18: Ben Franchuk: Re: Working Design - Anyone
33194: 01/07/19: Russell Shaw: Re: Working Design - Anyone
33222: 01/07/19: John_H: Re: Working Design - Anyone
33196: 01/07/19: Lasse Langwadt Christensen: Re: Working Design - Anyone
33150: 01/07/18: Keith R. Williams: Re: Working Design - Anyone
33224: 01/07/19: John Larkin: Re: Working Design - Anyone
33242: 01/07/20: Keith Wootten: Re: Working Design - Anyone
33255: 01/07/20: Andy Peters <andy [@] exponentmedia: Re: Working Design - Anyone
33107: 01/07/17: cyber_spook: Fibre Channel info?
33114: 01/07/17: Austin Lesea: Re: Fibre Channel info?
33123: 01/07/17: Muzaffer Kal: Re: Fibre Channel info?
33121: 01/07/17: Tom Wyckoff: Newbie Question
33122: 01/07/17: Ben Franchuk: Re: Newbie Question
33139: 01/07/18: Vladimir Dergachev: Re: Newbie Question
33299: 01/07/23: Tom Wyckoff: Re: Newbie Question
33126: 01/07/18: Dean: Help please: How to build a state machine into a VHDL block?
33163: 01/07/18: Don Husby: Re: Help please: How to build a state machine into a VHDL block?
33129: 01/07/18: Russell Shaw: How do i see buried nodes in maxplus2?
33135: 01/07/18: Wolfgang Loewer: Re: How do i see buried nodes in maxplus2?
33161: 01/07/19: Russell Shaw: Re: How do i see buried nodes in maxplus2?
33181: 01/07/18: bob elkind: Re: How do i see buried nodes in maxplus2?
33134: 01/07/18: Noddy: Project implementation
33138: 01/07/18: JianYong Niu: Re: Project implementation
33143: 01/07/18: Dave Vanden Bout: Re: Project implementation
33140: 01/07/18: Jon Harrison: FPGAs in Safety Involved Applications
33146: 01/07/18: Ray Andraka: Re: FPGAs in Safety Involved Applications
33157: 01/07/18: Austin Lesea: Re: FPGAs in Safety Involved Applications
33186: 01/07/18: Peter Ormsby: Re: FPGAs in Safety Involved Applications
33200: 01/07/19: Jon Harrison: Re: FPGAs in Safety Involved Applications
33238: 01/07/20: Victor Schutte: Re: FPGAs in Safety Involved Applications
33141: 01/07/18: thomas daehler: Spartan2XC2S30 vs ACEXEP1K30
33145: 01/07/18: Russell Shaw: Re: Spartan2XC2S30 vs ACEXEP1K30
33147: 01/07/18: Wolfgang Loewer: Re: Spartan2XC2S30 vs ACEXEP1K30
33148: 01/07/18: Jan Pech: Re: Spartan2XC2S30 vs ACEXEP1K30
33149: 01/07/18: Ray Andraka: Re: Spartan2XC2S30 vs ACEXEP1K30
33156: 01/07/18: Austin Lesea: Re: Spartan2XC2S30 vs ACEXEP1K30
33183: 01/07/18: bob elkind: Re: Spartan2XC2S30 vs ACEXEP1K30
33187: 01/07/19: Ray Andraka: Re: Spartan2XC2S30 vs ACEXEP1K30
33203: 01/07/19: bob elkind: Re: Spartan2XC2S30 vs ACEXEP1K30
33207: 01/07/19: Ray Andraka: Re: Spartan2XC2S30 vs ACEXEP1K30
33289: 01/07/22: Dave Feustel: Re: Spartan2XC2S30 vs ACEXEP1K30
33302: 01/07/23: Russell Shaw: Re: Spartan2XC2S30 vs ACEXEP1K30
33307: 01/07/22: bob elkind: Re: Spartan2XC2S30 vs ACEXEP1K30
33188: 01/07/19: Russell Shaw: Re: Spartan2XC2S30 vs ACEXEP1K30
33168: 01/07/18: Mike Treseler: Re: Spartan2XC2S30 vs ACEXEP1K30
33184: 01/07/18: Peter Ormsby: Re: Spartan2XC2S30 vs ACEXEP1K30
33185: 01/07/18: bob elkind: Re: Spartan2XC2S30 vs ACEXEP1K30
33142: 01/07/18: Dionissis Efstathiou: Altera's MAX devices configuration
33201: 01/07/19: Wolfgang Loewer: Re: Altera's MAX devices configuration
33144: 01/07/18: Martin Schoeberl: Xilinx WebPACK - ROM
33153: 01/07/18: Robert Siegmund: Re: Xilinx WebPACK - ROM
33164: 01/07/18: Martin Schoeberl: Re: Xilinx WebPACK - ROM
33216: 01/07/19: Michael Strothjohann: Re: Xilinx WebPACK - ROM
33154: 01/07/18: Ekrem Aras: Re: Xilinx WebPACK - ROM
33165: 01/07/18: Martin Schoeberl: Re: Xilinx WebPACK - ROM
33176: 01/07/18: Ray Andraka: Re: Xilinx WebPACK - ROM
33197: 01/07/18: Lasse Langwadt Christensen: Re: Xilinx WebPACK - ROM
33167: 01/07/18: Ray Andraka: Re: Xilinx WebPACK - ROM
33160: 01/07/18: Pete Fraser: Xilinx Multiply generator Core V3.1
33162: 01/07/18: Pete Fraser: Athlon 1.4 vs Pentium 4 1.7 for Foundation ISE/ModelSim?
33171: 01/07/18: Muzaffer Kal: Re: Athlon 1.4 vs Pentium 4 1.7 for Foundation ISE/ModelSim?
33174: 01/07/18: Nicholas Weaver: Re: Athlon 1.4 vs Pentium 4 1.7 for Foundation ISE/ModelSim?
33175: 01/07/18: cyber_spook: Re: Athlon 1.4 vs Pentium 4 1.7 for Foundation ISE/ModelSim?
33180: 01/07/18: Rick Filipkiewicz: Re: Athlon 1.4 vs Pentium 4 1.7 for Foundation ISE/ModelSim?
33256: 01/07/20: cyber_spook: Re: Athlon 1.4 vs Pentium 4 1.7 for Foundation ISE/ModelSim?
33522: 01/07/29: Rick Collins: Re: Athlon 1.4 vs Pentium 4 1.7 for Foundation ISE/ModelSim?
33595: 01/07/31: cyber_spook: Re: Athlon 1.4 vs Pentium 4 1.7 for Foundation ISE/ModelSim?
33547: 01/07/30: B. Joshua Rosen: Re: Athlon 1.4 vs Pentium 4 1.7 for Foundation ISE/ModelSim?
33668: 01/08/02: Srinivasan Venkataramanan: Re: Athlon 1.4 vs Pentium 4 1.7 for Foundation ISE/ModelSim?
34046: 01/08/12: Rick Collins: Re: Athlon 1.4 vs Pentium 4 1.7 for Foundation ISE/ModelSim?
33172: 01/07/18: FrankV.: FPGA / TDM Opportunity
33178: 01/07/18: Michael Kohne: possibly stupid lpm_fifo question...
33182: 01/07/18: Mike Treseler: Re: possibly stupid lpm_fifo question...
33189: 01/07/19: Michael Kohne: Re: possibly stupid lpm_fifo question...
33190: 01/07/19: Russell Shaw: Re: possibly stupid lpm_fifo question...
33199: 01/07/19: Wolfgang Loewer: Re: possibly stupid lpm_fifo question...
33195: 01/07/19: Andrew Gray: FPGA based SmartMedia controller
33198: 01/07/19: Stéphane: 30 m cable reception with APEX LVDS I/O ?????
33202: 01/07/19: bob elkind: Re: 30 m cable reception with APEX LVDS I/O ?????
33227: 01/07/19: Jamie Sanderson: Re: 30 m cable reception with APEX LVDS I/O ?????
33229: 01/07/19: John_H: Re: 30 m cable reception with APEX LVDS I/O ?????
33204: 01/07/19: Noddy: Taking 4MSB a problem in 2's complement?
33209: 01/07/19: Ray Andraka: Re: Taking 4MSB a problem in 2's complement?
33210: 01/07/19: Pete Fraser: Re: Taking 4MSB a problem in 2's complement?
33206: 01/07/19: Russell Shaw: How to see ram contents in maxplus2 simulation?
33221: 01/07/19: Wolfgang Loewer: Re: How to see ram contents in maxplus2 simulation?
33234: 01/07/20: Russell Shaw: Re: How to see ram contents in maxplus2 simulation?
33235: 01/07/19: bob elkind: Re: How to see ram contents in maxplus2 simulation?
33243: 01/07/20: Russell Shaw: Async RS flip-flop (was How to see ram contents in maxplus2 simulation?)
33251: 01/07/20: <robert.schoerXghuber@hoXme.inXs.de>: Re: Async RS flip-flop (was How to see ram contents in maxplus2 simulation?)
33259: 01/07/20: bob elkind: Re: Async RS flip-flop (was How to see ram contents in maxplus2
33211: 01/07/19: Vivian: SystemC
33217: 01/07/19: Michael Strothjohann: Re: SystemC
33219: 01/07/19: Michael Strothjohann: Re: SystemC
33220: 01/07/19: Brendan Lynskey: Re: SystemC
33237: 01/07/20: Kristian Wiklund: Re: SystemC
33225: 01/07/19: Jonathan Bromley: Re: SystemC
33239: 01/07/20: Robert Siegmund: Re: SystemC
33266: 01/07/20: Jeanan Del: Re: SystemC
33215: 01/07/19: Gonzalo Arana: UART problems
33772: 01/08/03: Jay: Re: UART problems
33231: 01/07/19: Gonzalo Arana: xilinx web pack problem
33241: 01/07/20: Edwin Naroska: Re: xilinx web pack problem
33244: 01/07/20: Brian Drummond: Re: xilinx web pack problem
33249: 01/07/20: DAVE WRIGHT: Re: xilinx web pack problem
33233: 01/07/19: ramshankar: foundation series 2.1i
33236: 01/07/19: Eric Smith: Re: foundation series 2.1i
33240: 01/07/20: Michael Boehnel: FND Timing Simulator - Watch *
33245: 01/07/20: pforyt: Spartan XL Readback Problem
33246: 01/07/20: Antonio: Modulator Sizing Questions
33261: 01/07/20: Eric Smith: Re: Modulator Sizing Questions
33264: 01/07/21: Ray Andraka: Re: Modulator Sizing Questions
33265: 01/07/21: Ray Andraka: Re: Modulator Sizing Questions
33544: 01/07/30: Antonio: Re: Modulator Sizing Questions
33555: 01/07/30: Ray Andraka: Re: Modulator Sizing Questions
33271: 01/07/21: Allan Herriman: Re: Modulator Sizing Questions
33247: 01/07/20: <khiltrop@gesytec.de>: Modelsim and bidir ports?
33250: 01/07/20: Mike Treseler: Re: Modelsim and bidir ports?
33319: 01/07/23: <khiltrop@gesytec.de>: Antwort: Re: Modelsim and bidir ports?
33248: 01/07/20: inGenius People: Senior IC Engineer
33252: 01/07/20: Russell Tessier: 2nd CFP: FPGA'2002
33254: 01/07/20: Francis: Schematic libraries in webpack ?
33366: 01/07/24: John Wertenbaker: Re: Schematic libraries in webpack ?
33370: 01/07/24: Mike Treseler: Re: Schematic libraries in webpack ?
33371: 01/07/24: Speedy Zero Two: Re: Schematic libraries in webpack ?
33257: 01/07/20: Duane Clark: Stopping the clock in Virtex
33258: 01/07/20: <yohyyr@nowasia.net>: The PC and Software Museum
33262: 01/07/21: Russell Shaw: I needs a saturable adder.
33290: 01/07/22: John_H: Re: I needs a saturable adder.
33297: 01/07/22: John_H: Re: I needs a saturable adder.
33301: 01/07/23: Russell Shaw: Re: I needs a saturable adder.
33306: 01/07/23: Russell Shaw: Re: I needs a saturable adder.
33321: 01/07/23: John_H: Re: I needs a saturable adder.
33811: 01/08/06: glen herrmannsfeldt: Re: I needs a saturable adder.
33830: 01/08/06: Ray Andraka: Re: I needs a saturable adder.
33856: 01/08/07: glen herrmannsfeldt: Re: I needs a saturable adder.
33865: 01/08/07: Ray Andraka: Re: I needs a saturable adder.
33267: 01/07/20: Expensimundo: Re: what tools run OK on windows 2000?
33269: 01/07/21: Philipp Krause: free VHDL and/or Verilog tools?
33272: 01/07/21: Dave Vanden Bout: Re: free VHDL and/or Verilog tools?
33336: 01/07/23: Jennifer Jenkins: Re: free VHDL and/or Verilog tools?
33280: 01/07/22: Peter Ormsby: Re: free VHDL and/or Verilog tools?
33282: 01/07/22: Russell Shaw: Re: free VHDL and/or Verilog tools?
33292: 01/07/22: Dave Feustel: Re: free VHDL and/or Verilog tools?
33303: 01/07/23: Russell Shaw: Re: free VHDL and/or Verilog tools?
33314: 01/07/23: Martin Schoeberl: Re: free VHDL and/or Verilog tools?
33341: 01/07/23: nk: Re: free VHDL and/or Verilog tools?
33495: 01/07/28: Steven K. Knapp: Re: free VHDL and/or Verilog tools?
33510: 01/07/29: Russell Shaw: Re: free VHDL and/or Verilog tools?
33270: 01/07/21: Anthony Ellis: Soldering Ceramic BGA's
33277: 01/07/21: chris: Re: Soldering Ceramic BGA's
33328: 01/07/23: Kevin Neilson: Re: Soldering Ceramic BGA's
33339: 01/07/23: cyber_spook: Re: Soldering Ceramic BGA's
33354: 01/07/24: Ray Andraka: Re: Soldering Ceramic BGA's
33364: 01/07/24: Edward: Re: Soldering Ceramic BGA's
33275: 01/07/21: Dave Feustel: Silo-3 Demo Program Crashes onDell 4100
33281: 01/07/21: Vladimir Dergachev: Re: Silo-3 Demo Program Crashes onDell 4100
33293: 01/07/22: Dave Feustel: Re: Silo-3 Demo Program Crashes onDell 4100
33298: 01/07/22: Jrrvvf: Re: Silo-3 Demo Program Crashes onDell 4100
33320: 01/07/23: Dave Feustel: Re: Silo-3 Demo Program Crashes onDell 4100
33345: 01/07/24: Srinivasan Venkataramanan: Re: Silo-3 Demo Program Crashes onDell 4100
33358: 01/07/24: Dave Feustel: Re: Silo-3 Demo Program Crashes onDell 4100
33378: 01/07/25: Srinivasan Venkataramanan: Re: Silo-3 Demo Program Crashes onDell 4100
33388: 01/07/25: Tim: Re: Silo-3 Demo Program Crashes onDell 4100
33425: 01/07/26: Srinivasan Venkataramanan: Re: Silo-3 Demo Program Crashes onDell 4100
33394: 01/07/25: Dave Feustel: Re: Silo-3 Demo Program Crashes onDell 4100
33344: 01/07/23: Clark Pope: Re: Silo-3 Demo Program Crashes onDell 4100
33276: 01/07/21: Falk Brunner: Measuring power consumption
33279: 01/07/22: Ray Andraka: Re: Measuring power consumption
33310: 01/07/23: Falk Brunner: Re: Measuring power consumption
33333: 01/07/23: Mike Treseler: Re: Measuring power consumption
33288: 01/07/22: Phil Hays: Re: Measuring power consumption
33362: 01/07/24: Falk Brunner: Re: Measuring power consumption
33291: 01/07/22: Nate Goldshlag: Re: Measuring power consumption
33300: 01/07/23: Russell Shaw: Re: Measuring power consumption
33304: 01/07/23: Phil Hays: Re: Measuring power consumption
33326: 01/07/23: Austin Lesea: Re: Measuring power consumption
33412: 01/07/26: Falk Brunner: Re: Measuring power consumption
33283: 01/07/22: Andrew Gray: Where can I download A|RT Builder & A|RT Designer
33284: 01/07/22: Andrew Gray: Maxplus II download sites
33285: 01/07/22: Maki: Re: Maxplus II download sites
33296: 01/07/22: William Meyer: Re: Maxplus II download sites
33329: 01/07/23: Leon Heller: Re: Maxplus II download sites
33286: 01/07/22: Michael Wichmann: Altera ISP - JTAG
33287: 01/07/22: Hong: Re: Altera ISP - JTAG
33327: 01/07/23: Falk Brunner: Re: Altera ISP - JTAG
33334: 01/07/23: Leon Heller: Re: Altera ISP - JTAG
33294: 01/07/22: Yi-Shin Li: a newbie question -- The cost between 3-to-1 MUX and 4-to-1 MUX
33312: 01/07/23: Thomas Stanka: Re: a newbie question -- The cost between 3-to-1 MUX and 4-to-1 MUX
33316: 01/07/23: Aki M Suihkonen: Re: a newbie question -- The cost between 3-to-1 MUX and 4-to-1 MUX
33295: 01/07/22: Dave Feustel: Configuration via Xilinx Multilinx Cable
33308: 01/07/23: Ben Franchuk: Re: Flex 10K10 prototyping system
33338: 01/07/23: Leon Heller: Re: Flex 10K10 prototyping system
33346: 01/07/23: Leon Heller: Re: Flex 10K10 prototyping system
33372: 01/07/24: Leon Heller: Re: Flex 10K10 prototyping system
33376: 01/07/25: C.Schlehaus: Re: Flex 10K10 prototyping system
33309: 01/07/23: Nicolas Matringe: Homemade Xilinx parallel cable problem
33313: 01/07/23: Daniel =?iso-8859-1?Q?Ha=F1czewski?=: Re: Homemade Xilinx parallel cable problem
33315: 01/07/23: Nicolas Matringe: Re: Homemade Xilinx parallel cable problem
33342: 01/07/24: Rick Filipkiewicz: Re: Homemade Xilinx parallel cable problem
33353: 01/07/24: Nicolas Matringe: Re: Homemade Xilinx parallel cable problem
33355: 01/07/24: Daniel =?iso-8859-1?Q?Ha=F1czewski?=: Re: Homemade Xilinx parallel cable problem
33363: 01/07/24: Greg Neff: Re: Homemade Xilinx parallel cable problem
33374: 01/07/25: Rick Filipkiewicz: Re: Homemade Xilinx parallel cable problem
33390: 01/07/25: Greg Neff: Re: Homemade Xilinx parallel cable problem
33416: 01/07/25: Iouri Besperstov: Re: Homemade Xilinx parallel cable problem
33379: 01/07/25: Klaus Falser: Re: Homemade Xilinx parallel cable problem
33383: 01/07/25: Nicolas Matringe: Re: Homemade Xilinx parallel cable problem
33422: 01/07/26: Klaus Falser: Re: Homemade Xilinx parallel cable problem
33365: 01/07/24: Speedy Zero Two: Re: Homemade Xilinx parallel cable problem + new question
33382: 01/07/25: Bertram Geiger: Re: Homemade Xilinx parallel cable problem + new question
33480: 01/07/27: Speedy Zero Two: Re: Homemade Xilinx parallel cable problem + new question
33776: 01/08/04: Kolja Sulimma: Re: Homemade Xilinx parallel cable problem + new question
33818: 01/08/06: Nicolas Matringe: Re: Homemade Xilinx parallel cable problem + new question
33311: 01/07/23: Michael Boehnel: EDN
33335: 01/07/23: John Eaton: Re: EDN
33408: 01/07/25: Paul Smart: Re: EDN
33317: 01/07/23: Laurent Gauch: 3.3i service pack 8
33478: 01/07/27: Jan Martin: Re: 3.3i service pack 8
33521: 01/07/29: Rick Collins: Re: 3.3i service pack 8
33550: 01/07/30: Dave Feustel: Re: 3.3i service pack 8
33567: 01/07/30: Jan Martin: Re: 3.3i service pack 8
33542: 01/07/30: Zimba: Re: 3.3i service pack 8
33322: 01/07/23: Zimba: Synchronous output enable not supported?
33324: 01/07/23: VhdlCohen: Re: Synchronous output enable not supported?
33325: 01/07/23: Jamie Sanderson: Re: Synchronous output enable not supported?
33331: 01/07/23: VhdlCohen: Re: Synchronous output enable not supported?
33348: 01/07/24: Zimba: Re: Synchronous output enable not supported?
33323: 01/07/23: Leon Heller: Flex 10K10 prototyping system
33337: 01/07/23: Gary Morton: Re: Flex 10K10 prototyping system
33332: 01/07/23: Ken Kent: HotII interrupts...
33347: 01/07/23: Antonio: Again some question on a QPSK modulator
33349: 01/07/24: Rick Filipkiewicz: Re: any vb sample code for access database function
33350: 01/07/24: Noddy: Reset during accumulation
33357: 01/07/24: Noddy: Re: Reset during accumulation
33533: 01/07/29: John_H: Re: Reset during accumulation
33351: 01/07/24: marc: Register Chain
33352: 01/07/24: Jyke: Re: Register Chain
33356: 01/07/24: Phil: Re: Register Chain
33361: 01/07/24: Don Husby: Re: Register Chain
33367: 01/07/24: Ray Andraka: Re: Register Chain
33369: 01/07/24: Mike Treseler: Re: Register Chain
33359: 01/07/24: Dave Feustel: Xilinx Foundation Software Eval Pkg Won't Instal
33375: 01/07/25: Rick Filipkiewicz: Re: Xilinx Foundation Software Eval Pkg Won't Instal
33396: 01/07/25: Dave Feustel: Re: Xilinx Foundation Software Eval Pkg Won't Instal
33466: 01/07/27: Dave Feustel: Re: Xilinx Foundation Software Eval Pkg Won't Instal
33360: 01/07/24: Daniel Stevens: IEEE1394
33377: 01/07/25: Russell Shaw: FPGA Express or Spectrum?
33384: 01/07/25: Nicolas Matringe: Re: FPGA Express or Spectrum?
33393: 01/07/25: Jon: Re: FPGA Express or Spectrum?
33404: 01/07/25: Andy Peters <andy [@] exponentmedia: Re: FPGA Express or Spectrum?
33410: 01/07/25: cyber_spook: Re: FPGA Express or Spectrum?
33433: 01/07/26: Andreas Bombe: Re: FPGA Express or Spectrum?
33405: 01/07/25: Mike Treseler: Re: FPGA Express or Spectrum?
33411: 01/07/25: Martin Schoeberl: Re: FPGA Express or Spectrum?
33428: 01/07/26: Nial Stewart: Re: FPGA Express or Spectrum?
33381: 01/07/25: LIU Xianhua: FSB bus
33385: 01/07/25: Gary Spivey: ModelSim and Cygwin
33389: 01/07/25: Andy Rushton: Re: ModelSim and Cygwin
33401: 01/07/25: Dennis McCrohan: Re: ModelSim and Cygwin
33386: 01/07/25: Gary Cook: In-Circuit Power Supply Verification of Xilinx Chips
33387: 01/07/25: Spehro Pefhany: Re: In-Circuit Power Supply Verification of Xilinx Chips
33395: 01/07/25: Jon: Re: In-Circuit Power Supply Verification of Xilinx Chips
33402: 01/07/25: Peter Alfke: Re: In-Circuit Power Supply Verification of Xilinx Chips
33735: 01/08/03: Hal Murray: Re: In-Circuit Power Supply Verification of Xilinx Chips
33391: 01/07/25: James Brennan: A DIME module with simple RAM?
33392: 01/07/25: Jae-cheol Lee: Q: dividing by 2 results in out-of-phase pulse sometimes
33465: 01/07/27: Falk: Re: Q: dividing by 2 results in out-of-phase pulse sometimes
33397: 01/07/25: Paul Teagle: Windows ME and Foundation ISE?
33435: 01/07/26: Rémi SEGLIE: Re: Windows ME and Foundation ISE?
33436: 01/07/26: Paul Teagle: Re: Windows ME and Foundation ISE?
33571: 01/07/30: Andy Peters <andy [@] exponentmedia: Re: Windows ME and Foundation ISE?
33398: 01/07/25: Blagomir Donchev: Foundation ISE and VCC software problem
33406: 01/07/25: Igor Koulikov: Bound Scan
33449: 01/07/26: Steven K. Knapp: Re: Bound Scan
33407: 01/07/25: Noddy: Digital Mixer
33525: 01/07/29: Ray Andraka: Re: Digital Mixer
33409: 01/07/25: David Wright: Application obstacle course
33415: 01/07/25: Dave Feustel: Re: Application obstacle course
33426: 01/07/26: Rick Filipkiewicz: Re: Application obstacle course
33423: 01/07/26: Rick Filipkiewicz: Re: Application obstacle course
33439: 01/07/26: Dave Feustel: Re: Application obstacle course
33450: 01/07/26: Andy Peters <andy [@] exponentmedia: Re: Application obstacle course
33467: 01/07/27: Dave Feustel: Re: Application obstacle course
33485: 01/07/28: Ben Franchuk: Re: The Continuing Saga of Installing Modelsim software on Windows 2000
33503: 01/07/28: Dave Feustel: Re: The Continuing Saga of Installing Modelsim software on Windows 2000 Pro
33490: 01/07/28: Dave Feustel: The Continuing Saga of Installing Modelsim software on Windows 2000 Pro
33491: 01/07/28: Tim: Re: The Continuing Saga of Installing Modelsim software on Windows 2000 Pro
33494: 01/07/28: Dave Feustel: Re: The Continuing Saga of Installing Modelsim software on Windows 2000 Pro
33502: 01/07/28: Rick Filipkiewicz: Re: The Continuing Saga of Installing Modelsim software on Windows 2000
33504: 01/07/28: Dave Feustel: Re: The Continuing Saga of Installing Modelsim software on Windows 2000 Pro
33505: 01/07/28: Dave Feustel: Re: The Continuing Saga of Installing Modelsim software on Windows 2000 Pro
33506: 01/07/28: Dave Feustel: Re: The Continuing Saga of Installing Modelsim software on Windows 2000 Pro
33508: 01/07/28: Jjdur Ukfjg: Re: The Continuing Saga of Installing Modelsim software on Windows 2000
33512: 01/07/28: Dave Feustel: Re: The Continuing Saga of Installing Modelsim software on Windows 2000 Pro
33515: 01/07/29: Russell Shaw: Re: The Continuing Saga of Installing Modelsim software on Windows 2000
33557: 01/07/30: Andy Peters <andy [@] exponentmedia: Re: The Continuing Saga of Installing Modelsim software on Windows 2000
33417: 01/07/26: Jason Stratos Papadopoulos: prospects for tiny FPGA supercomputer?
33420: 01/07/26: Phil Hays: Re: prospects for tiny FPGA supercomputer?
33424: 01/07/26: Thomas Stanka: Re: prospects for tiny FPGA supercomputer?
33443: 01/07/26: Jon Harrison: Re: prospects for tiny FPGA supercomputer?
33445: 01/07/26: John_H: Re: prospects for tiny FPGA supercomputer?
33455: 01/07/26: Jason Stratos Papadopoulos: Re: prospects for tiny FPGA supercomputer?
33912: 01/08/08: rodger: Re: prospects for tiny FPGA supercomputer?
33924: 01/08/08: Steven K. Knapp: Re: prospects for tiny FPGA supercomputer?
33930: 01/08/08: Dave Feustel: Re: prospects for tiny FPGA supercomputer?
33935: 01/08/08: Steven K. Knapp: Re: prospects for tiny FPGA supercomputer?
34028: 01/08/12: Jason Stratos Papadopoulos: Re: prospects for tiny FPGA supercomputer?
33418: 01/07/25: Gonzalo Arana: Simple question
33473: 01/07/27: Dylan Buli: Re: Simple question
33419: 01/07/25: Harry Chung: Prom: Download problem
33429: 01/07/26: Nicolas Matringe: Re: Prom: Download problem
33430: 01/07/26: Falk: Re: Prom: Download problem
33427: 01/07/26: Daniel =?iso-8859-1?Q?Ha=F1czewski?=: Free VHDL cores - where?
33434: 01/07/26: Edwin Naroska: Re: Free VHDL cores - where?
33438: 01/07/26: Dave Feustel: Re: Free VHDL cores - where?
33448: 01/07/26: Steven K. Knapp: Re: Free VHDL cores - where?
33431: 01/07/26: Michael Hosemann: Architecture Evaluation Tools
33432: 01/07/26: Rick Filipkiewicz: PQFP sockets
33437: 01/07/26: Greg Neff: Re: PQFP sockets
33452: 01/07/26: Rick Filipkiewicz: Re: PQFP sockets
33453: 01/07/26: Speedy Zero Two: Re: PQFP sockets
33457: 01/07/27: Rick Filipkiewicz: Re: PQFP sockets
33441: 01/07/26: Wilfried Philippi: PCI-Interface
33451: 01/07/26: Philip Freidin: Re: PCI-Interface
33483: 01/07/27: Joel Kolstad: Re: PCI-Interface
33460: 01/07/27: Zimba: Re: PCI-Interface
33501: 01/07/28: Hong: Re: PCI-Interface
33541: 01/07/30: Zimba: Re: PCI-Interface
33470: 01/07/27: Falk Brunner: Re: PCI-Interface
33442: 01/07/27: Russell Shaw: Scope of libraries in leonardo spectrum
33446: 01/07/26: Tom Verbeure: Re: Scope of libraries in leonardo spectrum
33454: 01/07/26: Jerry: Re: Scope of libraries in leonardo spectrum
33444: 01/07/26: Hong: FPGA Advantage
33456: 01/07/27: Russell Shaw: Re: FPGA Advantage
33458: 01/07/27: Russell Shaw: Opinions on cypress warp 6.1 and devices?
33462: 01/07/27: Eric Smith: Re: Opinions on cypress warp 6.1 and devices?
33463: 01/07/27: Rick Filipkiewicz: Re: Opinions on cypress warp 6.1 and devices?
33474: 01/07/27: Eric Smith: Re: Opinions on cypress warp 6.1 and devices?
33468: 01/07/27: David Wright: Re: Opinions on cypress warp 6.1 and devices?
33560: 01/07/30: Andy Peters <andy [@] exponentmedia: Re: Opinions on cypress warp 6.1 and devices?
33569: 01/07/30: Speedy Zero Two: Re: Opinions on cypress warp 6.1 and devices?
35283: 01/09/27: Jon Parker: Re: Opinions on cypress warp 6.1 and devices?
35296: 01/09/27: Eric Smith: Re: Opinions on cypress warp 6.1 and devices?
33459: 01/07/27: Frode Undseth: Too low output voltage on Altera 7000S??
33461: 01/07/27: Victor Schutte: Re: Too low output voltage on Altera 7000S??
33471: 01/07/27: Peter Alfke: Re: Too low output voltage on Altera 7000S??
33720: 01/08/02: Peter Alfke: Re: Too low output voltage on Altera 7000S??
33464: 01/07/27: Huang: SRL16
33469: 01/07/27: Austin Lesea: Re: SRL16
33481: 01/07/27: Ray Andraka: Re: SRL16
33489: 01/07/28: K.O: Re: SRL16
33492: 01/07/28: Tim: Re: SRL16
33526: 01/07/29: Ray Andraka: Re: SRL16
33538: 01/07/29: Huang: Re: SRL16
33563: 01/07/30: Peter Alfke: Re: SRL16
33578: 01/07/31: Ray Andraka: Re: SRL16
33472: 01/07/27: Paul Smart: Xilinx/Altera "behavioral" verilog
33475: 01/07/27: Rick Filipkiewicz: Re: Xilinx/Altera "behavioral" verilog
33476: 01/07/27: Rick Filipkiewicz: Re: Xilinx/Altera "behavioral" verilog
33554: 01/07/30: Paul Smart: Re: Xilinx/Altera "behavioral" verilog
33576: 01/07/30: Rick Filipkiewicz: Re: Xilinx/Altera "behavioral" verilog
33477: 01/07/27: Tim: Re: Xilinx/Altera "behavioral" verilog
33486: 01/07/28: Tim: Re: Xilinx/Altera "behavioral" verilog
33523: 01/07/29: B. Joshua Rosen: Re: Xilinx/Altera "behavioral" verilog
33530: 01/07/29: Tim: Re: Xilinx/Altera "behavioral" verilog
33531: 01/07/30: Jim Granville: Re: finite defect statistics
33534: 01/07/29: B. Joshua Rosen: Re: finite defect statistics
33536: 01/07/29: Ray Andraka: Re: finite defect statistics
33539: 01/07/30: Peter Alfke: Re: finite defect statistics
33546: 01/07/30: B. Joshua Rosen: Re: finite defect statistics
33558: 01/07/30: Ray Andraka: Re: finite defect statistics
33575: 01/07/30: Andy Peters <andy [@] exponentmedia: Re: finite defect statistics
33580: 01/07/30: B. Joshua Rosen: Re: finite defect statistics
33588: 01/07/31: Ray Andraka: Re: finite defect statistics
33593: 01/07/31: B. Joshua Rosen: Re: finite defect statistics
33601: 01/07/31: Peter Alfke: Re: finite defect statistics
33611: 01/07/31: Ray Andraka: Re: finite defect statistics
33656: 01/08/01: Ray Andraka: Re: DLL useage
33672: 01/08/02: Falk: Re: finite defect statistics
33711: 01/08/02: Ray Andraka: Re: finite defect statistics
33693: 01/08/02: Falk Brunner: DLL useage
33609: 01/07/31: Andy Peters <andy [@] exponentmedia: Re: finite defect statistics
33730: 01/08/02: Austin Franklin: Re: finite defect statistics
33614: 01/08/01: Jim Granville: Re: finite defect statistics
33617: 01/07/31: B. Joshua Rosen: Re: finite defect statistics
33619: 01/08/01: Ray Andraka: Re: finite defect statistics
33637: 01/08/01: B. Joshua Rosen: Re: finite defect statistics
33641: 01/08/01: B. Joshua Rosen: Re: finite defect statistics
33731: 01/08/03: Austin Franklin: Re: finite defect statistics
33748: 01/08/03: Ray Andraka: Re: finite defect statistics
33774: 01/08/04: Rick Collins: Re: finite defect statistics
33783: 01/08/05: mulp: Re: finite defect statistics
33794: 01/08/05: Austin Franklin: Re: finite defect statistics
34113: 01/08/14: joe christensen: Re: finite defect statistics
33632: 01/08/01: Allan Herriman: Re: finite defect statistics
34114: 01/08/14: joe christensen: Re: finite defect statistics
33479: 01/07/27: Andy Botterill: Re: Xilinx/Altera "behavioral" verilog
33488: 01/07/28: Andy Botterill: Re: Xilinx/Altera "behavioral" verilog
33528: 01/07/29: Andy Botterill: Re: Xilinx/Altera "behavioral" verilog
33561: 01/07/30: Paul Smart: Re: Xilinx/Altera "behavioral" verilog
33579: 01/07/31: Ray Andraka: Re: Xilinx/Altera "behavioral" verilog
33615: 01/07/31: Paul Smart: Re: Xilinx/Altera "behavioral" verilog
33620: 01/08/01: Ray Andraka: Re: Xilinx/Altera "behavioral" verilog
33629: 01/08/01: Rick Filipkiewicz: Re: Xilinx/Altera "behavioral" verilog
33643: 01/08/01: Ray Andraka: Re: Xilinx/Altera "behavioral" verilog
33834: 01/08/06: Paul Smart: Re: Xilinx/Altera "behavioral" verilog
33970: 01/08/09: Brian Philofsky: Re: Xilinx/Altera "behavioral" verilog
33566: 01/07/30: Andy Botterill: Re: Xilinx/Altera "behavioral" verilog
33496: 01/07/28: Dave Feustel: Can't Install Modelsim - Alternatives for Verilog Simulation???
33509: 01/07/28: Jjdur Ukfjg: Re: Can't Install Modelsim - Alternatives for Verilog Simulation???
33556: 01/07/30: Andy Peters <andy [@] exponentmedia: Re: Can't Install Modelsim - Alternatives for Verilog Simulation???
33540: 01/07/30: Srinivasan Venkataramanan: Re: Can't Install Modelsim - Alternatives for Verilog Simulation???
33721: 01/08/02: Dan Notestein: Re: Can't Install Modelsim - Alternatives for Verilog Simulation???
33857: 01/08/06: Alexandru Seibulescu: Re: Can't Install Modelsim - Alternatives for Verilog Simulation???
33858: 01/08/07: Dave Feustel: Re: Can't Install Modelsim - Alternatives for Verilog Simulation???
34359: 01/08/22: Dave Colson: Re: Can't Install Modelsim - Alternatives for Verilog Simulation???
34380: 01/08/22: Dave Feustel: Re: Can't Install Modelsim - Alternatives for Verilog Simulation???
34421: 01/08/24: Stephen Williams: Re: Can't Install Modelsim - Alternatives for Verilog Simulation???
34462: 01/08/26: <hamish@cloud.net.au>: Re: Can't Install Modelsim - Alternatives for Verilog Simulation???
34463: 01/08/26: Stephen Williams: Re: Can't Install Modelsim - Alternatives for Verilog Simulation???
33497: 01/07/28: feather head: Laid-off worker needs software
33499: 01/07/28: Speedy Zero Two: Re: Laid-off worker needs software
33511: 01/07/28: Steven K. Knapp: Re: Laid-off worker needs software
33507: 01/07/29: Andrew Bridger: Jitter Added by FPGA counter
33532: 01/07/29: John_H: Re: Jitter Added by FPGA counter
33535: 01/07/29: Ray Andraka: Re: Jitter Added by FPGA counter
33516: 01/07/28: Reiner Hartenstein: FPL 2001 - keynotes -- tutorials
33517: 01/07/29: Leon Heller: Announcement: Flex 10K10 design kit
33788: 01/08/05: Rick Filipkiewicz: Re: Why did Zephram spool outside all the users? We can't post
33789: 01/08/05: Hal Murray: About those "babble" posts here.
33797: 01/08/05: Chris Suslowicz: Re: Why did Zephram spool outside all the users? We can't post procedures unless Brion will grudgingly dig afterwards.
33813: 01/08/06: Å·Ç·§: Re: Why did Zephram spool outside all the users? We can't post procedures unless Brion will grudgingly dig afterwards.
34047: 01/08/12: Rick Collins: Re: Why did Zephram spool outside all the users? We can't post
33793: 01/08/05: Mark Ferguson: Re: Why did Zephram spool outside all the users? We can't post procedures unless Brion will grudgingly dig afterwards.
33548: 01/07/30: Russell Shaw: How to add carry optimizations
33552: 01/07/30: John_H: Re: How to add carry optimizations
33581: 01/07/31: Russell Shaw: Re: How to add carry optimizations
33590: 01/07/31: Ray Andraka: Re: How to add carry optimizations
33625: 01/08/01: Russell Shaw: Re: How to add carry optimizations
33549: 01/07/30: Jack Nimble: Help: Simple counter example in WebPack schamatic capture
33559: 01/07/30: Tomek: ERROR
33568: 01/07/30: Speedy Zero Two: Re: ERROR
33585: 01/07/31: Nicolas Matringe: Re: ERROR
33681: 01/08/02: Tomek: Re: ERROR
33683: 01/08/02: Nicolas Matringe: Re: ERROR
33562: 01/07/30: Reiner Hartenstein: multi-context FPGA
33573: 01/07/30: Dave Feustel: Re: multi-context FPGA
33592: 01/07/31: Jon: Re: multi-context FPGA
33587: 01/07/31: Cemal Coemert (TIP): Re: multi-context FPGA
33616: 01/07/31: Steven K. Knapp: Re: multi-context FPGA
33777: 01/08/04: Kolja Sulimma: Re: multi-context FPGA
33570: 01/07/30: Dick Ginther: i2c master
33577: 01/07/31: kryten_droid: Re: i2c master
33583: 01/07/31: Ingmar Hohmann: Re: i2c master
33597: 01/07/31: Jennifer Jenkins: Re: i2c master
33584: 01/07/31: kryten_droid: Re: i2c master
33596: 01/07/31: Rotem Gazit: Re: i2c master
33572: 01/07/30: Dave Feustel: Virtex-II Supports AMD Hypertransport Bus Protocol
33574: 01/07/30: Dave Feustel: Webpack Tutorials
33582: 01/07/31: Srinivasan Venkataramanan: Re: Webpack Tutorials
33624: 01/08/01: Dave Vanden Bout: Re: Webpack Tutorials
33586: 01/07/31: Martin Schoeberl: RAM - VHDL - Altera,...
33591: 01/07/31: Martin Schoeberl: Re: RAM... got it
33598: 01/07/31: Peter Alfke: Re: RAM... got it
33655: 01/08/01: Tim Hubberstey: Re: BlockRAM architecture
33608: 01/07/31: Mike Treseler: Re: RAM - VHDL - Altera,...
33622: 01/08/01: Russell Shaw: Re: RAM - VHDL - Altera,...
33650: 01/08/01: Mike Treseler: Re: RAM - VHDL - Altera,...
33665: 01/08/02: Russell Shaw: Re: RAM - VHDL - Altera,...
33674: 01/08/02: Martin Schoeberl: Re: RAM - VHDL - Altera,...
33679: 01/08/02: Russell Shaw: Re: RAM - VHDL - Altera,...
33703: 01/08/02: Mike Treseler: Re: RAM - VHDL - Altera,...
33699: 01/08/02: Mike Treseler: Re: RAM - VHDL - Altera,...
33628: 01/08/01: Martin Schoeberl: Re: RAM - VHDL - Altera,...
33652: 01/08/01: Mike Treseler: Re: RAM - VHDL - Altera,...
33753: 01/08/03: Iwo Mergler: Re: RAM - VHDL - Altera,...
33754: 01/08/04: Russell Shaw: Re: RAM - VHDL - Altera,...
33825: 01/08/06: Leon de Boer: Re: RAM - VHDL - Altera,...
33976: 01/08/09: Iwo Mergler: Re: RAM - VHDL - Altera,...
33589: 01/07/31: Noddy: Schematic user info
33594: 01/07/31: Klaus Falser: Re: Schematic user info
33602: 01/07/31: Kamal Patel: Re: Schematic user info
33603: 01/07/31: Kamal Patel: Re: Schematic user info
33599: 01/07/31: edgar: computer science Vs Computer Enginnering
33610: 01/07/31: Eric Smith: Re: computer science Vs Computer Enginnering
33612: 01/07/31: Rick Filipkiewicz: Re: computer science Vs Computer Enginnering
33613: 01/07/31: Ray Andraka: Re: computer science Vs Computer Enginnering
33634: 01/08/01: Gabriel Caffarena: Re: computer science Vs Computer Enginnering
33644: 01/08/01: Ray Andraka: Re: computer science Vs Computer Enginnering
33689: 01/08/02: Dave Feustel: Re: computer science Vs Computer Enginnering
33600: 01/07/31: Doug Wilson: Virtex2: Xilinx PCI core mapping error
33605: 01/07/31: Eric Crabill: Re: Virtex2: Xilinx PCI core mapping error
33604: 01/07/31: Kathy & Brian: Xilinx Spartan XL length count question.
33728: 01/08/02: Philip Freidin: Re: Xilinx Spartan XL length count question.
33606: 01/07/31: Michael Mellone: Programming Altera EPC16
33623: 01/08/01: Russell Shaw: Re: Programming Altera EPC16
33607: 01/07/31: Axel Sautter: Altera MPLD
33658: 01/08/01: Jay: Re: Altera MPLD
33666: 01/08/02: Peter Ormsby: Re: Altera MPLD
33621: 01/07/31: Alexander Litvinov: What way for Xilinx to ASIC migration ?
33657: 01/08/01: Jay: Re: What way for Xilinx to ASIC migration ?
33659: 01/08/01: Muzaffer Kal: Re: What way for Xilinx to ASIC migration ?
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