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Antonio wrote:
> Good Morning some question about VHDL :
>
> 1) In a project I've to use always the same clock edge ??? For a
> XCV1000 BG560 -4 which is better , the negative or the positive ??
I don't think it really matter but most people use positive edge so if
you have a choice, I would go with that.
> 2) Xilinx suggest to use the positional associations in the port map
> and not the named association, why ??
Where do you see that. The only place in our documentation that I have
seen any refernce to positional vs. named is in the Synthesis and
Simulation Design Guide and it says:
Use positional association in function and procedure calls, and in port
lists only when you assign all items in the
list. Use named association when you assign only some of the items
in the list. Also, Xilinx suggests that you
use named association to prevent incorrect connections for the
ports of instantiated components. Do not
combine positional and named association in the same statement as
illustrated in the following examples.
This is of course a suggestion and not a rule but I would always suggest
using named association.
> 3) The "IF" structure produce a more speed design respect to the
> "case" structure ??
Again, I am intersted to hear where this is said but I too have heard
this before and this is how I have heard it explained. Depending on the
synthesis tool used, you can get better performance out of IF-ELSE than
CASE because of the MUXFx's in the newer Virtex and Virtex-II silicon.
The reason being is nested MUX's of course is going to have priority
built into the structure and the nesteed MUXF5, MUXF6, MUXF7, and MUXF8
structures are very fast in the snewer V-II silicon. By using IF-ELSE
instead of cases for some structures allows the synthesis tool to more
easily map into the MUXFx and thus use this fast resource.
I do not think this applies to all cases but I can see instances where
an IF-ELSE might very well be faster than a case even for a fairly wide
function.
-- Brian
>
>
> Thank you, Antonio D'Ottavio
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<p>Antonio wrote:
<blockquote TYPE=CITE>Good Morning some question about VHDL :
<p>1) In a project I've to use always the same clock edge ??? For
a
<br>XCV1000 BG560 -4 which is better , the negative or the positive ??</blockquote>
<p><br>I don't think it really matter but most people use positive edge
so if you have a choice, I would go with that.
<br>
<br>
<blockquote TYPE=CITE>2) Xilinx suggest to use the positional associations
in the port map
<br>and not the named association, why ??</blockquote>
Where do you see that. The only place in our documentation that I
have seen any refernce to positional vs. named is in the Synthesis and
Simulation Design Guide and it says:
<p><i>Use positional association in function and procedure calls, and in
port lists only when you assign all items in the</i>
<br><i> list. Use named association when you assign
only some of the items in the list. Also, Xilinx suggests that you</i>
<br><i> use named association to prevent incorrect
connections for the ports of instantiated components. Do not</i>
<br><i> combine positional and named association
in the same statement as illustrated in the following examples.</i>
<p>This is of course a suggestion and not a rule but I would always suggest
using named association.
<br>
<blockquote TYPE=CITE>3) The "IF" structure produce a more speed design
respect to the
<br>"case" structure ??</blockquote>
Again, I am intersted to hear where this is said but I too have heard this
before and this is how I have heard it explained. Depending on the
synthesis tool used, you can get better performance out of IF-ELSE than
CASE because of the MUXFx's in the newer Virtex and Virtex-II silicon.
The reason being is nested MUX's of course is going to have priority built
into the structure and the nesteed MUXF5, MUXF6, MUXF7, and MUXF8 structures
are very fast in the snewer V-II silicon. By using IF-ELSE instead
of cases for some structures allows the synthesis tool to more easily map
into the MUXFx and thus use this fast resource.
<p>I do not think this applies to all cases but I can see instances where
an IF-ELSE might very well be faster than a case even for a fairly wide
function.
<br>
<p>-- Brian
<br>
<br>
<br>
<blockquote TYPE=CITE>
<p>Thank you, Antonio D'Ottavio</blockquote>
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Article: 33976Leon de Boer wrote: > > Curious, I tried this with FPGA express and it doesn't work so how would you > do it out of FPGA express back into MaxPlus2? > > Leon de Boer > ldeboer@attglobal.net > > "Iwo Mergler" <Iwo.Mergler@soton.sc.philips.com> wrote in message > news:3B6AAC1C.A3691D44@soton.sc.philips.com... > > > Martin Schoeberl wrote: > > > > > > > > A never ending problem! Trying to get RAMs in my design so that there > is > > > > not to much vendor specific code. > > > > For Altera I'm using Leonardo and Max+plus, for Xilinx WebPack. > > > > > > > > I need a RAM with rgistered rd and wr address and unregistered data > (in/out) > > > > ports. > > > > One version works: > > > > Generate a .tdf file with Altera wizard and declare the component in > the > > > > VHDL > > > > code. But now I have .tdf files. I want only VHDL. > > > > > > > > Sorry, missed the original message... > > > > MaxPlus2 can recognize 'magic names'. To implement any of the LPM memories > > in EABs, just instantiate the right component. In your case (assuming > 256x8 bits): > > > > entity syn_ram_256x8_irou is > > port ( Data : in std_logic_vector(7 downto 0); > > Address : in std_logic_vector(7 downto 0); > > WE : in std_logic; > > Q : out std_logic_vector(7 downto 0); > > Inclock : in std_logic > > ); > > > > Copy this name & portmap into your design. Leonardo will complain > > and generate EDF with a empty 'black box'. MaxPlus2 spots this and > > fills the gap with the right thing (TM). > > > > I guess you want to know how this magic works... Here we go: > > > > If you dig deep enough into your MaxPlus2 installation, you'll find > > a little DOS program called genmem.exe. This program generates a > > VHDL (or Verilog) component with the right name. The component itself > > is a handy simulation model for the memory, but make sure you don't > > try to synthesize it. > > > > Have a nice day, > > > > Iwo I never used FPGA express, but it works with Synopsys and Leonardo Spectrum. You should be able to synthesize empty blocks with your tool... maybe an option somewhere? IwoArticle: 33977
Markus Meng wrote: > > Hi all, > > concerning a prototype board serie we do have a configuration > problem with ~ 50% of the board produced. The problem > looks that the serial configuration in Master Mode does not take > place the first time. An external Watchdog does reinitiate the > configuration process ~ 1.6sec by forcing the program pin low. > Then the Spartan-II device XC2S150 restart the configuration > in Master Mode. Since there is no possibility the 'see' that the > CRC for example is wrong, nothing happens the DONE-pin > remains low. We use the ATMEL part 17LV010. Are there > any known issues regarding this combination? > > In the Xilinx Tool chain I did NOT select anything special, just > the defaults. Looking into the details with a scope I saw that the > CCLK ~3.1 MHz. This is maybe a reasonable value. Make sure that you've got the reset/OE polarity correct on the Atmel part. It defaults to the "wrong way" for Xilinx. -andyArticle: 33978
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Antonio wrote:
> Really often when I try to map my project on Xilinx , the mapper show
> me the following warning :
>
> " All of the external outputs in this design are using slew rate
> limited output drivers. The delay on speed critical outputs can be
> dramatically reduced by designating them as fast outputs in the
> schematic ??? "
>
> How I can do this, I mean designate output as fast output ?? This
> could speed up all my project ??
The easiest way is probably specifying it in you UCF file:
-----------------------------------
Fast or Slow Attributes
-----------------------------------
Assign an OBUF to be FAST or SLOW:
INST obuf_name FAST ; #Alternate: NET pad_net FAST;
INST obuf_name SLOW ; #Alternate: NET pad_net SLOW;
By the way, I got that from http://www.xilinx.com/techdocs/2449.htm where
other UCF constraint syntax is listed.
Obviously, added care needs to be observed in board layout since you now
have faster outputs but then again, that should not be ignored even if
you had specified slow outputs.
-- Brian
>
>
> Thanks you all ...
>
> Antonio D'Ottavio
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Article: 33979Weird. Here's how I always set up my Win NT/2K boxen: 1) Each user has administrator privileges. 2) The user "Administrator" gets deleted. Your system admin may not like this (they tend to be anal) but if it's your machine, you can do what you want. -a Harry Chung wrote: > > Hi, > > I am trying to install 2.1i Foundation Series (Student Version) in Win2K, but I think I got a problem of administrative privileges. I have followed the procedure in answer database #11010 to solve some probelms. However, when I started to run the implementation, a message box prompted to indicate that "revengine" was failed to update the system registry, then the Flow Engine was terminated with fatal error. Two error message were showed as follow: > > 1. The instruction at "0x00371999" referenced memory at "0x000f062b". The memory could not be "read". > > 2. The instruction at "0x77fc90cd" reference memory at "0x000f0103". The memory could not be "written". > > Moreover, that is the log file content: > > ------------------------------------------------------------------------------------------------ > > map -p xcv600e-8-hq240 -o map.ncd test.ngd test.pcf<br> > map: version C.22<br> > Copyright (c) 1995-1999 Xilinx, Inc. All rights reserved.<br> > Using target part 'v600ehq240-8'.<br> > Reading NGD file "test.ngd"...<br> > Processing FMAPs...<br> > Removing unused or disabled logic...<br> > Running cover...<br> > Writing file map.ngm...<br> > Running directed packing...<br> > Running delay-based packing...<br> > Running related packing...<br> > Writing design file "map.ncd"...<br> > > Design Summary:<br> > Number of errors: 0<br> > Number of warnings: 1<br> > Number of Slices: 53 out of 6,912 1%<br> > Slice Flip Flops: 33<br> > 4 input LUTs: 56<br> > Number of Slices containing<br> > unrelated logic: 0 out of 53 0%<br> > Number of bonded IOBs: 65 out of 154 42%<br> > Number of GCLKs: 1 out of 4 25%<br> > Number of GCLKIOBs: 1 out of 4 25%<br> > Total equivalent gate count for design: 777<br> > Additional JTAG gate count for IOBs: 3,168<br> > FATAL_ERROR:NgdHelpers:basmpreport.c:104:1.1.2.2 - Not able to add errors to file 'map.mrp'. Process will terminate. To resolve this error, please consult the Answers Database at http://support.xilinx.com > > PROGRAM ABNORMALLY TERMINATED > > -------------------------------------------------------------------------------------------------- > > Is that the problem of administrative privileges? If yes, what are the other registry keys that I need to set as full control? If not, what is the problem going on? Thank you very much! > > Best regards, > > HarryArticle: 33980
This is a multi-part message in MIME format. --------------C2ACC0E6B6CCD69BCFAD56EC Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Marius Vollmer wrote: > Kamal Patel <kamal.patel@xilinx.com> writes: > > [Alliance being discontinued.] > > > That is correct Robert. > > Does this mean that Solaris will no longer be supported as a > place-and-route platform? Solaris is not going away. -- Brian --------------C2ACC0E6B6CCD69BCFAD56EC Content-Type: text/x-vcard; charset=us-ascii; name="brian.philofsky.vcf" Content-Transfer-Encoding: 7bit Content-Description: Card for Brian Philofsky Content-Disposition: attachment; filename="brian.philofsky.vcf" begin:vcard n:Philofksy;Brian x-mozilla-html:TRUE org:Xilinx, Inc.;System Level & Alliance Marketing adr:;;;;;; version:2.1 email;internet:brian.philofsky@xilinx.com title:Technical Marketing Engineer fn:Brian Philofksy end:vcard --------------C2ACC0E6B6CCD69BCFAD56EC--Article: 33981
I suspect a problem during power-up. Both FPGA and PROM each have a sensor that decides when Vcc is high enough to start operating. If the PROM is slower than the FPGA, then CCLK pulses will start kicking before the PROM is ready to receive them. As a result, the bitstream is wrong. I have never seen that problem with Xilinx PROMs, that's why I don't have a ready answer. You would have to delay the FPGA's wake-up sequence somehow, to make it as slow as the PROM. More deviously: Check that the PROM output is constantly High immediately after Vcc is applied. If it is, then you can increase the length-count value by any reasonable number ( 100 or even 1000 ). This effectively gives the FPGA a long, even unknown, sequence of 1s preceding the bitstream. The FPGA ignores that, but the length-counter counts ever single CCLK tick, so you must increase the length-count value. Try it, it's simple. PeterAlfke ============ Markus Meng wrote: > Hi all, > > concerning a prototype board serie we do have a configuration > problem with ~ 50% of the board produced. The problem > looks that the serial configuration in Master Mode does not take > place the first time. An external Watchdog does reinitiate the > configuration process ~ 1.6sec by forcing the program pin low. > Then the Spartan-II device XC2S150 restart the configuration > in Master Mode. Since there is no possibility the 'see' that the > CRC for example is wrong, nothing happens the DONE-pin > remains low. We use the ATMEL part 17LV010. Are there > any known issues regarding this combination? > > In the Xilinx Tool chain I did NOT select anything special, just > the defaults. Looking into the details with a scope I saw that the > CCLK ~3.1 MHz. This is maybe a reasonable value. > > Any help would be appreciated! > > markus > > -- > ******************************************************************** > ** Meng Engineering Telefon 056 222 44 10 ** > ** Markus Meng Natel 079 230 93 86 ** > ** Bruggerstr. 21 Telefax 056 222 44 10 ** > ** CH-5400 Baden Email meng.engineering@bluewin.ch ** > ******************************************************************** > ** Theory may inform, but Practice convinces. -- George Bain **Article: 33982
hello, i want to implement a prallel multplier for VIRTEX family, which toggles between two values. what's the optimal one in terms of area thanksArticle: 33983
Ray Andraka wrote: > If they are constant (ie not dependent on a signal) then they should get > hardcoded as a constant. Yes, I might go ahead and do that. It occurred to me after posting this, that since I already had written some C code that generates these, a simple change would enable it to print them out in a VHDL friendly format that I could just cut and paste. > Another alternative to writing a function would be > to use a generate statement and assign a local constant a computed value > based on the for...generate index. I do this frequently for generating RLOCs > for placing xilinx primitives. > > FOO:for i in 1 to 20 generate > constant bar:std_logic_vector(9 downto > 0):=std_logic_vector(to_unsigned(i*i,10)); > constant rloc_string:string:="R" & itoa(9-i/2) & "C0.S1"; > attribute RLOC of U1:label is rloc_string; > begin > U1:... Hmm... That is a very good idea! Thanks, I will definitely be using that soon. Duane -- My real email is akamail.com@dclark (or something like that).Article: 33984
Marius Vollmer <marius.vollmer@uni-dortmund.de> writes: > Kamal Patel <kamal.patel@xilinx.com> writes: > > [Alliance being discontinued.] > > > That is correct Robert. > > Does this mean that Solaris will no longer be supported as a > place-and-route platform? Then does this also mean no more distributed par (i.e. -m nodefile) runs :-( Petter -- ________________________________________________________________________ Petter Gustad 8'h2B | (~8'h2B) - Hamlet in Verilog http://gustad.comArticle: 33985
Here we need to support various foundries, so this is the general design
methodolgy:
1) VHDL - ModelTech Vcom/Vsim - Functional Simulation(unit delays) via Test
Benches
2) Synopys Dc_shell/DAnalyzer
3) Place & Route(Foundry Specific)
Altera - Max2Plus
Xilinx - Alliance & XACT 5.2(For Legacy fpgas)
Quicklogic - Quickworks/QuickTools
4) Obtain post-route vhdl and delay definition from the foundry specific tools
and run post-route
functional(w/ delays) simulation on ModelTech Vcom/Vsim
Article: 33986
Reading the excerpt from my post it looks like I miscommunicated. A function call
in VHDL, if it does not use signals as input, should result in hardcoded constants.
As you point out, you can also just use a hardcoded table of constants. I do that
often especially when you have a table of constants derived from trig functions or
log functions etc. If the constants change depending on the application, you can
use yor C program to print out a complete VHDL package file containing a generated
table of constants. That way, for example if you are doing something like a log
converter for an arbitrary base, you run you C program to generate a package
containing the constants and then compile your VHDL including the package.
Sometimes generating the constants needed in VHDL can be a real pain, especially
for transcendentals in code that needs to be synthesizable. Below is such a
package file generated by a C program. This package is for a log magnitude
computer. The C gui lets you chose the log base, and the package is generated from
that:
---parameters package generated by parameters.cpp program
--
--File: PARAMETERS.VHD
--Design Units: Parameters package
-- Test_vectors (text file)
--Purpose: Contains all parameters to control design
-- implementation:bit widths, precision etc
--
--
--Note: Synthesizable under Synplicity 5.08a for Altera
--
--Limitations: Care should be taken when altering this file by hand:
-- specifically, several constants including the
-- ROM tables are dependent on the number of iterations
-- and the widths of some data paths. Users are
-- strongly encouraged to use the parameters.exe
-- program to generate new parameters.vhd files with
-- the appropriate test vectors file.
--
--Errors: none Known
--
--library: atan pacakge (ATAN.VHD) required for type definitions
--
--
--
--Author Automatically Generated by PARAMETERS.EXE
-- Andraka Consulting Group, Inc.
-- 16 Arcadia Drive
-- North Kingstown, RI 02852
-- +1 401-884-7930 FAX +1 401-884-7950
-- email: randraka@ids.net
-- http://users.ids.net/~randraka
--
-- copyright (c) 1999, Andraka Consulting Group, Inc. All rights reserved
--
--
--
--
--
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.atan.all;
package parameters is
type TABLE_TYPE is array (NATURAL range <>) of integer;
type TABLE_DEF is (LOG_MANTISSA, LOG_EXPONENT, FP_MANTISSA);
type OUTPUT_TYPE is (LOG,FLOAT);
constant output_format: OUTPUT_TYPE:= LOG;
constant angle_system: ANGLE_UNIT:= BAM;
constant input_width: integer:= 32;
constant cordic_rotator_width: integer:= 11;
constant cordic_phase_width: integer:= 11;
constant cordic_iterations: integer:= 6;
constant phase_output_width: integer:= 9;
constant mag_table_input_width: integer:= 8;
constant mag_table_output_width: integer:= 8;
constant exp_table_output_width: integer:= 12;
constant fract_mag_bits: integer:= 4; --used only by test bench
--cordic_gain= 1.646492;
--cordic_offset without round= 843;
-- w/ rounding= 840;
constant cordic_offset: integer:= 840;
--log base = 1.122018
--log_mantissa look up table
-- table format is 4.4
constant MANT_LUT: TABLE_TYPE:= (
0, 1, 2, 3, 4, 5, 6, 7, -- 0:7
8, 9, 10, 11, 12, 13, 14, 15, -- 8:15
16, 17, 18, 19, 20, 21, 21, 22, -- 16:23
23, 24, 25, 26, 27, 28, 29, 29, -- 24:31
30, 31, 32, 33, 34, 34, 35, 36, -- 32:39
37, 38, 38, 39, 40, 41, 42, 42, -- 40:47
43, 44, 45, 45, 46, 47, 48, 48, -- 48:55
49, 50, 51, 51, 52, 53, 54, 54, -- 56:63
55, 56, 56, 57, 58, 59, 59, 60, -- 64:71
61, 61, 62, 63, 63, 64, 65, 65, -- 72:79
66, 67, 67, 68, 69, 69, 70, 70, -- 80:87
71, 72, 72, 73, 74, 74, 75, 75, -- 88:95
76, 77, 77, 78, 79, 79, 80, 80, -- 96:103
81, 81, 82, 83, 83, 84, 84, 85, --104:111
86, 86, 87, 87, 88, 88, 89, 89, --112:119
90, 91, 91, 92, 92, 93, 93, 94, --120:127
94, 95, 95, 96, 96, 97, 98, 98, --128:135
99, 99, 100, 100, 101, 101, 102, 102, --136:143
103, 103, 104, 104, 105, 105, 106, 106, --144:151
107, 107, 108, 108, 109, 109, 110, 110, --152:159
111, 111, 111, 112, 112, 113, 113, 114, --160:167
114, 115, 115, 116, 116, 117, 117, 117, --168:175
118, 118, 119, 119, 120, 120, 121, 121, --176:183
121, 122, 122, 123, 123, 124, 124, 125, --184:191
125, 125, 126, 126, 127, 127, 128, 128, --192:199
128, 129, 129, 130, 130, 130, 131, 131, --200:207
132, 132, 132, 133, 133, 134, 134, 135, --208:215
135, 135, 136, 136, 136, 137, 137, 138, --216:223
138, 138, 139, 139, 140, 140, 140, 141, --224:231
141, 142, 142, 142, 143, 143, 143, 144, --232:239
144, 145, 96, 96, 96, 96, 96, 96, --240:247
96, 96, 96, 96, 96, 96, 96, 96 --248:255
);
--log_exponent look up table
-- table format is 8.4
constant EXP_LUT: TABLE_TYPE:= (
2890, 2794, 2697, 2601, 2505, 2408, 2312, 2216, -- 0:7
2119, 2023, 1927, 1830, 1734, 1638, 1541, 1445, -- 8:15
1349, 1252, 1156, 1060, 963, 867, 771, 674, -- 16:23
578, 482, 385, 289, 193, 96, 0, -96 -- 24:31
);
end package parameters;
Duane Clark wrote:
> Ray Andraka wrote:
> > If they are constant (ie not dependent on a signal) then they should get
> > hardcoded as a constant.
>
> Yes, I might go ahead and do that. It occurred to me after posting this,
> that since I already had written some C code that generates these, a
> simple change would enable it to print them out in a VHDL friendly
> format that I could just cut and paste.
>
> > Another alternative to writing a function would be
> > to use a generate statement and assign a local constant a computed value
> > based on the for...generate index. I do this frequently for generating RLOCs
> > for placing xilinx primitives.
> >
> > FOO:for i in 1 to 20 generate
> > constant bar:std_logic_vector(9 downto
> > 0):=std_logic_vector(to_unsigned(i*i,10));
> > constant rloc_string:string:="R" & itoa(9-i/2) & "C0.S1";
> > attribute RLOC of U1:label is rloc_string;
> > begin
> > U1:...
>
> Hmm... That is a very good idea! Thanks, I will definitely be using that
> soon.
>
> Duane
>
> --
> My real email is akamail.com@dclark (or something like that).
--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
Article: 33987Assuming you have just one clock cycle per multiply, and that your multiplier is wide enough that a look up doesn't cut it, then your best bet is a "limited set" multiplier. See the multiplier page on my website for details. For just two constants, you get a 3xN partial product per column of LUTs. If you were to use the standard virtex parallel multiplier structure from coregen, you'd have only a 2xN partial product per lut, plus you'd probably want to register the input because you'd have a high fanout into a carry chain. Another alternative is to use BRAMs for your partial products. That would use less CLBs, but uses up the BRAM pretty quickly, and can't be made as fast as a strictly lut based design. "K.O" wrote: > hello, > > i want to implement a prallel multplier for VIRTEX family, which toggles between > two values. > what's the optimal one in terms of area > > thanks -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.comArticle: 33988
hi. i am a new user to the virtex2 and i am having trouble finding documentation on how to set up the clocking. here is my configuration: i have an input clock going to an IBUFG and then to a DCM. On the DCM, i am using the CLK0, CLK180, and CLKDV outputs. these three outputs are going to three BUFGMUX's (i would rather use BUFG's but i am not sure if they are still supported). my goal is to constrain the placement so that all of the BUFGMUXs are on the same edge of the chip (or quadrant if that is possible) along with the DCM. any assistance would be greatly appreciated. skitzArticle: 33989
Both of you are capable of better, helpful answers. Don't encourage trolls in this newsgroup... and don't ridicule persons who might legitimately be asking questions for the first time > > Also, how long should a piece of string be. > Hopefully longer than the cave you are in. :-)Article: 33990
Hi all, I am working on a new design , using Virtex II 2V250FG456. Is there a source for Orcad symbols (.olb) for Virtex II family parts or do I need to generate my own ?. Thanks, Benoit.Article: 33991
Hi; I'd like to find out if anyone has been using this tool suite from Xilinx, along with Matlab/Simulink and either Alliance or Foundation tool suite from Xilinx. There are some engineers that I work with that have shown some interest in this package and I'd like to hear/relay any current experiences that others have had to my users. Thanks, BobArticle: 33992
Orcad Capture 9.1 (or maybe 9.2) and later has a GENERATE PART function, I think it's under the TOOLS menu. It generates schematic symbols from Xilinx database files (or Altera, for that matter). It may not be a symbol that is exactly to your liking, but it automates the most excruciating and critical task: getting *all* of the pins/pin names/pin numbers/power pins into an editable schematic symbol. You can then cut/paste or copy these pins to a multi-part symbol of your more customised design. This is much less tedioius than manual entry, and much less error prone. -- Bob Elkind, the e-team Benoît wrote: > Hi all, > > I am working on a new design , using Virtex II 2V250FG456. > > Is there a source for Orcad symbols (.olb) for Virtex II family parts > or do I need to generate my own ?. > > Thanks, > > Benoit.Article: 33994
Hello Petter, As I stated in my initial response the functionality will be the same, only the GUI will change. So Solaris support and implementation options will not be removed. Best regards, Kamal Patel Petter Gustad wrote: > Marius Vollmer <marius.vollmer@uni-dortmund.de> writes: > > > Kamal Patel <kamal.patel@xilinx.com> writes: > > > > [Alliance being discontinued.] > > > > > That is correct Robert. > > > > Does this mean that Solaris will no longer be supported as a > > place-and-route platform? > > Then does this also mean no more distributed par (i.e. -m nodefile) > runs :-( > > Petter > -- > ________________________________________________________________________ > Petter Gustad 8'h2B | (~8'h2B) - Hamlet in Verilog http://gustad.comArticle: 33995
Don't email to me please, I'm posting on behalf of Abhimanyu Rastogi <abhi_rastogi@hotmail.com>. This fellow posted yesterday, I posted a followup, and he needs some gentle hand holding through his first work-study project. I'm not in a position to "adopt" him, but perhaps the group as a whole can provide enough free minutes and free energy to help him. ============================== Hi, Sorry to bother u again..... i have a quick question I need a good approach to write a code for an interface document i wrote... i've tried a few approaches to write the code in AHDL myself...... and i'm still woeking on it.... but i was wondering if u could give me some proper direction on how to go about write the code in AHDL..... i have attached the interface document..... I really appreciate ur help.... Thx Abhimanyu Rastogi PS. Since i'm on a work-term .... i can't contact my teachers and TA..... besides they are not in the same city...... <3-page spec document from original email deleted>Article: 33996
Abhimanyu Rastogi: Here are my suggestions: 1. Typically a spec is written from the "top - down". Starting at the top level of the board or system design, provide a description of what the overall system or sub-system functions are. As the spec progresses, the lower levels of design are filled in: how each sub-function (or sub-sub-function, etc.) are partitioned "architected". This continues until the entire design is described and implemented. Typically, the spec is never "completely finished" in the abstract sense, but is complete enough to describe the lowest level components (and their interactions and interfaces) well enough to be designed and debugged. I'm not sure if you have that level of detail (or the overall high-level design view) in your spec, yet. Critically reviewing and critiquing your spec requires more than a few casual minutes of attention. 2. In the absence of a beautifully written spec, do this: Take out a pad of paper, and draw a bubble or a box for each of the functions of the FPGA design. Add to each bubble a list of input and output signals. Then, for each box, on a separate page, draw a flow-chart of the box. If the flow-chart is too complex to fit on one page, then break the box up into smaller, simpler boxes that *can* be flowcharted on one page. This set of flowcharts will be your "map" for the FPGA design. 3. Each flow-chart needs to be translated into design code. A one-page flow-chart is about the right level of complexity for a corresponding code "module" or routine, or function. Design and implement and simulate these low-level function individually. They are small enough (in terms of complexity) to allow you to see the coding language issues as well as the design issues that will need to be solved in the course of the design. 4. When you are all done, the whole design needs to be tied together in code, just as they are tied together in your hierarchical flowcharts. After having done 5 or 6 of the low-level flowchart design implementations, you'll be starting to develop a design style. Revisit the first modules that you've implemented, and update them if you think that you would do them differently based on what you've learned along the way. This isn't a 1-semester course in design methodology, but it is one approach that can help get you on your way. In my opinion, you've either taken on more than you can handle, or someone has thrown you a boat-anchor and told you to swim. Congratulations and welcome to the world of design engineering. A. If you are working in a work-study program, there should be a mentor available for you - on the job. Is there anyone responsible for reviewing your work? That would be the logical place to start looking for an on-site mentoring resource. B. If this was arranged by one of your profs, then you need to get support along the way from your prof or TA. The argument that they are out of city doesn't hold. Phone lines and email don't care whether or not you're in the same city. C. If you have no support from either the company for whom you are working, or the school that is sponsoring you, then you should not have been given (or accepted) this assignment/job. You may get the help you need from this newsgroup, but your situation is *NOT* this newsgroup's responsibility. Having said that, I wish you well, and I encourage you. Don't give up. -- Bob Elkind, the e-team fpga/design consulting bob elkind wrote (on behalf of Abhimanyu Rastogi): > Don't email to me please, I'm posting on behalf of Abhimanyu Rastogi <abhi_rastogi@hotmail.com>. > This fellow posted yesterday, I posted a followup, and he needs some gentle hand holding through > his first work-study project. I'm not in a position to "adopt" him, but perhaps the group as a whole > can provide enough free minutes and free energy to help him. > > ============================== > > Hi, > > Sorry to bother u again..... i have a quick question > I need a good approach to write a code for an interface document i wrote... i've tried a few approaches to write the code in AHDL myself...... > and i'm still woeking on it.... but i was wondering if u could give me some proper direction on how to go about write the code in AHDL..... i > have attached the interface document..... > > I really appreciate ur help.... > > Thx > Abhimanyu Rastogi > > PS. Since i'm on a work-term .... i can't contact my teachers and TA..... besides they are not in the same city...... > > <3-page spec document from original email deleted>Article: 33997
I've tried it. Your experience with it will depend on what you expect out of it. For the average designer who knows little to nothing about hardware DSP, and for the Systems guy who knows nothing about hardware design, this is a great tool. It lets you get into DSP in the FPGAs without having to know alot of the gory details. It is basically is a front end for putting the Xilinx DSP coregen macros into a design and simulating them in a way that is more DSP friendly. If you can do your design with the coregen macros, then it is not a bad tool. Designers already doing DSP designs in FPGAs may find the tool too immature to compete with the designs they are already doing, so those users may not be as smitten with the tool. The tool does a good job with the coregen pieces, but control logic as well as your own DSP macro designs can be difficult to deal with through the tool. For the price, it is a worthwhile tool to add to your arsenal. Robert Myers wrote: > Hi; > > I'd like to find out if anyone has been using this > tool suite from Xilinx, along with Matlab/Simulink and > either Alliance or Foundation tool suite from Xilinx. > > There are some engineers that I work with that have > shown some interest in this package and I'd like to > hear/relay any current experiences that others have > had to my users. > > Thanks, > Bob -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.comArticle: 33998
Hi, You might try connecting the Atmel READY pin to the Xilinx PROGRAM pin. This guarantees that the Atmel will hold off the Xilinx until it (the Atmel) is ready to operate. It is suggested in the Atmel Apps. This is the way I have it and I have had no config problems. Dave Colson Markus Meng wrote: > Hi all, > > concerning a prototype board serie we do have a configuration > problem with ~ 50% of the board produced. The problem > looks that the serial configuration in Master Mode does not take > place the first time. An external Watchdog does reinitiate the > configuration process ~ 1.6sec by forcing the program pin low. > Then the Spartan-II device XC2S150 restart the configuration > in Master Mode. Since there is no possibility the 'see' that the > CRC for example is wrong, nothing happens the DONE-pin > remains low. We use the ATMEL part 17LV010. Are there > any known issues regarding this combination? > > In the Xilinx Tool chain I did NOT select anything special, just > the defaults. Looking into the details with a scope I saw that the > CCLK ~3.1 MHz. This is maybe a reasonable value. > > Any help would be appreciated! > > markus > > -- > ******************************************************************** > ** Meng Engineering Telefon 056 222 44 10 ** > ** Markus Meng Natel 079 230 93 86 ** > ** Bruggerstr. 21 Telefax 056 222 44 10 ** > ** CH-5400 Baden Email meng.engineering@bluewin.ch ** > ******************************************************************** > ** Theory may inform, but Practice convinces. -- George Bain **Article: 33999
Thx again.... for all the suggestions.... i'm sure they'll help me a lot.... and yeah....i like the way u use humour....with the words of knowledge... Well, i'm just a 2nd yr student....and i love to take challenging jobs..... and in engineering u know that nobody gives up...... VHDL and FPGA is a 4th yr course .... so... b4 i started this job i had not much knowledge bout it.... but i've learned a lot during this work-term... Another thing...there is no ASIC expert at my workplace..... so they asked me if i would like to work on upgrading there existing altera interface.... cuz...we r putting a daughter card on to our existing module.... i said yes...why not .... n infact i've learned a lot.... reading n writing AHDL codes.... I asked for a good approach cuz.... i thought i was missing the proper way of handling FPGA's ....cuz i've learned everything myself....so far.... without ne formal training...... and i don't mind it..... and as u said not to give up...... i will not.... Thx Abhimanyu Rastogi.... bob elkind <eteam@aracnet.com> wrote in message news:3B73F0C7.B8C7B02C@aracnet.com... > Abhimanyu Rastogi: > > Here are my suggestions: > > 1. Typically a spec is written from the "top - down". Starting at the top level of the board or system design, provide a description of what the > overall system or sub-system functions are. As the spec progresses, the lower levels of design are filled in: how each sub-function (or > sub-sub-function, etc.) are partitioned "architected". This continues until the entire design is described and implemented. Typically, the spec > is never "completely finished" in the abstract sense, but is complete enough to describe the lowest level components (and their interactions and > interfaces) well enough to be designed and debugged. > > I'm not sure if you have that level of detail (or the overall high-level design view) in your spec, yet. Critically reviewing and critiquing your > spec requires more than a few casual minutes of attention. > > 2. In the absence of a beautifully written spec, do this: Take out a pad of paper, and draw a bubble or a box for each of the functions of the > FPGA design. Add to each bubble a list of input and output signals. Then, for each box, on a separate page, draw a flow-chart of the box. If > the flow-chart is too complex to fit on one page, then break the box up into smaller, simpler boxes that *can* be flowcharted on one page. This > set of flowcharts will be your "map" for the FPGA design. > > 3. Each flow-chart needs to be translated into design code. A one-page flow-chart is about the right level of complexity for a corresponding > code "module" or routine, or function. Design and implement and simulate these low-level function individually. They are small enough (in terms > of complexity) to allow you to see the coding language issues as well as the design issues that will need to be solved in the course of the > design. > > 4. When you are all done, the whole design needs to be tied together in code, just as they are tied together in your hierarchical flowcharts. > After having done 5 or 6 of the low-level flowchart design implementations, you'll be starting to develop a design style. Revisit the first > modules that you've implemented, and update them if you think that you would do them differently based on what you've learned along the way. > > This isn't a 1-semester course in design methodology, but it is one approach that can help get you on your way. > > In my opinion, you've either taken on more than you can handle, or someone has thrown you a boat-anchor and told you to swim. Congratulations and > welcome to the world of design engineering. > > A. If you are working in a work-study program, there should be a mentor available for you - on the job. Is there anyone responsible for > reviewing your work? That would be the logical place to start looking for an on-site mentoring resource. > > B. If this was arranged by one of your profs, then you need to get support along the way from your prof or TA. The argument that they are out of > city doesn't hold. Phone lines and email don't care whether or not you're in the same city. > > C. If you have no support from either the company for whom you are working, or the school that is sponsoring you, then you should not have been > given (or accepted) this assignment/job. > > You may get the help you need from this newsgroup, but your situation is *NOT* this newsgroup's responsibility. Having said that, I wish you > well, and I encourage you. Don't give up. > > -- Bob Elkind, the e-team fpga/design consulting > > bob elkind wrote (on behalf of Abhimanyu Rastogi): > > > Don't email to me please, I'm posting on behalf of Abhimanyu Rastogi <abhi_rastogi@hotmail.com>. > > This fellow posted yesterday, I posted a followup, and he needs some gentle hand holding through > > his first work-study project. I'm not in a position to "adopt" him, but perhaps the group as a whole > > can provide enough free minutes and free energy to help him. > > > > ============================== > > > > Hi, > > > > Sorry to bother u again..... i have a quick question > > I need a good approach to write a code for an interface document i wrote... i've tried a few approaches to write the code in AHDL myself...... > > and i'm still woeking on it.... but i was wondering if u could give me some proper direction on how to go about write the code in AHDL..... i > > have attached the interface document..... > > > > I really appreciate ur help.... > > > > Thx > > Abhimanyu Rastogi > > > > PS. Since i'm on a work-term .... i can't contact my teachers and TA..... besides they are not in the same city...... > > > > <3-page spec document from original email deleted> > >
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