Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Harjo Otten wrote: > > Hi, > > We're creating an PCI interface card that hold 8 serial ports. In my FPGA > desing (Spartan II) I've created two (for every port) three processes. One > that shifts data in, one that shifts data out and one that gets data from > and sends data to the PCI core (Xilinx). > > These shifter processes use a clock frequency divided from the 'master > clock'. Now here's my problem: I get a lot of gated clocks when I implement > it like this, but since the frequency is very low (128K max )every thing > works fine. When I try to remove these gated clocks (I'm still not sure on > how to do this, but usually I try to implement clock buffers) I get the > message that there are not enough clock buffers available. I must say that > sounds pretty logical to me since there are only 4 clockbuffers in our > Spartan and at least 9 clocks (one for every port, and one for the master > clock). > Does anybody have any idea on how to remove the gated clocks in this desing, > or should I just ignore them ?? I've seen different comments on gated clock > questions lately, so I'm a bit confused..... > > thanx, > > H. change all the uart clks to clk enables, and run everything of the master clk -Lasse -- Lasse Langwadt Christensen, -- A Dane in Phoenix, ArizonaArticle: 35251
Speedy Zero Two wrote:
>
> Hi,
>
> Hmm, Gated clocks.......
>
> I have two examples where this "warning" arises,
>
> firstly,
>
> assign out = enable && clk;
> The enable may go high while clk is high and give a shortened pulse.
unless out is used to clk something I don't think this should give
a gated clk warning, more likely some thing like "using clk as data"
another issue is if the enable is out of a FF clk'ed by clk, because
the clk used for the assignment may not be from the fast clk net
and skewed so there will be a glitch
>
> secondly, this one I found recently,
>
> wire reset = (counter ==6);
> always @(.....clk or ......reset)
> begin
> if (reset) counter =0; else counter = counter +1;
> end
>
> The counter is reset if the output equals 6, but during transactions there
> is an undetermined state so a reset may occur sxporadically !!
that's also a pretty ugly, something like this would be nicer
always @(.....clk)
begin
if(counter == 5)
counter = 0;
else
counter = counter + 1;
end
-Lasse
-- Lasse Langwadt Christensen,
-- A Dane in Phoenix, Arizona
Article: 35252Thanks for the suggestion. One more enquiry though (I am a newbie, after all). Using the Core generated BlockRAM, will it automatically be put into one of the available BlockRAMs on the Spartan II, or do I have to add locational constraints. Thanks adrian > I would suggest putting this big LUT in one of the available BlockRAMs, each of > which is 4096 bits, organized any way you want ( and dual-ported, although that > feature may not be any advantage in your case). > Saves area and routing, and will most likely be faster. > > Remember, you can obviously use any Virtex/SpartanII 4096 bit dual-ported RAM or > ROM=LUT also as two totally independent single-port 2048 bit RAMs or ROMs.Article: 35253
Nial Stewart <nials@britain.agilent.com> writes: > Martin Thompson wrote: > > All on a current design of mine which is 64% of LEs and ~50% of EABs > >in a FLEX10K100E. > > I wonder if this is pushing the tools hard enough to see distinct > differences in compilation times? > True enough - I just whacked in what I have working currently. If anyone wants to offer some bugger/more demanding files for more tests, I can probably bench them as well. <snip results> > I wonder if the tools don't run much better on a P4 because they're > not optimised for it? That seems to be the general excuse for P4 > performance against Athlons running slower. > Probably true, but none of the vendors have told me when/whether they will ship Althon and/or P4 optimised code. Are they likely to want to support two binaries for "Intel" architected machines? > If you can, what about trying the same tests on a 1.4G Althlon with > >512M DDRam? > > Nial. Hopefully I can get one on loan - or if anyone has one, I may be able to get my code released for someone to test. Cheers, Martin -- martin.j.thompson@trw.com TRW Automotive Technical Centre, Solihull, UKArticle: 35254
John_H wrote: > Please let us know > 1) synthesis tool, > 2) coding language > > Jens-Christian Lache wrote: > > > Hi! > > To reduce the fanout of a tristate signal leading to 64 iobs I > > tried dublicate this signal. How do I tell > > the synthesis tool now not to remove my dublicated logic? > > ( I tried to use a BUFG as well, but that didn't work at all) > > thanks for your help, > > -jc- The synthesis tool is synopsis fpga express. -jc-Article: 35255
Hi, I am looking for an application note on how to program a flash that is connected to the pins of a small PLD (XC9500). Later the PLD/flash combination should boot an FPGA. But first I need a way to programm the flash through the JTAG interface of the PLD. Is this possible ? Is there some software available to do this ? I think it should be somthing like a scriptable JTAG tool set.... Everything I found are app notes that describe the booting of the fpga though the PLD/flash combination but noone cares about programming the flash for the first time :-) Any ideas or experiences ? MatthiasArticle: 35256
Hi Does anyone know how I can simulate a faster clock using the maxplus waveform editor? The fastest clock I can simulate is one with a period of 200ns, because the default resolution on maxplus is 100ns. Thanks AndrewArticle: 35257
Patrick Hibbs wrote: > Also, I've killed a few 2000E's by starving them of current. > Make sure to have voltage regulators that can handle the > current demands. Ouch - how did that kill them? I would have thought that a good but weak (current limiting) regulator wouldn't damage the devices... Failure modes that I can think of: regulator oscillations or overshoot (shouldn't happen), or dangerously corrupted configuration due to out of spec voltages (seems unlikely). - Reinoud (Spam goes to wanabe, mail to wanadoo.)Article: 35258
Hi, I'm having a problem creating a core generated Single Port Block Ram which is read only. The core generator does not seem to be including my .coe file data which looks like this: memory_initialization_radix = 16; memory_initilization_vector = 0,0,0,0,1, ...,B; (64 entries) has anyone experienced a similar problem with this core? thanks adrianArticle: 35259
Forgot to add: The core generator says that 90% of the core was unplaced.Article: 35260
Open the "waveform editer" (via MaxPlusII button) If the waveform editor is the active window then in OPTIONS there is an option GRID SIZE. Here you can change your default grid size. This grid size is used (as far as I know) for the clock generation (Edit > overwrite > clock) Egbert Molenkamp "Andrew Gray" <andrew@tuks.co.za> wrote in message news:1001585216.341147@nntp.up.ac.za... > Hi > > Does anyone know how I can simulate a faster clock using the maxplus > waveform editor? The fastest clock I can simulate is one with a period of > 200ns, because the default resolution on maxplus is 100ns. > > Thanks > > Andrew > >Article: 35261
Hi, You can also switch off the "Snap to Grid" Option to get rid of all restrictions. HTH, CarlhermannArticle: 35262
"Noddy" <g9731642@campus.ru.ac.za> wrote in message news:1000966178.498009@turtle... > Could someone please tell me a shorter method for doing the following. Using > Foundation 3.1, I first implement my design, and once it is implemented, > then can I use the Xilinx Constraints Editor to provide timing constraints. > Once this is done, I need to implement my design again. I have to go through > this entire process every time I make changes in my design (due to net name > changes etc.). > Is there a quicker way?? This process takes me about 20 minutes (20minutes I > could spend doing something more productive than waiting around) > If you're using a schematic then attach the constraint to the net (from the net naming dialog box). There's probably a similar way to attach the constraints within the source (eg. VHDL file) but I don't know it.Article: 35263
If you can use the period constraint, you won't be subjected to the net name
changes. If you must use the from:to, then select the sources adn destinations
as registers in your design, as these tend to have more stable names. You can
also attach TNMs to signals in the design to create names for groups of signals
that won't change with resynthesis. These follow the same usage rules a s
described for schematics in the xilinx documentation. Use user attributes to
attach the tnms to signals or component labels:
attribute TNM:string;
attribute TNM of U1:label is "signal_source";
attribute TNM of net:signal is "signal_net";
peterc wrote:
> "Noddy" <g9731642@campus.ru.ac.za> wrote in message
> news:1000966178.498009@turtle...
> > Could someone please tell me a shorter method for doing the following.
> Using
> > Foundation 3.1, I first implement my design, and once it is implemented,
> > then can I use the Xilinx Constraints Editor to provide timing
> constraints.
> > Once this is done, I need to implement my design again. I have to go
> through
> > this entire process every time I make changes in my design (due to net
> name
> > changes etc.).
> > Is there a quicker way?? This process takes me about 20 minutes (20minutes
> I
> > could spend doing something more productive than waiting around)
> >
>
> If you're using a schematic then attach the constraint to the net (from the
> net naming dialog box).
>
> There's probably a similar way to attach the constraints within the source
> (eg. VHDL file) but I don't know it.
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 35264Hi, Does anyone have a *formal* syntax description for UCF as used in the Xilinx 3.x tools? I know UCF is described in the Xilinx documentation, but I'm looking for something that is concise, complete and correct. BNF etc. would be ideal. I'm writing a syntax highlighting description for my source code editor. Bye, Allan. P.S. If anybody mentions "emacs" in a reply I will put them in my kill file :)Article: 35265
I am searching this for some time now. I need it to programm the old XC3000. Has anybody a clue how to get it ? Thanks a lot JAK PS: Ah yes, please feel free to email any suggestion to josi.kein@gmx.netArticle: 35266
Not sure if you need to design an FIR filter ASIC, or if finding one to use in your project is OK. If it is the later, try: http://www.graychip.com/GC2011/GC2011.html Regards - Brad Evans kuldeep wrote: > > thanx robert but unfortunately i cannot change the coefficients to > suit this method :-( so i have to look for some other method. any more > pointers will be appriciated. > --kuldeep > > "RM" <yeren@gmx.de> wrote in message news:<9oq2pu$i9q$1@f40-3.zfn.uni-bremen.de>... > > the following reference (you can get more by google'ing with FIR BIT SERIAL > > ftp://ftp.ittc.ukans.edu/pub/projects/DSP/FPGA/Bit_Serial.pdf > > is intended for FPGA use, but it _might_ be suitable for asic, too, because > > it > > is on designs that only include bit shift operations and additions instead > > of > > multiplications. Bad side effect: you will have to calculate a new filter > > that > > meets the restrictions of the method.. > > robert > > > > "kuldeep" <kkdeep@mailcity.com> schrieb im Newsbeitrag > > news:a0f016a9.0109250458.7bb874f1@posting.google.com... > > > i have to implement a 64 tap FIR filter with fixed coefficients in > > > hardware. I have found some architecture suitable for fpga (using LUTs > > > of fpga) which don't use multipliers. can somebody point me to > > > architecture suitable for ASIC?. Since the coefficients are fixed, i > > > want to optimize or avoid the multipliers.The input sample rate is 16 > > > MHz with 12 bits (in 2s complement). > > > thanx > > > kuldeepArticle: 35267
Hi jacky , Thanx for reply. This seems to be good architecture as i can tradeoff throughput with hardware . Fully serial approach will not work for me as my input data is coming at 16Mhz, 12-bit wide. That means i need clock of 192MHz (16x12) which i can't afford .correct me ..so i will go for some mix of serial -parllel approach. i have two doubts: quoting a line from ur reply : 1."you better add coefficient before feeding the partial products table" Here do u mean adding inputs (for which coeffcient happen to be same) before feeding the partial product table? Plese elaborate further how can i take advantage of symmetrical coeffcients. 2. i have odd number (65) coeffcients. Each LUT take 4 coeff. so where will the last coeff go?? should i use 1 LUT for this single coeff. thanx and regds KuldeepArticle: 35268
Hi, I'm working on a new design , and I think using ALTERA APEX EP20K600EBC652 - 2. (and Flash EPC8) Do someone know where I could find the Orcad symbols (.olb) for these components. Thanks, B HAMON. bhamon@elios-informatique.frArticle: 35269
hi,
I have a problem which I feel difficult to explain.
library ieee;
use ieee.std_logic_1164.all;
entity test is
port(
A: in integer range 0 to 127;
Y: out integer range 0 to 127
);
end test;
architecture test_bev of test is
signal B: integer range 0 to 127;
begin
process (A) --process A
begin
B <= A;
Y <= B;
end if;
end process;
end test_bev;
As for my understanding, the process A will only execute when change on
signal A. So Let say, I only change the value A for once, this value should
be assigned to B; Mean while Y is assigned with OLD B value. As long as no
change on signal A, this process will be suspended, i.e Y == value of OLD B.
However, when I simulate using MAX+PLUS II, the results show that Y is
update to A input values after short delay. As if the sensitivity list does
not have any effect .. ( Or may be the compiler has included all the signal
into sensivity list ...)..
Article: 35270Hi Matthias, The only big disadvantage of SRAM fpgas is: there is no single chip solution.You always need a configuration memory on startup. The ideal configuration memory is available from XILINX: The XC18V00 series of jtag in system programmable fpga proms - see http://www.xilinx.com/partinfo/ds026.pdf They work well, but are difficult to get and expensive. There is often a byte or word wide flash memory in the system which could be used for the fpga configuration. You can built your own cpld prom loader with a jtag interface, but you must use a separate jtag chain for the cpld and the prom loader. The jtag interface is well documented and simple, but the spi interface needs less logic to implement. The spi interface is a simple 4 wire interface for data transfer from a master to a slave device: spiclk - data transfer clock, data is valid after the negative edge and taken at the positive edge. spics - chip select, syncs frame start and end spimosi - master out / slave in spimiso - master in / slave out Consider a PC with its parallel printer port as a spi master. Connect spiclk,spics,spimosi to any of the printer output databits, and spimiso to any input of the port. Your cpld is the spi slave. Create a spi frame format, e.g.: For a 16bit wide 128kByte parallel flash you need to transfer a 16bit address for the flash and a 16bit dataword for each address. Define a command set. Reading and writing of flash data and address are required commands. Also a command for address auto incrementing would be nice. Simple 4 bit command : bit3 - read=0/write=1 bit2 - data=0/address=1 bit1 - address auto increment enable =1 bit0 - not used or device selector A flashdata fd read from address fa has the following frame format (2 frames): <command 110x> <fa> <command 001x> <fd> The next read command fetches data from fa+1: <command 001x> <fd> Writing data to the flash uses the command 101x and so on. Write a Visual Basic application that transfers data in spi frames to the flash prom. The solution is simple and works well in several applications. The downloading time is about 2 minutes for 64kBytes with address increment option. The logic fits into a XC9572XL. For less power consumption and less costs you can use a mix of XC9536XL and some 74HC595 shift regs. A detailed application note will be availlable in the future on my website. Mike "Matthias Fuchs" <matthias.fuchs@esd-electronics.com> schrieb im Newsbeitrag news:3BB2E378.38B42639@esd-electronics.com... > Hi, > > I am looking for an application note on how to program a flash that is > connected to the pins of a small PLD (XC9500). > Later the PLD/flash combination should boot an FPGA. But first I need a > way to programm the flash through the JTAG interface of the PLD. Is this > possible ? Is there some software available to do this ? I think it > should be somthing like a scriptable JTAG tool set.... > > Everything I found are app notes that describe the booting of the fpga > though the PLD/flash combination but noone cares about programming the > flash for the first time :-) > > Any ideas or experiences ? > > MatthiasArticle: 35271
Hello to the newsgroup, maybe some of you may help me. I'm a newbie in FPGA programming, so I apologize from now if I am going to ask silly questions. I have some VHDL code I have to synthesize on Altera Flex10K devices. I use Leonardo Spectrum, version v20001a2.75. Altera docs say Flex10K devices contain some EAB blocks, and these blocks can contain complex functions (like multipliers), or implement RAM (each EAB should contain 2048 memory bits). I would like to implement some logic in these blocks, in order to save space among the other logic cells. How can I instruct Leonardo Spectrum to put into these EABs my design units? Leonardo Spectrum docs and Altera docs say it is necessary to specify these attributes: ATTRIBUTE logic_option:STRING; ATTRIBUTE noopt:BOOLEAN; ATTRIBUTE logic_option OF u1:LABEL IS "implement_in_eab=on"; ATTRIBUTE NOOPT of u1:LABEL IS TRUE; where u1 is an instance of a component, specified in a VHDL architecture block Well, I tried to synthesize the example from Leonardo docs (p.146 of Leonardo Spectrum Synthesis and Technology Manual - leospec_tech.pdf) with and without these lines, and the result is the same. The report indicates the same usage statistic, and the netlist is the same and doesn't contain EAB blocks (only F1_LUT,F2_LUT,F3_LUT,CARRY and similar). Shouldn't I see in the synthesized netlist the instantiation of some EAB blocks? Am I doing something wrong? Thanks in advance for your answers, Aldo Romani -- Posted from micro202.deis.unibo.it [137.204.56.202] via Mailgate.ORG Server - http://www.Mailgate.ORGArticle: 35272
Thanks for the suggestion... did it, but it appears I get better placer scores using the distrbted arithmetic instead. Also, (I'm using the LUT's in a digital mixer), I get timing problems using the Block RAM, but not using the DA. adrian > I would suggest putting this big LUT in one of the available BlockRAMs, each of > which is 4096 bits, organized any way you want ( and dual-ported, although that > feature may not be any advantage in your case). > Saves area and routing, and will most likely be faster. > > Remember, you can obviously use any Virtex/SpartanII 4096 bit dual-ported RAM or > ROM=LUT also as two totally independent single-port 2048 bit RAMs or ROMs. > > Peter Alfke, Xilinx ApplicationsArticle: 35273
yaohan schrieb: > > However, when I simulate using MAX+PLUS II, the results show that Y is > update to A input values after short delay. As if the sensitivity list does > not have any effect .. ( Or may be the compiler has included all the signal > into sensivity list ...).. yes. From my point of view, the sensitivity list is just some kind of dinosaur from the good, old days when VHDL was defined and the guys wantet to make the language designed according to theoretical standards. Nowaday (and even in the good old days) a compiler should have no problem to find the input signals of a process (clocks, data) by itself. -- MFG FalkArticle: 35274
There is one think I forgot to tell you: The CLB-LUT is a combinatorial device: You give it a new address input, and you get the new output "immediately", i.e. within a nanosecond or two. The BlockRAM ( or BlockROM) is a clocked device, even in its read operation. You get the new output after applying the next clock edge (You decide on rising or falling). This sequential behavior has its advantages and disadvantages, but in any case, you must be aware of it. Sorry for not telling you before. "Better placement" is puzzling. If you have an unused BlockRAM, it takes no extra space at all, while your CLB implementation takes a fair number of CLBs and routing resources. Peter Alfke, Xilinx Applications. ======================== Noddy wrote: > Thanks for the suggestion... did it, but it appears I get better placer > scores using the distrbted arithmetic instead. Also, (I'm using the LUT's in > a digital mixer), I get timing problems using the Block RAM, but not using > the DA. > > adrian > > > I would suggest putting this big LUT in one of the available BlockRAMs, > each of > > which is 4096 bits, organized any way you want ( and dual-ported, although > that > > feature may not be any advantage in your case). > > Saves area and routing, and will most likely be faster. > > > > Remember, you can obviously use any Virtex/SpartanII 4096 bit dual-ported > RAM or > > ROM=LUT also as two totally independent single-port 2048 bit RAMs or ROMs. > > > > Peter Alfke, Xilinx Applications
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z