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Hi, I am a newbie here, and I have some problem with virtex II
configuration. anybody can help me?
condition:
1,device: Virtex II (Xc2v3000) engineering sample
2,mode pins: m0,m1,m2 floating (i think they're high and mean device
is in slave mode)
3,software: 3.1i + v2 patch + 3.3 patch + service pack 8
4,implementation: Hardware debugger
5,clock freq.: 27MHz
verilog hdl source:
always @(posedge clock)
a = a + 1;
note: a is 4 bit-width. clock is 27MHz.
when synthesized by xilinx:
test result:
a[0]: 13.5Mhz,
a[1]: 13.5Mhz,
a[2]: 13.5Mhz,
a[3]: 13.5Mhz.
when synthesized by fpga advantage:
test result:
a[0]: 13.5Mhz,
a[1]: 3.3V
a[2]: 3.3V
a[3]: 3.3V
I am sure no hard-wire connection problem, is there any software
problem with my system, and could the device be configured by the
above mothod? Somebody tell me the foundation 4.1 is must, is he
right? and Xilinx don't give us the software because we are small
client. :(
Thanks in advance.
Article: 35051Uzytkownik "Kevin Brace" <kevinbraceusenet@hotmail.com> napisal w wiadomosci news:cc7b0b5f.0109160959.10769322@posting.google.com... > Does anyone know how to calculate the time it takes to program > Spartan II or Virtex I/-E/II part during power-up? You can calculate it, if you know configuration clk speed (2MHz or 8MHz) and how long is bitstrem.Article: 35052
I'm trying to generate some mcs files for the 18v04 to config a
xc2v6000. I've simply scaled up the command I've been using for the
xcv1000e:
promgen -c -w -p mcs -x xc18v04 xc18v04 xc18v04 xc18v04 xc18v04 -u 0 chip.bit
This results in:
ERROR:Bitstream:29 - 0x25b06c bytes loaded up from 0x0 exceeds maximum 0xfffff
for Mcs86 prom format.
Does this mean that you can't use MCS format for the xc2v6000 since
it results in a 20-bit overflow? It doesn't make sense since the
18v04's are the same size no matter if I'm using two of them with a
xcv1000e or five with a xc2v6000.
It seems like hex and exo is OK. tek appears to have a 64K limit on
the number of bits.
However, Xilinx jtagprog seems to only accept mcs files, even though
the error message indicated that it's looking for an exo file as well:
D:\pegu\virtex2>jtagprog -batch jtag
JTAGProgrammer:Release 3.3.06i_V2_SE2 - JTAG Boundary-Scan Download D.27
Copyright: 1991-1999
JTAGProgrammer:Release 3.3.06i_V2_SE2 - JTAG Boundary-Scan Download D.27
Copyright:1991-1999
Sizing system available memory...done.
Cable Hardware: 1
Cable Firmware: 101
Cable FPGA: c
Cable Algorithm: 100
Cable ID type is 'MULTILINX'
Cable is connected to 'usb1'
Active command: 'part XC18V04:chip_0 XC18V04:chip_1'
Loading Boundary-Scan Description Language (BSDL) file
'D:/bin/xilinx/data/xc18v04.bsd'.....completed successfully.
Checking boundary-scan chain integrity...done.
Verifying device positions in boundary-scan chain...
Instance 'chip_0' at position '1'...verified.
Instance 'chip_1' at position '2'...verified.
Verification completed.
Boundary-scan chain validated successfully.
Active command: 'erase -f chip_0'
'chip_0': Checking boundary-scan chain integrity...done.
'chip_0': Putting device in ISP mode...done.
'chip_0': Erasing device...done.
'chip_0': Erasure completed successfully.
Active command: 'erase -f chip_1'
'chip_1': Checking boundary-scan chain integrity...done.
'chip_1': Putting device in ISP mode...done.
'chip_1': Erasing device...done.
'chip_1': Erasure completed successfully.
Active command: 'program -v chip_0'
'chip_0': Checking boundary-scan chain integrity...done.
'chip_0': Putting device in ISP mode...done.
'chip_0': Erasing device...done.
ERROR:JTag - Unable to locate .exo/.mcs file chip_0.exo'.
Ensure that the path to the file is valid.
Try to remove spaces in your path name.
Check that file attributes are set to read and write.
'chip_0': Programming terminated due to error.
Active command: 'program -v chip_1'
'chip_1': Checking boundary-scan chain integrity...done.
'chip_1': Putting device in ISP mode...done.
'chip_1': Erasing device...done.
ERROR:JTag - Unable to locate .exo/.mcs file chip_1.exo'.
Ensure that the path to the file is valid.
Try to remove spaces in your path name.
Check that file attributes are set to read and write.
'chip_1': Programming terminated due to error.
Active command: 'quit'
The exo files are there:
D:\pegu\virtex2>dir *.exo
Volume in drive D has no label.
Volume Serial Number is D44D-BD68
Directory of D:\pegu\virtex2
09/19/2001 09:48p 1,474,573 chip_0.exo
09/19/2001 09:48p 1,474,573 chip_1.exo
09/19/2001 09:49p 1,474,573 chip_2.exo
09/19/2001 09:49p 1,474,573 chip_3.exo
09/19/2001 09:49p 1,048,640 chip_4.exo
5 File(s) 6,946,932 bytes
0 Dir(s) 2,449,846,272 bytes free
The board that I'm using for this test has only two 18v04's mounted
(for the xcv100e) but jtagprog should not care.
I have no problems programming the 18v04's using mcs files which I
generated for for the xcv1000e.
So how do you program your 18v04's using jtagprog and large Virtex-II
devices? I could not find any notes about this in the Virtex-II User
Guide.
Thanks.
Petter
P.S. Seems like somebody has to come up with a new file format to
support future gigabit config PROM's :-)
--
________________________________________________________________________
Petter Gustad 8'h2B | (~8'h2B) - Hamlet in Verilog http://gustad.com
Article: 35053Marius Vollmer <marius.vollmer@uni-dortmund.de> wrote: > I'm having problems mixing and matching VHDL and EDIF source files in > FPGA Compiler II. Basically, I want to instantiate a RAM block that > has been generated by the Xilinx CoreGen tool in a VHDL description. > I can't get it to work, and from the documentation that I could find, > it should just work, without any tricks. I suspect there is something > wrong with buses, since single-bit signals connect fine, while buses > don't. I've seen this. It is easy to fix. [snip] > I created a second FPGA Compiler II project, and added outer.vhdl to > it. I also added "inner.edf", the netlist exported above. The files > could be analyzed all right. When I created an implementation for the > "outer" component of the "outer.vhdl" file, I got the following > warnings: There lies the problem. I am going to assume that you are using Foundation 3.1i (or something similar), and tell you how I got it working there... There is a note somewhere on Xilinx's site specifying that you are not supposed to add the EDIF file to the project when instantiating a black box object (which is basically what you are doing here). Just create the component instantiation as usual, and when doing the Implementation "Translate" stage, it will merge the EDIF files for you before doing the Place & Route. You also have to be sure not to allow I/O pads to be inserted in the "lower" black box synthesis. Finally, be sure that the filename of the EDIF file matches your component name (other than the .edf of course). This works fine for me, although it makes simulation more painful, as you have to simulate using the timing results file, which is somewhat annoying when you are trying to do a functional simulation to prove that you designed the logic correctly, but it does work. I needed to do this as I was trying to link in several OpenCore IP cores that were written in Verilog into my VHDL project, and this seemed to be the simplest way. > Warning: Cannot link cell 'outer/comp' to its reference design > 'inner'. You will still get a warning similar to this when synthesizing. > What's going on? I'm grateful for any hints. Let me know if this helps :) Ciao. GavinArticle: 35054
Getting replicated LUTs is tough. Even the syn_keep attribute doesn't usually help out. You may need to go to annoying lengths to get what you want. I've instantiated LUT primitives before and I've hated doing it because the INIT attribute defines the logic. I don't like creatingm y own logic tables. You can invoke a lower level module (jeeze) and include a syn_hier directive on that module of "hard" or "firm" (either or both may work) to completely replicate the LUTs without optimizing one away. Without the syn_hier directive you'd probably see one external LUT that feeds both of the module instances if you looked into HDL_Analyst (or the edif). Don Husby wrote: > How do I prevent Synplify from optimizing away my > attempts to replicate logic? > > For the following code, synplify will merge the two instances > of Shift into the same net: > > wire [1:0] Shift /* synthesis syn_keep=1 */; > assign Shift[0]= Sending & !Stall | !Ready; // > assign Shift[1]= Sending & !Stall | !Ready; // Replicated > > Also, is there some way to get synplify to print a message when > it encounters an attribute? Otherwise, there's no way to tell > if the attribute has an error that causes it to not be recognized > as an attribute.Article: 35055
Instead of putting the syn_keep on Shift, which will just preserve Shift[0] and Shift[1] driven by common logic through the optimization process, you should make a copy of the most non critical input signal using syn_keep. This will keep the optimizer from merging the logic generating Shift[0] and Shift[1]. wire Sending_copy /* synthesis syn_keep=1 */ = Sending; wire [1:0] Shift /* synthesis syn_keep=1 */; assign Shift[0]= Sending & !Stall | !Ready; // assign Shift[1]= Sending_copy & !Stall | !Ready; // Replicated In the case of sequential elements like inferred flip-flops, you can use the syn_preserve attribute. This stops sequential optimizations such as merging of identical flops. Don Husby wrote: > How do I prevent Synplify from optimizing away my > attempts to replicate logic? > > For the following code, synplify will merge the two instances > of Shift into the same net: > > wire [1:0] Shift /* synthesis syn_keep=1 */; > assign Shift[0]= Sending & !Stall | !Ready; // > assign Shift[1]= Sending & !Stall | !Ready; // Replicated > > Also, is there some way to get synplify to print a message when > it encounters an attribute? Otherwise, there's no way to tell > if the attribute has an error that causes it to not be recognized > as an attribute. >Article: 35056
"Antonio" <dottavio@ised.it> wrote in message news:fb35ea96.0109182334.167e6250@posting.google.com... > I want to produce 21 coefficients for a SquareRootRaisedCosine filter > that interpolate 3, until now I used Matlab and it's function rcosine > but it automatically produce a 19 coefficient filter and I don't like > to add two zeroes to produce the filter I need, can you explain how I > can design this filter ??? > > Really Thanks in any case ... Systolix Filter Express has a Raised Cosine Filter option: http://www.systolix.co.uk I've only used it for ordinary FIR filters with a DSP. Leon -- Leon Heller, G1HSM leon_heller@hotmail.con http://www.geocities.com/leon_heller Low-cost Altera Flex design kit: http://www.leonheller.comArticle: 35057
Hi, Could someone tell me what the equivalent gate count value in the Xilinx mrp file represents, is it the number of gates that the design would occupy using NAND gate e.t.c, does it assume that a NAND gate is 2 gates and how accurate is the gate count figure. What is the equivalent gate count for a Spartan CLB excluding the registers ? Thanks JasArticle: 35058
"Kevin Neilson" wrote: > Do you have "resource sharing" disabled? Enabled or disabled it has no effect. > Also, if you are trying to reduce > fanout, just use the "syn_maxfan" directive and Synplify will replicate for > you. I'd prefer to have control of how a net gets replicated so that I can floorplan the components that it drives. For example, if odd bits are on one side of the chip and even bits are on the other, it would be much more optimal to split a clock-enable along those lines. If I let the tool do it for me, each split of the net will probably drive a few odd bits and a few even bits, and therefore must cross the entire length of the chip. > "Don Husby" <husby_d@yahoo.com> wrote in message > news:35802095.0109181335.38d1e3a1@posting.google.com... > > How do I prevent Synplify from optimizing away my > > attempts to replicate logic? > > > > For the following code, synplify will merge the two instances > > of Shift into the same net: > > > > wire [1:0] Shift /* synthesis syn_keep=1 */; > > assign Shift[0]= Sending & !Stall | !Ready; // > > assign Shift[1]= Sending & !Stall | !Ready; // Replicated > > > > Also, is there some way to get synplify to print a message when > > it encounters an attribute? Otherwise, there's no way to tell > > if the attribute has an error that causes it to not be recognized > > as an attribute.Article: 35059
On 19 Sep 2001 16:23:03 +0200, Petter Gustad <newsmailcomp1@gustad.com> wrote: > >I'm trying to generate some mcs files for the 18v04 to config a >xc2v6000. I've simply scaled up the command I've been using for the >xcv1000e: > >promgen -c -w -p mcs -x xc18v04 xc18v04 xc18v04 xc18v04 xc18v04 -u 0 chip.bit > >This results in: > >ERROR:Bitstream:29 - 0x25b06c bytes loaded up from 0x0 exceeds maximum 0xfffff > for Mcs86 prom format. > >Does this mean that you can't use MCS format for the xc2v6000 since >it results in a 20-bit overflow? It doesn't make sense since the >18v04's are the same size no matter if I'm using two of them with a >xcv1000e or five with a xc2v6000. > >It seems like hex and exo is OK. tek appears to have a 64K limit on >the number of bits. I first ran into this problem when I started using XCV2000E devices about a year ago. The Intel Hex format (.mcs) supports 16 bit (64k), 20 bit (1M) and 32 bit (4G) addressing modes. The 32 bit addressing mode was added to the specification by Intel in the mid 1980s. Xilinx have only just started supporting it with the 4.1 release. My fix for the 3.x tools was to use promgen to generate a Motorola hex file (.exo) and use a simple Perl script to convert this to Intel hex. I am unable to post my Perl script due to company policy. You can find file format definitions at: http://www.wotsit.org/ Regards, Allan.Article: 35060
"Tim" <tim@rockylogic.com.nospam.com> wrote in message news:<1000828502.6663.0.nnrp-07.9e9832fa@news.demon.co.uk>... > Look it up in Synplicity help, but what you need is > something like this: > > attribute syn_noclockbuf : boolean; > attribute syn_noclockbuf of ClkA : signal is true; > attribute syn_noclockbuf of ClkB : signal is true; > > > "Richard Wilkinson" <richard.wilkinson@csr.com> wrote in message > news:587eaa3a.0109180331.71484f12@posting.google.com... > > Hi All, > > > > I am having a problem with Synplify inferring BUFG cells when it has > > actually run out of BUFGs to add. In this case, I am using Synplify > > 6.1.3 and have instantiated a BUFGDLL and a single BUFG. Obviously > > this takes up 2 of the 4 BUFGs in the Virtex2E that I'm using, but > > then Synplify infers 3 more BUFGs as it decides that I have only > > instantiated 1 BUFG in my code. > > > > I have tried usign Synplify 6.2.4 but that actually synthesises some > > of my logic incorrectly. > > > > Is this BUFG problem a bug with Synplify 6.1.3 or can Synplify just > > not count to 4 properly? > > > > Has anyone else had this problem? > > > > Cheers, > > > > Rich I had a similar problem; Synplicity ignored the syn_noclockbuf attributes, both in the HDL source and in the SCOPE (attribute editor) window. Finally, I solved the problem by instantiating exactly the clock-buffers and connections I wanted as black boxes and adding an XC_GLOBAL_BUFFERS attribute with the exact number of BUFGs I had in the code. Note that this attribute can't be used in the HDL code but only in the .SDC file.Article: 35061
Could someone please tell me a shorter method for doing the following. Using Foundation 3.1, I first implement my design, and once it is implemented, then can I use the Xilinx Constraints Editor to provide timing constraints. Once this is done, I need to implement my design again. I have to go through this entire process every time I make changes in my design (due to net name changes etc.). Is there a quicker way?? This process takes me about 20 minutes (20minutes I could spend doing something more productive than waiting around) Thanks adrianArticle: 35062
allan_herriman.hates.spam@agilent.com (Allan Herriman) writes: > I first ran into this problem when I started using XCV2000E devices > about a year ago. Alan, Thank you for your explanation. I'll check the format descriptions and see how much work it's to write a program to convert the files. Petter -- ________________________________________________________________________ Petter Gustad 8'h2B | (~8'h2B) - Hamlet in Verilog http://gustad.comArticle: 35063
Hello Newsgroup, I am using a Insight EvaluationBoard with a Xilinx SpartanII FPGA on it. I want to program a digital PLL for use in a measuring system. Do I have to reinvent the wheel, or is there anything comparable out there which is worth a look? I am looking for sourcecode in VHDL. Thank you! SteffenArticle: 35064
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Hi all, Can anybody tell me how I can clock 'a process on the rising AND falling edge of a clock signal ? I want to do something like : <<<<<if (clock_in'event and clock_in='1' and clock_in='0') then >>>>> but it doesn't work. Please help AbrahamArticle: 35066
Noddy wrote: > Could someone please tell me a shorter method for doing the following. Using > Foundation 3.1, I first implement my design, and once it is implemented, > then can I use the Xilinx Constraints Editor to provide timing constraints. > Once this is done, I need to implement my design again. I have to go through > this entire process every time I make changes in my design (due to net name > changes etc.). > Is there a quicker way?? This process takes me about 20 minutes (20minutes I > could spend doing something more productive than waiting around) > > Thanks > adrian rightclick on the project name in the file tab of the upper left main window and say "edit constraints". You will have to do this by hand. -jc-Article: 35067
Thanks, one other question though. Every time I change my design, I have to delete the .ucf file first, then implement, then edit constraints, then implement again. Otherwise, Foundation complains about an invalid revision. Any answers? Regards Adrian > rightclick on the project name in the file tab > of the upper left main window and say "edit constraints". > You will have to do this by hand. > -jc- >Article: 35068
Can't be done on Xilinx, anyhow; the hardware in the FPGA can only operate on one edge or the other. Instead you should double your clock speed. |Hi all, | |Can anybody tell me how I can clock 'a process on the rising AND falling |edge of a clock signal ? | |I want to do something like : |<<<<<if (clock_in'event and clock_in='1' and clock_in='0') then >>>>> |but it doesn't work. | |Please help |Abraham -- Posted using Nographer - News in your Browser http://www.nographer.com - free, open source, and smartArticle: 35069
> |I want to do something like : > |<<<<<if (clock_in'event and clock_in='1' and clock_in='0') then >>>>> > |but it doesn't work. It is not possible that clk is 1 and 0 at the same time. Maybe like this: if (clk'event and clk = '1') or (clk'event and clk = '0') then ... or: if clk'event then ... -- PanuArticle: 35070
"Assaf Sarfati" <assaf_sarfati@yahoo.com> wrote in message
news:44b0ca4e.0109192053.5c6e81cf@posting.google.com...
> "Tim" <tim@rockylogic.com.nospam.com> wrote in message
news:<1000828502.6663.0.nnrp-07.9e9832fa@news.demon.co.uk>...
> > Look it up in Synplicity help, but what you need is
> > something like this:
> >
> > attribute syn_noclockbuf : boolean;
> > attribute syn_noclockbuf of ClkA : signal is true;
> > attribute syn_noclockbuf of ClkB : signal is true;
> >
> >
> > "Richard Wilkinson" <richard.wilkinson@csr.com> wrote in message
> > news:587eaa3a.0109180331.71484f12@posting.google.com...
> > > Hi All,
> > >
> > > I am having a problem with Synplify inferring BUFG cells when it has
> > > actually run out of BUFGs to add. In this case, I am using Synplify
> > > 6.1.3 and have instantiated a BUFGDLL and a single BUFG. Obviously
> > > this takes up 2 of the 4 BUFGs in the Virtex2E that I'm using, but
> > > then Synplify infers 3 more BUFGs as it decides that I have only
> > > instantiated 1 BUFG in my code.
> > >
> > > I have tried usign Synplify 6.2.4 but that actually synthesises some
> > > of my logic incorrectly.
> > >
> > > Is this BUFG problem a bug with Synplify 6.1.3 or can Synplify just
> > > not count to 4 properly?
> > >
> > > Has anyone else had this problem?
> > >
> > > Cheers,
> > >
> > > Rich
>
>
> I had a similar problem; Synplicity ignored the syn_noclockbuf
> attributes, both in the HDL source and in the SCOPE (attribute editor)
> window. Finally, I solved the problem by instantiating exactly the
> clock-buffers and connections I wanted as black boxes and adding an
> XC_GLOBAL_BUFFERS attribute with the exact number of BUFGs I had in
> the code. Note that this attribute can't be used in the HDL code but
> only in the .SDC file.
Works OK (in VHDL) if you put the attribute in the arch like this:
architecture rtl of foo is
attribute syn_noclockbuf : boolean;
attribute syn_noclockbuf of rtl: architecture is true;
begin
....
or this:
attribute syn_noclockbuf of MyCLk: signal is true;
At least it worked last time I use Synplify...
Article: 35071Noddy wrote: > Thanks, one other question though. Every time I change my design, I have to > delete the .ucf file first, then implement, then edit constraints, then > implement again. Otherwise, Foundation complains about an invalid revision. > Any answers? > > Regards > Adrian > > > rightclick on the project name in the file tab > > of the upper left main window and say "edit constraints". > > You will have to do this by hand. > > -jc- > > Hi Noddy! I am not completly sure if I am the right person for you to chat with. I discovered the "Timing / Location Constraints" last week for the first time. I use only one revision, and I havn't had any problems concerning the revision. My problem is, that when there is s.th. wrong with the ucf file and the implementation fails, it doesn't recognize the changes to the ucf file. I have to synthezise again, to make it accept the new ucf file. Quite annoying... If you like to, we could talk a little about constrains. I still can't really handle them. Could you post your ucf file? -jc-Article: 35072
Tried that aswell. It doesn't work. thankx anyway. Panu H <panuh[@]cs.tut.fi> wrote in message news:9ociem$s7d$1@news.cc.tut.fi... > > |I want to do something like : > > |<<<<<if (clock_in'event and clock_in='1' and clock_in='0') then >>>>> > > |but it doesn't work. > > It is not possible that clk is 1 and 0 at the same time. > > Maybe like this: > if (clk'event and clk = '1') or (clk'event and clk = '0') then ... > or: > if clk'event then ... > > -- Panu > > >Article: 35073
Hallo, the quicklogic datasheet "eclipse_1.pdf", marked prelininary and last updated 8/24/2000 doesn't have pinouts. I asked local support for pinouts on Mondayay and they forwarded it to quicklogic america, but I haven't got a feedback yet. Does anybody have the pinout of the eclipse parts and can forward it to me? Thanks in advance -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 35074
Hello,
I have a problem with pin location constraints using Verilog/FPGA express.
I have the following simple design:
module test(A, B);
input A; //synopsys attribute LOC "P63"
output B;
assign B=A;
endmodule
When I run synthesis and then place and route, the Xilinx PAR tools give the
following warning:
WARNING:NgdBuild:483 - Attribute "LOC" on "N_A" is on the wrong type of
object.
Please see the "Attributes, Constraints, and Carry Logic" section of the
Libraries Guide for more information on this attribute.
It turns out, that FPGA express puts the constraint on the output net of the
input buffer of A, in stead of A itself.
Does anyone know how to solve this from within Verilog?
Kind Regards,
Johan
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