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Hi, I have got solution for the problem. the vendor sold the engineering sample to me, but not provided the errata sheets. :-( I am wondering why i can't be the distributor of xilinx but some "insight"? there are some problem with the bitgen, both for 3.3i and 4.1i. and now xilinx has released two patch for 3.3i and 4.1i. ( i don't have money to get 4.1i ) you are welcome. :-)Article: 35076
Gavin Hurlbut <gjhurlbu@beirdo.ott.uplink.on.ca> writes: > There is a note somewhere on Xilinx's site specifying that you are > not supposed to add the EDIF file to the project when instantiating > a black box object (which is basically what you are doing here). > Just create the component instantiation as usual, and when doing the > Implementation "Translate" stage, it will merge the EDIF files for > you before doing the Place & Route. That's it! Thanks a 0xf4240! Looks like I have confused `compiler' and `linker' or some such, to speak in (to me) more familiar terms. I'm now happily co-simulating my toy memory design, and looking at two beautifully identical waveforms: one from the simulator and one from the logic analyzer. What then is the use of using EDIF as an input to the sythesizer? I suppose you could do part of your design as a schematic and export that as EDIF, right? In such a netlist, your buses would not be expanded, or? But I would probably export schematic netlists as VHDL anyway, just to make sure. Not that I'm going to paint my designs... ;) > You also have to be sure not to allow I/O pads to be inserted in the > "lower" black box synthesis. Yes, I didn't insert pads. I hadn't listed this in my description, sorry. > Finally, be sure that the filename of the EDIF file matches your > component name (other than the .edf of course). Hmm, how are EDIF netlists matched up by ngdbuild? RTFM, I suppose... > This works fine for me, although it makes simulation more painful, > as you have to simulate using the timing results file, which is > somewhat annoying when you are trying to do a functional simulation > to prove that you designed the logic correctly, but it does work. I'm not there yet. I can functionally simulate the generated cores, but I haven't tried `physical' timing yet. > You will still get a warning similar to this when synthesizing. Yes, I get a warning that the `black boxes' could not be linked, but I don't get any warnings about unmatched ports any longer. > > What's going on? I'm grateful for any hints. > > Let me know if this helps :) It helped tremendously. Please have a virtual beer on me. :)Article: 35077
You can do it by turning one of the LUT inputs into a vector, and putting syn_keep
on the vector:
signal lut_input:std_logic;
signal lut_input_vec:std_logic_vector(7 downto 0);
attribute syn_keep:boolean;
attribute syn_keep of lut_input_vec:signal is true;
begin
lut_input_vec<=(others=> lut_iput);
for i in 0 to 7 generate
begin
lut_output(i)<= lut_input_vec(i) <rest of lut logic function>;
John_H wrote:
> Getting replicated LUTs is tough. Even the syn_keep attribute doesn't usually
> help out. You may need to go to annoying lengths to get what you want. I've
> instantiated LUT primitives before and I've hated doing it because the INIT
> attribute defines the logic. I don't like creatingm y own logic tables.
>
> You can invoke a lower level module (jeeze) and include a syn_hier directive
> on that module of "hard" or "firm" (either or both may work) to completely
> replicate the LUTs without optimizing one away. Without the syn_hier
> directive you'd probably see one external LUT that feeds both of the module
> instances if you looked into HDL_Analyst (or the edif).
>
> Don Husby wrote:
>
> > How do I prevent Synplify from optimizing away my
> > attempts to replicate logic?
> >
> > For the following code, synplify will merge the two instances
> > of Shift into the same net:
> >
> > wire [1:0] Shift /* synthesis syn_keep=1 */;
> > assign Shift[0]= Sending & !Stall | !Ready; //
> > assign Shift[1]= Sending & !Stall | !Ready; // Replicated
> >
> > Also, is there some way to get synplify to print a message when
> > it encounters an attribute? Otherwise, there's no way to tell
> > if the attribute has an error that causes it to not be recognized
> > as an attribute.
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 35078"Tim" <tim@rockylogic.com.nospam.com> writes: > Try checking outer.edf to see if the bus representation maps. From > memory, I cannot recall the exact syntax. I did this (with a slightly different outer.vhdl that wouldn't get optimized away completely), and it too talks about "input<0>", etc, just as inner.edf. I can't brain-parse EDIF yet, but I suspect that the names should match. > so outer.edn should also go the "input<0>" route. If it uses "input[0]" > or whatever, the files will not mate. There should be a switch in the > synth to control 'bus style'. There is an option to set the bus naming style for XNF imports. Supposedly, you don't need a bus naming style for EDIF, since EDIF has its own native way of describing buses, right? (Or so says the EDIF blurb I have skimmed. (But if that is the case, why doesn't the EDIF produced by FPGA Compiler II make use of it?)) Anyway that wasn't the problem after all, as Gavin has pointed out. EDIF netlists that are ready to be implemented should be merged by the backend tools, which is in our case the Translate stage carried out by the Xilinx ngdbuild tool. It somehow magically pulls in referenced netlists. Thanks anyway!Article: 35079
Abraham Henry Vlok <wagter@tuks.co.za> wrote in message news:1000990968.542535@nntp.up.ac.za... > Tried that aswell. It doesn't work. Doesn't work in simulation or synthesis?Article: 35080
You can never use a rising and a falling edge of a signal in a process. Even if you mirror the signal (not_clk <= not clk) you won't be able to use the two clock signals in one process. You can however now use two processes en then use another to tie them together. The easy way to go here is to indeed dubble your signal speed. This is easily done with the use of a DLL or DCM. Good luck, LennartArticle: 35081
Marius Vollmer <marius.vollmer@uni-dortmund.de> wrote: > I'm now happily co-simulating my toy memory design, and looking at two > beautifully identical waveforms: one from the simulator and one from > the logic analyzer. Excellent. > What then is the use of using EDIF as an input to the sythesizer? I > suppose you could do part of your design as a schematic and export > that as EDIF, right? In such a netlist, your buses would not be > expanded, or? But I would probably export schematic netlists as VHDL > anyway, just to make sure. Not that I'm going to paint my > designs... ;) I'm not exactly sure. I struggled with the same problem for most of a Saturday before getting it to behave. I think they suggest you import the schematics (if in EDIF) in the same black-box way. I guess if you can export as VHDL, that would be ideal :) >> Finally, be sure that the filename of the EDIF file matches your >> component name (other than the .edf of course). > Hmm, how are EDIF netlists matched up by ngdbuild? RTFM, I suppose... Dunno. As far as I can tell, it requires an exact match of the component name and the filename of the EDIF. I couldn't find it in any FM, so I'm just guessing, but that seems to work for me so far. >> This works fine for me, although it makes simulation more painful, >> as you have to simulate using the timing results file, which is >> somewhat annoying when you are trying to do a functional simulation >> to prove that you designed the logic correctly, but it does work. > I'm not there yet. I can functionally simulate the generated cores, > but I haven't tried `physical' timing yet. I try to do my functional simulations first :) I never quite get the silly Foundation Simulator to get the black-box EDIF imported with my top-level design, but the timing simulation output worked great. I think it's just a matter of sitting there for another Saturday with mucho beer and threatening the tools a bit more. :) >> Let me know if this helps :) > It helped tremendously. Please have a virtual beer on me. :) Will do. Unfortunately, I don't have any German beer right now (ran out), so I'll have to deal with Moosehead (an eastern Canadian beer), which I do have in my fridge. :) Ciao GavinArticle: 35082
I suggest you to contact http://www.frontierd.com/index.html this company who recently merged with Philips is "leader" in creating optimized vhdl files from algorithems in C I personnaly have no interrest in these companies, just posting regards ------ User of http://www.foorum.com/. The best tools for usenet searching.Article: 35083
Hi there, Our company is working in the area of 3D imaging. We are developing a new technology to perform the rendering which is not based on polygons. We would now want to develop a piece of hardware that would perform the necessary calculation (just like 3D accelerators do) to do the rendering. So we are looking for a development platform that would include some kind of interface with a PC (pci or other), a FPGA chip, a DSP, memory... If you have any hint or advice to give us, your help would be appreciated. Samuel Richard SGDL SystemArticle: 35084
Well, If you have the part, but no errata sheet, then you do not have "delivery" of the product, and if it were me personally, I wouldn't pay until I had what was sold to me. Austin cycle wrote: > Hi, I have got solution for the problem. > the vendor sold the engineering sample to me, but not provided the > errata sheets. :-( > I am wondering why i can't be the distributor of xilinx but some > "insight"? > there are some problem with the bitgen, both for 3.3i and 4.1i. and > now xilinx has released two patch for 3.3i and 4.1i. ( i don't have > money to get 4.1i ) > you are welcome. > :-)Article: 35085
You first have to generate a double-frequency clock. It's easy and uses only one ff, one inverter,and one XOR: Feed the input frequency into the XOR, feed the other input of the XOR together with the D input of the flip-flop from the inverted Q output of that flip-flop. Then use the XOR output to clock the flip-flop, and also use the XOR as the double-frequency output. Now you have a double-frequency clock and can do anything you want. Virtex circuits give you the clock doubling for free in their Digital Clock Manager circuit. Peter Alfke, Xilinx Applications. =========================== Abraham Henry Vlok wrote: > Hi all, > > Can anybody tell me how I can clock 'a process on the rising AND falling > edge of a clock signal ? > > I want to do something like : > <<<<<if (clock_in'event and clock_in='1' and clock_in='0') then >>>>> > but it doesn't work. > > Please help > AbrahamArticle: 35086
Hi Jas, You may find the information you are looking for in an Application Note entitled "Gate Count Capacity Metrics for FPGAs." It can be found at the following URL: http://support.xilinx.com/xapp/xapp059.pdf You can also reference the following app brief for more info on gate count metrics: http://www.xilinx.com/xbrf/xbrf011.pdf I hope this helps. Best regards, Kamal Patel jas wrote: > Hi, > > Could someone tell me what the equivalent gate count value in the > Xilinx mrp file represents, is it the number of gates that the design > would occupy using NAND gate e.t.c, does it assume that a NAND gate is > 2 gates and how accurate is the gate count figure. > > What is the equivalent gate count for a Spartan CLB excluding the > registers ? > > Thanks > > JasArticle: 35087
Can anyone give me some insight as to the maximum attainable clock rate for the various Xilinx families? I have a requirement where I need to count the pulse width of a pulse using a VERY high speed counter (~2.5GHz). I realize that this is not attainable in an FPGA and am planning on using an ECL front end. I need to mimimize the amount of logic to minimize the impact of switching noise on a very sensitive analog amplifier/high speed comparator. The question is then; if all I want is to have a digital counter (either synchronous or asynchronous is suitable in this case) what is the maximum toggle rate of the various familes assuming an externally generated clock (no clock doublers, etc.) Please don't give me a lecture on asynchronous being bad design practice. In this case it really doesn't matter. Also, has anyone had any real experience with the LVPECL I/O on Virtex E, Spartan2, etc? Thanks, Theron HicksArticle: 35088
You might just want to consider what octave you want to work in. For a
2.5GHz counter you'd want an FPGA that can deal with sampling data up to:
1) 2.5GHz
2) 1.25GHz
3) 625MHz
4) 312MHz
and so on.
Using LVDS you can look at Altera's Mercury family for 1.25GHz (with some
design issues related to deserialization) or Altera's Apex for 625MHz (same
concerns); Xilinx Virtex-II will do a nice job at 625MHz without so much
overhead. More families will hit 312MHz for sampling with internal
demultiplexing to run internal logic more favorably at 156 or 78MHz. Be
careful - without using the internal PLLs you'll end up with more severe
limits to your clock speed because the I/O sourced clocks have more absolute
limits.
Did you know you can get phase resolution better than your 400pS target with
A/D conversion of controlled ramps or sinusoids? With good design, better
than 5pS resolution is attainable with other techniques. The high speed,
low noise analog is imposing for many designers, however.
Theron Hicks wrote:
> Can anyone give me some insight as to the maximum attainable clock rate
> for the various Xilinx families? I have a requirement where I need to
> count the pulse width of a pulse using a VERY high speed counter
> (~2.5GHz). I realize that this is not attainable in an FPGA and am
> planning on using an ECL front end. I need to mimimize the amount of
> logic to minimize the impact of switching noise on a very sensitive
> analog amplifier/high speed comparator. The question is then; if all I
> want is to have a digital counter (either synchronous or asynchronous is
> suitable in this case) what is the maximum toggle rate of the various
> familes assuming an externally generated clock (no clock doublers, etc.)
> Please don't give me a lecture on asynchronous being bad design
> practice. In this case it really doesn't matter.
>
> Also, has anyone had any real experience with the LVPECL I/O on Virtex
> E, Spartan2, etc?
>
> Thanks,
> Theron Hicks
Article: 35089Steffen Thieringer schrieb: > > Hello Newsgroup, > I am using a Insight EvaluationBoard with a Xilinx SpartanII FPGA on it. > I want to program a digital PLL for use in a measuring system. > Do I have to reinvent the wheel, or is there anything comparable out there > which is worth a look? > I am looking for sourcecode in VHDL. I have the VHDL description of the more less famous 74HC297, a simple digitall PLL. I you are interested in, drop me a mail. -- MFG FalkArticle: 35090
Theron Hicks wrote: > > Can anyone give me some insight as to the maximum attainable clock rate > for the various Xilinx families? I have a requirement where I need to > count the pulse width of a pulse using a VERY high speed counter > (~2.5GHz). There is more than one way to measure a pulse width. What is the Pulse Width range, and its repetition rate ? -jgArticle: 35091
Im interested in making use of the clock enable pins
that exist in the Virtex CLBs.
I have got a VHDL component, which expects a streams
of values to be entered in serial. However, the I/O
bandwidth of my board is not sufficient to supply the
stream. I would like to specify a value to be used as
the clock enable for the entire component. This way
I would be able to prepare one set of values, raise the
clock enable for just one clock cycle, then lower it
again while I prepare the next set of values.
The VHDL component is behavioral, and computer generated.
So, I am unable to modify the code which generates it, or
I would have added a "data valid" signal to the component
This is unfortunatly not possible. It also contains
several other components, which I also cannot modify.
I thought about using a gated clock, IE:
my_gated_clock <= CLK and my_clock_enable;
And then using the gated clock to drive the clock of
the component, but this seems quite primitive, and
likly to cause clock scew, or other nasty problems.
I know that clock signals have dedicated resources
and it occured to me that using a gated clock would
cause the clock signal to be a regular signal, which
might cause problems. I am uneasy about messing with
the actual clock lines.
I looked around in the synplify manuals and found
an attribute called "syn_direct_enable" which appears
to be for specifying a clock enable for a component,
but the description of the attribute is poor. I have
not been able to get it to work.
If I am able to figure out how to easily make use of
the Clock enable I will be able to use them for other
"data valid" type signals to generate more efficient
code.
Any suggestions? Examples?
--
_____ _____
___ | | __ |
|___| | --| -|
|_____|__|__|
Article: 35092questions below: Austin Lesea wrote: > John_H wrote: > >> How long (if at all) does it take to settle from this >> delay-line-switched >> phase change? > > It takes 84 clocks on the CLKIN input, plus three on the PSCLK input > to effect a change (increment or decrement). If those are tied > together (commonly done) that is 87 clocks. You MUST wait for PSDONE > before PSEN is asserted to inc or dec again. 87 clocks to move 1/256 cycle (on average) gives 45ppm of frequency adjustment capability if continuous phase adjustment is achieved - disappointingly slow. If I could directly control the phase value directly (best choice), inc/dec by more than 1/256, or have the change occur sooner (15 clocks?) the usability of the DCM increases significantly. >> Can the phase shift be "wrapped around" such that decrementing >> past -255 >> ends up back at zero? > > No. The phase shift increments until it overflows (sticks at 255), or > decrements until 0 (then sticks at 0). An external counter is > required if you want to keep track of it. If you PSOVERFLOW, the unit > needs a RESET to go again. Does the RESET do nasty things to the clock or is it a seamless transition to zero phase? (I guess I'm grasping at straws) --- new question --- Can the BUFGMUX primitives be cascaded to allow selection of, say, 4 clocks? More specifically, 4 clock phases from a DCM?Article: 35093
Jim,
Pulse rep rate is 500KHz. Pulse width is from 25% to 50% of pulse
period. Note that the pulse rep rate could be less. Needs to be accurately
measured to about 400psec. Thanks.
Jim Granville wrote:
> Theron Hicks wrote:
> >
> > Can anyone give me some insight as to the maximum attainable clock rate
> > for the various Xilinx families? I have a requirement where I need to
> > count the pulse width of a pulse using a VERY high speed counter
> > (~2.5GHz).
>
> There is more than one way to measure a pulse width.
> What is the Pulse Width range, and its repetition rate ?
>
> -jg
Article: 35094So you want to measure a roughly one microsecond pulse, and achieve a resolution of 400 ps. I know of no FPGA that gives you a 2.4 GHz count rate, but you can use multiple counters in parallel, each using a phase-offset clock ( 0, 90, 180, 270 degrees). In Virtex-II, you can use four phases of a 400 MHz clock, giving you a resolution of roughly 600 ps. At room temperature, I am sure you can achieve even better resolution. If the time to be measured is synchronous with the clock, and is repetitive, then you can of course easily achieve much better precision. I assumed one-shot, incoherent, asynchronous operation. Peter Alfke, Xilinx Application Theron Hicks wrote: > Jim, > Pulse rep rate is 500KHz. Pulse width is from 25% to 50% of pulse > period. Note that the pulse rep rate could be less. Needs to be accurately > measured to about 400psec. Thanks. > > Jim Granville wrote: > > > Theron Hicks wrote: > > > > > > Can anyone give me some insight as to the maximum attainable clock rate > > > for the various Xilinx families? I have a requirement where I need to > > > count the pulse width of a pulse using a VERY high speed counter > > > (~2.5GHz). > > > > There is more than one way to measure a pulse width. > > What is the Pulse Width range, and its repetition rate ? > > > > -jgArticle: 35095
Theron Hicks wrote: > > Jim, > Pulse rep rate is 500KHz. Pulse width is from 25% to 50% of pulse > period. Note that the pulse rep rate could be less. Needs to be accurately > measured to about 400psec. Thanks. You can set up a Tapped Delay line + Capture Registers + priority encoder to get very fine resolutions. Peter A. will have a better idea of just how fine, but 400ps should be doable. What is the Chain-Tap delay ? This will need a calibrate cycle, and a read cycle. Example: Use Gated 100MHz to get to 10ns LSB, then calibrate Taps / 10ns, and a chain of 40 taps of nom 400ps each. Some care will be needed on the LSB-Tap capture boundary, and a simple calculation gives pulse width. -jg > > Jim Granville wrote: > > > Theron Hicks wrote: > > > > > > Can anyone give me some insight as to the maximum attainable clock rate > > > for the various Xilinx families? I have a requirement where I need to > > > count the pulse width of a pulse using a VERY high speed counter > > > (~2.5GHz). > > > > There is more than one way to measure a pulse width. > > What is the Pulse Width range, and its repetition rate ? > > > > -jgArticle: 35096
It says in the Virtex-E databook that the the clock input to a DLL can be stopped & restarted as long as the clock is stopped while its low. How does this square with the max cycle-to-cycle input variation parameter of 1nsec. ? When the clock is re-started does this mean that the the first new rising edge has to be in the same place +/- 1 nsec it would have been if the clock had not been stopped ?Article: 35097
You can combine bitsteams. The CRCs are separate for each device. Philip On Tue, 11 Sep 2001 08:55:34 +0200, Edwin Pijpers <epij@oce.nl> wrote: >Is it possible to use a combination of Spartan and SpartanII devices in >the same serial configuration chain?? or do I get problems with the CRC >check. > >Edwin Pijpers Philip Freidin FliptronicsArticle: 35098
I hope you understand that all the delays reported by the timing analyzer and the FPGA_Editor are worst case delays. You cannot get bestcase or actual delays. So if you have two paths and the tools tell you the delays are 16nS and 20nS adding 4 nS to the first one does not solve your problem because you dont know what the actual delays are, only the worst values that they might be. For instance, the real delays might be 6 ns and 18ns. Adding 4 does not match them. Or they might be both actually 14 nS. adding 4 stops them from being matched. Or any one of an infinite number of other possibilities. Without criticizing your design, when people ask about delay matching and screwing around with routing to adjust timing for any reason other than meeting a cycle time requirement, my thinking is that you may need to rethink your design approach. Good luck, Philip Freidin On Wed, 19 Sep 2001 11:35:47 +0200, "Chih-Hsun Lin" <Chih-Hsun.Lin@cern.ch> wrote: >Hi : >Thanks very much for your answer. > >Actually, my case is that two async signals come out from the same CLB to 2 >output pads. >I want the routing delay for those two signals shall be similar. The usual >routing medthod >is to get minimum delay. In order to match the routing delay, I think the >easy way shall be >increase routing dealy for one signal to match the other. However, I did not >find a way to >do it easily in FPGA editor. > >Best regards, >Lin CH > Philip Freidin FliptronicsArticle: 35099
On Thu, 20 Sep 2001 10:46:38 +0200, "Abraham Henry Vlok" <wagter@tuks.co.za>
wrote:
>Hi all,
>
>Can anybody tell me how I can clock 'a process on the rising AND falling
>edge of a clock signal ?
I bet you mean OR
>I want to do something like :
><<<<<if (clock_in'event and clock_in='1' and clock_in='0') then >>>>>
>but it doesn't work.
Probably just this:
if (clock_in'event) then
but although this might be acceptable to simulation, this won't be
synthesizable.
>Please help
>Abraham
>
Philip
Philip Freidin
Fliptronics
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