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Sergio Masci wrote:
> So you don't need any special tools
Not for synthesis or simulation.
> So you do need a special tool to help you "figure out
> the ROM required data to do what you want"
You need some way to determine the ROM data.
There is likely no commercial tool for this
so you will have to roll your own with C,
perl, python etc., or do it manually.
> Again this is what tools are for, to make working things out easier, to
> reduce the possibility of introducing errors, to make it easier to maintain.
Sounds like more work than a conventional
state machine design, but if you feel
inspired, go for it.
> Implementing a complex state machine in a ROM that takes a few
> cycles to process an event has still got to be a hell of a lot faster
> (execution wise) than implementing a CPU core to do the
> processing.
Agreed.
I was comparing a state machine design
constrained to use a ROM to a conventional
state machine design.
The advantage of the ROM is not clear to me
in this case.
--Mike Treseler
Article: 35501
"S. Ramirez" wrote:
>
> Has anyone done a trade study recently on Synplify vs. Leonardo? If
> yes and you would like to share the results, please do so here or email me
> privately. A client company has asked me to do a trade study of the several
> products on the market, and I would like to get some preliminary information
> on these two products. I am particularly interested in actual synthesis
> results of real application test cases. A simple description of the test
> cases along with the results is sufficient. Also, I am interested in any
> outstanding features and/or quirks of the two products.
If you want an unbiased trade study, I would
suggest that you download the tools and run
your own test cases. It's not very difficult.
--Mike Treseler
Article: 35502Rick Filipkiewicz schrieb: > > I'm only considering the V-2s in order to get DDR DRAM going with a 125MHz target speed for the Huhh, be careful with your word choice. V-2s are dangerous things ;-)) SCNR. -- MFG FalkArticle: 35503
Mike Treseler wrote: > I was comparing a state machine design > constrained to use a ROM to a conventional > state machine design. > The advantage of the ROM is not clear to me > in this case. Well, a complex FSM runs faster, and is much cheaper ( requires zero real estate if a BlockRAM is left over ) To some people, speed and cost are compelling arguments. :-) Peter AlfkeArticle: 35504
C A L L F O R P A P E R S
Special issue on Programmable Logic
The ACM Transactions on Design Automation (TODAES)
Guest Editors: Majid Sarrafzadeh (UCLA) and Rajeev Jayaraman (Xilinx)
The ACM Transactions on Design Automation (TODAES) will publish a
special issue on
Programmable Logic in October of 2002. Authors are invited to submit
manuscripts which demonstrate original research related to programmable
logic in areas relating to automatic architecture generation/evaluation,
implementations, tools and applications.
SUBMISSION GUIDELINES:
Authors should submit an electronic Postscript or pdf copy of their
paper
following the guidelines published by TODAES (see www.acm.org/todaes).
Make sure to indicate at the end of your abstract that your submission
is for
the special issue on PLDs.
PUBLICATION SCHEDULE:
MANUSCRIPT DUE: November 16, 2001 (5pm PST)
ACCEPTANCE NOTIFICATION: February 22, 2002
FINAL MANUSCRIPT DUE: April 5, 2002
PUBLICATION DATE: October 1, 2002
--
Rajeev Jayaraman, Ph.D
Director, Physical Implementation Tools,
Xilinx Inc.
Article: 35505What is the minimum tool required to simulate the virtex2 device? I have been told that modelsim_xe/starter 5.5b will work. Is this true in anyone's experience? In particular I am trying to simulate a very simple sistem with bufgmux's and DCM's and some simple counters and adders. I cannot even get the system to work with a bufgmux let alone a DCM. Does anyone happen to have a simple set of known good VHDL code files out there that utilize a BUFGMUX and/or a DCM? Thanks.Article: 35506
Mike Treseler wrote: > > Sergio Masci wrote: > > > So you don't need any special tools > > Not for synthesis or simulation. > > > So you do need a special tool to help you "figure out > > the ROM required data to do what you want" > > You need some way to determine the ROM data. > There is likely no commercial tool for this > so you will have to roll your own with C, > perl, python etc., or do it manually. It seems the BlockRAM(ROM)s of many larger FPGAs can not only do FSM, but also any wide-logic decodes, so can become more like the wide product terms seen in CPLDs. (In practise, not as wide as the CPLD fanin, but better than a CLB) Re determining ROM data ( RAM Preload ): I tried CUPL on this, and it can support STATE entry, suited to .D registers ( and thus == SYNC RAM ) STATE entry, suited to .T registers ( would need new .T RAM ? ) Table Entry, similar to ROM array Condition code, for expression to node evaluation. Boolean Eqn entry or any combination of the above CUPL can also quickly functionally simulate the state engine. Output format options include ASCII HEX, (but that seems to be device-locked ?), and std .PLA, which is available on all devices. ( PLA is also output by many other PLD tools ) The ASCII .PLA could be converted to ROM array HEX info fairly easily, with some scripts, as it is a simple re-organise problem. Someone may already have a PLA to ROM, or PLA to HEX ? > > Again this is what tools are for, to make working things out easier, to > > reduce the possibility of introducing errors, to make it easier to maintain. > > Sounds like more work than a conventional > state machine design, but if you feel > inspired, go for it. Yes, it will be more work than conventional state design, but has potential size/speed benefits that can warrant the extra effort ( normally after the logic flow is proven :-) -jgArticle: 35507
Is that a reasonable schedule in these days of electronic publishing? From an April final manuscript to an October publication is almost six months! Half a year for typesetting ? Is this the 21st century, or are these guys still chiseling in stone ? Peter Alfke, just his usual impatient self. ================================ Rajeev Jayaraman wrote: > C A L L F O R P A P E R S > > Special issue on Programmable Logic > The ACM Transactions on Design Automation (TODAES) > > > > PUBLICATION SCHEDULE: > > MANUSCRIPT DUE: November 16, 2001 (5pm PST) > ACCEPTANCE NOTIFICATION: February 22, 2002 > FINAL MANUSCRIPT DUE: April 5, 2002 > PUBLICATION DATE: October 1, 2002 >Article: 35508
> I believe FSMs implemented in PROMs were common in the past - what
> tools did people use back then in order to derive the PROM contents?
Yes. Very common, but the last time I worked on one was early or mid
80s. PALs filled in most of that nitch.
I think the key idea is that you got to change a pile of complicated
hardware into reasonable software. That may not help if your hardware
designers aren't reasonably comfortable with writing software.
The way we generated the ROM contents was to write the
"program" that you wanted to execute.
The middle of the program is a giant case statement, dispatching on the
current state. That's inside a wrapper that iterates through all the
addresses on the ROM. The end of the program just wrote out the "code"
in whatever format your ROM-blaster wanted.
Thus (roughly):
for (addr=0; addr<maxAddr; addr++) {
current_state = addr & 0x1f; /* 5 bits for state */
input1 = (addr >> 5) & 1;
input2 = (addr >> 6) & 1;
...
output1 = 0; /* Setup default state for all outputs */
...
switch (current_state) on {
state1:
next_state = xxx;
output 1 = xxx;
break;
state2:
if (input1) xxx
else xxx;
break;
...
endcase:
next_state = init;
break;
}
output[addr] = next_state |
output1 << 5 |
output2 << 6 |
...
} /* end of addr loop */
for (addr=0; addr<maxAddr; addr++) {
printf blah blah blah...
}
--
These are my opinions, not necessarily my employeers. I hate spam.
Article: 35509Hi, Are there timing issues on a Spartan device if the reset is asynchronous to the system clock, i.e could a problem occur where by the device is taken out of reset on the active clock edge, hence certain registers in the device remain in reset and the others are not. If so how is this solved, by registering the reset and not reseting that register?. Thanks jonArticle: 35510
>Are there timing issues on a Spartan device if the reset is >asynchronous to the system clock, i.e could a problem occur where by >the device is taken out of reset on the active clock edge, hence >certain registers in the device remain in reset and the others are >not. If so how is this solved, by registering the reset and not >reseting that register?. There was a lot of discussion on this area a year or so ago. My memory... The global reset signal isn't really as useful as you would like. It's just too slow. There are various kludges you can work out that will (roughly) do the right thing. I seem to remember that one of them was to generate a local reset signal and use that to startup a FSM. That takes a separate "reset" signal for each FSM and some mental checking to work it into the FSM logic. -- These are my opinions, not necessarily my employeers. I hate spam.Article: 35511
Jonathan Bromley <Jonathan.Bromley@doulos.com> writes: <snip> > Not entirely unreasonable with 256x8 PROMs, but still a b****y pain. binary pain? :-) Martin -- martin.j.thompson@trw.com TRW Automotive Technical Centre, Solihull, UKArticle: 35512
Good question.
This has been covered previously. The thread was titled:
"Is it necessary to synchronize the reset signal in an FPGA ?"
You can read my comments and others in the Archive at:
http://www.fpga-faq.com/archives/27900.html#27917
Philip
On 8 Oct 2001 23:49:23 -0700, jasjasjasjas@hotmail.com (jas) wrote:
>Hi,
>
>Are there timing issues on a Spartan device if the reset is
>asynchronous to the system clock, i.e could a problem occur where by
>the device is taken out of reset on the active clock edge, hence
>certain registers in the device remain in reset and the others are
>not. If so how is this solved, by registering the reset and not
>reseting that register?.
>
>Thanks
>
>jon
Philip Freidin
Fliptronics
Article: 35513Dedicated reset nets within FPGAs should be 'trees' which means that regardless of how long it takes for the reset to propagate throughout the chip, it arrives at all flops at the same time (roughly). Unfortunately - whether this is true or not, you can still release an asynchronous reset at the same time as a clock and you can't tell which cycle the flops are reset in. The basic idea is that asynchronous resets can be applied asynchronously but must be removed synchronously (very hard to do) to avoid problems. An alternative is to ensure your logic cannot get in a stuck state (good design practice) and use other methods to synchronise the various element of the system. A. "Hal Murray" <hmurray-nospam@megapathdsl.net> wrote in message news:ts58san373oj0b@corp.supernews.com... > > >Are there timing issues on a Spartan device if the reset is > >asynchronous to the system clock, i.e could a problem occur where by > >the device is taken out of reset on the active clock edge, hence > >certain registers in the device remain in reset and the others are > >not. If so how is this solved, by registering the reset and not > >reseting that register?. > > The global reset signal isn't really as useful as you would like. > It's just too slow. > > There are various kludges you can work out that will (roughly) > do the right thing. I seem to remember that one of them > was to generate a local reset signal and use that to startup > a FSM. That takes a separate "reset" signal for each FSM > and some mental checking to work it into the FSM logic.Article: 35514
Does somebody on this group has any experience with implementing a Microblaze soft processor core in a Virtex-2 device? Is a certain device size required to be able to implement one instance of such a core? best regards, SebastianArticle: 35515
Hey, Listers!
I've got two questions:
1.
How do you simplify this so that only one PORT MAP section left?
out_fifo_a: fifo128x8 port map (
clk => clk, sinit => not_reset, din => wsample(0), wr_en => WE_Sample(0),
rd_en => frame_clk_oc, dout => Sin_a1, full => open, empty => open);
out_fifo_b: fifo128x8 port map (
clk => clk, sinit => not_reset, din => wsample(1), wr_en => WE_Sample(1),
rd_en => frame_clk_oc, dout => Sin_b1, full => open, empty => open);
out_fifo_c: fifo128x8 port map (
clk => clk, sinit => not_reset, din => wsample(2), wr_en => WE_Sample(2),
rd_en => frame_clk_oc, dout => Sin_a2, full => open, empty => open);
2.
How do you simplify this so that only one data_out line left at the end?
data <= data_out(0) when read_fifo(0) = '1' or read_status(0) = '1' else
data_out(1) when read_fifo(1) = '1' or read_status(1) = '1' else
data_out(2) when read_fifo(2) = '1' or read_status(2) = '1' else
data_out(3) when read_fifo(3) = '1' or read_status(3) = '1' else
data_out(4) when read_fifo(4) = '1' or read_status(4) = '1' else
data_out(5) when read_fifo(5) = '1' or read_status(5) = '1' else
"00000000" & data_out_spi when read_spi_status = '1' or
read_spi_datareg = '1' else
msg_data when msg_rd_stat = '1' else
"ZZZZZZZZZZZZZZZZ";
The aim is to have a constant defined in GENERIC that tells how much PORT
MAP and DATA OUT section is needed.
Thanks for all...
Zoltan
Article: 35516I've got a W2K machine similar to yours, and got the ISE4.1 programmer to work with the parallel cable. The fileset file shows both the parallel and multilinx driver, but there's a well-documented bug affecting multilinx and some W2K installations. Originally I had the problem of the parallel not working, but it did start working after a re-install. I think maybe the install problems encountered when trying to load the multilinx caused something to not work with the parallel, but it's possible that I forgot to change the environment variable as needed. Whatever, I've now got ISE 3.3 and ISE 4.1 loaded, both cables work with 3.3 and just the parallel with 4.1. Regards Dave Kinsell delete an 'x' from address for email reply "Seb" <someone@microsoft.com> wrote in message news:%Qjv7.59250$y7.681072@dbsch1.home.nl... > i think i found out what the problem is: the Xilinx parallel III driver was > not installed (at least it didn't appear in the fileset file as the > documentation states). However, after installing the driver using the custom > installation in the setup tool, communication still doesn't work (and the > driver is still not mentioned in the fileset file). I'm puzzled (it may be a > bug?) > > I finally installed the good old JTAG programmer of the Webpack. This one > works. > > regards, > Sebastian > > > "Sebastian" <novalid@ress> wrote in message > news:3bbc1ee6$0$216$4d4ebb8e@oce.news.eu.uu.net... > > Hi Group > > > > My iMPACT program can not establish communication with the cable when > trying > > to reach the JTAG chain. > > > > My setup is straightforward: a standard pc with ecp+epp printerport, > windows > > 2000 and the small Virtex2 evaluation board connected to the parallel > port. > > I'm using Xilinx ISE4. > > > > The cable, power, etc. are all properly connected. What can be the cause? > Do > > i need to make specific port settings in Windows? > > > > thanx in advance, > > regards, > > Sebastian > > > > > >Article: 35517
Also check out Ken Chapman's latest "techXclusive" on the Xilinx web site: http://www.xilinx.com/support/techxclusives/global-techX19.htm Titled: "Get Smart About Reset (Think Local, Not Global)" Some good overview. Jason Daughenbaugh Design Engineer Advanced Electronic Designs, Inc. 2304 N. 7th Ave, Suite C-4 Bozeman, MT 59715 http://www.aedinc.netArticle: 35518
Just a note on using GSR-not using GSR with synthesis. GSR routing is free, it is dedicated copper...and can be used for nothing else. If you do NOT use GSR, and have a reset in your design (as you probably should) you are using regular routing resources for this possibly very prolific global net. In order for synthesis to use GSR (at least Synplicity) EVERY flop must be attached to GSR, or it will use regular routing resources. Why are using regular routing resources bad? If your design is quite full, it can significantly impact timing and tool run time. One design I had in an XCV300 went from 45 minutes to 9 minutes PAR time when I used GSR. As Philip's post suggests (hell, says), it is VERY easy to still use the GSR and design such that this does not create any problems with your design. It just takes a little understanding of how your design works, and a bit of engineering. "jas" <jasjasjasjas@hotmail.com> wrote in message news:fe3da0d7.0110082249.42642566@posting.google.com... > Hi, > > Are there timing issues on a Spartan device if the reset is > asynchronous to the system clock, i.e could a problem occur where by > the device is taken out of reset on the active clock edge, hence > certain registers in the device remain in reset and the others are > not. If so how is this solved, by registering the reset and not > reseting that register?. > > Thanks > > jonArticle: 35519
Hi all, I like to compare my design gate counts with diff vendors' specification. Is there a way to compare for my PDA fir filter specification like i/p bits : 16 o/p bits : 24 coeff : 24 tap size : 8, 16,32,64 also I am using shift register for shifting incoming data. Some how I come to know that my design performance can improve if I use RAM intead of shifter. How can I implement that? Thanks n_d_solankiArticle: 35520
Dear list, We have an application where we need to generate and send to a digital projector and capture by a megapixel digital camera up to 40 images per second. Each image should be digitally processed in a real time. The operations will be relatively simple mostly logical commands applied to every pixel of each image. We would like to know what hardware would be most advantageous for this project (DSP? FPGA? or other?). We would be interested in a consulting help in this area. Proximity to Los Angeles area is prefered. Michael Feygin 310-965-0129 e-mail: Mfeygin@cubictechnologies.comArticle: 35521
Hi Does anyone know how to read a file from a SmartMedia card? I would like to read an MP3 file from a SmartMedia card using VHDL. How do I locate the start of the file, and how do I read a continuous data stream until the end of the file? Thanks AndrewArticle: 35522
Get a good book on verilog, it's soo easy in comparison, now what have I started......... "Radó Zoltán" <zrado@leasingtechnology.com> wrote in message news:9pur5l$ake$1@namru.matavnet.hu... > Hey, Listers! > > I've got two questions: > > 1. > How do you simplify this so that only one PORT MAP section left? > > out_fifo_a: fifo128x8 port map ( > clk => clk, sinit => not_reset, din => wsample(0), wr_en => WE_Sample(0), > rd_en => frame_clk_oc, dout => Sin_a1, full => open, empty => open); > > out_fifo_b: fifo128x8 port map ( > clk => clk, sinit => not_reset, din => wsample(1), wr_en => WE_Sample(1), > rd_en => frame_clk_oc, dout => Sin_b1, full => open, empty => open); > > out_fifo_c: fifo128x8 port map ( > clk => clk, sinit => not_reset, din => wsample(2), wr_en => WE_Sample(2), > rd_en => frame_clk_oc, dout => Sin_a2, full => open, empty => open); > > > 2. > How do you simplify this so that only one data_out line left at the end? > > data <= data_out(0) when read_fifo(0) = '1' or read_status(0) = '1' else > data_out(1) when read_fifo(1) = '1' or read_status(1) = '1' else > data_out(2) when read_fifo(2) = '1' or read_status(2) = '1' else > data_out(3) when read_fifo(3) = '1' or read_status(3) = '1' else > data_out(4) when read_fifo(4) = '1' or read_status(4) = '1' else > data_out(5) when read_fifo(5) = '1' or read_status(5) = '1' else > "00000000" & data_out_spi when read_spi_status = '1' or > read_spi_datareg = '1' else > msg_data when msg_rd_stat = '1' else > "ZZZZZZZZZZZZZZZZ"; > > The aim is to have a constant defined in GENERIC that tells how much PORT > MAP and DATA OUT section is needed. > > Thanks for all... > > Zoltan > > > >Article: 35523
Do they not provide that in the datasheet? "himanshu" <himan_2000@indiatimes.com> wrote in message news:adf7cebe.0110080015.832fe8d@posting.google.com... > Hi, > can any body tell me what is the maximum clock speed at which xilinx > virtex-2 fpga can work?? It has got 8 DLLs..what is the maximum clock > rate they can provide. do i have to divide that frequency for clock > stability? > Thanks in advance > HimanshuArticle: 35524
My greatest grief with Xilinx (right after the blunder Xilinx made switching suppliers of the serial proms - the new supplier couldn't deliver as scheduled and the old one had been axed) has been the power-up sequencing. The FPGAs and serial proms have internal power-up sequencing circuitry so you think: "I'm ok using that". Wrong. I have seen the serial prom & FPGA get out of sync due to either too fast/slow Vcc rise time and/or a small spike on Vcc at the wrong moment. The serial prom's address counter will keep going & eventually recycle, but this takes forever! I've ALWAYS used a seperate power reset circuit after that. "Austin Franklin" <austin@darkroom88.com> wrote in message news:<ts62seat66qg87@corp.supernews.com>... > Just a note on using GSR-not using GSR with synthesis. GSR routing is free, > it is dedicated copper...and can be used for nothing else. If you do NOT > use GSR, and have a reset in your design (as you probably should) you are > using regular routing resources for this possibly very prolific global net. > In order for synthesis to use GSR (at least Synplicity) EVERY flop must be > attached to GSR, or it will use regular routing resources. > > Why are using regular routing resources bad? If your design is quite full, > it can significantly impact timing and tool run time. One design I had in > an XCV300 went from 45 minutes to 9 minutes PAR time when I used GSR. > > As Philip's post suggests (hell, says), it is VERY easy to still use the GSR > and design such that this does not create any problems with your design. It > just takes a little understanding of how your design works, and a bit of > engineering. > > "jas" <jasjasjasjas@hotmail.com> wrote in message > news:fe3da0d7.0110082249.42642566@posting.google.com... > > Hi, > > > > Are there timing issues on a Spartan device if the reset is > > asynchronous to the system clock, i.e could a problem occur where by > > the device is taken out of reset on the active clock edge, hence > > certain registers in the device remain in reset and the others are > > not. If so how is this solved, by registering the reset and not > > reseting that register?. > > > > Thanks > > > > jon
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Compare FPGA features and resources
Threads starting:
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