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You'll get a much better response out of this newsgroup if you try the design yourself first. Post your code after you've given it a try and ask why it isn't doing something specific.
Rvsoln wrote:
> hi:
> I am a fpga beginner,now i have a small design.can you advise me how to implement it?
> There is 8 data in a fifo(16x255). they must be tagged and divided when they are be read out from the fifo according to clock.So that i can operate any one of them to do other .For Example:the first data is Data0,and the second data is Data1....the eighth data is Data7.At the begining i want to implement it by shift register or state machine,but i cann't finished it
> alone as my poor digital circuit .
> it is better if you can write out verilog source code for me
> thanks!
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 37476"Rick Filipkiewicz" <rick@algor.co.uk> wrote in message news:3C16BA88.96F9E549@algor.co.uk... > Don't do it. To be precise it is by far the best practice to make sure that > during simulation startup all RAMs are initialised to unknowns since .... > ... IMO This "feature" is very dangerous and using it will make the code > highly non-portable. It also encourages s/w engineers to be sloppy & not > initialise RAMs before using them leading to some really deep and hard to > trace bugs later on. Rick, What's wrong with initializing RAMs to all zeros? That way, you get a known simulation, but you also make the SW engineers initialize the RAMs, since all zeros is mostly useless. At least the hardware will come up in a known state. Simon Ramirez, Consultant Synchronous Design, Inc. Oviedo, FL USAArticle: 37477
MaxplusII came bundled with a VHDL synthesizer (a toy) and a simulator
that was a only a little less comfortable than a root canal without
anesthesia. I don't remember if there is one in Quartus (if there is I
didn't bother installing it after the fight with the one in MaxPlus
years ago).
Mike Treseler wrote:
> Falk Brunner wrote:
>
> > So what about the simulator?
> > The VHDL compiler is a sissy
>
> Maxplus and Quartus are tools
> to place and route edif or vhdl netlists.
> To do synthesis or simulation,
> you need other tools.
>
> -- Mike Treseler
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 37478
"George P. Kosmopoulos" wrote:
> >Max plus is the easiest tool i've ever used.
> >
You obviously haven't done anything that wasn't happy with the pushbutton flow.
If that flow doesn't produce results, getting MaxplusII to produce what you want
can be a very trying experience.
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 37479
Simon, and Rick,
I think you guys are jumping to conclusions. No one said that the RAM was even
software accessible, or if it is it may be for a reprogrammable state machine
that has to start up with a default program. There are many reasons for
wanting to initialize a block RAM (or in the case of Altera, an EAB). For that
matter, the same initialization problem occurs when these blocks are used as
ROM.
The message he is getting indicates that perhaps he already has figured out how
to initialize it for simulation (that is done through generics on the
instantiated component). The initialization done with generics does not flow
through to the edif netlist, and therefore is not available for the place and
route. For xilinx, you can attach INIT= attributes to the component instance
with the initialization in it to pass the init values to the netlist. The
gotcha there is the init generics are bitvectors and the INIT= attributes are
hex strings, so you need to be careful about how you do it. You can also
generate initial values to be added thorugh the ucf, although I have not done
it that way (the instance names have to be static and known). There is a
similar mechanism for Altera, although I do not recall the name of the
attribute or the format.
If the memory is strictly read-only (ie. a ROM), Synplicity will infer the ROM
and put the correct attributes on it to initialize it. If you can't find the
information elsewhere, you could infer a ROM in the Altera device, and then
examine the edif netlist to find the name and format of the initialization
attributes for Altera. The same name and format will apply to a RAM.
"S. Ramirez" wrote:
> "Rick Filipkiewicz" <rick@algor.co.uk> wrote in message
> news:3C16BA88.96F9E549@algor.co.uk...
>
> > Don't do it. To be precise it is by far the best practice to make sure
> that
> > during simulation startup all RAMs are initialised to unknowns since ....
> > ... IMO This "feature" is very dangerous and using it will make the code
> > highly non-portable. It also encourages s/w engineers to be sloppy & not
> > initialise RAMs before using them leading to some really deep and hard to
> > trace bugs later on.
>
> Rick,
> What's wrong with initializing RAMs to all zeros? That way, you get a
> known simulation, but you also make the SW engineers initialize the RAMs,
> since all zeros is mostly useless. At least the hardware will come up in a
> known state.
> Simon Ramirez, Consultant
> Synchronous Design, Inc.
> Oviedo, FL USA
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 37480Mark wrote: > I am doing some research on place and route tools. I would like to > collect as much information as possible about them. My primary focus > is on Xilinx, but I would like to know if there are particular > features on other vendors tools that you like or dislike. Tilde (~) in front of timing values in the timing report (.twr). For Xilinx tools, this means that the path's delay could not be exactly calculated by the normal method. To quote the documentation: "In a timing report, a tilde (~) preceding a delay value indicates that the delay value is approximate. Values with the tilde cannot be calculated exactly because of excessive delays, resistance, or capacitance on the net, that is, the path is too complex to calculate accurately. The tilde (~) also means that the path may exceed the numerical value listed next to the tilde by as much as 20%" -- Phil HaysArticle: 37481
Replying to my own note. > Tilde (~) in front of timing values in the timing report (.twr). > > For Xilinx tools, this means that the path's delay could not be exactly > calculated by the normal method. To quote the documentation: > > "In a timing report, a tilde (~) preceding a delay value indicates that the > delay value is approximate. Values with the tilde cannot be calculated exactly > because of excessive delays, resistance, or capacitance on the net, that is, the > path is too complex to calculate accurately. > The tilde (~) also means that the path may exceed the numerical value listed > next to the tilde by as much as 20%" The best solution I know of is to add the "PENALIZE TILDE=##" command to the (.pcf) file. This command defaults to zero, and a value of 20 (twenty percent) should be the minimum. As the pcf file is both written by map and is a source to building the design correctly, this can cause problems with source control, so I have in my command file: # # Copy blank pcf file to design name before starting design # copy ..\blank.pcf design_name.pcf # blank.pcf is in the source directory, on level up, and is source controlled. Example blank.pcf SCHEMATIC START ; SCHEMATIC END ; PENALIZE TILDE=20; -- Phil HaysArticle: 37482
So you think that Xcell project of counter divider will work when implemented on FPGA, why ?? And the final answer that all it's OK I'll have only when I'll test the output of the FPGA. Regarding the other suggestion I would want to say that this is not just a counter but a counter/divider this means that I've to use both clock's edge to have a master_clock/3 , this essentially means that I've not solved my problem, but thanks in any caseArticle: 37483
hi, Some more basic question. Advance thanks first. I have designed a design using Xilinx XCV1000. it is working well in the pre synthesis simulation and post synthesis simulation. Now my question, i want to make use of the Constraints ( like UCF, NCF, etc), could some one throw more light on these or where can i get a full view of it. I tried in xilinx website, but could not get ( may be could not find) what i want. I know that UCF is used to specify the reletaion b/w output pins with output signals. Expecting your views and pointers. RamnathArticle: 37484
Hope my query is clear - What I want to know is - Of the Several Hard(ARM, MIPS..etc.) & Soft(Nios, ...etc.) IPs or Cores available for FPGAs, what is the Real Basis for their selection ina particular Application & WHY? Expecting a prompt reply to the above...........Dennis klonsky@hotmail.com (Noel Klonsky) wrote in message news:<cec6f878.0112110700.6f477981@posting.google.com>... > FPGAs positioned as a co-processor can accelerate software bottlenecks > by executing in parallel. > > Sometimes you can find processes of an FPGA design that by their > nature are sequential. These processes can therefore be executed by > the microprocessor. > > Best of both world's I guess > > Noel > > > > sacrosantus@yahoo.com (Dennis) wrote in message news:<24f80317.0112110215.4b06c7ec@posting.google.com>... > > sacrosantus@yahoo.com (Dennis) wrote in message news:<24f80317.0112100326.7f6c2a3b@posting.google.com>... > > > Can the Community help me in understanding the basis for the Choice of > > > Processor Cores in FPGAs(Both embedded & soft) for different kinds of > > > applications? > > > > > > Dennis Richards > > > > > > > > And Most Importantly WHY????? > > > > DennisArticle: 37485
Ramnath, Xilinx has on-line manuals on their web site, where you can find very good information on their UCF file usage: http://support.xilinx.com/support/library.htm In this page, each Xilinx software version has its own manual. It has Java browser capability, so it will take a few minutes to download the manual layout. In this page, go to "Development Reference Guide" on the left, which is Java browser, and there you'll find "Using Timing Constraints". Manual of some other commands that can be used in UCF file can be found in "Libraries Guide" and there you go to "Attributes, Carry Logic.." chapter. Link to M1.5/M1.5i manuals is http://toolbox.xilinx.com/docsan/2_1i/ in the page above, but if Xilinx puts M1.5x manual link, i.e., http://support.xilinx.com/support/sw_manuals/1_5i/index.htm to http://support.xilinx.com/support/library.htm, it will be much better from the reachability point of view. Utku Ramnath wrote: > > hi, > > Some more basic question. > > Advance thanks first. > > I have designed a design using Xilinx XCV1000. it is working well in > the pre synthesis simulation and post synthesis simulation. > > Now my question, i want to make use of the Constraints ( like UCF, > NCF, etc), could some one throw more light on these or where can i get > a full view of it. I tried in xilinx website, but could not get ( may > be could not find) what i want. > > I know that UCF is used to specify the reletaion b/w output pins > with output signals. > > Expecting your views and pointers. > > RamnathArticle: 37486
See if the device programmer has an option for setting "slow slew" outputs. Also, putting a 22-100ohm or more resistor on the glitch- affected input forms a low-pass filter with the pin input capacitance, getting rid of glitches. If the pin that's causing the glitch is driving a fair bit of capacitance, and the timing is less critical, then a series resistor on that one can fix things. Robert Abiad wrote: > > Hi, > > I should have been more clear. I will certainly do what I can to > eliminate the crosstalk (I'm confident I know what is causing it). My > question is whether changing the layout is enough to inspire confidence. > From Philip's response (which looks like a solution), it sounds like > he never trusts that his clocks will be glitch free (is that fair > Philip?). > > In general, do you always design so that external signals do not > directly feed flip-flop clocks (provided that the timing allows this)? > I've gotten away with driving FFs with all sorts of external signals > before, but I've only recently been using parts that have edges fast > enough to cause serious crosstalk and fast enough to respond to the > resulting glitches. > > -robert > > Peter Alfke wrote: > > > > > > > Robert Abiad wrote: > > > > Hi, > > > > I've recently run into the problem of getting crosstalk onto a clock > > input due to a layout problem. <snip>Or is the right approach to > > just eliminatethe glitching? > > > > Your first attempt should always be to eliminate the glitch if at all > > possible, even if it costs and hurts.Article: 37487
Hi
if you want to use a ram you can generate the functional vhdl using Altera
Megawizard (in Maxplus-Quartus or HdlDesigner ). To initialize it use a hex
(intel format) file that you can generate in Maxplus-Quartus and it's
required by Megawizard.
Then you can simulate the initialized ram.
In the netlist file, the path of hex file is got and, if correct, Maxplus
initializes the ram on chip using it.
If it doesn't find the hex file, Max-Quartus initialize the ram in some
devices (Flex, Apex etc) to a 0 value.
bye
Roberta
Litvinov wrote:
> Hello there,
>
> I'm use Mentor Leonardo and Altera Max+PlusII.
>
> Tell me, please, how to set
> initial data for RAM?
>
> library ieee;
> use ieee.std_logic_arith.all;
> use ieee.std_logic_1164.all;
>
> entity RAM is
> port(A : in std_logic_vector(7 downto 0);
> DO : out std_logic_vector(7 downto 0);
> DI : in std_logic_vector(7 downto 0);
> RW : in std_logic);
> end RAM;
>
> architecture behavior of RAM is
> signal DD : std_logic_vector (7 downto 0);
> begin
> DO<=DD when (RW)='1' else "ZZZZZZZZ";
> process (A,DI,RW)
> subtype TMemItem is std_logic_vector(7 downto 0);
> type TMemData is array(Integer range 0 to 255) of TMemItem;
> variable Mem : TMemData :=
> ("00000000","00000000","00000000","00000000",
> ...
> "10110100","11000011","11010010","11100001");
> begin
> if RW='1' then
> DD<=Mem(CONV_UNSIGNED(A,A'Length));
> else
> Mem(CONV_UNSIGNED(A,A'Length)):=DI;
> DD<="ZZZZZZZZ";
> end if;
> end process;
> end behavior;
>
> I needed synthesized VHDL description.
> Leonardo says:
> "W:/vhdl/BJCards.VHD",line 457: Warning, initial value for Mem is ignored
> for synthesis.
> But ACEX1 EP1K50QC208 supports initializing a memory. How to explain this
> for Leonardo?
Article: 37488Hi I have a problem programming the configuration ROM on my Insight Virtex2 evaluation board (xc2v40). Simply put; the FPGA won't configure itself with the ROM content. The 'done' LED does not go on after pushing the Program button. I have selected the correct type of ROM device etc. The MCS file is correctly created and verification after programming the ROM succeeds. Do you have any idea what can be the cause of this problem? I'm using ISE4.1 regards, SebArticle: 37489
Make sure the Mode pins are all pulled to ground on the board, jumpers installed. When generating the bit file make sure that your options are as follows: Under configuration tab only select the box for CRC check. Under startup select CCLK and make sure NO WAIT is selected for DLL and DCI options. Do not select "internal done pipe" Under read back options only select "Enable Readback and reconfiguration" That has worked on many different boards for me including the Insight eval board for virtex-II. Bryan "Sebastian" <novalid@ress> wrote in message news:3c178167$0$223$4d4ebb8e@oce.news.eu.uu.net... > Hi > > I have a problem programming the configuration ROM on my Insight Virtex2 > evaluation board (xc2v40). Simply put; the FPGA won't configure itself with > the ROM content. The 'done' LED does not go on after pushing the Program > button. I have selected the correct type of ROM device etc. The MCS file is > correctly created and verification after programming the ROM succeeds. > > Do you have any idea what can be the cause of this problem? > > I'm using ISE4.1 > > regards, > Seb > >Article: 37490
Robert Abiad wrote: > <snip> > In general, do you always design so that external signals do not > directly feed flip-flop clocks (provided that the timing allows this)? > <snip> In general, clocks (or other edge triggered signals) can be designed to avoid crosstalk and glitching. I have no problem taking clocks into FPGAs; heck, there has to be at least one. Using techniques like point-to-point routing (one source, one destination), solid ground planes, avoiding routes over splits in power planes, source termination, appropriate separation from other signals (relative to the distance from the ground plane), the signal fidelity on the board of these critical signals can be kept very pretty. Even with sub-ns edge rates. Much of the signal fidelity puzzle is experience. Buying experience in the form of a book or borrowing experience through the help of a coworker can help build up the base you need to produce boards that make you smile when you take a scope probe to your pins. That said, my design techniques tend to use a master clock (or two) and generate and receive slower clocks with the master clock. While a design may use 20 different clocks, most can usually digest down to one or two allowing global clock resources to be used to their fullest and reducing the effects of crossing clock domains to the synchronizers where the outside clocks meet the master clock.Article: 37491
This is a multi-part message in MIME format. --------------DAEB85487332DED57BF1E684 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit David, If you are using the Auto Core insertor, then the tool appends the constraints to the ncf file (or ucf - I cannot remember now), but it is only going to be slow. What would be more concerning is the skew since you are going to be on local routing, so I would suggest that you check to see that a MAXSKEW constraint is used with LOWSKEWLINES. Make sure that MAXSKEW is not really tight (ie <300ps) or the tool might rip up the LOWSKEWLINES and deviate to local routing. Dave David Brown wrote: > Hello > > Does anyone have an idea as to what would be an adequate constraint to > minimize the skew on the JTAG clock ? > > Xilinx's ILA Cores user guide tells us that when your design has already > used all of the BUFG (4 in my xcv600) that you should place the JTAG clock > on regular routing. They don't suggest a time value for an adequate > constraint. > > -Dave Brown --------------DAEB85487332DED57BF1E684 Content-Type: text/x-vcard; charset=us-ascii; name="dhawke.vcf" Content-Transfer-Encoding: 7bit Content-Description: Card for David Hawke Content-Disposition: attachment; filename="dhawke.vcf" begin:vcard n:;David Hawke tel;cell:(44) 778 875 5002 tel;fax:(44) 1291 621 541 tel;home:(44) 1291 621 655 tel;work:(44) 870 7350 517 x-mozilla-html:FALSE org:Xilinx UK;Northern European Sales version:2.1 email;internet:dhawke@xilinx.com title:Xilinx Field Applications Engineer adr;quoted-printable:;;Benchmark House=0D=0A203 Brooklands Road=0D=0A;Weybridge;Surrey;KT14 ORH;United Kingdom fn:David Hawke end:vcard --------------DAEB85487332DED57BF1E684--Article: 37492
"S. Ramirez" wrote: > Rick, > What's wrong with initializing RAMs to all zeros? That way, you get a > known simulation, but you also make the SW engineers initialize the RAMs, > since all zeros is mostly useless. At least the hardware will come up in a > known state. > Simon Virtex BlockRAMs are initialized to all-zeros by default, but can be initialized during configuration to any desired data. That makes them usable as ROMs. Peter AlfkeArticle: 37493
Thanks for the answers. Using a pragma, generic and attribute combination I
managed to sort this one out.
It is pretty twisted so for anyone strugling with the same issue
here is a VHDL code fragment:
...................................
component DCM
-- synthesis translate_off
generic
DLL_FREQUENCY_MODE : string;
DUTY_CYCLE_CORRECTION : boolean
);
-- synthesis translate_on
port ( CLKIN : in std_logic;
...............
STATUS : out std_logic_vector(7 downto 0)
);
end component;
....................................
attribute DLL_FREQUENCY_MODE : string;
attribute DUTY_CYCLE_CORRECTION : string;
attribute DLL_FREQUENCY_MODE of dll_ext: label is "HIGH";
attribute DUTY_CYCLE_CORRECTION of dll_ext: label is "TRUE";
attribute DLL_FREQUENCY_MODE of dll_int: label is "LOW";
attribute DUTY_CYCLE_CORRECTION of dll_int: label is "TRUE";
....................................
begin
.............................
dll_ext: DCM
port map (CLKIN=>sys_clk,
.............
LOCKED=>dll_ext_lock);
dll_int: DCM
port map (CLKIN=>sys_clk2,
..............
LOCKED=>dll_int_lock);
........................
jakab
jakab tanko <jtanko@ics-ltd.com> wrote in message
news:9v5g29$5ah$1@news.storm.ca...
> Hi,
>
> This error message is driving me nuts:
>
> ERROR:NgdBuild:604 - logical block 'ddr_ctlr/clk_dll1/dll_u' with type
> 'DCMZ0' is unexpanded. Symbol 'DCMZ0' is not supported in target
> 'virtex2'.
>
> I have a DCM component in my design (VHDL) and I use Synplify to generate
> the netlist (edif)
> for the Xilinx ISE. Somewhere along this path the DCM turns into DCMZ0 and
> I get the error message from the ISE tool.
> I searched xilinx answer records but got nowhere, did anybody
> run into this?
> Thanks,
> jakab
>
>
Article: 37494Banana wrote: > So you think that Xcell project of counter divider will work when > implemented on FPGA, why ?? Because the logic design is correct. The simulator usually has a problem with a combinatorial latch because the simulator is not intelligent enough to cope with the ambiguity of the latch state. In reality the ambiguity resolves itself, and is therefore meaningless. > And the final answer that all it's OK I'll > have only when I'll test the output of the FPGA. > Regarding the other suggestion I would want to say that this is not > just a counter but a counter/divider this means that I've to use both > clock's edge to have a master_clock/3 , this essentially means that > I've not solved my problem, You have never explained why ( or that ) you need 50/50 duty cycle. Do you really need it ? Why ? What's wrong with 33% duty cycle ? And by the way, use the DLL, it does it for you. Peter Alfke > > > but thanks in any caseArticle: 37495
Russell Shaw wrote: > See if the device programmer has an option for setting "slow slew" > outputs. Also, putting a 22-100ohm or more resistor on the glitch- > affected input forms a low-pass filter with the pin input capacitance, > getting rid of glitches. If the pin that's causing the glitch is > driving a fair bit of capacitance, and the timing is less critical, > then a series resistor on that one can fix things. > These "fixes" used to work years ago, when outputs were softer, and flip-flops were slower and thus more forgiving. Nowadays we create output transition times well below 1 ns, and input flip-flops can resolve 1 GHz ( whether the user likes that or not !), so everybody has to be more concerned about signal integrrity on the pc-board. Peter AlfkeArticle: 37496
I'll just add that HIGH SPEED DIGITAL DESIGN:- ISBN 0-13-395724-1 it's a great book which explains a lot. Dave "John_H" <johnhandwork@mail.com> wrote in message news:3C178E64.CCF4A46C@mail.com... > Robert Abiad wrote: > > > <snip> > > In general, do you always design so that external signals do not > > directly feed flip-flop clocks (provided that the timing allows this)? > > <snip> > > In general, clocks (or other edge triggered signals) can be designed to avoid > crosstalk and glitching. I have no problem taking clocks into FPGAs; heck, > there has to be at least one. Using techniques like point-to-point routing > (one source, one destination), solid ground planes, avoiding routes over splits > in power planes, source termination, appropriate separation from other signals > (relative to the distance from the ground plane), the signal fidelity on the > board of these critical signals can be kept very pretty. Even with sub-ns edge > rates. > > Much of the signal fidelity puzzle is experience. Buying experience in the > form of a book or borrowing experience through the help of a coworker can help > build up the base you need to produce boards that make you smile when you take > a scope probe to your pins. > > > That said, my design techniques tend to use a master clock (or two) and > generate and receive slower clocks with the master clock. While a design may > use 20 different clocks, most can usually digest down to one or two allowing > global clock resources to be used to their fullest and reducing the effects of > crossing clock domains to the synchronizers where the outside clocks meet the > master clock. >Article: 37497
After 2 days searching xilinx's site and manuals i found that i have the Alliance ISE4, yes i have no vhdl support. I downloaded the WEBPACK 4.1 because i want my sources to be in VHDL but i have another problem now, webpack does not support VirtexE XCV600 (goes up to XCV300). My implementation will be on a XCV600 FPGA , is there any way to make WEBPACK support the above FPGA? "Tobias Stumber" <tobias.stumber@de.bosch.com> wrote in message news:Xns91749DAD7607Bsrt2lr@128.15.0.244... > "H.L" <alphaboran@yahoo.com> wrote in > news:9v1rij$2oa5$1@ulysses.noc.ntua.gr: > > > Hello all, > > i just installed xilinx ise 4. I decided to run the tutorial but when i > > create a new project (named tutorial) i have a big problem : the ONLY > > design flow i can select is the EDIF, i want to use the XST VHDL > > design flow fot the tutorial's purposes but its absent. Can anyone help > > me? > > > > Harris L. > > > > > > > > What kind of device have you choosen ? XST vhdl is not valid > for XC9500-family CPLDs for example. > If you have installed the Alliance ISE4.1i youn dont't have > vhdl support at all. You must have the Foundation ISE4.1i. > > -- > -- Kind regards, > -- Tobias Stumber, Robert Bosch Gmbh, Leonberg GermanyArticle: 37498
Peter Alfke <peter.alfke@xilinx.com> writes: > Virtex BlockRAMs are initialized to all-zeros by default, but can be > initialized during configuration to any desired data. That makes them > usable as ROMs. Speaking of which, if you want them initialized to zeros, or perhaps to don't cares, is there a way to omit the BlockRAM config data from the config PROM in order to use a smaller PROM? If you're using a processor to load the FPGA, it could obviously do some flavor of decompression, but I'm asking about the "dumb" case. Speaking of using processors to load FPGAs, has anyone studied how compressible FPGA config data is? I'd expect in general to find that higher the device utilization results in less compressible config data, but even for high utilization I expect the data may still be fairly compressible. If the config data for repetitive structures in the FPGA don't tend to be byte-aligned in the config stream, a compression algorithm operating on bytes may not come close to optimum efficiency.Article: 37499
"H.L" <alphaboran@yahoo.com> writes: > but i have another problem now, > webpack does not support VirtexE XCV600 (goes up to XCV300). My > implementation will be on a XCV600 FPGA , is there any way to make WEBPACK > support the above FPGA? Yes. By deinstalling Webpack and installing Foundation ISE 4.1.
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