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Guessing that cache size has a first order effect on sim/compilation timing (!), are there any 'commodity' PCs which have better-than-average secondary/tertiary caches? Or are all the cache arrangements dictated by the chipset manufacturers, and effectively identical? As I recall, Athlon primary cache size = 2x Duron, and similarly for P[3|4]/Celeron.Article: 37426
Ray Andraka <ray@andraka.com> writes: >The hardware to do a PDP-8 is really quite minimal. As I recall, the >6502 had quite a few bells and whistles in the instruction set. I'd >also be vey impressed if you got a 6502 clone running at even 100 MHz in >an FPGA. The structure is not well matched to the FPGA, and designs >that are specifically tailored to the FPGA architecture have difficulty >running above about 100 MHz. I don't know them that well to compare, but I would think a 6502 wouldn't be hard to do in an FPGA. Maybe the speed was a little off, though probably not much longer before they are that fast. I think it takes a number of clock cycles for each instruction in a real 6502, and maybe in an emulated one, too. Not so many bells or whistles as the 6800. -- glenArticle: 37427
gah@ugcs.caltech.edu (glen herrmannsfeldt) writes: > I don't know them that well to compare, but I would think a 6502 > wouldn't be hard to do in an FPGA. Maybe the speed was a little > off, though probably not much longer before they are that fast. > > I think it takes a number of clock cycles for each instruction > in a real 6502, and maybe in an emulated one, too. It's fairly difficult to design it for the same number of clock cycles; the actual 6502 design is done cleverly. If you don't mind taking more clock cycles per instruction, it becomes easier to do in an FPGA, though it still takes a LARGE number of CLBs. > Not so many bells or whistles as the 6800. True. And easier ot match the cycle counts, as well.Article: 37428
> it still takes a LARGE number of CLBs. A compact, quick, and easy way to implement a 6502 in an FPGA may be to build a 100-200 LUT RISC, and then emulate the 6502 in software. (An acceptable 6502 ISA emulator would probably fit in a couple of V-II BRAMs.) The same goes for any complex bit of hardware that only has to run at a few MHz. Jan Gray Gray Research LLCArticle: 37429
I'm sorry for my intervention. I do not have an answer to original poster but an additional question in similar nature. I'm new to FPGA, VHDL, CUPL and I would like build an adderss decoder for an ISA bus board by using GAL16V8D (or something similar) rather than 7485, 74688 etc conventional TTLs. Would some one help/show/point me how to use programmable logic devices to build an adr. decoder/chip select circuit for I/O and/or memory mapped ISA bus board ? Thanks. Miem Chan miemchan@yahoo.com.au "ikauranen" <ikauranen@netscape.net> wrote in message news:b0438406.0112091404.765e9599@posting.google.com... > Hello Jason, > For implementation of the PC104/ISA interface, I suggest you to use > read/write strobes, address ADDR[], address enable AEN, and CH READY > (if delay is required) signals, without the clock. Thus, the design > will include [inferred, in the case of VHDL] register and comparator; > no state machines is required. > > Best Regards, > Igor KauranenArticle: 37430
Greetings, I apologise for the two dupes of my last message. I had some teething problems with my news client. Does anyone have any suggestions about doing functional simulations of designs containing DCM or DLLs? I am not doing anything real fancy with these DCMs, only clock mirroring, deskewing and generation of an antiphase clock, so I can model their behaviour with two assignment statements: new_clk <= old_clk; new_clk_N <= not old_clk; The trouble with doing this is that each net will see the edge in different a delta, so any net manipulated by both new_clk and old_clk will not do the expected thing because one will always appear to be one cycle behind the other, even when they aren't supposed to be. Short of doing timed simulation, which on a design of this size is infeasible, are there any tricks that can be pulled to get around this phenomenon? -- David Miller, BCMS (Hons) | When something disturbs you, it isn't the Endace Measurement Systems | thing that disturbs you; rather, it is Mobile: +64-21-704-djm | your judgement of it, and you have the Fax: +64-21-304-djm | power to change that. -- Marcus AureliusArticle: 37431
I heard that there is a $3995 special promotion for Synplicity's Synplify? FPGA synthesis solution. What is the difference between this special promotion and the 'full' version. Anybody knows?Article: 37432
Mike Treseler <mike.treseler@flukenetworks.com> wrote in message news:<3C15143B.5340D05D@flukenetworks.com>... > VHDL can do nested loops and arrays. > A numeric and math library can cover > the * and sqrt. Hi all gurus, Yet another newbie question from me. It looks like one will have to synthesize a "multiplier", a "divider" and a "square rooter"? How does one go about implementing these blocks? I am especially curious about the sqrt. Thanks. TA TA kahheanArticle: 37433
"Andrew Gray" <andrewgray@iafrica.com> wrote in message news:<3bf9932d.0@news1.mweb.co.za>... > I have their evaluation version but my design exceeds the memory limitation. Hi Andrew, You can get Modelsim Altera Edition free from Altera's website. There is no limit to the lines of code that can be simulated with ModelSim Altera Edition. However the ModelSim Altera Edition has a performance speed hit since it is free... You can get it at... http://www.altera.com/products/software/oem/oem-ms.html Take care, >Asher< PS: For synthesis you can also get Exemplar Logic LeonardoSpectrum from Altera for free too... However, a friend of mine was using LeonardoSpectrum and said it was pretty buggy software... Because of this, I would recommend not using it and using Altera's native synthesis in Quartus II.Article: 37434
"Andrew Gray" <andrewgray@iafrica.com> wrote in message news:<3bf9932d.0@news1.mweb.co.za>... > I have their evaluation version but my design exceeds the memory limitation. Also... modelsim has some info on Modelsim Altera-Edition at... http://www.model.com/partners/altera.asp Take care, >Asher<Article: 37435
Kurt,
The $3995 version is a one year, node-locked license that is
non-renewable and expires at the end of the year 2002. It does not come
with HDL Analyst, which in my opinion is invaluable for large, complex
designs. To get HDL Analyst, it costs $4,995. I think this is a steal,
since 50% of the purchase price can be applied to a new and possibly
different license the following year.
It sounds to me that Synplicity recognizes that companies are strapped
for cash, and this low price allows us to use Synplify. Then in one year,
when the economy rebounds and everyone is spending again (yeah!), we can opt
for a permanent license while still applying 50% of this year's license to
the new product.
We have Synplicity and it is the best synthesizer that we've run
across. I am amazed at how inventive companies are to weather this economic
downturn.
Simon Ramirez, Consultant
Synchronous Design, Inc.
Oviedo, FL USA
"Kurt" <kdu@quantum3d.com> wrote in message
news:1683007b.0112101717.72f9819b@posting.google.com...
> I heard that there is a $3995 special promotion for Synplicity's
> Synplify? FPGA synthesis solution. What is the difference between this
> special promotion and the 'full' version.
>
> Anybody knows?
>
Article: 37436"Asher C. Martin" wrote: > > "Andrew Gray" <andrewgray@iafrica.com> wrote in message news:<3bf9932d.0@news1.mweb.co.za>... > > I have their evaluation version but my design exceeds the memory limitation. > > Hi Andrew, > > You can get Modelsim Altera Edition free from Altera's website. There > is no limit to the lines of code that can be simulated with ModelSim > Altera Edition. However the ModelSim Altera Edition has a performance > speed hit since it is free... > > You can get it at... > > http://www.altera.com/products/software/oem/oem-ms.html > > Take care, > >Asher< > > PS: For synthesis you can also get Exemplar Logic LeonardoSpectrum > from Altera for free too... However, a friend of mine was using > LeonardoSpectrum and said it was pretty buggy software... Because of > this, I would recommend not using it and using Altera's native > synthesis in Quartus II. Leonardo works well, if you compensate for the gui bugs. Modelsim is only free if you get a subscription.Article: 37437
Using a PLD for address decoding is not hard if you know how to use the tools for designing with PLDs. The ISA decode is really just a wide AND gate with inversions on the logic low signals. You can design a PLD using a schematic based tool or you can use an HDL like CUPL, ABEL or VHDL. Often the tools are free from the logic supplier. None of this is hard. Start by getting your hands on the tools. Check with your PLD source. Miem Chan wrote: > > I'm sorry for my intervention. > I do not have an answer to original poster but an additional question in > similar nature. > > I'm new to FPGA, VHDL, CUPL and I would like build an adderss decoder for an > ISA bus board by using GAL16V8D (or something similar) rather than 7485, > 74688 etc conventional TTLs. > > Would some one help/show/point me how to use programmable logic devices to > build an adr. decoder/chip select circuit for I/O and/or memory mapped ISA > bus board ? > > Thanks. > > Miem Chan > miemchan@yahoo.com.au > > "ikauranen" <ikauranen@netscape.net> wrote in message > news:b0438406.0112091404.765e9599@posting.google.com... > > Hello Jason, > > For implementation of the PC104/ISA interface, I suggest you to use > > read/write strobes, address ADDR[], address enable AEN, and CH READY > > (if delay is required) signals, without the clock. Thus, the design > > will include [inferred, in the case of VHDL] register and comparator; > > no state machines is required. > > > > Best Regards, > > Igor Kauranen -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 37438
On Tue, 11 Dec 2001 11:37:42 +1100, "Miem Chan" <miemchan@yahoo.com.au> wrote: > >I'm new to FPGA, VHDL, CUPL and I would like build an adderss decoder for an >ISA bus board by using GAL16V8D (or something similar) rather than 7485, >74688 etc conventional TTLs. > >Would some one help/show/point me how to use programmable logic devices to >build an adr. decoder/chip select circuit for I/O and/or memory mapped ISA >bus board ? > >Thanks. > >Miem Chan >miemchan@yahoo.com.au The following code is for a trivial PAL that is used to load FPGAs via the ISA bus. It implements 2 single bit output ports and 3 single bit input ports. These connect to the FPGA's pins: PIN 18 PROG ; output PIN 19 CCLK ; output PIN 20 DIN ; output PIN 21 INIT ; input PIN 22 DONE ; input The rest of the pins go to the ISA bus, except for a chip select that can also go to the FPGA, if you need it (after config is done). Philip Freidin >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>> THIS CODE COMES WITH NO GUARANTEES. USE AT YOUR OWN RISK. NO SUPPORT AVAILABLE. COPY AND REDISTRIBUTE IF YOU WISH. (give me credit if you want) WRITTEN FOR THE NO LONGER AVAILABLE PAL COMPILATION SOFTWARE FROM INTEL. REWRITE FOR SOMETHING ELSE THAT YOU HAVE AVAILABLE. YOUR MILAGE MAY VARY. >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>> Title I/O Port for configuring LCA from PC Bus Pattern None Revision 1.0 Author Philip Freidin Company Fliptronics Date 08/17/94 CHIP config 22V10 PIN 1 IOW ; input PIN 2 SA9 ; input PIN 3 SA8 ; input PIN 4 SA7 ; input PIN 5 SA6 ; input PIN 6 SA5 ; input PIN 7 SA4 ; input PIN 8 SA3 ; input PIN 9 SA2 ; input PIN 10 SA1 ; input PIN 11 SA0 ; input PIN 13 AEN ; input PIN 14 SD0 ; input PIN 15 DEV_SEL ; output PIN 16 FPGA_SEL ; output ;PIN 17 PIN 18 PROG ; output PIN 19 CCLK ; output PIN 20 DIN ; output PIN 21 INIT ; input PIN 22 DONE ; input PIN 23 IOR ; input string base_addr ' SA9 * SA8 * /SA7 * /SA6 * /SA5 * /SA4 * /SA3 ' string dev_0 ' /SA2 * /SA1 ' string dev_2 ' /SA2 * SA1 ' string dev_4 ' SA2 * /SA1 ' string dev_6 ' SA2 * SA1 ' equations ; the following is for a base address of 0x0300 ; this matches addresses 0x0300, 0x0302 and 0x0304 for this PAL, and 0x0306 ; for the FPGA. ; PAL select is for R/W on 0x0300 and 0x0302, and W only on 0x0304 DEV_SEL = base_addr * dev_0 * /AEN * /IOW + base_addr * dev_0 * /AEN * /IOR + base_addr * dev_2 * /AEN * /IOW + base_addr * dev_2 * /AEN * /IOR + base_addr * dev_4 * /AEN * /IOW DEV_SEL.trst = vcc ; FPGA select is for R/W on 0x0306 (and its aliases) FPGA_SEL = base_addr * dev_6 * /AEN * /IOW + base_addr * dev_6 * /AEN * /IOR FPGA_SEL.trst = vcc din := sd0 * DEV_SEL * dev_0 + din * /DEV_SEL + din * dev_2 + din * dev_4 din.trst = vcc cclk := sd0 * DEV_SEL * dev_2 + cclk * /DEV_SEL + cclk * dev_0 + cclk * dev_4 cclk.trst = vcc prog := sd0 * DEV_SEL * dev_4 + prog * /DEV_SEL + prog * dev_0 + prog * dev_2 prog.trst = vcc sd0 = DEV_SEL * dev_0 * done + DEV_SEL * dev_2 * init sd0.trst = DEV_SEL * /ior ; end of design SIMULATION VECTOR A := [ SA9 SA8 SA7 SA6 SA5 SA4 SA3 SA2 SA1 SA0 ] ; ; start with iow high, address bus at 0, and done, init, and sd0 low, ; and aen and ior high ; setf IOW setf a := 0x0000 setf /done /init /sd0 aen ior ; ; while address is 0 and aen is high, clock with sd0 both 0 and 1 ; no outputs should change ; clockf IOW setf sd0 clockf IOW setf /sd0 clockf IOW ; ; now bring aen low and do it again ; no outputs should change ; setf /aen sd0 clockf IOW setf /sd0 clockf IOW ; ; take aen high, and set address to 0x0300 ; no outputs should change ; setf aen setf a := 0x300 clockf IOW setf sd0 clockf IOW ; ; with aen low, address at 0x0300, we now write a 1 to DIN ; setf /aen clockf IOW ; DIN=1 CCLK=X PROG=X ; ; set aen high, make sure we dont write ; setf aen /sd0 ; DIN=1 CCLK=X PROG=X clockf IOW ; ; set aen low, set address to 2ff, make sure we dont write ; setf /aen setf a := 0x02ff clockf IOW ; DIN=1 CCLK=X PROG=X ; ; now write a 0 to cclk and the prog ; setf a := 0x302 clockf IOW ; DIN=1 CCLK=0 PROG=X setf a := 0x304 clockf IOW ; DIN=1 CCLK=0 PROG=0 setf a := 0x300 setf /sd0 clockf IOW ; DIN=0 CCLK=0 PROG=0 ; ; set aen high, and sd0. all outputs should remain unchanged ; setf aen sd0 setf a := 0x300 clockf IOW ; DIN=0 CCLK=0 PROG=0 setf a := 0x302 clockf IOW ; DIN=0 CCLK=0 PROG=0 setf a := 0x304 clockf IOW ; DIN=0 CCLK=0 PROG=0 ; ; now write 1 to din, cclk and prog ; setf /aen setf a := 0x0300 clockf IOW ; DIN=1 CCLK=0 PROG=0 setf a := 0x302 clockf IOW ; DIN=1 CCLK=1 PROG=0 setf a := 0x304 clockf IOW ; DIN=1 CCLK=1 PROG=1 ; ; now write 0 to din, cclk, prog ; setf /sd0 setf a := 0x0300 clockf IOW ; DIN=0 CCLK=1 PROG=1 setf a := 0x302 clockf IOW ; DIN=0 CCLK=0 PROG=1 setf a := 0x304 clockf IOW ; DIN=0 CCLK=0 PROG=0 ; ; now try some reads. first do a non-read ; setf sd0 setf a := 0 setf /ior setf ior ; ; now read DONE ; setf a := 0x0300 setf /ior ; ; now check that done passes through ; setf done ; ; now read init ; setf a := 0x0302 ; ; now change init ; setf init setf /init ; ; end read ; setf ior ; ; do a read from the fpga ; setf a := 0x0306 setf /ior setf ior ; ; do a write to the fpga ; clockf IOW ; end of simulation Philip Freidin FliptronicsArticle: 37439
hi: I am a fpga beginner,now i have a small design.can you advise me how to implement it? There is 8 data in a fifo(16x255). they must be tagged and divided when they are be read out from the fifo according to clock.So that i can operate any one of them to do other .For Example:the first data is Data0,and the second data is Data1....the eighth data is Data7.At the begining i want to implement it by shift register or state machine,but i cann't finished it alone as my poor digital circuit . it is better if you can write out verilog source code for me thanks!Article: 37440
In article <MwkQ7.4189$e24.305022@news.uswest.net>, arast@qwest.net (Alex Rast) wrote: >In article <3C1168C2.5637145@xilinx.com>, Eric Crabill > <eric.crabill@xilinx.com> wrote: .. >> >>I believe, if you select File-->Main Properties... >>In the Route Options pane, you must at least turn off the >>Automatic Routing option. I typically turn off the other >>two, too (Enhanced Manual Routing and Delay Based Routing) >>because when I'm routing by hand, I am trying to achieve a >>specific result. > >Yes, I turned them all off. No go. I would always turn such options off as a >matter of course. The first thing I do when getting any new piece of S/W is to >go through every option setting in every dialog that I can find and turn off >all "auto-" anything. > >The Manual Route menu item remains greyed. Greying of the Manual Route option happens if you select connections in the switch boxes (so that there are yellow lines). So before performing the route, you need to unselect all switch boxes. I seem to remember having determined this before and just needed to jog my memory. That being said, it wasn't enough. No, the tool is very selective as to the order in which you route connections, which makes it a process of trial and error to route when you want to route subnets first. Typically that's the case I have in mind because I have a bunch of components all together, tied to the same net, that I then need to route somewhere further afield, perhaps to another cluster of components. Then, having routed the subnets, you need to lock the routing or when you connect up the subnets, the S/W will rearrange your routing willy-nilly. This, as it turns out was the main problem I'd been running into. I still can't claim to be able to spell out the logic behind the software, despite being able to spell out the logic behind the *hardware* in great detail. But I've determined that for critical routing it typically takes a combination of trial and error, and locking subnets. The one BIG hassle remaining is that if you route a subnet, then route up the rest of the net only to find it unsatisfactory, you can't unroute the rest of the net without unrouting the subnet. Tedious. Alex Rast arast@inficom.com arast@qwest.netArticle: 37441
I've already tried to implement this circuit : http://www.xilinx.com/xcell/xl33/xl33_30.pdf but how it is described in the article, it could have some glitch problem during simulation phase and in fact I've it using Aldec 5.1 . Can you explain me better how I can implement your idea in vhdl ??? ThanksArticle: 37442
sacrosantus@yahoo.com (Dennis) wrote in message news:<24f80317.0112100326.7f6c2a3b@posting.google.com>... > Can the Community help me in understanding the basis for the Choice of > Processor Cores in FPGAs(Both embedded & soft) for different kinds of > applications? > > Dennis Richards And Most Importantly WHY????? DennisArticle: 37443
"Kurt" <kdu@quantum3d.com> wrote in message news:1683007b.0112101717.72f9819b@posting.google.com... > I heard that there is a $3995 special promotion for Synplicity's > Synplify? FPGA synthesis solution. What is the difference between this > special promotion and the 'full' version. Kurt, Where did you hear about this special promotion? I can't find any information on the website.... Thanks MHArticle: 37444
Hello, I have been using a 8051 controller to program a XC9536 cpld using the JTAG interface. I have programmed several hundreds of units in the last couple of years without any problems, but now programming the cpld by the 8051 fails for more than half the units produced. The PCB's do not show shorts or open connections or other production errors. With some care the cpld (while on the pcb) was connected to a Multilinx programming device which succesfully programs the cpld. The programming algorithm on the 8051 is based on Xilinx app notes XAPP058 and XAPP067. The CPLD fails to generate the correct TDO output for verification after a program or erase instruction. The scope shows appropriate XRUNTEST idle times for these instructions (640us/1300ms). TCK period is larger than 2us. On the scope I compared JTAG output from the 8051 and the multilinx device. The only real difference is that the multilinx does not instruct the cpld to return to Run/test/idle mode after update-IR (see figure 7 in XAPP058) for the instructions 'isp enable', 'erase' and 'program', which are then immediately followed by a SDR instruction. Questions: - Has anything changed recently in the JTAG interface for the xc9536 that might cause a microcontroller to fail programming the cpld. - Where do i find detailed information on JTAG timing and xc9536 timing during programming. It is not found in the Xilinx data book. - Are there timing constraints associated with the Jtag interface or xc9536 other than the TCK period and XRUNTEST idle times? - besides the xc9536.bsd file there exists a xc9536_v2.bsd file. The device marking does not say so, but could the device be a v2 type that must be used with the other bsd file? And if so, how do i use that files, i can not select a version-2 9536 as a target device. Thanks, Alco Looye alco@cardiocontrol.comArticle: 37445
> process (clk) > begin > if reset='1' then > cnt_1<="0000"; > cnt_2<="0000"; > cnt_3<="0000"; > elsif clk='1' and clk'event then > cnt_1<=cnt_1+1; > if cnt_1=15 then > cnt_2<=cnt_2+1; > if cnt_2=15 then > cnt_3<=cnt_3+1; > end if; > end if; > end if; > end process; > Thank you another time, I understood what you mean, but my problem is just for that particular structure. Anyway thank you for your hints, Luigi.Article: 37446
Hi, averybody, I must use "ramb4_s1_s16" in my Xilinx vertexE based coding. But I don't have the file "ramb4_s1_s16.vhd". I have tried to modify the any single port RAMB4, but failed. Thanks. Gyunseog.Article: 37447
Hello, Does anyone know how disable and enable the 'auto-keyboard switching' in the HDL editor in ISE 4.1 ? Auto-keyboard switching is the term Microsoft uses for the stupid --> you must type a ' and a <space> to display a ' (or "). It is really getting on my nerves, and I don't know how to switch it of. (in Word it's under tools / options / edit) Please let me know, Greetings, LennartArticle: 37448
Gyunseog Yang wrote: > > Hi, averybody, > > I must use "ramb4_s1_s16" in my Xilinx vertexE based coding. > But I don't have the file "ramb4_s1_s16.vhd". > I have tried to modify the any single port RAMB4, but failed. > > Thanks. > > Gyunseog. If you have a Xilinx tool installed in your machine, UNIX (Sun/HP) or Winxx whatever, there should be RAMB4_* entity/architecture codes in unisim_VCOMP.vhd in $XILINX/vhdl/src/unisims (for RTL simulation) $XILINX/vhdl/src/simprims (for gate-level simulation) In the case of Verilog, where you can use Verilog models of Xilinx elements in your VHDL design (if you have mixed-language simulator like Modelsim), then RAMB4_* Verilog models are stored in separate files, unlike VHDL, in $XILINX/verilog/src/unisims (for RTL simulation) $XILINX/verilog/src/simprims (for gate-level simulation) If you have any Xilinx tools installed, you must have these directories. Otherwise, your installation is incomplete. Please go your CAD admin. UtkuArticle: 37449
"S. Ramirez" wrote: > Kurt, > The $3995 version is a one year, node-locked license that is > non-renewable and expires at the end of the year 2002. It does not come > with HDL Analyst, which in my opinion is invaluable for large, complex > designs. To get HDL Analyst, it costs $4,995. I think this is a steal, > since 50% of the purchase price can be applied to a new and possibly > different license the following year. > It sounds to me that Synplicity recognizes that companies are strapped > for cash, and this low price allows us to use Synplify. Then in one year, > when the economy rebounds and everyone is spending again (yeah!), we can opt > for a permanent license while still applying 50% of this year's license to > the new product. > We have Synplicity and it is the best synthesizer that we've run > across. I am amazed at how inventive companies are to weather this economic > downturn. > Simon Ramirez, Consultant > Synchronous Design, Inc. > Oviedo, FL USA > > "Kurt" <kdu@quantum3d.com> wrote in message > news:1683007b.0112101717.72f9819b@posting.google.com... > > I heard that there is a $3995 special promotion for Synplicity's > > Synplify? FPGA synthesis solution. What is the difference between this > > special promotion and the 'full' version. > > > > Anybody knows? > > Beware: node-locked => you can't run Synplify from the command line using a Tcl script.
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