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Austin Lesea wrote:
<snip>
> This is something we have carefully characterized, as we are the 'FPGA Lab'
> responsible for the verification of the design.
>
Is there a suitable LVDS test board available from Xilinx, or one
of the distributors, to make both clock tree jitter and wide LVDS
output bus skew measurements prior to building a real board?
I've been meaning to measure the Virtex-II clock distribution and
DDR output register phase noise directly on an HP 3048A under various
conditions, but haven't been able to locate a suitable FPGA test board
that also has at least 16, preferably 32, pairs of LVDS outputs to
measure the data line skew.
The most promising one I'd found was the Insight Microblaze board,
whose color glossy mentions 16 bits of LVDS out, but am awaiting detail
from Insight on the LVDS and clock connectors & PCB routing thereof.
e.g.:
- SMA connector pairs ( or a suitable balanced connector ) to at least
one LVDS global clock input & output
- 16-32 bits of controlled impedance, balanced LVDS output pair runs,
sourced from the same bank ( or at least the same side of the chip ),
routed to a suitable connector
Brian
Article: 37251Hi Philip, Just out of curiosity... > If a metastability occured or you failed a setup/hold requirement, you might > see something like the following: > > 1,0,0,0 <- (1) > 0,0,0,0 <- (2) > 1,0,0,0 > 1,1,0,0 > 1,1,1,0 <- match case > 1,1,1,1 > 1,1,1,1 I do not understand how (1) going to (2) is possible. I am thinking you are showing the possible scenario when we sample the SPI enable signal right on its rising transition. The '1' output from the first FF in (1) may be undergoing meta-instability, so in (2), the second FF may clock out either '1' or '0'. But surely in (2), the first FF would be outputting a '1'? I am thinking we may see something like below. > 1,0,0,0 <- (1) > 1,0,0,0 <- (2) > 1,1,0,0 > 1,1,1,0 <- match case > 1,1,1,1 > 1,1,1,1 Also, is the 4th FF necessary? Can't we just decode on 2nd and 3rd FF being "10"? (see below) > 1,0,0 > 1,0,0 > 1,1,0 <- match case > 1,1,1 Also, why can't we use the decoded enable signal directly (instead of passing it through yet another FF, as you described in your post). I am questioning very minor details. But I don't want to miss knowing anything fundamental pitfall. :-) Thanks in advance. TA TA kahheanArticle: 37252
Folks, I am using Leonardo Spectrum to synthesize my design. However in the PPR stage (Mapping) the following error message occurs : ERROR:NgdBuild:455 - logical net 'CLK_R' has multiple drivers ERROR:NgdBuild:466 - input pad net 'CLK_R' has illegal connection Can you give me some advices to solved this problem ? FYI: I am targeting to Xilinx XCV800. Thank you for your attention. Regards, BasukiArticle: 37253
On 4 Dec 2001 18:14:25 -0800, kahhean@hotmail.com (Chua Kah Hean) wrote:
>Hi Philip,
Hi
> .... following stuff ....
>I am questioning very minor details. But I don't want to miss knowing
>anything fundamental pitfall. :-)
You are right to ask these questions, I will address each one.
In particular, my answer to you gave recommendations, without explanation
or justification. I will try and remedy this in this response. As your questions
indicate, you understand my intent, just not why I am making the
recomendations that I have made.
On 4 Dec 2001 18:14:25 -0800, kahhean@hotmail.com (Chua Kah Hean) wrote:
>Hi Philip,
>
>Just out of curiosity...
>
>> If a metastability occured or you failed a setup/hold requirement, you might
>> see something like the following:
>>
>> 1,0,0,0 <- (1)
>> 0,0,0,0 <- (2)
>> 1,0,0,0
>> 1,1,0,0
>> 1,1,1,0 <- match case
>> 1,1,1,1
>> 1,1,1,1
>
>I do not understand how (1) going to (2) is possible. I am thinking
>you are showing the possible scenario when we sample the SPI enable
>signal right on its rising transition. The '1' output from the first
>FF in (1) may be undergoing meta-instability, so in (2), the second FF
>may clock out either '1' or '0'. But surely in (2), the first FF
>would be outputting a '1'? I am thinking we may see something like
>below.
>
>> 1,0,0,0 <- (1)
>> 1,0,0,0 <- (2)
>> 1,1,0,0
>> 1,1,1,0 <- match case
>> 1,1,1,1
>> 1,1,1,1
You are right. But the problem is with the fact that I didnt explain the time
scale for the sequence. You have made the reasonable assumption that
each line of my table is the result after each rising clock (in the 40 MHz
domain). But what I was intending to show is the first flipflop going
metastable, and going from 0 to 1 and back to 0 within 1 cycle. The rest of
the lines of the table are the shift register state after each clock. Here is
the table again, with some time stamps.
The 40MHz clock rising edge occurs every 25ns, starting at T = 0 ns.
The flipflops have a clock to output settling time delay of 1 ns
0,0,0,0 time = 0 ns
0,0,0,0 time = 1 ns
0,0,0,0 time = 25 ns
1,0,0,0 time = 26ns
0,0,0,0 time = 30ns
1,0,0,0 time = 51ns
1,1,0,0 time = 76 ns
1,1,1,0 time = 101 ns <- match case
1,1,1,1 time = 126 ns
1,1,1,1 time = 151 ns
We see at time 30 ns that Q0 returns back to 0 without a clock event. I.E. it
went metastable because the D input was changing very close to T = 25 ns
You will note that if we remove the line for 30 ns, we get the table you
suggested. I.E. only show the state after each rising clock edge.
>Also, is the 4th FF necessary? Can't we just decode on 2nd and 3rd FF
>being "10"? (see below)
>
>> 1,0,0
>> 1,0,0
>> 1,1,0 <- match case
>> 1,1,1
Yes we could, but it would not be as reliable. We could even throw away
the 3rd FF, and just decode 1,0 , and this would also work, but would be
even less reliable. As you may know, the time it takes a FF to resolve
a metastable state is unbounded (could be infinity), but the probability
that it takes longer than some specified time is a negative exponential
function of the specified time (called the resolution time). My above example
suggests that the first FF resolves the metastability in less than 5 ns. But
this is not guaranteed, it could take longer (with lower probability of
happening).
Let's look at the highly unlikely case of the metastability taking 24.5 ns
to resolve, and it resolves back to 0:
0,0,0,0 time = 0 ns
0,0,0,0 time = 1 ns
0,0,0,0 time = 25 ns
1,0,0,0 time = 26ns FF 0 has gone metastable, but out put is seen as 1
1,0,0,0 time = 49.0ns
0,0,0,0 time = 49.5ns FF 0 resolves metastability, goes back to 0, but
FF 1 sees enough of FF 0 being 1 to go to 1 itself,
but FF 1 goes metastable
1,1,0,0 time = 51 ns FF 0 now goes to solid 1, FF 1 is metastable
1,0,0,0 time = 54 ns FF 1 resolves metastable and goes back to 0.
1,1,0,0 time = 76 ns FF 0 and 1 are both solid 1
1,1,1,0 time = 101 ns <- match case
1,1,1,1 time = 126 ns
1,1,1,1 time = 151 ns
How likely is this? Very rare, but possible. An old rule of thumb is that
the probability of metastability not being resolved drops by a factor
of 40 for every additional nanosecond of resolution time. So for however
rare the resolves in 5 ns case might have been, this case is far less
likely:
(in the following "^" is "raised to the power")
Resolved by 49.5 ns, clock was at 25 ns => 24.5 ns resolution time.
24.5 ns - 5 ns => 19.5 ns
probability ratio is 1 divided by 40^19.5 which
my calculator says is about 1.7 * 10^31
If the 5 ns case occured once per second, the 24.5 ns case would occur
once per 5.5 * 10^23 years. More than enough time for you to ship the
product, get your bonus cheque, and change jobs and be working for
another company before a failure occurs.
But:
A) the 40 times improvement may be itself off by a factor of 4, either
way (i.e. 10 thru to 160).
B) I might be building big systems with 100s or 1000s of such sub
circuits.
C) I might be shipping millions of systems.
(although it is hard to imagine a high volume consumer product that
would need 1000 synchronization boundaries :-)
D) maybe the failure rate at 5 ns occurs 1000 times a second
This could give numbers like:
(1000 / (10^19.5)) * 1000 * 1000000
= 3.16 * 10^-17 * 10^3 * 10^6 = 3.16 * 10^-8 (failures per second
across all systems built)
=> 1 failure per 1.0027 years.
( i.e. build 1,000,000 systems each with 1000 resoultion circuits,
each of which fails 1000 times a second at the 5 ns resolution time,
and given an extra 19.5 ns of resoultion time, and the improvement
for resolution is a factor of 10 per each extra ns)
Are these numbers silly. Yep. Do they show that even with great
amounts of resolving time (19.5 ns is lots) , I can still contrive
a situation where failures may occur before I have moved on to my
next job.
Plus, chip vendors dont have up to date metastability numbers for
current products, and I probably made some mistakes in the above
math.
Would you want a pacemaker from a batch that one of will fail every
year? does your answer change if the batch size is 1000000
pacemakers?
Coming back to reality, let me just say that at some point my eyes
just gloss over and it is easier to add an extra stage or two of
resolution, and know that the mean time to failure exceeds the life
of the universe, rather than figure out if the failure rate is once
a year or once a mega-year. This assumes that the latency is not a
big issue. This is what your case is like. If latency is an issue,
then detailed analysis is required, to minimize the number of
stages.
So, now on to the answer :-)
My recommendation was look for 1,1,1,0
Which has a 25 ns resolving time from FF 0 to FF 1 , and 25 ns more
from FF 1 to FF 2. FF 3 is not involved in this calculation, as we
are detecting that it is still 0. So basically 2 stages of resolution,
or 50 ns. From experience with FPGAs, this should be more than enough.
Dropping out the last stage as you asked, and matching 1,1,0 basically
only gives a single stage of metastability resolution. Without
detailed calculations, I would not feel comfortable with this.
>Also, why can't we use the decoded enable signal directly (instead of
>passing it through yet another FF, as you described in your post).
By passing it through 1 more FF, I get 2 things. First, I get to be
really comfortable, because it is adding another (approx) 25 ns of
resolution time, and second, the timing model for distribution
of the CE signal from this last FF, is simple as no gates are involved.
>I am questioning very minor details. But I don't want to miss knowing
>anything fundamental pitfall. :-)
I hope you find the above useful.
>Thanks in advance.
>TA TA
>kahhean
Philip Freidin,
Metastability Crusader.
Philip Freidin
Fliptronics
Article: 37254Hi folks, while modeling all those drivers, buffers and latches around my FPGA, I ran into a problem which may be caused by "PULLUPS". My PULLUP is a component which drives the line(s) with 'H' so that it can be overwritten from other driving sources on that net. Imagine my pullup now on a "DIR" input of a 245-buffer. The pullup keeps the "DIR" signal high during FPGA boot procedure and everything is save in the real world. In my testbench I defined the pullup as mentioned above and connected it to my model of the 245-buffer. Now the problem occurs: In the model the behavior of the buffer only depends on the status of signals which can be one of '1' or '0'. If I apply a 'H' (or 'L') to the inputs, the behavior of the model is not correct. My first suggestion was to redesign all my models so that they can also handle the mixed signals '1','0','H' and 'L'. This is a huge bunch of work so my question: How do you handle pullups in board level simulations ? Is there perhaps an easier way to go ? -- TomArticle: 37255
"Kuan Zhou" <zhouk@rpi.edu> wrote in message news:Pine.SOL.3.96.1011204163738.11666B-100000@rcs-sun1.rcs.rpi.edu... > Hi, > Is there a free version of JBit or JRoute that > I can get from the website? You need to contact Xilinx directly at: JBits@xilinx.com. They will then send you the relevant details. Stephen Melnikoff. -- Stephen Melnikoff - s.j.melnikoff@iee.org Electronic, Electrical and Computer Engineering University of Birmingham, Birmingham, UKArticle: 37256
Laurent, to configure an ACEX 1K device in a JTAG chain you need to create a JAM file (.jam or .jbc). You can then use a JAM-Player on a PC or embedded platform to drive the JAM file to the JTAG chain. MAX+plus II Baseline should be able to generate JAM files. Open the Programmer and go to "File/Create JAM or SVF file". You can download various JAM players and find more information on JAM at: http://www.jamisp.com - Wolfgang http://www.elca.de "Laurent SANDRIN" <laurent.sandrin@espci.fr> schrieb im Newsbeitrag news:9uihpq$1r32$1@vishnu.jussieu.fr... > I would like to know how to generate jedec files for jtag programming with > Max++ baseline V10.0 and a ByteblasterMV ? > Do we have to get full Max++ in order to generate jedec ? > We are trying to programm an Acex 1K100 through a JTAG chain that also > contains Xilinx PLDs and a DSP from TI. > Thanks > > Laurent > >Article: 37257
Hi all, I have two huge Xilinx FPGA lots advertised on ebay. Some of the chips are used, but others I believe are new. Check the link below. Enjoy! JIQ http://cgi6.ebay.com/aw-cgi/eBayISAPI.dll?ViewListedItems&userid=avayan&include=0&since=-1&sort=2&rows=25Article: 37258
Brian, Contact your FAE. The total clock skew in a 2V6000 is +/- 60 ps to any IOB, anywhere (using DDR FF's). The flight time of the package is +/- 40 ps. If you need to equalize the flight times for the package by trace lengths on the pcb, we offer a map of the flight times per pin, in 5 mm length increments. Compensating for the clock tree is not practical. The FAE has access to the timing budgets, SPI POS 4 IP core literature, our own LVDS serdes solutions cores, and all preliminary timing information. The sample window, when using the variable phase shift to place the clock in the center of the data is being characterized fully right now, and will be available shortly. The number includes the clock tree skew, and jitter from the DCM, as well as the sample window of the input FF's, and a system jitter budget for other activity, but needs a little more work yet before we publish it (have to make such small measurements in a tester environment on thousands of parts!). The next data sheet will contain such information for clock and data forwarding applications. Austin Brian Davis wrote: > Austin Lesea wrote: > <snip> > > This is something we have carefully characterized, as we are the 'FPGA Lab' > > responsible for the verification of the design. > > > Is there a suitable LVDS test board available from Xilinx, or one > of the distributors, to make both clock tree jitter and wide LVDS > output bus skew measurements prior to building a real board? > > I've been meaning to measure the Virtex-II clock distribution and > DDR output register phase noise directly on an HP 3048A under various > conditions, but haven't been able to locate a suitable FPGA test board > that also has at least 16, preferably 32, pairs of LVDS outputs to > measure the data line skew. > > The most promising one I'd found was the Insight Microblaze board, > whose color glossy mentions 16 bits of LVDS out, but am awaiting detail > from Insight on the LVDS and clock connectors & PCB routing thereof. > > e.g.: > > - SMA connector pairs ( or a suitable balanced connector ) to at least > one LVDS global clock input & output > > - 16-32 bits of controlled impedance, balanced LVDS output pair runs, > sourced from the same bank ( or at least the same side of the chip ), > routed to a suitable connector > > BrianArticle: 37259
You'd be doing yourself and us a favor if you'd post full part numbers of all the parts. Jose I Quinones wrote: > > Hi all, > > I have two huge Xilinx FPGA lots advertised on ebay. Some of the chips > are used, but others I believe are new. Check the link below. Enjoy! > > JIQ > > http://cgi6.ebay.com/aw-cgi/eBayISAPI.dll?ViewListedItems&userid=avayan&include=0&since=-1&sort=2&rows=25Article: 37260
Jim Stewart wrote: > > You'd be doing yourself and us a favor if you'd post full part numbers > of all the parts. and accepted international bids AndyArticle: 37261
Nick wrote: > > hi, > > I am using Quartus I, to compile a ( medium size project 18% logic > element 10%memory) for an APEX20KE400. > > I am using verilogXL to compile the net list output of the compilation > and i find a setup problem on an internal register, regardless of the > clock frequency that i use, to feed the design for the simulation purposes. If you are talking about a synthesis netlist, I wouldn't worry about it. > The quartus did not report any such problem and did met my timing > requirements If the quartus register to register timing passes, you should be fine. Consider loading Quartus II. -- Mike TreselerArticle: 37262
This is a multi-part message in MIME format. --------------7216D6A6BBF18521E01BFFE2 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Mike Treseler wrote: > Nick wrote: > > > > hi, > > > > I am using Quartus I, to compile a ( medium size project 18% logic > > element 10%memory) for an APEX20KE400. > > > > I am using verilogXL to compile the net list output of the compilation > > and i find a setup problem on an internal register, regardless of the > > clock frequency that i use, to feed the design for the simulation purposes. > > If you are talking about a synthesis netlist, I wouldn't worry about it. > > > The quartus did not report any such problem and did met my timing > > requirements > > If the quartus register to register timing passes, you should be fine. I don't know. I would be a little more cautious. Is this path crossing clock domains? I don't think the timing reports defaultly report paths crossing clock boundaries. Is clock skew being accounted for? Not sure exactly how Quartus accounts for this but is especially important if you are not using global clock resources (i.e. using more than 4 clocks). Are you clocking on both edges of the clock? Does any part of the path originate from an I/O? Is the path to a clock enable? Seems I have heard about problems with Quartus where in certain circumstances would not properly report timing to register clock enables. I am not saying there is necessarily a problem here but I also would not blindly disregard this as it may manifest itself as an intermittent problem later. If it was me, I would want to get to the bottom of the problem. If you were targeting Xilinx, I could give you some suggestions to help debug this issue but... -- Brian > > > Consider loading Quartus II. > > -- Mike Treseler --------------7216D6A6BBF18521E01BFFE2 Content-Type: text/x-vcard; charset=us-ascii; name="brian.philofsky.vcf" Content-Transfer-Encoding: 7bit Content-Description: Card for Brian Philofsky Content-Disposition: attachment; filename="brian.philofsky.vcf" begin:vcard n:Philofsky;Brian x-mozilla-html:FALSE adr:;;;;;; version:2.1 email;internet:brian.philofsky@xilinx.com fn:Brian Philofsky end:vcard --------------7216D6A6BBF18521E01BFFE2--Article: 37263
Does anyone know if WebPack and Student Edition can be installed at the same time? Thanks. -DaveArticle: 37264
Brian Philofsky wrote:
> I don't know. I would be a little more cautious. Is this path crossing clock
> domains?
I was assuming a synchronous design.
He said it was an internal register.
> Is clock skew being accounted for? Not sure exactly how Quartus
> accounts for this but is especially important if you are not using global clock
> resources (i.e. using more than 4 clocks).
Yes, in either case.
> Are you (Nick) clocking on both edges of the clock?
I hope not.
> Does any part of the path originate from an I/O? Is the path to a clock
> enable? Seems I have heard about problems with Quartus where in certain
> circumstances would not properly report timing to register clock enables.
Reference please?
> I am not saying there is necessarily a problem here but I also would not blindly
> disregard this as it may manifest itself as an intermittent problem later. If it
> was me, I would want to get to the bottom of the problem. If you were targeting
> Xilinx, I could give you some suggestions to help debug this issue but...
Is this a sales call?
--Mike Treseler
Article: 37265
Austin Lesea wrote:
>
> Contact your FAE.
>
Been there. Done that.
March '01:
Xilinx rep/FAE : XC2V40 board in San Jose labs
nothing available for customer use
Oct/Nov. '01:
Xilinx rep/FAE : nothing available for customer use
Avnet Xilinx FAE : no such animal
Insight Xilinx FAE : awaiting technical detail
Could you at least confirm or deny the existence, if not
the customer availability, of the "16 bit LVDS demo board"
mentioned in the VHDL source files for XAPP-265 ?
snippet from top16.vhd:
-- Top level design for 16 bit Xilinx LVDS demo board version 1
thanks,
Brian
Article: 37266Brian, See below. Austin Brian Davis wrote: > Austin Lesea wrote: > > > > Contact your FAE. > > > Been there. Done that. Please email me at austin@xilinx.com and tell me who your FAE is. > > > March '01: > Xilinx rep/FAE : XC2V40 board in San Jose labs > nothing available for customer use Yes. That was true. > > > Oct/Nov. '01: > Xilinx rep/FAE : nothing available for customer use > Avnet Xilinx FAE : no such animal > Insight Xilinx FAE : awaiting technical detail Yes, that was true, too. > > > Could you at least confirm or deny the existence, if not > the customer availability, of the "16 bit LVDS demo board" > mentioned in the VHDL source files for XAPP-265 ? It exists now, and it is being "finished." Marketing Apps will get really mad at me if I say anything more. And, with good reason, as they have to bless the pcb, the documentation, and the rest before they go live with it. > > snippet from top16.vhd: > -- Top level design for 16 bit Xilinx LVDS demo board version 1 > > thanks, > Brian We recognize now that we did not have the all of the necessary collateral pcb's ready like we did at the launch of Virtex for Virtex II. There are at least 12 pcbs that can be built for any product release, and we will do a better job in the future.Article: 37267
designed FPGA for Apple II computer... I want it...Article: 37268
where is FPGA APPLE...Article: 37269
Hi All, Just been reading about the different uses for FPGA's and was wondering if anyone knows if MPEG4 decoding is well suited for a FPGA, or is a more traditional microprocessor/controller better? (also, are there FPGA 'beginner' boards for PC's available, or do I have to devote a career to them first? :) ) Thanks, QuigleyArticle: 37270
I want to implement FFT in FPGA with block float dataword format.Who can tell me where there is introduction of block float calculator?Article: 37271
Hi, If the SPI clock is much slower than the FPGA clock (1/8 or less), it may be easier to synchronize the three input signals and run the whole receive logic on the global FPGA clock: * Use a two-FF synchronizer on all input lines (one may be in the I/O pad); * Use an Edge Detector on the synchronized SPI-clock to enable shifting of an (also synchronized) SPI-data bit into your shift-register. VR <crossing@notjordanbutaclockdomain.com> wrote in message news:<9uevt7$1aq$1@news.utdallas.edu>... > Hey all. > > I have a uC that's updating a register in my XC4010E via a standard "three-wire" SPI. > > The uC writes to an 8-bit shift register in the FPGA -- the uC's SPI clock is used to clock > the FPGA flip-flops and the SPI_nCS (chip select) is used as the ENABLE(active low) to the > register for shifting. > > To prevent any odd behavior, I am double buffering my data -- the shift register is one > buffer, and I parallel load the data from the shift register into a second 8-bit register, > which is clocked by my FPGA native 40MHz clock. (The 2nd register feeds the inputs of a > loadable free running counter). > > My problem is in the the control of the second register. I only want this register to update > when data(in the SPI register) is valid but the SPI register is being clocked by something > completely asynchronous to the FPGA's clock. > > My first idea was to use the SPI_nCS as the ENABLE(active high) on the second register; the > register would clock in data on rising edges of the FPGA clock and only when SPI_nCS was high. > Since the SPI_nCS "envelope" surrounds an SPI transaction, when the signal is NOT low, I know > an SPI operation wouldn't be occurring. > > I also wondered if a better solution might be to use three T-flip-flops and divide down the > uC's SPI clock by 8, so on the 8th clock(when the last bit from the uC gets clocked into the > shiftreg) I register the SPI register's data. I would use the output from the third T-FF as > the ENABLE(active high) on my 2nd register and still clock the 2nd register from the FPGA > 40MHz clock. > > I'm sure all of the above will work, but I didn't know which would be a better solution (if > any) and if there are other things to keep in mind. > > Thanks, > VR.Article: 37272
"Kiyoung SON" <elcielo0@hitel.net> writes: > designed FPGA for Apple II computer... > I want it... There's an FPGA on the Apple II Video Overlay card. That's been out of production for at least eight years, though. Nice card.Article: 37273
Thanks for this insight. Using an FPGA-editor isn't objectionable, as standard-cell ASIC design flows require a lot of backend work. (So the FPGA-editor is probably just a small bit of work compared to the workflow of an ASIC backend.) I was merely stressing over the possibility of having to 'over-register' signals to trim critical-paths in an FPGA-part. By 'over-registering', I mean inserting excessively amounts of flipflops at 'unnatural' points. My friend's company was considering a perpetual-license for Synopsys's PCI IP core. Since the target architecture is a standard-cell ASIC, I very much doubt that core would run "out of the box" on an FPGA-device, even on a relatively state-of-the-art VirtexE. > IIRC, the VirtexE was the first family they claimed for 66MHz 64 bit. To > get there, you need to use the TRDY logic that is embedded along the sides > of the array. The synthesis tools and even the mapper and pAR don't know > about this little added logic, so if you need to use it, you have to go into > the FPGA editor and add it to the design. Without it, I think you'll find > that you won't hit the 66 MHz 64 bit PCI spec, certainly not for the > original 2.5v Virtex, and I'm pretty sure not for the Virtex E either.Article: 37274
> "Kiyoung SON" <elcielo0@hitel.net> writes: > > designed FPGA for Apple II computer... > > I want it... > > There's an FPGA on the Apple II Video Overlay card. That's > been out of production for at least eight years, though. > Nice card. Hmm, I think the original poster wanted to know if there was an AppleII implementation/emulation available on FPGA...
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