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> I generate code from an assembler that's then run through a > little utility to create a series of "INIT_xx=" attributes. > Is it possible to script the update so that I don't have to > key anything ? I think I have seen posted before that it's > possible to modify the bitstream (using a program) to do this. > I'd like to automate the whole thing if possible. (My coding > skills are expert C/C++ preferred and I'm not afraid to hack > things as long as I have the info..). Another method, besides FPGA Editor, would be the XDL ASCII design language; alas, it is also missing from the Webpack tools. XDL is a nifty ASCII <-> NCD conversion utility that was supplied and documented in the xilinx/userware/doc directory of the 2.1i release; the executable is still supplied sans documentation ( other than its' built in help ) in the later versions. Also note, if you try the FPGA Editor trick with 2.1i ( i.e. the student edition tools), the INIT attributes can not be edited properly within the FPGA Editor, see Xilinx solution record 7167 in the answers archive ( I don't think they ever fixed that in any 2.1i service packs ). Your best bet may be to use Jbits or hack your own bitstream editor as you mention; I think the Xilinx app notes on Virtex bitstreams give enough information to do this. When I started using block RAMs for my own processor tinkering, I came up with a mental list of ways to get the bits into their proper places, which went something like this: 1) VHDL file generator, constant array for simulation & inferred RAMs 2) VHDL file generator, INIT attributes for instantiated RAMs 3) FPGA Editor command script 4) XDL based NCD file editing 5) homebrew bitstream mangler In the real world, once I had #2 working, the first 'real' program I wrote was a tiny debug monitor, which lets me download over an RS232 link. Once that was working, I never got around to writing any of the others... A small 'copy N bytes of data from the serial port into RAM & execute' bootstrap routine would fit in even less space than a tiny monitor; a small ROM built with a single bank of 32 x instruction_width CLB ROM's would probably hold it with room to spare, leaving the entire block RAM free for user code. BrianArticle: 38001
What is an "FPGA editor" ? :) Anyway, since you know that RAM block content initialization is accomplished (in Xilinx FPGA tools) via INIT_XX parameters, and understand that nice ISE GUI is just a wrapper to accomplish the same, I would advise to a) learn Perl (shouldn't take more than a week, assuming you know C/C++). You can accomplish the same thing in C/C++, but this is kinda thing Perl is ideal for, plus you get an incentive to learn a new language :) b) learn how to use makefile mechanish to drive ISE/Webpack to regen the bit file. Perl would parse your ASM file(s) into hex string(s) and put them where they belong in VHD source. Makefile would allow to automate .bit regeneration. There might be a way to do a surgery directly on .bit file, but I'd imagine it is safeguarded via some CRC mechanism that would make it rather hard, especially since you wouldnt save a whole lotta time ... unless you have to (re)PAR a 3M+ gate design on a 386 PC :) Gotta thank Xilinx for giving us BlockRAM. They tried to stay within HDL semantics as far as initialization goes ... but for large ROM-like designs, an easier way to init it would be a better alternative, even at expense of being proprietory. My $.02Article: 38002
Sounds like a posting from an Altera employee. Kevin Brace (don't respond to me directly, respond within the newsgroup)Article: 38003
who can post CRC-32 48bit(width) verilog source code?Article: 38004
Kenily <aiurh@iuehr.erug> writes: > who can post CRC-32 48bit(width) verilog source code? http://www.easics.com/webtools/crctool Petter -- ________________________________________________________________________ Petter Gustad 8'h2B | (~8'h2B) - Hamlet in Verilog http://gustad.comArticle: 38005
Mardin <chens_w@yahoo.com.cn> writes: > who can post it? http://www.easics.com/webtools/crctool Petter -- ________________________________________________________________________ Petter Gustad 8'h2B | (~8'h2B) - Hamlet in Verilog http://gustad.comArticle: 38006
rickman <spamgoeshere4@yahoo.com> wrote: > My problem surfaced when I reloaded simulations from scratch repeatedly > without restarting Modelsim. Because there was no way to position and > size the windows on startup and I found it irritating to have to save > the waveform setups just because I added a couple of signals, I would > just reload the simulation and keep using my current window setups. > After 5 or so reloads Modelsim would crap out under NT. It never crashed > the machine, so it could be restarted. But it took a couple of minutes > to get everything organized again so I could see what I was looking for. > This was reported to Mentor, so it may be fixed by now. It isn't fixed in (PE) 5.5d; possibly in 5.5e but I'd guess not. Hamish -- Hamish Moffatt VK3SB <hamish@debian.org> <hamish@cloud.net.au>Article: 38007
<hamish@cloud.net.au> wrote in message news:3c2f0ccb$0$32687$afc38c87@news.optusnet.com.au... > It isn't fixed in (PE) 5.5d; possibly in 5.5e but I'd guess not. No, not fixed yet! Probabely it will be fixed in PE 5.6............ PatrickArticle: 38008
> > the inconvenience, I'm told that the optimization that comes from the > > elimination of the netlist is a huge advantage that XST now has. > > I'm really not ready to buy the ``huge advantage ...''. Running edif2ngd to > create a .ngo file from a .edf takes hardly any time at all. Interestingly it seems that also ispDesignStarter (Lattice), which comes with Synplify, switched to encrypted netlists recently. I might be mistaken, but I was just able to locate a file which looks very similar to an edif file instead of the edf file that was generated in earlier version. It seems hiding the EDIF output became some kind of general fashion for "free" tools. Why do the vendors not want us to access the netlist ?Article: 38009
Tim Boescke wrote: > > > the inconvenience, I'm told that the optimization that comes from the > > > elimination of the netlist is a huge advantage that XST now has. > > > > I'm really not ready to buy the ``huge advantage ...''. Running edif2ngd > to > > create a .ngo file from a .edf takes hardly any time at all. > > Interestingly it seems that also ispDesignStarter (Lattice), which comes > with > Synplify, switched to encrypted netlists recently. I might be mistaken, > but I was just able to locate a file which looks very similar to an edif > file instead of the edf file that was generated in earlier version. > > It seems hiding the EDIF output became some kind of general fashion for > "free" tools. Why do the vendors not want us to access the netlist ? I'd suggest that its an outburst of paranoia that it might be possible to re-target e.g. CoreGen netlists to another technology. IIRC Leonardo Spectrum has some facility like this.Yet another round in the seemingly endless, depressing, fight against marketing's desperate desire to lock us all into proprietary standards. By all means let the Vendors use encrypted netlists or binary formats for their own IP but but I'll thank you to *leave my designs alone!* . There have been at least 3 occasions in the past where the only way I could work around a tool bug was to use the last backstop and Perl hack the netlists directly (one XNF & two EDIF).Article: 38010
Patrick Muller wrote: > <hamish@cloud.net.au> wrote in message > news:3c2f0ccb$0$32687$afc38c87@news.optusnet.com.au... > > It isn't fixed in (PE) 5.5d; possibly in 5.5e but I'd guess not. > > No, not fixed yet! Probabely it will be fixed in PE 5.6............ > > Patrick Oh dear! I've been extolling the virtues of ModelSim and now I find that upgrading from 5.4c to 5.5e is causing problems. Specifically almost all the sims run o.k. but in one case where I use a PLI based CPU bus model a restart+run causes ModelSim to go total SPLAAT. It could be a bug in the PLI code (its not mine) that was being hidden by 5.4c ... Anyone know how to debug a PC based PLI application ?Article: 38011
Damn, a stupid question, but I can't figure out how. I have a design in foundation 4.1 (schematics, yeah, call me geriatric but I THINK in schematics, as tedious as it is), targeting a Virtex E. How can I retarget the design to a Spartan II, as painlessly as possible. Can I just force a compile saying "Compile Spartan II", or is there a convert tool? I'm not using any virtex E specific features. -- Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 38012
Hi, I have a path with large combinational logic and long route but the result should only be used after 2 clock cycles which means there is sufficient time for the signals to pass through it. How can I force the TRACE program not to think this is the critical path? I am using Xilinx XCV1000E and with Synopsys DC/FPGA Express and Xilinx Alliance 3.1i. Any hints or pointers to documents are welcome. Thanks in advance! ---- BrittleArticle: 38013
I wrote: Oh dear! ... It looks like ModelSim is o.k. (except for the memory leak!) & the problem was the PLI stuff. It was relying on a couple of global variables being maintained across a restart. Since they were pointers all hell broke loose when the PLI app tried to free the memory they ``pointed at''.Article: 38014
rickman wrote: > ... > My problem surfaced when I reloaded simulations from scratch repeatedly > without restarting Modelsim. Because there was no way to position and > size the windows on startup... Well, I guess that is one advantage of using the Linux version then. The Gnome window manager in Linux makes this very easy.Article: 38015
As long as you aren't using any virtexE specific stuff, like the LVDS or too
many DLLs, you should be able to convert just by changing the target in the
xilinx tools. I am assuming the schematic was done with the xilinx unified
library.
Nicholas Weaver wrote:
> Damn, a stupid question, but I can't figure out how.
>
> I have a design in foundation 4.1 (schematics, yeah, call me geriatric
> but I THINK in schematics, as tedious as it is), targeting a Virtex
> E.
>
> How can I retarget the design to a Spartan II, as painlessly as
> possible. Can I just force a compile saying "Compile Spartan II", or
> is there a convert tool? I'm not using any virtex E specific
> features.
>
> --
> Nicholas C. Weaver nweaver@cs.berkeley.edu
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 38016khtsoi@cse.cuhk.edu.hk wrote: > I have a path with large combinational logic and long route but the result > should only be used after 2 clock cycles which means there is sufficient > time for the signals to pass through it. How can I force the TRACE program > not to think this is the critical path? I am using Xilinx XCV1000E and with > Synopsys DC/FPGA Express and Xilinx Alliance 3.1i. Any hints or pointers to > documents are welcome. Thanks in advance! You need a FROM:TO constraint in your UCF (user constraints file) to indicate that the maximum delay FROM the source flip flop to the TO flip-flop is twice the normal clock period. See the constraints guide (in 4.1i) or libraries guide(?) (in 3.x) for details. Hamish -- Hamish Moffatt VK3SB <hamish@debian.org> <hamish@cloud.net.au>Article: 38017
Isn't it better to target recently released Spartan-IIE (0.18u part) rather than older Spartan-II (0.22u part) unless there are special reasons on doing so? Other than connecting 5V I/O stuff like 5V PCI, I think there are very little reasons using Spartan-II instead of Spartan-IIE. I heard somewhere that compared to Virtex-E, Spartan-IIE has half of BlockRAM and DLL (4 instead of 8). That is somewhat different from what Xilinx did when they released Spartan-II (kept the same amount of BlockRAM and DLL that Virtex had). Kevin Brace (don't respond to me directly, respond within the newsgroup) Nicholas Weaver wrote: > > Damn, a stupid question, but I can't figure out how. > > I have a design in foundation 4.1 (schematics, yeah, call me geriatric > but I THINK in schematics, as tedious as it is), targeting a Virtex > E. > > How can I retarget the design to a Spartan II, as painlessly as > possible. Can I just force a compile saying "Compile Spartan II", or > is there a convert tool? I'm not using any virtex E specific > features. > > -- > Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 38018
I am not sure what you are asking, but don't all microprocessors process some kind of instruction codes? Perhaps, readers of news:comp.arch might be able to do a better job answering your question (news:comp.arch.fpga is for pretty much for the users of FPGAs). Kevin Brace (don't respond to me directly, respond within the newsgroup) "M. Sachemo" wrote: > > can some body help me understand what an instruction processor is? > thanks for your reply > newbieArticle: 38019
Thanks! But there is not 48bit(width)Article: 38020
Thanks! ---- BrittleArticle: 38021
To change target in Foundation 4.1 between (more or less) compatible chip types: At the "Project Manager" window (the one with the little boxes on it for design entry etc.), select the "File" pull down menu, and choose "Project Type". Or you can just type ^T, but I can never remember that. A box labeled "Change Project Type" will come up, and you can use the bottom left pull down menu to select between the various architectures. Of course this will only work if you included the architecture you want in your install. That's why I always install them all. I've noticed that some of the schematics tend to be a bit messed up when you do this. In particular, the "IPAD" component tends to be different sizes between certain Xilinx families. Changing the project type can cause them to become disattached. To fix this, you have to go through all the schematic pages and move the IPADs back or forth one 'tic' or whatever the unit of measurement in schematics is. I'd report this little fact as a bug, but it isn't much of a show stopper. Carl -- Posted via Mailgate.ORG Server - http://www.Mailgate.ORGArticle: 38022
Freny, the only time I've experienced something like what you're talking about is when I've screwed up the Project Manager image. So here's the way of doing that: (1) Make PM too small. Then the flowchart gets hidden and you can't click it. (2) Move the bar that separates the "Files / Versions" side from the "Flow / Contents / Reports / Synthesis" side too far to the right. Then there's not enough room to show the "Simulation" and "Verification" buttons. (3) Move the vertical bar that separates the top half of the screen from the bottom half too far up. (4) Choose "Contents", "Reports", or "Synthesis" instead of "Flow" over where the flowchart is usually shown. Other than that, the tool has worked great for me for years. For the sake of your self esteem, I hope that your problem is more complicated, and requires repair by reinstalling Foundation. Carl -- Posted via Mailgate.ORG Server - http://www.Mailgate.ORGArticle: 38023
Sure there is, but it is not obvious. check the 32 AND the 16 bit
boxes. That gives you the 48 bit variant.
Kenily wrote:
> Thanks!
> But there is not 48bit(width)
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 38024Hi I am using synplicity for synthesizing my code and targetting the edif to xilinx par. In par i am giving area constraint to for hierarchical design. INST "U1/U2/U3" AREA_GROUP=g0; AREA_GROUP g0 ..... I have found that some of my hierarchical block nets are not synthesized with name U1/U2/U3 etc. Instead they are named as G_900.. Bcas of this par tool is not able to place them in specified area. These nets are some combo logic which has been synthesized and given some interim name by synplicity. Is there any way i can tell synplicity tool to prepand all of them with hierarchy name??
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