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"Paul" wrote > In the end I'm hoping that I can utilise ActiveHDL to significantly reduce > my simulation bottleneck. The evaluation version is worth installing just to get the VHDL and Verilog help (.CHM) files.Article: 39526
Hello I'm new to implementation with FPGA's. I want to implement two RAM's with (256 Byte depth 1 Byte width)*8 places I want to save the coordinates of objekts from a video image. I want to switch between these two RAM's for writing (the coordinates) ,respectively reading (processing for edge detection). I have a Spartan II Board with a XC2S50. this device has 8 Blocks of 4096 Bit Dual Port Ram. I wanted to use these Blocks for my design, but I have problems, connecting them to my bigger Ram. I think I need 4 Block's for each RAM. Do I also need 4 multiplexers to connect the 4 Block Ram outputs. to one output ? Or what can I do to have access to one big RAM. For any help and tips I'm very grateful. Jens NiemannArticle: 39527
Hi - On Tue, 12 Feb 2002 13:24:06 -0500, "Theron Hicks" <hicksthe@egr.msu.edu> wrote: >Perhaps that is the case. While the data sheet does not say that, the >timing diagrams in the data sheet show a continuous clock. I will give it a >try. > >I had hoped to clock the write when I needed to store a value and then clock >the read when I needed to read a value. Basicly, the 32 data values are >being generated over about a 5 microsecond period but the data must be >transmitted over a 10 microsecond period to allow for an acceptable data >rate. Thus for the first 5 microseconds data is being both generated and >transmitted. During the second 5 microseconds the transmit function is just >catching up to the generated values. Is this reasonable? The overall goal sounds reasonable. But the function will be a lot easier to implement if you replace read and write pulses with continuous clocks, and use synchronous enables to qualify data writes and reads. The problems with using clock pulses or gated clocks have been pretty much beaten to death in this newsgroup, so I won't belabor the point. Bob Perlman -- Cambrian Design Works digital design, signal integrity http://www.cambriandesign.com e-mail: respond to bob at the domain above.Article: 39528
"Jens Niemann" <jensniemann@gmx.de> schrieb im Newsbeitrag news:a4btlp$q8h$1@newsserver.rrzn.uni-hannover.de... > Hello I'm new to implementation with FPGA's. > I want to implement two RAM's with (256 Byte depth 1 Byte width)*8 places > I want to save the coordinates of objekts from a video image. > I want to switch between these two RAM's for writing (the coordinates) > ,respectively reading (processing for edge detection). > > I have a Spartan II Board with a XC2S50. > this device has 8 Blocks of 4096 Bit Dual Port Ram. Right. > I wanted to use these Blocks for my design, but I have problems, connecting > them to my bigger Ram. > I think I need 4 Block's for each RAM. Yes. > Do I also need 4 multiplexers to connect the 4 Block Ram outputs. to one > output ? Yes. > Or what can I do to have access to one big RAM. Use Coregen to create such a big RAM, it creates the MUX and other control stuff for you. But Coregen is commercial, not available with WEBPACK. But creating the MUX by hand is not very complicated. -- MfG FalkArticle: 39529
Requirement: two sets of 8 memories, 265x8bits. The eight 4096 bit rams can be configured as two sets of four RAMs configured as 2048x2 bits allowing the memory bank select (3 bits) and the address (8 bits) to give the 2084 addresses in this configuration. No muxing required. The RAMB4_S2 primitive should get you what you need. Instantiate 4 (nearly) identical 2-bit RAMs to get your 8-bit values. See the library guide for the particulars ( http://toolbox.xilinx.com/docsan/xilinx4/data/docs/lib/chap09/lib09035.htm ) - John_H Jens Niemann wrote: > Hello I'm new to implementation with FPGA's. > I want to implement two RAM's with (256 Byte depth 1 Byte width)*8 places > I want to save the coordinates of objekts from a video image. > I want to switch between these two RAM's for writing (the coordinates) > ,respectively reading (processing for edge detection). > > I have a Spartan II Board with a XC2S50. > this device has 8 Blocks of 4096 Bit Dual Port Ram. > I wanted to use these Blocks for my design, but I have problems, connecting > them to my bigger Ram. > I think I need 4 Block's for each RAM. > Do I also need 4 multiplexers to connect the 4 Block Ram outputs. to one > output ? > Or what can I do to have access to one big RAM. > > For any help and tips I'm very grateful. > > Jens NiemannArticle: 39530
ls_user <ls@swissonline.ch> wrote in message news:<ee74c6d.9@WebX.sUN8CHnE>... > Austin: Konkurrenz belebt das Geschaeft. > > Please ask Peter for translation. > > regards > > The Amateur Austin, pls don't work get too frustrated in you efforts to come out with CDR and a workable embedded processor solution in the next decade. Both companies have been innovative and have a range of firsts. Basically being first just gives a time to market advantage which is followed by the other company following. Sad to see Xilinx ppl(engineers??) stoop to altera bashing.Article: 39531
Use the memory address to do the muxing for you. It sounds like you need a
total of 16 256 byte pages which you will select for read/write. Use the 8 RAMs
in dual port 4Kx1 configuration, with each one storing one bit. All share a
common (or duplicated) address for reads and for writes. You can use one port
for writing and one for reading, then all the muxing is accounted for by
selecting the upper bits of the address.
Falk Brunner wrote:
> "Jens Niemann" <jensniemann@gmx.de> schrieb im Newsbeitrag
> news:a4btlp$q8h$1@newsserver.rrzn.uni-hannover.de...
> > Hello I'm new to implementation with FPGA's.
> > I want to implement two RAM's with (256 Byte depth 1 Byte width)*8 places
> > I want to save the coordinates of objekts from a video image.
> > I want to switch between these two RAM's for writing (the coordinates)
> > ,respectively reading (processing for edge detection).
> >
> > I have a Spartan II Board with a XC2S50.
> > this device has 8 Blocks of 4096 Bit Dual Port Ram.
>
> Right.
>
> > I wanted to use these Blocks for my design, but I have problems,
> connecting
> > them to my bigger Ram.
> > I think I need 4 Block's for each RAM.
>
> Yes.
>
> > Do I also need 4 multiplexers to connect the 4 Block Ram outputs. to one
> > output ?
>
> Yes.
>
> > Or what can I do to have access to one big RAM.
>
> Use Coregen to create such a big RAM, it creates the MUX and other control
> stuff for you. But Coregen is commercial, not available with WEBPACK.
> But creating the MUX by hand is not very complicated.
>
> --
> MfG
> Falk
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 39532
There is a tool in the 4.1 tools called xpower that will take the VCD
file from your simulation and the NCD from the place and route to
provide a more accurate power computation based on your simulation.
Tamar Poker wrote:
> Hi.
> I am looking for an excell sheet to do power estimation for virtex2
> device.
> Unfortunately the excell sheet I found on the web is only for Virtex
> ane Virtex-E (xapp152).
>
> Is there something similiar for Virtex2 ?
>
> Tamar.
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 39533Ray Andraka <ray@andraka.com> wrote in message news:<3C69215D.E69A4215@andraka.com>... > Be careful with the SRL16 timing. There is a minimum pulse width on the > WE pin that is not reported by the timing anaylzer. In VirtexE-7, for > example the minimum pulse width for the SRL16 write limits the clock to > about 235 MHz even though the routing would allow it to go considerably > faster. Eeew, ugly. Well I guess I can use two interleaved LFSR and still come out ahead of an FF only implementation. > Also, as Tim says, always follow the SRL16 with the associated > flip-flop. The clock to Q of the SRL16 is really slow compared to that > of the flip-flop. Buffering the output with a flip-flop avoids putting > that long clock to Q in series with the prop delay thorugh a LUT and the > routing. I checked the floorplan and the SRL16 are mapped with an FF at their end. However the taps were placed in strategically dubious positions so that a lot of routing was going on to keep the number of SRL16 minimal. Spacing the taps by 17 fixed that particular problem. I have no idea if that is going to be a good LFSR, this is just to see how the mapping works. Result: post PAR the timing analyzer now claims a clock rate of 320MHz for a -6 Spartan-II ... > For the VHDL, include the ieee.numeric_std library. WIth that you can > use the signed and unsigned types instead of integers. These are bit > vectors closely related to std_logic_vector but since the format is > defined you can do math on them. Thanks, that seemed to do the trick. I'm still at loss assigning literals, the compiler wants to get bitstrings or arithmetic expressions with some unsigned signal. BTW, what is IEEE.std_logic_unsigned for? I could not get that to work so far. Aside#2: I plan on getting a CoolRunner-II and Spartan-II(E) dev kit from Insight. Any caveats or opinions on these (preferrably from someone who has used them)? Any other dev kit (must be available _now_ and have a distributor in Germany) that I should have a look at? PCI cards are no-go, I'm strictly notebook based at the moment. Achim Gratz.Article: 39534
I disagree. I have some 3200e designs with which I am having real problems with using the lowskew lines & constraints, and have seen flakey results from ILA cores on the lowskew lines for the core. Be careful is all I can say. Your results will vary run to run with no new input files. Furthermore, near as I can tell, the tools really can't analyze hold/race very well, so you can't add a constraint which will tell you whether or not it will work. They do a great job of estimating max delays, which are crucial to making PERIOD constraints, however they do a poor job of modeling min delays, which are more germain to the hold/race problem. It doesn't help that with Xilinx parts, the parts are much faster than the published numbers, especially at nominal temp & voltage. I have a situation currently where I have known skew problems using secondary lines, but can't get the tool to provide adequate analysis of it. The timing numbers are enough off that I can't even accomplish a hand analysis, even knowing down to about eight FF to FF transfers where the problem lies, so it is no wonder the P&R tool can't work it. That aside, I have had them ILA cores work using the lowskew lines, and I have had them flat not work using the lowskew lines, and I have had them kind of work using lowskew lines (sometimes trigger, sometimes return junk data, etc). My take, however, is that your analysis systems must be pretty trustworthy or it is pretty hard to make progress. Nothing worse than questioning the reliability of the data you are looking at while trying to diagnose problems... "Sanket Bandyopadhyay" <sanket@insight.memec.co.in> wrote in message news:ee73ac3.1@WebX.sUN8CHnE... > HI, > ILA cores are robust enough and won't pose a timing problem if local resources are used.Moreover if at all you think ILA is causing such a problem---go to Constraints Editor---use LOWSKEWLINES control for the clock net. > regds. > Sanket. > Xilinx FAE from Insight.Article: 39535
> > JTAG. M0-M2 are programmed for internal pullups and not grounded with > > jumpers. I'm using parallel port cable with 2 74HC125 chips, I made it > > using Xilinx drawing. > > Readback doesn't seem to work with iMPACT and a parallel JTAG cable. Read > answer record 8097 for the list of supported devices and operations. Answer record 8097: Parallel Cable III (JTAG Cable) 3. iMPACT v4.1i (or later) software: - Supports JTAG configuration of XC18V00, XC4000E/EX/XL/XLA/XV, XC9500/XL/XV, Spartan/XL/II, and Virtex/E/II. - Supports slave serial configuration of Spartan/XL/II, XC4000E/EX/XL/XLA/XV, and Virtex/E/II. Nothing about readback :(Article: 39536
"Kunde passen auf." Oder wie sie sagen in Rom: Caveat Emptor. Austin (Ich kann Deutschen lesen, Danke) (But excuse my written German, as I am not up to the colloquialisms or the venarcular) ls_user wrote: > Austin: Konkurrenz belebt das Geschaeft. > > Please ask Peter for translation. > > regards > > The AmateurArticle: 39537
Whose bashing? Whose frustrated? I am having a little fun, but I am too busy now, so you too, have some fun. Austin "arpit.desai" wrote: > ls_user <ls@swissonline.ch> wrote in message news:<ee74c6d.9@WebX.sUN8CHnE>... > > Austin: Konkurrenz belebt das Geschaeft. > > > > Please ask Peter for translation. > > > > regards > > > > The Amateur > > Austin, pls don't work get too frustrated in you efforts to come out > with CDR and a workable embedded processor solution in the next > decade. > > Both companies have been innovative and have a range of firsts. > Basically being first just gives a time to market advantage which is > followed by the other company following. Sad to see Xilinx > ppl(engineers??) stoop to altera bashing.Article: 39538
Is/was anyone Altera bashing? (in this thread, at least) I'm happy to see both sides of the (multi-sided) coin represented in the newsgroup and appreciate the visits by the folks close to the silicon and the tools (even Synplicity's CTO, Ken McElvain visits on occasion). "arpit.desai" wrote: > ls_user <ls@swissonline.ch> wrote in message news:<ee74c6d.9@WebX.sUN8CHnE>... > > Austin: Konkurrenz belebt das Geschaeft. > > > > Please ask Peter for translation. > > > > regards > > > > The Amateur > > Austin, pls don't work get too frustrated in you efforts to come out > with CDR and a workable embedded processor solution in the next > decade. > > Both companies have been innovative and have a range of firsts. > Basically being first just gives a time to market advantage which is > followed by the other company following. Sad to see Xilinx > ppl(engineers??) stoop to altera bashing.Article: 39539
That's because the Parallel III cable isn't capable of readback. You need an
Xchecker cable (which are getting about as rare as hen's teeth these days) or a
multilinx programmer to do readback.
Aare Tali wrote:
> > > JTAG. M0-M2 are programmed for internal pullups and not grounded with
> > > jumpers. I'm using parallel port cable with 2 74HC125 chips, I made it
> > > using Xilinx drawing.
> >
> > Readback doesn't seem to work with iMPACT and a parallel JTAG cable. Read
> > answer record 8097 for the list of supported devices and operations.
>
> Answer record 8097:
>
> Parallel Cable III (JTAG Cable)
>
> 3. iMPACT v4.1i (or later) software:
> - Supports JTAG configuration of XC18V00, XC4000E/EX/XL/XLA/XV,
> XC9500/XL/XV, Spartan/XL/II, and Virtex/E/II.
> - Supports slave serial configuration of Spartan/XL/II,
> XC4000E/EX/XL/XLA/XV, and Virtex/E/II.
>
> Nothing about readback :(
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 39540"Ray Andraka" <ray@andraka.com> wrote in message news:3C69ACAC.923863B5@andraka.com... > That's because the Parallel III cable isn't capable of readback. You need an > Xchecker cable (which are getting about as rare as hen's teeth these days) or a > multilinx programmer to do readback. Actually I did find something interesting. In Answer # 13461 they state that only some Spartan-IIs won't verify, those with AFP in the manufacturing code. I can personally atest to the fact that a XC2S100 TFQP144AFP0121 won't.Article: 39541
Achim Gratz wrote:
> Ray Andraka <ray@andraka.com> wrote in message news:<3C69215D.E69A4215@andraka.com>...
> > Be careful with the SRL16 timing. There is a minimum pulse width on the
> > WE pin that is not reported by the timing anaylzer. In VirtexE-7, for
> > example the minimum pulse width for the SRL16 write limits the clock to
> > about 235 MHz even though the routing would allow it to go considerably
> > faster.
>
> Eeew, ugly. Well I guess I can use two interleaved LFSR and still come
> out ahead of an FF only implementation.
Yep.
>
>
> > Also, as Tim says, always follow the SRL16 with the associated
> > flip-flop. The clock to Q of the SRL16 is really slow compared to that
> > of the flip-flop. Buffering the output with a flip-flop avoids putting
> > that long clock to Q in series with the prop delay thorugh a LUT and the
> > routing.
>
> I checked the floorplan and the SRL16 are mapped with an FF at their
> end. However the taps were placed in strategically dubious positions
> so that a lot of routing was going on to keep the number of SRL16
> minimal. Spacing the taps by 17 fixed that particular problem. I have
> no idea if that is going to be a good LFSR, this is just to see how
> the mapping works. Result: post PAR the timing analyzer now claims a
> clock rate of 320MHz for a -6 Spartan-II ...
Like I said, that is the speed of the routing. From page 16 of the Spartan-II 2.5v FPGA
Family:DC and Switching Characteristics (http://www.xilinx.com/partinfo/ds001_3.pdf) the
minimum pulse width, high (Tsrph) and Low(Tsrpl) are both 2.9ns for the -6 SpartanII.
That means the max clock frequency for the SRL16 is about 172 MHz. This is one of those
things not reported by the timing analyzer.
Generally speaking you don't want to just pull convenient taps, especially evenly spaced
ones as most combinations will result in truncated LFSR sequences. Refer to xilinx app
note xapp052 for a table of taps for maximal lenght sequences. You can set the lengths of
the SRL16s by setting the address to get taps out at places you need them without going to
extremes. I think all the polynomials listed in the xilinx note use either 2 or 4
feedback taps. In most cases, you can pick the length for a convenient tap arrangement --
for example chose the next longer one if it means 2 taps instead of 4.
Xilinx: Perhaps a good thing to do would be to add a note in the timing reports when the
period constraint on a clock that clocks an SRL16 is less than the minimum period dictated
by the min pulse widths. Same for the minimum and maximum clocks for the clkdlls.
Several people I am aware of have missed these limitations in recent designs.
>
>
> > For the VHDL, include the ieee.numeric_std library. WIth that you can
> > use the signed and unsigned types instead of integers. These are bit
> > vectors closely related to std_logic_vector but since the format is
> > defined you can do math on them.
>
> Thanks, that seemed to do the trick. I'm still at loss assigning
> literals, the compiler wants to get bitstrings or arithmetic
> expressions with some unsigned signal. BTW, what is
> IEEE.std_logic_unsigned for? I could not get that to work so far.
Std_logic_unsigned and std_logic_signed were synopsis libraries. They generally cannot
coexist in the same entity because they have conflicting declarations. Despite the name,
they are also not standard among different vendors. For the assignments, you can use
casts for related types. Std_logic_vector, unsigned, and signed are related types so;
Numeric_std is an IEEE standard library. Us it instead of wrestling with all the problems
of std_logic_unsigned, std_logic_arith and std_logic_signed.
slv_signal<= std_logic_vector(unsigned_signal);
unsigned_signal<= unsigned(slv_signal);
Does that answer your question?
>
>
> Aside#2: I plan on getting a CoolRunner-II and Spartan-II(E) dev kit
> from Insight. Any caveats or opinions on these (preferrably from
> someone who has used them)? Any other dev kit (must be available _now_
> and have a distributor in Germany) that I should have a look at? PCI
> cards are no-go, I'm strictly notebook based at the moment.
>
> Achim Gratz.
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 39542Wow, thats a messy clock scheme. I think you're either going to have to find a way to get the high frequency output of the uP PLL onto your PCB or find a way to bypass the PLL altogether on your uP and feed in an external clock. The clocking scheme you have described does not seem to be realizable by conventional digital techniques. Richard Meester <rme@quest-innovations.com> wrote in message news:<3C69673E.14128675@quest-innovations.com>... > Hi Jay, > > Jay wrote: > > > If all your clocks are derived from the same reference and phase > > locked then your do not need to worry about metastability other than > > the conventional set-up and hold requirements required of your > > receiving flip flops common to all standard synchronous designs. Be > > aware that the static timing checks done by typical FPGA tools do not > > handle multi-clock relationships very well, but a timing back > > annotated gate level sim should give you meaningful checks. > > > > To say it another way, you do not need to do the cascaded flip flip > > thing that you would do when you have signals coming in from an > > ASYNCHRONOUS clock domain. > > > > The FPGA is not driven by the same clock that drives the CPU, the CPU has an external 10 Mhz and an internal PLL, the FPGA > has an external 100Mhz clock, or a 10Mhz clock and uses the spartanII dll's. Having said this it seems that the signals doe > come from an asynchronous clock domain right? > > Since my design is pipelined can i see this pipeline as the cascaded flip flop thing if i check the signals at the end of > my pipe? > > Thanks. > > Richard > > > > > Regards > > > > Richard Meester <rme@quest-innovations.com> wrote in message news:<3C68C144.A80A47AE@quest-innovations.com>... > > > Hi Jay, > > > > > > Yes, we have an external CPU and external memory. We develop the FPGA to be a DMA controller and some more activity. > > > We have internal registers inside the FPGA which need to be addressed as a memory device. After this the FPGA can > > > become bus master. > > > > > > What i have done now is that i clock the FPGA at 100Mhz, scan the lines and check for the appropriate signals and go > > > from there. I have 4 clock cycles at 100Mhz at the moment, but in future will advance to 2 clock cycles to respond. > > > Once the FPGA becomes a bus-master i add a pipeline stage which will allow 1 clock cycle addresses and delayed data > > > lines when it comes to a read. Also bus turnaround will have a 4 cycle latency. I will transfer chunks of 16/32 words > > > so the benefit of the pipeline is definately there. Now my problem is do i need to synchronize and concern about > > > metastability on the incomming lines when the FPGA is a memory device for the external processor? > > > > > > Thanks, > > > > > > Richard > > > > > > Jay wrote: > > > > > > > I think I misunderstood your configuration. Do you have a uP chip > > > > that you've purchased talking to your FPGA as a memory device? > > > > > > > > Richard Meester <rme@quest-innovations.com> wrote in message news:<3C64E594.9060200@quest-innovations.com>... > > > > > Hi Jay, > > > > > Thanks for the response, > > > > > > > > > > Jay wrote: > > > > > > > > > > > I'm going to make some assumptions because I'm not sure if I > > > > > > understand your description, correct me if I'm wrong. > > > > > > > > > > > > Like you suggested, go ahead and run your internal processor at twice > > > > > > the external interface. Enable the data capture and data launch flops > > > > > > on every other clock. Clock every flip/flop in your design on the > > > > > > higher 2X clock. > > > > > > > > > > > > > > > What do you meen by every other clock, clock the lines, and than wait > > > > > one clock, and then clock again for the next complete cycle? > > > > > > > > > > Don't i have a metastability problem with the asynchronous read/write/cs > > > > > lines > > > > > > > > > > the problem is that the signal below is i.e. the r/w signal. it is > > > > > asynchronous. if i sample this at twice the frequency i will at > > > > > somepoint get the correct valie that i need to trigger on. > > > > > > > > > > ---\________/------ > > > > > > > > > > ^ ^ samples at one of these points at 100 Mhz. > > > > > ^ DATA must be stable at this point > > > > > > > > > > However i need to have the data stable before the rising edge of this > > > > > signal, which is one clock cycle wide @ 100 Mhz. so i have one clock > > > > > cycle to put the data on the bus. > > > > > I see how to design this, but i am worried about metastability on the > > > > > asynchronous lines. If i need to take care of this i need to add 2 flops > > > > > behind it, and after that start making the data available. Overall this > > > > > will take me at least 3 clock cycles. > > > > > > > > > > > > > > > Richard > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > Don't try to have a 66MHz mem interface and 100MHz internal clock. > > > > > > Maintain that 2/1 ratio. Run the memory at 50 and the processor at > > > > > > 100 or run the memory at 66, and run the processor at 133MHz. Your > > > > > > life will be much easier. > > > > > > > > > > > > Hope this help, > > > > > > Regards > > > > > > Richard Meester <rme@quest-innovations.com> wrote in message news:<3C63F9C2.6CBF3BE7@quest-innovations.com>... > > > > > > > > > > > >>Hi All, > > > > > >> > > > > > >>I have some problems finding a good design practice for a bus-interface. > > > > > >> > > > > > >>We have a processor running internally at 100Mhz, and externally at > > > > > >>50Mhz (2 internal bus cycles used for 1 complete external bus cycle). > > > > > >>Now the addresses are set, the cs lines are set, the re_n and we_n > > > > > >>signals are set and the data is set or read. I know all the timing > > > > > >>variables on these lines. > > > > > >> > > > > > >>Now i need to design a bus interface, but i want the internal clock to > > > > > >>run at least at 66 Mhz because i need to access ram at this speed and > > > > > >>want to keep the internal clock speeds at the same speed. > > > > > >> > > > > > >>Now how can i best trigger my internal signals, the we_n line goes > > > > > >>active low after 8 nsecs of valid data, should i use this signal and > > > > > >>feed it into a fflop to trigger on, or should i let the flop trigger at > > > > > >>the internal clock speed and detect that the line has changed state and > > > > > >>take action from there, or should i make the desing completely > > > > > >>combinatorial? > > > > > >> > > > > > >>Thanks in advance, > > > > > >> > > > > > >>Richard > > > > > >>Article: 39543
Without a second processor doing other tasks is extremely sluggish, and running a short
sim or synthesis run while a place and route is in progress (for example) is out of the
question. The second processor doesn't speed up any of the EDA tools that I am aware of.
The difference is that I can do reasonable work (not just text edits) while I've got
something else running. To make it at all useful, you've got to load the machine up with
memory so that it isn't paging a lot, and you should have some good fast storage. I have
a dual PIII-800e and a single PIII833 here. I'll take the dual any day over the single
because I'm not left sitting on my hands while a sim runs.
Jay wrote:
> To play the devil's avocado a little bit here... Regarding the dual
> processor thing. I wish it weren't true, but all the EDA software
> I've used on the PC is single threaded. So on a long P&R, while one
> processor is near 100% and the other sits idle. So you want to edit
> your word document or browse the web whilest you wait. The .0001% of
> the total CPU cyles you take for these types of low MIP activities has
> such a small impact I'm not sure its always worth getting the extra
> processor. So your P&R takes 11 hours and 2 minutes instead of taking
> just 11 hours.
>
> We had a dual P3 1GHz and were concerned that since the OS was
> shifting the P&R task back and forth between the 2 CPU's, it was
> constantly having to refill the caches. We pulled the second CPU and
> have not put it back or noticed a difference by our completely
> unscientific measures. Also in these days of GHz processors and MHz
> memory, the CPU's are often memory bound, so putting another processor
> on that same memory bus isn't going to give you twice as much juice.
>
> I'd love to see some benchmarks for a P&R on the same machine with 1
> and 2 processors populated.
>
> Regards
>
> Ray Andraka <ray@andraka.com> wrote in message news:<3C693054.2EBAF61D@andraka.com>...
> > We also use dual processor machines in order to stay productive during a long
> > sim or PAR, and I've also found it economical to replace the system when I can
> > double the processor performance. That has been working out to every 18 months
> > or so, and I've been spending about $8K US per box each time.
> >
> > Regarding the Aldec, buy it. You'll be very glad you did. It is not only a
> > world class simulator (only Modelsim compares), but it also has an excellent
> > design entry suite along with version control and various productivity tools. I
> > personally don't know how I did without it.
> >
> > Paul wrote:
> >
> > > > This time I've gone for the xeons A) to avoid P4 (crapomatic) and B)
> > > > the cost of RAID has gone up. I'd have gone Dual MP1900+ if I could
> > > > have found one. Quantity of RAM is easy to gauge once to get going,
> > > > just make sure you choose a PC that can take shedloads if it proves
> > > > necessary.
> > >
> > > Thanks for the advice Julian which I agree with 100%
> > >
> > > In fact last week the order went out to www.overclockers.co.uk for my nice
> > > dual Athlon 1900+ with 1GB RAM. No SCSI though as I'm happy with IDE these
> > > days.
> > >
> > > I agree about not changing development tools, but the Aldec ActiveHDL sure
> > > does look nice compared with Altera's offering... Luckily budget constraints
> > > stop me buying it anyway.
> > >
> > > Paul
> >
> > --
> > --Ray Andraka, P.E.
> > President, the Andraka Consulting Group, Inc.
> > 401/884-7930 Fax 401/884-7950
> > email ray@andraka.com
> > http://www.andraka.com
> >
> > "They that give up essential liberty to obtain a little
> > temporary safety deserve neither liberty nor safety."
> > -Benjamin Franklin, 1759
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 39544
Ray wrote:
> That's because the Parallel III cable isn't capable of readback. You need an
> Xchecker cable (which are getting about as rare as hen's teeth these days) or
> multilinx programmer to do readback.
Alas, 4.x iMPACT software support for the venerable Xchecker cable has
gone the way of the HMAP. ( and the floorplanner carry chain RPM :) )
From Answer Record 8097:
"3. iMPACT software does not support the XChecker cable."
I discovered this shortly after finding an interesting 'feature' of
iMPACT 4.x wherein slave serial download via the parallel cable leaves
CCLK parked low before and after configuration. ( Which, for certain
4000 series family members, is a serious violation of download protocol.)
Brian
Article: 39545Ray Andraka wrote: > That's because the Parallel III cable isn't capable of readback. You need an > Xchecker cable (which are getting about as rare as hen's teeth these days) or a > multilinx programmer to do readback. > > While its true Xilinx have never supported readback of FPGA config data through the JTAG/Parallel-III under JTAGProgrammer and now IMPACT there doesn't seem to be anything in principle to stop it. In fact there are a couple of apps notes (XAPP138/139) that seem to have enough info to allow such a tool to be constructed as long as you've got independent access to the PC's parallel port. As far as I can tell Xilinx have never done this because they have provided the HWDebugger+MultiLinx route.Article: 39546
I have a nice Rijndael encoder implementation for the Spartan II/Virtex FPGAs (over 1 Gbps, 115 MHz, <800 clb slices, fully key agile, Spartan II-100-5 (according to static timing analysis)). Once I get the last minor interfacing bug squished, I'll release it under the LGPL. The question is, is there a more convenient way than it's current form (a Foundation/aldec schematic design, consisting of about 5-6 schematic specified RLOCed blocks which are placed with RLOC_ORIGINs) to release it instead of just the schematics? EG, a nice way to turn the schematic pieces into a more portable modules? Some RLOCing is needed to specify the design to a specific chip (to balance delays between blockrams and to place the subkey generation in the appropriate place, and to tile to larger bandwidth). -- Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 39547
Hi Jay, Why is it not possible, to me these look like two asynchronous systems? We have another option. The PLL puts out div2 or div4 or div8 clock i.e. 50Mhz clock, we could feed this clock into a spartanII dll which puts out a times2/4/8 clock to get it to 100Mhz. Do you think this will work? Thanks, Richard Jay wrote: > Wow, thats a messy clock scheme. I think you're either going to have > to find a way to get the high frequency output of the uP PLL onto your > PCB or find a way to bypass the PLL altogether on your uP and feed in > an external clock. The clocking scheme you have described does not > seem to be realizable by conventional digital techniques. > > Richard Meester <rme@quest-innovations.com> wrote in message news:<3C69673E.14128675@quest-innovations.com>... > > Hi Jay, > > > > Jay wrote: > > > > > If all your clocks are derived from the same reference and phase > > > locked then your do not need to worry about metastability other than > > > the conventional set-up and hold requirements required of your > > > receiving flip flops common to all standard synchronous designs. Be > > > aware that the static timing checks done by typical FPGA tools do not > > > handle multi-clock relationships very well, but a timing back > > > annotated gate level sim should give you meaningful checks. > > > > > > To say it another way, you do not need to do the cascaded flip flip > > > thing that you would do when you have signals coming in from an > > > ASYNCHRONOUS clock domain. > > > > > > > The FPGA is not driven by the same clock that drives the CPU, the CPU has an external 10 Mhz and an internal PLL, the FPGA > > has an external 100Mhz clock, or a 10Mhz clock and uses the spartanII dll's. Having said this it seems that the signals doe > > come from an asynchronous clock domain right? > > > > Since my design is pipelined can i see this pipeline as the cascaded flip flop thing if i check the signals at the end of > > my pipe? > > > > Thanks. > > > > Richard > > > > > > > > Regards > > > > > > Richard Meester <rme@quest-innovations.com> wrote in message news:<3C68C144.A80A47AE@quest-innovations.com>... > > > > Hi Jay, > > > > > > > > Yes, we have an external CPU and external memory. We develop the FPGA to be a DMA controller and some more activity. > > > > We have internal registers inside the FPGA which need to be addressed as a memory device. After this the FPGA can > > > > become bus master. > > > > > > > > What i have done now is that i clock the FPGA at 100Mhz, scan the lines and check for the appropriate signals and go > > > > from there. I have 4 clock cycles at 100Mhz at the moment, but in future will advance to 2 clock cycles to respond. > > > > Once the FPGA becomes a bus-master i add a pipeline stage which will allow 1 clock cycle addresses and delayed data > > > > lines when it comes to a read. Also bus turnaround will have a 4 cycle latency. I will transfer chunks of 16/32 words > > > > so the benefit of the pipeline is definately there. Now my problem is do i need to synchronize and concern about > > > > metastability on the incomming lines when the FPGA is a memory device for the external processor? > > > > > > > > Thanks, > > > > > > > > Richard > > > > > > > > Jay wrote: > > > > > > > > > I think I misunderstood your configuration. Do you have a uP chip > > > > > that you've purchased talking to your FPGA as a memory device? > > > > > > > > > > Richard Meester <rme@quest-innovations.com> wrote in message news:<3C64E594.9060200@quest-innovations.com>... > > > > > > Hi Jay, > > > > > > Thanks for the response, > > > > > > > > > > > > Jay wrote: > > > > > > > > > > > > > I'm going to make some assumptions because I'm not sure if I > > > > > > > understand your description, correct me if I'm wrong. > > > > > > > > > > > > > > Like you suggested, go ahead and run your internal processor at twice > > > > > > > the external interface. Enable the data capture and data launch flops > > > > > > > on every other clock. Clock every flip/flop in your design on the > > > > > > > higher 2X clock. > > > > > > > > > > > > > > > > > > What do you meen by every other clock, clock the lines, and than wait > > > > > > one clock, and then clock again for the next complete cycle? > > > > > > > > > > > > Don't i have a metastability problem with the asynchronous read/write/cs > > > > > > lines > > > > > > > > > > > > the problem is that the signal below is i.e. the r/w signal. it is > > > > > > asynchronous. if i sample this at twice the frequency i will at > > > > > > somepoint get the correct valie that i need to trigger on. > > > > > > > > > > > > ---\________/------ > > > > > > > > > > > > ^ ^ samples at one of these points at 100 Mhz. > > > > > > ^ DATA must be stable at this point > > > > > > > > > > > > However i need to have the data stable before the rising edge of this > > > > > > signal, which is one clock cycle wide @ 100 Mhz. so i have one clock > > > > > > cycle to put the data on the bus. > > > > > > I see how to design this, but i am worried about metastability on the > > > > > > asynchronous lines. If i need to take care of this i need to add 2 flops > > > > > > behind it, and after that start making the data available. Overall this > > > > > > will take me at least 3 clock cycles. > > > > > > > > > > > > > > > > > > Richard > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > Don't try to have a 66MHz mem interface and 100MHz internal clock. > > > > > > > Maintain that 2/1 ratio. Run the memory at 50 and the processor at > > > > > > > 100 or run the memory at 66, and run the processor at 133MHz. Your > > > > > > > life will be much easier. > > > > > > > > > > > > > > Hope this help, > > > > > > > Regards > > > > > > > Richard Meester <rme@quest-innovations.com> wrote in message news:<3C63F9C2.6CBF3BE7@quest-innovations.com>... > > > > > > > > > > > > > >>Hi All, > > > > > > >> > > > > > > >>I have some problems finding a good design practice for a bus-interface. > > > > > > >> > > > > > > >>We have a processor running internally at 100Mhz, and externally at > > > > > > >>50Mhz (2 internal bus cycles used for 1 complete external bus cycle). > > > > > > >>Now the addresses are set, the cs lines are set, the re_n and we_n > > > > > > >>signals are set and the data is set or read. I know all the timing > > > > > > >>variables on these lines. > > > > > > >> > > > > > > >>Now i need to design a bus interface, but i want the internal clock to > > > > > > >>run at least at 66 Mhz because i need to access ram at this speed and > > > > > > >>want to keep the internal clock speeds at the same speed. > > > > > > >> > > > > > > >>Now how can i best trigger my internal signals, the we_n line goes > > > > > > >>active low after 8 nsecs of valid data, should i use this signal and > > > > > > >>feed it into a fflop to trigger on, or should i let the flop trigger at > > > > > > >>the internal clock speed and detect that the line has changed state and > > > > > > >>take action from there, or should i make the desing completely > > > > > > >>combinatorial? > > > > > > >> > > > > > > >>Thanks in advance, > > > > > > >> > > > > > > >>Richard > > > > > > >> -- Quest Innovations tel: +31 (0) 227 604046 fax: +31 (0) 227 604053 http://www.quest-innovations.comArticle: 39548
Good Morning, the speed of my project is all depending on the speed of the RAM I use in it, I need a RAM 3072x12, to obtain it I used CORE GENERATOR , choose single port RAM version 3.0 arranged for VIRTEX (in my case I use XCV1000BG560-4) but the speed is really low, a maximum of 50MHz and I repeat the speed of my circuit is only depending on the RAM that can be read only (Essentially it is a ROM) and must be read on every negative front of the clock. Can you tell me the setting I've to do for this core to obtain the maximum speed ?? I've choose a dimension of 4096x12 , thinks this help for the speed. Thanks AntonioArticle: 39549
Hi, Am busy working on a project using Foundation 3.3i, so am hesitant to do any software upgrades until the project is complete. I am thus sitting with the Xilinx upgrade pack, which Xilinx kindly posted to me, that contains software for Foundation 4.1 and ISE 4.1. Could someone please give a quick comparison? Which should I be using? Does Xilinx see a need for its customers to upgrade to Foundation 4.1 while it is trying to market ISE 4.1? Sorry if this question seems a bit trivial/newbie-ish, but I learn everything about FPGA's from this newsgroup. cheers adrian
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