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Hello Ray, Would you say anything about Altera's PLL internal clock skew in a similar conditions (while using CLKLOCK for x1 and CLKBOOST for x2 clocks)? Valeri Serebrianski.Article: 39501
"Paul" <nospam@nospamplease.com> wrote: I've no experience of Modelsim full but I can offer the following on the PC front.... > >I'm in the middle of a project and am finding that as the design comes >together, compilation and more especially simulation is becoming a real >problem. > As a rule I never change my toolset during projects except for specific bug fixes. > >c) I've been toying with getting a 2GHz P4 or an AMD 1900+ or even a dual >processor rig. (With 1Gb RAM). Does performance scale well (i.e. CPU bound >or memory bandwidth bound) and does an MP setup provide any noticeable >improvement or are all tools resolutely single threaded. > Go dual. It'll do very little to improve the rate of simulation of your project but a great deal to improve your sanity. Your simulation will get absolutely 100% of one processor while the other handles the OS giving a small speed increase. The rest of the cycles on processor two are then at your disposal for documenting the last sim, writing the next one, writing endless progress reports, playing freecell, whatever. The cost of the 2nd processor is trivial once you've spec'd a decent scsi based system. That said if your current setup is IDE, even if it's ATA100, go scsi as soon as you can. This is of more benefit than the 2nd processor. I've found it is economic to replace my workstation whenever I can double the processor performance. I've used: P60 (yuk) Dual P200mmx IDE Dual Pii 300 SCSI 2. Dual Piii 650 SCSI 3 RAID (typing on this) Dual Piii xeon 1.7G, SCSI U160, dual 22" (currently being set up) This time I've gone for the xeons A) to avoid P4 (crapomatic) and B) the cost of RAID has gone up. I'd have gone Dual MP1900+ if I could have found one. Quantity of RAM is easy to gauge once to get going, just make sure you choose a PC that can take shedloads if it proves necessary. Long story short: The most expensive PC you can find costs bugger all compared to having you sit and watch an egg timer hour after hour. jac Julian Cox Hardware Development ABB August Ltd Fault Tolerant Industrial Controls Observe antispam measure in my email address (CoxJA@)Article: 39502
> This time I've gone for the xeons A) to avoid P4 (crapomatic) and B) > the cost of RAID has gone up. I'd have gone Dual MP1900+ if I could > have found one. Quantity of RAM is easy to gauge once to get going, > just make sure you choose a PC that can take shedloads if it proves > necessary. Thanks for the advice Julian which I agree with 100% In fact last week the order went out to www.overclockers.co.uk for my nice dual Athlon 1900+ with 1GB RAM. No SCSI though as I'm happy with IDE these days. I agree about not changing development tools, but the Aldec ActiveHDL sure does look nice compared with Altera's offering... Luckily budget constraints stop me buying it anyway. PaulArticle: 39503
Ray Andraka <ray@andraka.com> wrote in message news:<3C617D80.98BA6DF5@andraka.com>... > If you do this in xilinx, the individual LFSRs can be made > very compact (1 CLB) using the SRL16 shift registers (and they could > easily be long enough not to repeat within your lifetime once seeded). I installed the WEBpack software and tried a few implementations. Currently the shift register (SRL16 based implementation inferred from VHDL) limits the speed even though it's listed as zero levels of logic. Even so, it looks like I can get the design (it is quite a bit larger than just the LFSR) to run at about 300MHz (post PAR)in a Spartan-II. With the LFSR speed problem lifted and a few more pipeline registers added I think I can up that to 350...380MHz. Not bad, considering that this is about twice the minimum speed that I targeted. As a sidenote, I started doing this in VHDL (I have done my designs in schematic so far and have a few hours of Verilog experience) to maybe learn something. VHDL is a bit too verbose for my tastes and currently I'm stuck trying to find all the Xilinx specific attributes that I would need to attach to guide the PAR process. Another question: do you really need to write all the conversion functions from STD_LOGIC_VECTOR to integer and back? I would guess that was a standard library function, but I can't look since they are all compiled (or I didn't find the sources, whatever). Achim Gratz.Article: 39504
Achim Gratz wrote > Currently > the shift register (SRL16 based implementation inferred from VHDL) > limits > the speed even though it's listed as zero levels of logic. You can make them faster by always including the flop. This makes your shhift register a 17-bit object (16-bit SRL16, followed by 1-bit FF)Article: 39505
Be careful with the SRL16 timing. There is a minimum pulse width on the
WE pin that is not reported by the timing anaylzer. In VirtexE-7, for
example the minimum pulse width for the SRL16 write limits the clock to
about 235 MHz even though the routing would allow it to go considerably
faster. Also, as Tim says, always follow the SRL16 with the associated
flip-flop. The clock to Q of the SRL16 is really slow compared to that
of the flip-flop. Buffering the output with a flip-flop avoids putting
that long clock to Q in series with the prop delay thorugh a LUT and the
routing.
For the VHDL, include the ieee.numeric_std library. WIth that you can
use the signed and unsigned types instead of integers. These are bit
vectors closely related to std_logic_vector but since the format is
defined you can do math on them.
Tim wrote:
> Achim Gratz wrote
>
> > Currently
> > the shift register (SRL16 based implementation inferred from VHDL)
> > limits
> > the speed even though it's listed as zero levels of logic.
>
> You can make them faster by always including the flop.
> This makes your shhift register a 17-bit object
> (16-bit SRL16, followed by 1-bit FF)
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 39506Austin: Konkurrenz belebt das Geschaeft. Please ask Peter for translation. regards The AmateurArticle: 39507
Don't know. I haven't run across the problem with Altera, but then we've
taken the tact of treating 2x clocks similarly in any device to avoid future
problems. I am sure there is an internal skew. Analog PLLs do a better job
of swallowing jitter, but have other problems such as increased sensitivity to
the supply voltage.
Valeri Serebrianski wrote:
> Hello Ray,
>
> Would you say anything about Altera's PLL internal clock skew in a similar
> conditions (while using CLKLOCK for x1 and CLKBOOST for x2 clocks)?
>
> Valeri Serebrianski.
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 39508
We also use dual processor machines in order to stay productive during a long
sim or PAR, and I've also found it economical to replace the system when I can
double the processor performance. That has been working out to every 18 months
or so, and I've been spending about $8K US per box each time.
Regarding the Aldec, buy it. You'll be very glad you did. It is not only a
world class simulator (only Modelsim compares), but it also has an excellent
design entry suite along with version control and various productivity tools. I
personally don't know how I did without it.
Paul wrote:
> > This time I've gone for the xeons A) to avoid P4 (crapomatic) and B)
> > the cost of RAID has gone up. I'd have gone Dual MP1900+ if I could
> > have found one. Quantity of RAM is easy to gauge once to get going,
> > just make sure you choose a PC that can take shedloads if it proves
> > necessary.
>
> Thanks for the advice Julian which I agree with 100%
>
> In fact last week the order went out to www.overclockers.co.uk for my nice
> dual Athlon 1900+ with 1GB RAM. No SCSI though as I'm happy with IDE these
> days.
>
> I agree about not changing development tools, but the Aldec ActiveHDL sure
> does look nice compared with Altera's offering... Luckily budget constraints
> stop me buying it anyway.
>
> Paul
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 39509
I am having a major problem implementing the coregen asynchronous FIFO.
Modelsim shows pins left open and even my control signals are being screwed
up. The FIFO sort of works but the signals are not quite what I defined in
my test bench. Anybody else had problems with this core?
I am inserting my test bench and wrapper file below so you can try mine if
you like.
--test bench .. fifotest_tb.vhd
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY testbench IS
END testbench;
ARCHITECTURE behavior OF testbench IS
COMPONENT fifotest
PORT(
din : IN std_logic_vector(15 downto 0);
wr_en : IN std_logic;
wr_clk : IN std_logic;
rd_en : IN std_logic;
rd_clk : IN std_logic;
ainit : IN std_logic;
dout : OUT std_logic_vector(15 downto 0);
full : OUT std_logic;
empty : OUT std_logic
);
END COMPONENT;
SIGNAL din : std_logic_vector(15 downto 0);
SIGNAL wr_en : std_logic;
SIGNAL wr_clk : std_logic;
SIGNAL rd_en : std_logic;
SIGNAL rd_clk : std_logic;
SIGNAL ainit : std_logic;
SIGNAL dout : std_logic_vector(15 downto 0);
SIGNAL full : std_logic;
SIGNAL empty : std_logic;
signal c : std_logic;
BEGIN
uut: fifotest PORT MAP(
din => din,
wr_en => wr_en,
wr_clk => wr_clk,
rd_en => rd_en,
rd_clk => rd_clk,
ainit => ainit,
dout => dout,
full => full,
empty => empty
);
process
begin
c<='0', '1' after 2000 ns;
wait;
end process;
process
begin
din<=x"0000", x"0001" after 100 ns, x"0002" after 200 ns, x"0003" after 300
ns, x"0004" after 400 ns;
wait for 500 ns;
end process;
process
begin
wr_en<='1', '0' after 1000 ns;
rd_en<='0', '1' after 1000 ns;
wait for 2000 ns;
end process;
process
begin
wr_clk<='0' and c and wr_en, '1' and c and wr_en after 40 ns, '0' and c and
wr_en after 60 ns;
rd_clk<='0' and c and rd_en, '1' and c and rd_en after 40 ns, '0' and c and
rd_en after 60 ns;
wait for 100 ns;
end process;
process
begin
ainit<='1', '0' after 1000 ns;
wait;
end process;
END;
--fifo wrapper file.. fifotest.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity fifotest is
Port ( din: IN std_logic_VECTOR(15 downto 0);
wr_en: IN std_logic;
wr_clk: IN std_logic;
rd_en: IN std_logic;
rd_clk: IN std_logic;
ainit: IN std_logic;
dout: OUT std_logic_VECTOR(15 downto 0);
full: OUT std_logic;
empty: OUT std_logic);
end fifotest;
architecture Behavioral of fifotest is
component fifo16x63
port (
din: IN std_logic_VECTOR(15 downto 0);
wr_en: IN std_logic;
wr_clk: IN std_logic;
rd_en: IN std_logic;
rd_clk: IN std_logic;
ainit: IN std_logic;
dout: OUT std_logic_VECTOR(15 downto 0);
full: OUT std_logic;
empty: OUT std_logic);
end component;
-- XST black box declaration
attribute box_type : string;
attribute box_type of fifo16x63: component is "black_box";
-- FPGA Express Black Box declaration
attribute fpga_dont_touch: string;
attribute fpga_dont_touch of fifo16x63: component is "true";
-- Synplicity black box declaration
attribute syn_black_box : boolean;
attribute syn_black_box of fifo16x63: component is true;
begin
your_instance_name : fifo16x63
port map (
din => din,
wr_en => wr_en,
wr_clk => wr_clk,
rd_en => rd_en,
rd_clk => rd_clk,
ainit => ainit,
dout => dout,
full => full,
empty => empty);
end Behavioral;
-- the fifo is just the basic 16 wide by 63 deep asynchronous fifo with
nothing changed
-- in the standard options
-- I get an extra pulse in rd_clk with each burst.
-- The pulse should show up in write clock.
-- Is there a problem with my test bench that is generating this misplaced
clock?
-- Also, the simulate post-translate shows a missed signal connection
internal to the fifo.
-- Any ideas?
Article: 39510hi all, While going through the spi-4 2.0 specification, i have the following doubts. Can any one make me clear?? 1. What is the significance of CALENDAR_M. How does this value is determined? 2. Why do we have to iterate the calendar sequence for CALENDAR_M times? 3. If the calendar_M is set to a large value, how does it impact? 4. The data transmitter will transmit data based on the FIFO status. Based on which FIFO status it will transmit whether based on the first iteration or last iteration(calendar_m)? Thanks in Advance DineshArticle: 39511
Rick, Seriously, we didn't invent them, we just placed them in a fabric, and supported them in the FPGA. And as it turns out, you can get a patent for just that kind of assembly of non patentable items arranged in a new or novel way together to perform an improved function. Altera, and we have lots of patents, and now that the legal hassling is over, we can apply all of our efforts to supplying our customers with the best possible products. I appeciate all of the comments, and it is absolutely critical that Xilinx listen to customers, because that is what we did with Virtex, and Virtex II (and are still doing). No time to fiddle around, I have the next two product generations to help design, document, and support. Austin rickman wrote: > I guess I didn't realize that Xilinx invented multipliers and adders. > > Thanks Xilinx. ;) > > Austin Lesea wrote: > > > > Imitation is the sincerest form of flattery. > > > > Thank you, Altera (from all of the IC Designers here at Xilinx). > > > > Austin > > > > Muzaffer Kal wrote: > > > > > looks really cool. I especially like the embedded multipliers and > > > adders. Isn't competition great? > > > http://www.altera.com/products/devices/stratix/stx-index.jsp > > > > > > Muzaffer Kal > > > > > > http://www.dspia.com > > > DSP algorithm implementations for FPGA systems > > -- > > Rick "rickman" Collins > > rick.collins@XYarius.com > Ignore the reply address. To email me use the above address with the XY > removed. > > Arius - A Signal Processing Solutions Company > Specializing in DSP and FPGA design URL http://www.arius.com > 4 King Ave 301-682-7772 Voice > Frederick, MD 21701-3110 301-682-7666 FAXArticle: 39513
Sorry for not providing enough information... > How are you programming it? JTAG? SelectMAP? Serial? JTAG. M0-M2 are programmed for internal pullups and not grounded with jumpers. I'm using parallel port cable with 2 74HC125 chips, I made it using Xilinx drawing. > If it's jtag, then I don't know why it isn't verifying. But, here's a > hypothesis for you: (as Falk alluded to), the configuration port goes > away after the FPGA goes into run mode, so the software can't read the > bitstream back. > > If you provide -g persist:yes to bitgen, I think the config port stays > active and the reads should work. I tried that and this creates another problem. I'm using NU Horizons Digilab D2E board (not bad, but I would be even more happier if they would make one of 2 changes - use XC2S200 for 5V compatibility or XC2S300E for bigger size at minimum cost increase). Configuration pins on this board are used as general I/O and bitgen complains that these persistent pins should be prohibited from use. I kind of expected that JTAG works at any time and the only configuration mismatches would be in RAM contents...Article: 39514
adrianw@ise.canberra.edu.au (Dr A.P. Whichello) wrote in message news:<1f7dnuo.em6q4i5syxxsN@1cust120.tnt1.cbr1.da.uu.net>... > You had to Watch him. > > Adrian. no, you had to watch THIS guy: http://w8ch.com/jsm.html ...Mr Wizard was cool, but he was a pale shell of a scientist when compared to the mighty Julius. =) Too bad he's not rerun on TV anymore--his lectures were kicking and the Dr Frankenstein look simply couldn't be beat. -t [my, this thread has become massively off topic by now]Article: 39515
Hi - I don't speak VHDL, so I may be misinterpreting your code. It appears that you're gating the read and write clocks on and off. Why? Why not run them continuously, and gate the read and write enables? I designed my own asynchronous FIFO; it requires free-running read and write clocks. Maybe the Coregen FIFO does, too. Bob Perlman -- Cambrian Design Works digital design, signal integrity http://www.cambriandesign.com e-mail: respond to bob at the domain above. On Tue, 12 Feb 2002 10:57:02 -0500, "Theron Hicks" <hicksthe@egr.msu.edu> wrote: >I am having a major problem implementing the coregen asynchronous FIFO. >Modelsim shows pins left open and even my control signals are being screwed >up. The FIFO sort of works but the signals are not quite what I defined in >my test bench. Anybody else had problems with this core? > >I am inserting my test bench and wrapper file below so you can try mine if >you like. > >--test bench .. fifotest_tb.vhd > >LIBRARY ieee; >USE ieee.std_logic_1164.ALL; >USE ieee.numeric_std.ALL; > >ENTITY testbench IS >END testbench; > >ARCHITECTURE behavior OF testbench IS > > COMPONENT fifotest > PORT( > din : IN std_logic_vector(15 downto 0); > wr_en : IN std_logic; > wr_clk : IN std_logic; > rd_en : IN std_logic; > rd_clk : IN std_logic; > ainit : IN std_logic; > dout : OUT std_logic_vector(15 downto 0); > full : OUT std_logic; > empty : OUT std_logic > ); > END COMPONENT; > > SIGNAL din : std_logic_vector(15 downto 0); > SIGNAL wr_en : std_logic; > SIGNAL wr_clk : std_logic; > SIGNAL rd_en : std_logic; > SIGNAL rd_clk : std_logic; > SIGNAL ainit : std_logic; > SIGNAL dout : std_logic_vector(15 downto 0); > SIGNAL full : std_logic; > SIGNAL empty : std_logic; > signal c : std_logic; > >BEGIN > > uut: fifotest PORT MAP( > din => din, > wr_en => wr_en, > wr_clk => wr_clk, > rd_en => rd_en, > rd_clk => rd_clk, > ainit => ainit, > dout => dout, > full => full, > empty => empty > ); > > process > begin > c<='0', '1' after 2000 ns; > wait; > end process; > > process > begin > din<=x"0000", x"0001" after 100 ns, x"0002" after 200 ns, x"0003" after 300 >ns, x"0004" after 400 ns; > wait for 500 ns; > end process; > > process > begin > wr_en<='1', '0' after 1000 ns; > rd_en<='0', '1' after 1000 ns; > wait for 2000 ns; > end process; > > process > begin > wr_clk<='0' and c and wr_en, '1' and c and wr_en after 40 ns, '0' and c and >wr_en after 60 ns; > rd_clk<='0' and c and rd_en, '1' and c and rd_en after 40 ns, '0' and c and >rd_en after 60 ns; > wait for 100 ns; > end process; > > process > begin > ainit<='1', '0' after 1000 ns; > wait; > end process; > >END; > >--fifo wrapper file.. fifotest.vhd > >library IEEE; >use IEEE.STD_LOGIC_1164.ALL; >use IEEE.STD_LOGIC_ARITH.ALL; >use IEEE.STD_LOGIC_UNSIGNED.ALL; > >entity fifotest is > Port ( din: IN std_logic_VECTOR(15 downto 0); > wr_en: IN std_logic; > wr_clk: IN std_logic; > rd_en: IN std_logic; > rd_clk: IN std_logic; > ainit: IN std_logic; > dout: OUT std_logic_VECTOR(15 downto 0); > full: OUT std_logic; > empty: OUT std_logic); > >end fifotest; > >architecture Behavioral of fifotest is >component fifo16x63 > port ( > din: IN std_logic_VECTOR(15 downto 0); > wr_en: IN std_logic; > wr_clk: IN std_logic; > rd_en: IN std_logic; > rd_clk: IN std_logic; > ainit: IN std_logic; > dout: OUT std_logic_VECTOR(15 downto 0); > full: OUT std_logic; > empty: OUT std_logic); >end component; > >-- XST black box declaration >attribute box_type : string; >attribute box_type of fifo16x63: component is "black_box"; > >-- FPGA Express Black Box declaration >attribute fpga_dont_touch: string; >attribute fpga_dont_touch of fifo16x63: component is "true"; > >-- Synplicity black box declaration >attribute syn_black_box : boolean; >attribute syn_black_box of fifo16x63: component is true; > >begin > >your_instance_name : fifo16x63 > port map ( > din => din, > wr_en => wr_en, > wr_clk => wr_clk, > rd_en => rd_en, > rd_clk => rd_clk, > ainit => ainit, > dout => dout, > full => full, > empty => empty); > >end Behavioral; > > >-- the fifo is just the basic 16 wide by 63 deep asynchronous fifo with >nothing changed >-- in the standard options >-- I get an extra pulse in rd_clk with each burst. >-- The pulse should show up in write clock. >-- Is there a problem with my test bench that is generating this misplaced >clock? >-- Also, the simulate post-translate shows a missed signal connection >internal to the fifo. >-- Any ideas? >Article: 39516
> > How are you programming it? JTAG? SelectMAP? Serial? > > JTAG. M0-M2 are programmed for internal pullups and not grounded with > jumpers. I'm using parallel port cable with 2 74HC125 chips, I made it > using Xilinx drawing. Readback doesn't seem to work with iMPACT and a parallel JTAG cable. Read answer record 8097 for the list of supported devices and operations. JimArticle: 39517
Hi. I am looking for an excell sheet to do power estimation for virtex2 device. Unfortunately the excell sheet I found on the web is only for Virtex ane Virtex-E (xapp152). Is there something similiar for Virtex2 ? Tamar.Article: 39518
Perhaps that is the case. While the data sheet does not say that, the timing diagrams in the data sheet show a continuous clock. I will give it a try. I had hoped to clock the write when I needed to store a value and then clock the read when I needed to read a value. Basicly, the 32 data values are being generated over about a 5 microsecond period but the data must be transmitted over a 10 microsecond period to allow for an acceptable data rate. Thus for the first 5 microseconds data is being both generated and transmitted. During the second 5 microseconds the transmit function is just catching up to the generated values. Is this reasonable? Thanks, Theron Hicks "Bob Perlman" <no-spam@sonic.net> wrote in message news:9hgi6ucoac4cc14j1dsvl6so8krqr5rpfr@4ax.com... > Hi - > > I don't speak VHDL, so I may be misinterpreting your code. It appears > that you're gating the read and write clocks on and off. Why? Why > not run them continuously, and gate the read and write enables? > > I designed my own asynchronous FIFO; it requires free-running read and > write clocks. Maybe the Coregen FIFO does, too. > > Bob Perlman > -- > Cambrian Design Works > digital design, signal integrity > http://www.cambriandesign.com > e-mail: respond to bob at the domain above. > > On Tue, 12 Feb 2002 10:57:02 -0500, "Theron Hicks" > <hicksthe@egr.msu.edu> wrote: > > >I am having a major problem implementing the coregen asynchronous FIFO. > >Modelsim shows pins left open and even my control signals are being screwed > >up. The FIFO sort of works but the signals are not quite what I defined in > >my test bench. Anybody else had problems with this core? > > > >I am inserting my test bench and wrapper file below so you can try mine if > >you like. > > > >--test bench .. fifotest_tb.vhd > > > >LIBRARY ieee; > >USE ieee.std_logic_1164.ALL; > >USE ieee.numeric_std.ALL; > > > >ENTITY testbench IS > >END testbench; > > > >ARCHITECTURE behavior OF testbench IS > > > > COMPONENT fifotest > > PORT( > > din : IN std_logic_vector(15 downto 0); > > wr_en : IN std_logic; > > wr_clk : IN std_logic; > > rd_en : IN std_logic; > > rd_clk : IN std_logic; > > ainit : IN std_logic; > > dout : OUT std_logic_vector(15 downto 0); > > full : OUT std_logic; > > empty : OUT std_logic > > ); > > END COMPONENT; > > > > SIGNAL din : std_logic_vector(15 downto 0); > > SIGNAL wr_en : std_logic; > > SIGNAL wr_clk : std_logic; > > SIGNAL rd_en : std_logic; > > SIGNAL rd_clk : std_logic; > > SIGNAL ainit : std_logic; > > SIGNAL dout : std_logic_vector(15 downto 0); > > SIGNAL full : std_logic; > > SIGNAL empty : std_logic; > > signal c : std_logic; > > > >BEGIN > > > > uut: fifotest PORT MAP( > > din => din, > > wr_en => wr_en, > > wr_clk => wr_clk, > > rd_en => rd_en, > > rd_clk => rd_clk, > > ainit => ainit, > > dout => dout, > > full => full, > > empty => empty > > ); > > > > process > > begin > > c<='0', '1' after 2000 ns; > > wait; > > end process; > > > > process > > begin > > din<=x"0000", x"0001" after 100 ns, x"0002" after 200 ns, x"0003" after 300 > >ns, x"0004" after 400 ns; > > wait for 500 ns; > > end process; > > > > process > > begin > > wr_en<='1', '0' after 1000 ns; > > rd_en<='0', '1' after 1000 ns; > > wait for 2000 ns; > > end process; > > > > process > > begin > > wr_clk<='0' and c and wr_en, '1' and c and wr_en after 40 ns, '0' and c and > >wr_en after 60 ns; > > rd_clk<='0' and c and rd_en, '1' and c and rd_en after 40 ns, '0' and c and > >rd_en after 60 ns; > > wait for 100 ns; > > end process; > > > > process > > begin > > ainit<='1', '0' after 1000 ns; > > wait; > > end process; > > > >END; > > > >--fifo wrapper file.. fifotest.vhd > > > >library IEEE; > >use IEEE.STD_LOGIC_1164.ALL; > >use IEEE.STD_LOGIC_ARITH.ALL; > >use IEEE.STD_LOGIC_UNSIGNED.ALL; > > > >entity fifotest is > > Port ( din: IN std_logic_VECTOR(15 downto 0); > > wr_en: IN std_logic; > > wr_clk: IN std_logic; > > rd_en: IN std_logic; > > rd_clk: IN std_logic; > > ainit: IN std_logic; > > dout: OUT std_logic_VECTOR(15 downto 0); > > full: OUT std_logic; > > empty: OUT std_logic); > > > >end fifotest; > > > >architecture Behavioral of fifotest is > >component fifo16x63 > > port ( > > din: IN std_logic_VECTOR(15 downto 0); > > wr_en: IN std_logic; > > wr_clk: IN std_logic; > > rd_en: IN std_logic; > > rd_clk: IN std_logic; > > ainit: IN std_logic; > > dout: OUT std_logic_VECTOR(15 downto 0); > > full: OUT std_logic; > > empty: OUT std_logic); > >end component; > > > >-- XST black box declaration > >attribute box_type : string; > >attribute box_type of fifo16x63: component is "black_box"; > > > >-- FPGA Express Black Box declaration > >attribute fpga_dont_touch: string; > >attribute fpga_dont_touch of fifo16x63: component is "true"; > > > >-- Synplicity black box declaration > >attribute syn_black_box : boolean; > >attribute syn_black_box of fifo16x63: component is true; > > > >begin > > > >your_instance_name : fifo16x63 > > port map ( > > din => din, > > wr_en => wr_en, > > wr_clk => wr_clk, > > rd_en => rd_en, > > rd_clk => rd_clk, > > ainit => ainit, > > dout => dout, > > full => full, > > empty => empty); > > > >end Behavioral; > > > > > >-- the fifo is just the basic 16 wide by 63 deep asynchronous fifo with > >nothing changed > >-- in the standard options > >-- I get an extra pulse in rd_clk with each burst. > >-- The pulse should show up in write clock. > >-- Is there a problem with my test bench that is generating this misplaced > >clock? > >-- Also, the simulate post-translate shows a missed signal connection > >internal to the fifo. > >-- Any ideas? > > >Article: 39519
On Tue, 12 Feb 2002 01:28:06 GMT, Ray Andraka <ray@andraka.com> wrote: >Depends if you use primitives that are unique to a particular family or not. For >example, if your edif contains a clkdlle, then it is virtexe specific. If it >contains only unisim primitives that are common to all families, then you have >something that will work on multiple families. Our ultra-fast FFT core, for >example uses the same edif netlist for spartanII, virtex and virtexE. It contains >RLOCs, so it is not compatible with VirtexII. > Thanks Ray. How can I control which primitives are used to make a single EDIF universal? I'm using the Xilinx Foundation 3.3i Project Navigator with XST to synthesize from VHDL, then a DOS batch file for the EDIF to MCS process. This is for a black_box component, so no I/O pads involved. The project setup in Project Navigator includes selecting a part - I don't know what use XST makes of that selection other than putting the selected part name in the EDIF file. Can XST be run as a DOS command line with switches to select a library of universal primitives? John >In Memory of tecNovia wrote: > >> >> My question is - is the EDIF file truly generic or is it already >> family specific. To generate black_box EDIF files for other users to >> take and link, do I only need one EDIF file, or do I need one for >> VertexE, one for Spartan, etc? >> >> JohnArticle: 39520
To play the devil's avocado a little bit here... Regarding the dual processor thing. I wish it weren't true, but all the EDA software I've used on the PC is single threaded. So on a long P&R, while one processor is near 100% and the other sits idle. So you want to edit your word document or browse the web whilest you wait. The .0001% of the total CPU cyles you take for these types of low MIP activities has such a small impact I'm not sure its always worth getting the extra processor. So your P&R takes 11 hours and 2 minutes instead of taking just 11 hours. We had a dual P3 1GHz and were concerned that since the OS was shifting the P&R task back and forth between the 2 CPU's, it was constantly having to refill the caches. We pulled the second CPU and have not put it back or noticed a difference by our completely unscientific measures. Also in these days of GHz processors and MHz memory, the CPU's are often memory bound, so putting another processor on that same memory bus isn't going to give you twice as much juice. I'd love to see some benchmarks for a P&R on the same machine with 1 and 2 processors populated. Regards Ray Andraka <ray@andraka.com> wrote in message news:<3C693054.2EBAF61D@andraka.com>... > We also use dual processor machines in order to stay productive during a long > sim or PAR, and I've also found it economical to replace the system when I can > double the processor performance. That has been working out to every 18 months > or so, and I've been spending about $8K US per box each time. > > Regarding the Aldec, buy it. You'll be very glad you did. It is not only a > world class simulator (only Modelsim compares), but it also has an excellent > design entry suite along with version control and various productivity tools. I > personally don't know how I did without it. > > Paul wrote: > > > > This time I've gone for the xeons A) to avoid P4 (crapomatic) and B) > > > the cost of RAID has gone up. I'd have gone Dual MP1900+ if I could > > > have found one. Quantity of RAM is easy to gauge once to get going, > > > just make sure you choose a PC that can take shedloads if it proves > > > necessary. > > > > Thanks for the advice Julian which I agree with 100% > > > > In fact last week the order went out to www.overclockers.co.uk for my nice > > dual Athlon 1900+ with 1GB RAM. No SCSI though as I'm happy with IDE these > > days. > > > > I agree about not changing development tools, but the Aldec ActiveHDL sure > > does look nice compared with Altera's offering... Luckily budget constraints > > stop me buying it anyway. > > > > Paul > > -- > --Ray Andraka, P.E. > President, the Andraka Consulting Group, Inc. > 401/884-7930 Fax 401/884-7950 > email ray@andraka.com > http://www.andraka.com > > "They that give up essential liberty to obtain a little > temporary safety deserve neither liberty nor safety." > -Benjamin Franklin, 1759Article: 39521
If all your clocks are derived from the same reference and phase locked then your do not need to worry about metastability other than the conventional set-up and hold requirements required of your receiving flip flops common to all standard synchronous designs. Be aware that the static timing checks done by typical FPGA tools do not handle multi-clock relationships very well, but a timing back annotated gate level sim should give you meaningful checks. To say it another way, you do not need to do the cascaded flip flip thing that you would do when you have signals coming in from an ASYNCHRONOUS clock domain. Regards Richard Meester <rme@quest-innovations.com> wrote in message news:<3C68C144.A80A47AE@quest-innovations.com>... > Hi Jay, > > Yes, we have an external CPU and external memory. We develop the FPGA to be a DMA controller and some more activity. > We have internal registers inside the FPGA which need to be addressed as a memory device. After this the FPGA can > become bus master. > > What i have done now is that i clock the FPGA at 100Mhz, scan the lines and check for the appropriate signals and go > from there. I have 4 clock cycles at 100Mhz at the moment, but in future will advance to 2 clock cycles to respond. > Once the FPGA becomes a bus-master i add a pipeline stage which will allow 1 clock cycle addresses and delayed data > lines when it comes to a read. Also bus turnaround will have a 4 cycle latency. I will transfer chunks of 16/32 words > so the benefit of the pipeline is definately there. Now my problem is do i need to synchronize and concern about > metastability on the incomming lines when the FPGA is a memory device for the external processor? > > Thanks, > > Richard > > Jay wrote: > > > I think I misunderstood your configuration. Do you have a uP chip > > that you've purchased talking to your FPGA as a memory device? > > > > Richard Meester <rme@quest-innovations.com> wrote in message news:<3C64E594.9060200@quest-innovations.com>... > > > Hi Jay, > > > Thanks for the response, > > > > > > Jay wrote: > > > > > > > I'm going to make some assumptions because I'm not sure if I > > > > understand your description, correct me if I'm wrong. > > > > > > > > Like you suggested, go ahead and run your internal processor at twice > > > > the external interface. Enable the data capture and data launch flops > > > > on every other clock. Clock every flip/flop in your design on the > > > > higher 2X clock. > > > > > > > > > What do you meen by every other clock, clock the lines, and than wait > > > one clock, and then clock again for the next complete cycle? > > > > > > Don't i have a metastability problem with the asynchronous read/write/cs > > > lines > > > > > > the problem is that the signal below is i.e. the r/w signal. it is > > > asynchronous. if i sample this at twice the frequency i will at > > > somepoint get the correct valie that i need to trigger on. > > > > > > ---\________/------ > > > > > > ^ ^ samples at one of these points at 100 Mhz. > > > ^ DATA must be stable at this point > > > > > > However i need to have the data stable before the rising edge of this > > > signal, which is one clock cycle wide @ 100 Mhz. so i have one clock > > > cycle to put the data on the bus. > > > I see how to design this, but i am worried about metastability on the > > > asynchronous lines. If i need to take care of this i need to add 2 flops > > > behind it, and after that start making the data available. Overall this > > > will take me at least 3 clock cycles. > > > > > > > > > Richard > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > Don't try to have a 66MHz mem interface and 100MHz internal clock. > > > > Maintain that 2/1 ratio. Run the memory at 50 and the processor at > > > > 100 or run the memory at 66, and run the processor at 133MHz. Your > > > > life will be much easier. > > > > > > > > Hope this help, > > > > Regards > > > > Richard Meester <rme@quest-innovations.com> wrote in message news:<3C63F9C2.6CBF3BE7@quest-innovations.com>... > > > > > > > >>Hi All, > > > >> > > > >>I have some problems finding a good design practice for a bus-interface. > > > >> > > > >>We have a processor running internally at 100Mhz, and externally at > > > >>50Mhz (2 internal bus cycles used for 1 complete external bus cycle). > > > >>Now the addresses are set, the cs lines are set, the re_n and we_n > > > >>signals are set and the data is set or read. I know all the timing > > > >>variables on these lines. > > > >> > > > >>Now i need to design a bus interface, but i want the internal clock to > > > >>run at least at 66 Mhz because i need to access ram at this speed and > > > >>want to keep the internal clock speeds at the same speed. > > > >> > > > >>Now how can i best trigger my internal signals, the we_n line goes > > > >>active low after 8 nsecs of valid data, should i use this signal and > > > >>feed it into a fflop to trigger on, or should i let the flop trigger at > > > >>the internal clock speed and detect that the line has changed state and > > > >>take action from there, or should i make the desing completely > > > >>combinatorial? > > > >> > > > >>Thanks in advance, > > > >> > > > >>Richard > > > >>Article: 39522
Hi Jay, Jay wrote: > If all your clocks are derived from the same reference and phase > locked then your do not need to worry about metastability other than > the conventional set-up and hold requirements required of your > receiving flip flops common to all standard synchronous designs. Be > aware that the static timing checks done by typical FPGA tools do not > handle multi-clock relationships very well, but a timing back > annotated gate level sim should give you meaningful checks. > > To say it another way, you do not need to do the cascaded flip flip > thing that you would do when you have signals coming in from an > ASYNCHRONOUS clock domain. > The FPGA is not driven by the same clock that drives the CPU, the CPU has an external 10 Mhz and an internal PLL, the FPGA has an external 100Mhz clock, or a 10Mhz clock and uses the spartanII dll's. Having said this it seems that the signals doe come from an asynchronous clock domain right? Since my design is pipelined can i see this pipeline as the cascaded flip flop thing if i check the signals at the end of my pipe? Thanks. Richard > > Regards > > Richard Meester <rme@quest-innovations.com> wrote in message news:<3C68C144.A80A47AE@quest-innovations.com>... > > Hi Jay, > > > > Yes, we have an external CPU and external memory. We develop the FPGA to be a DMA controller and some more activity. > > We have internal registers inside the FPGA which need to be addressed as a memory device. After this the FPGA can > > become bus master. > > > > What i have done now is that i clock the FPGA at 100Mhz, scan the lines and check for the appropriate signals and go > > from there. I have 4 clock cycles at 100Mhz at the moment, but in future will advance to 2 clock cycles to respond. > > Once the FPGA becomes a bus-master i add a pipeline stage which will allow 1 clock cycle addresses and delayed data > > lines when it comes to a read. Also bus turnaround will have a 4 cycle latency. I will transfer chunks of 16/32 words > > so the benefit of the pipeline is definately there. Now my problem is do i need to synchronize and concern about > > metastability on the incomming lines when the FPGA is a memory device for the external processor? > > > > Thanks, > > > > Richard > > > > Jay wrote: > > > > > I think I misunderstood your configuration. Do you have a uP chip > > > that you've purchased talking to your FPGA as a memory device? > > > > > > Richard Meester <rme@quest-innovations.com> wrote in message news:<3C64E594.9060200@quest-innovations.com>... > > > > Hi Jay, > > > > Thanks for the response, > > > > > > > > Jay wrote: > > > > > > > > > I'm going to make some assumptions because I'm not sure if I > > > > > understand your description, correct me if I'm wrong. > > > > > > > > > > Like you suggested, go ahead and run your internal processor at twice > > > > > the external interface. Enable the data capture and data launch flops > > > > > on every other clock. Clock every flip/flop in your design on the > > > > > higher 2X clock. > > > > > > > > > > > > What do you meen by every other clock, clock the lines, and than wait > > > > one clock, and then clock again for the next complete cycle? > > > > > > > > Don't i have a metastability problem with the asynchronous read/write/cs > > > > lines > > > > > > > > the problem is that the signal below is i.e. the r/w signal. it is > > > > asynchronous. if i sample this at twice the frequency i will at > > > > somepoint get the correct valie that i need to trigger on. > > > > > > > > ---\________/------ > > > > > > > > ^ ^ samples at one of these points at 100 Mhz. > > > > ^ DATA must be stable at this point > > > > > > > > However i need to have the data stable before the rising edge of this > > > > signal, which is one clock cycle wide @ 100 Mhz. so i have one clock > > > > cycle to put the data on the bus. > > > > I see how to design this, but i am worried about metastability on the > > > > asynchronous lines. If i need to take care of this i need to add 2 flops > > > > behind it, and after that start making the data available. Overall this > > > > will take me at least 3 clock cycles. > > > > > > > > > > > > Richard > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > Don't try to have a 66MHz mem interface and 100MHz internal clock. > > > > > Maintain that 2/1 ratio. Run the memory at 50 and the processor at > > > > > 100 or run the memory at 66, and run the processor at 133MHz. Your > > > > > life will be much easier. > > > > > > > > > > Hope this help, > > > > > Regards > > > > > Richard Meester <rme@quest-innovations.com> wrote in message news:<3C63F9C2.6CBF3BE7@quest-innovations.com>... > > > > > > > > > >>Hi All, > > > > >> > > > > >>I have some problems finding a good design practice for a bus-interface. > > > > >> > > > > >>We have a processor running internally at 100Mhz, and externally at > > > > >>50Mhz (2 internal bus cycles used for 1 complete external bus cycle). > > > > >>Now the addresses are set, the cs lines are set, the re_n and we_n > > > > >>signals are set and the data is set or read. I know all the timing > > > > >>variables on these lines. > > > > >> > > > > >>Now i need to design a bus interface, but i want the internal clock to > > > > >>run at least at 66 Mhz because i need to access ram at this speed and > > > > >>want to keep the internal clock speeds at the same speed. > > > > >> > > > > >>Now how can i best trigger my internal signals, the we_n line goes > > > > >>active low after 8 nsecs of valid data, should i use this signal and > > > > >>feed it into a fflop to trigger on, or should i let the flop trigger at > > > > >>the internal clock speed and detect that the line has changed state and > > > > >>take action from there, or should i make the desing completely > > > > >>combinatorial? > > > > >> > > > > >>Thanks in advance, > > > > >> > > > > >>Richard > > > > >> -- Quest Innovations tel: +31 (0) 227 604046 fax: +31 (0) 227 604053 http://www.quest-innovations.comArticle: 39523
"Jay" <kayrock66@yahoo.com> wrote in message news:d049f91b.0202121027.11f52c8e@posting.google.com... > To play the devil's avocado a little bit here... Regarding the dual > processor thing. I wish it weren't true, but all the EDA software > I've used on the PC is single threaded. I agree to a certain extent, but don't you find that when a simulation etc is underway the machine feels extremely sluggish. Having that extra CPU to do other things isn't a great performance boost, but it allows the user a more responsive machine for other tasks. I do however agree with the problem of tasks hopping processor to processor as this is often a problem with high-performance games that actually run slower on a dual procesor machine. On Intel MP boards the CPUs do indeed share the same memory bus, but the dual processor Athlon MPs have separate full buses to alleviate memory problems to a large extent. I think though that your point that the second processor may not give many advantages is a valid one unless software deliberately makes use of it. Its a £300 gamble I was willing to take, but wouldn't have if Xeons were my only choice as the cost differential would have been considerably higher. Paul PS Thanks to everyone who's given their thoughts here. Most useful. In the end I'm hoping that I can utilise ActiveHDL to significantly reduce my simulation bottleneck.Article: 39524
This is not too much of a reply, but... Running XST yields this usage message: Usage: xst [-ifn <InputFile>] [-ofn <OutputFile>] [-quiet] And looking in the foobar.xst file written by the GUI shows -p switch which surely selects the part family. I would expect that you can experiment from heer to get a batch version of XST. For an easier life, use Synplicity :) "In Memory of tecNovia" wrote > On Tue, 12 Feb 2002 01:28:06 GMT, Ray Andraka <ray@andraka.com> wrote: > > >Depends if you use primitives that are unique to a particular family or not. For > >example, if your edif contains a clkdlle, then it is virtexe specific. If it > >contains only unisim primitives that are common to all families, then you have > >something that will work on multiple families. Our ultra-fast FFT core, for > >example uses the same edif netlist for spartanII, virtex and virtexE. It contains > >RLOCs, so it is not compatible with VirtexII. > > > > Thanks Ray. > > How can I control which primitives are used to make a single EDIF > universal? I'm using the Xilinx Foundation 3.3i Project Navigator with > XST to synthesize from VHDL, then a DOS batch file for the EDIF to MCS > process. This is for a black_box component, so no I/O pads involved. > > The project setup in Project Navigator includes selecting a part - I > don't know what use XST makes of that selection other than putting > the selected part name in the EDIF file. > > Can XST be run as a DOS command line with switches to select a library > of universal primitives? > > John
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