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Jim Kearney wrote: > > "Tim" <tim@rockylogic.com.nooospam.com> wrote in message > news:1015642799.2102.0.nnrp-12.9e9832fa@news.demon.co.uk... > > I feel really, really stupid at having to ask this... > > > > What is the name of the connectors on the end of the wires > > on Xilinx download cables? I mean the socket thingies > > which fit over 0.025" posts - I think they crimp onto the > > fairly thick wires. > > > > They may be in the DigiKey Catalog, but I cannot find > > them ;) > > I had a need for these too, but Digi-key doesn't have quite the right parts. > But I think you'll find what you want on pg. 215 of the Mouser catalog, e.g. > part # 571-7874992 and its associated snap-in receptacles. > > Jim I haven't looked at the catalog, but this is like something like the Molex or Amp pins for 0.1" sockets. They are nice connectors, but they require you to buy a crimp tool that costs several hundred dollars. Of course if this is not for production, you can get by with something makeshift. But my experience is that you need the right crimp tool for a reliable connection. Amp and Molex will even sell you an economy tool, but they make no claim that it makes a good crimp. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 40601
Theron, Thank you for your kind words. Now that our friend has opened his mind to us, we should best let it lie undisturbed. The more attention, the worse for all of us. Austin Theron Hicks wrote: > Isuser on drugs? I wish I could figure out how to kill file him. > > Peter, Austin and others, > > Keep up the good work. I wish other semiconductor vendors had half the help available that I > get here for free. BTW, that is why Xilinx is designed in to my product. Fortunately I have > that option available to me. > > Isuser, > Did you ever consider that that is what they get paid for? Would you expect TI to > recomend an On-Semi part to replace a TI part? Do your own vendor research or live with the > free help. > > Theron Hicks > > lsuser wrote: > > > peter, thank you very much. > > > > There is a reason why I´ve posted that. > > > > any_user: could somebody tell me why jtag programming is not working with my ispLSI 2023? > > > > Peter Alfke : I don´t know but you could use Xilinx XC95K or Coolrunner. > > > > any_user: Exist other firms which have such fpgas > > > > Peter Alfke: I don´t know but you could use Xilinx Virtex 2. > > > > etc etc etc. > > > > know what i mean?Article: 40602
hicks, like drugs, hicksArticle: 40603
The information's probably in the timing report or can be put there. The path report will give you a step by step of the delay segments including all routing and combinatorial delays from clock-to-out to the setup. If there are two levels of logic, you may see why in the timing path information for that constraint. Play with the tool. Discover the info it provides. Hristo Stevic wrote: > hello, > just try to expirement little bit with the constraint > > i have IFD-->FD-->FD-->OFD > > i have set this constraint > > TIMESPEC TS_F0 = FROM FFS TO FFS 20ns; > > in the timing report. say that this constraint is met with 2 level of > logics, taught should be 1 (or even 0) > any explanation > Thanks > > -- > Posted via Mailgate.ORG Server - http://www.Mailgate.ORGArticle: 40604
Rick, I strongly encourage everyone to get a good SI tool. You can play with it in about 3 minutes, and get valid answers trivially. I also have a very slow acess line (at home), so you may want to consider emailing Hyperlynx and getting the demo CD. By the way, the FAE force is all outfitted with their tool now, so they can instantly evaluate filed SI issues. Austin rickman wrote: > The answer to that is very simple. Because it took me about 2 minutes > to ask such a simple question which Peter answered in about 1 minute, > very likely. > > On the other hand, I could have spent 15 minutes reading about the > Hyperlynx tools (after finding the right page), spend what, maybe half > an hour to a couple of hours downloading the tools, (I am working over a > 28Kbps link) and then a couple more hours learning how to use the tool, > setting it up, getting the result and then not trusting it since I have > no way to make sure both I and the tool did it correctly. I have tried > using "free" tools before that were provided by vendors. It is not > uncommon that they don't work right, are hard to use or even crap out my > machine (that happened to me with Swift Designer from TI for their power > converter chips). > > So let me see... 3 minutes vs. 3 hours... > > Maybe Hyperlynx really is easy to use. But it is not justified at this > point even if it takes 5 minutes to get the answer. > > I will be giving Hyperlynx a try later when I am ready to lay out the > board. I have a 100 MHz SDRAM memory interface. But until then, I just > need a little info to get the schematic finished. > Thanks for the diagram. Seeing that encourages me to give it a try. > > Austin Lesea wrote: > > > > Simulate it with IBIS. > > > > Why does everyone avoid such a simple solution? The Hyperlynx demo is free, > > and includes some useful IBIS models (like Xilinx parts). > > > > Austin > > > > rickman wrote: > > > > > I need to drive a CMOS device with a Spartan II E chip. The data sheet > > > only guarantees 2.4 volts on the output at 24 mA. Nothing is said about > > > lighter loads, for example a CMOS input. Working with an odd Vdd on the > > > CMOS device of 3.8 volts, I get a Vih of 2.66 volts. Is it safe to > > > assume that the Spartan device will pull fully to 3.3 volts (or very > > > near) with such a light load? The input current on the CMOS device is > > > <10 uA. Or should I use pullups? In spite of the data sheet note > > > saying that the internal pullups should not be used to pull external > > > signals, will they be sufficient to provide sufficient pullup with such > > > a light load? I am not even sure if you can enable the pullups on pin > > > used as outputs. Anyone have experience with this? > > > > > > -- > > > > > > Rick "rickman" Collins > > > > > > rick.collins@XYarius.com > > > Ignore the reply address. To email me use the above address with the XY > > > removed. > > > > > > Arius - A Signal Processing Solutions Company > > > Specializing in DSP and FPGA design URL http://www.arius.com > > > 4 King Ave 301-682-7772 Voice > > > Frederick, MD 21701-3110 301-682-7666 FAX > > -- > > Rick "rickman" Collins > > rick.collins@XYarius.com > Ignore the reply address. To email me use the above address with the XY > removed. > > Arius - A Signal Processing Solutions Company > Specializing in DSP and FPGA design URL http://www.arius.com > 4 King Ave 301-682-7772 Voice > Frederick, MD 21701-3110 301-682-7666 FAXArticle: 40605
>> I am trying to convert an old project written in MachXL DSL to a more >modern >> Mach device. Since the current Lattice software does not support DSL, I am >> going to have to convert to another design language. As far as I can see, >> my choices are Verilog, VHDL and ABEL. I was recommended to learn either >> Verilog or VHDL, preferably VHDL since that is more used here in Europe, >but >> no mention was made of ABEL. As far as I can see, however, ABEL is a much >> simpler language, which should be more than sufficient for my needs. As >far >> as I have understood it from what I have read so far, both Verilog and VHDL >> are simulation languages, and only a small part of the language is actually >> synthesizable in hardware, whereas ABEL is designed as as hardware >> description language. VHDL and VErilog are the most widely accepted synthesis and simulation languages. The nice thing about that is that you can also verify your design in the same environment. On the surface, for synthesis (which requires a subset of the language), the two HDLs look pretty much alike, except for the the syntax. There are also differences in the aRITHMETIC OPERATIONS (Signed/unsigned stuff). There are also differences in constructs for design verification. There are differences in timing of the underlying simulator, visibility, types. The trick in design and verification is the methodology, architecture, and style rules. This is where you'll find my book Real Chip Design and Verification Using Verilog and VHDL very useful. a) Chapter 9 address VHDL/Verilog comparisons, and explains Verilog for VHDL users (like you). It also provides style guides, particularly for VHDL users. b) It provides many small, but real examples in both HDL so that you quickly see and understand style and rules for synthesis. c) It addresses verification using transaction based methodology in both HDL, along with error injection methodology. d) It addresses the methodology in designing control machines (chapter 5) and styles for FSMs in both HDL e) It address arithmetic machines, and for Verilog, some of the nasty things of arithmetic in Verilog'95. f) It addresses metastability issues and methods to resolve them g) Chapter 8 on minimizing errors would help you understand some realities of designs, and methods to minimize errors. For editor, I strongly recommend EMACS with VHDL and Verilog templates, available everywhere, but is also on the CD for Windows(all versions). The CD includes under Cadence subdirectory the Verilog-XL Reference in html and PDF. This is an excellent reference material on Verilog, better than any textbook. --------------------------------------------------------------------------- Ben Cohen Publisher, Trainer, Consultant (310) 721-4830 http://www.vhdlcohen.com/ vhdlcohen@aol.com Author of following textbooks: * Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 0-9705394-2-8 * Component Design by Example ", 2001 isbn 0-9705394-0-1 * VHDL Coding Styles and Methodologies, 2nd Edition, 1999 isbn 0-7923-8474-1 * VHDL Answers to Frequently Asked Questions, 2nd Edition, isbn 0-7923-8115 ------------------------------------------------------------------------------Article: 40606
It is true that the answer took me only a minute... But that's because it was a simple question. I will or can not answer complicated signal-integrity questions this way. Peter Alfke rickman wrote: > The answer to that is very simple. Because it took me about 2 minutes > to ask such a simple question which Peter answered in about 1 minute, > very likely. > > On the other hand, I could have spent 15 minutes reading about the > Hyperlynx tools (after finding the right page), spend what, maybe half > an hour to a couple of hours downloading the tools, (I am working over a > 28Kbps link) and then a couple more hours learning how to use the tool, > setting it up, getting the result and then not trusting it since I have > no way to make sure both I and the tool did it correctly. I have tried > using "free" tools before that were provided by vendors. It is not > uncommon that they don't work right, are hard to use or even crap out my > machine (that happened to me with Swift Designer from TI for their power > converter chips). > > So let me see... 3 minutes vs. 3 hours... > > Maybe Hyperlynx really is easy to use. But it is not justified at this > point even if it takes 5 minutes to get the answer. > > I will be giving Hyperlynx a try later when I am ready to lay out the > board. I have a 100 MHz SDRAM memory interface. But until then, I just > need a little info to get the schematic finished. > Thanks for the diagram. Seeing that encourages me to give it a try. > > Austin Lesea wrote: > > > > Simulate it with IBIS. > > > > Why does everyone avoid such a simple solution? The Hyperlynx demo is free, > > and includes some useful IBIS models (like Xilinx parts). > > > > Austin > > > > rickman wrote: > > > > > I need to drive a CMOS device with a Spartan II E chip. The data sheet > > > only guarantees 2.4 volts on the output at 24 mA. Nothing is said about > > > lighter loads, for example a CMOS input. Working with an odd Vdd on the > > > CMOS device of 3.8 volts, I get a Vih of 2.66 volts. Is it safe to > > > assume that the Spartan device will pull fully to 3.3 volts (or very > > > near) with such a light load? The input current on the CMOS device is > > > <10 uA. Or should I use pullups? In spite of the data sheet note > > > saying that the internal pullups should not be used to pull external > > > signals, will they be sufficient to provide sufficient pullup with such > > > a light load? I am not even sure if you can enable the pullups on pin > > > used as outputs. Anyone have experience with this? > > > > > > -- > > > > > > Rick "rickman" Collins > > > > > > rick.collins@XYarius.com > > > Ignore the reply address. To email me use the above address with the XY > > > removed. > > > > > > Arius - A Signal Processing Solutions Company > > > Specializing in DSP and FPGA design URL http://www.arius.com > > > 4 King Ave 301-682-7772 Voice > > > Frederick, MD 21701-3110 301-682-7666 FAX > > -- > > Rick "rickman" Collins > > rick.collins@XYarius.com > Ignore the reply address. To email me use the above address with the XY > removed. > > Arius - A Signal Processing Solutions Company > Specializing in DSP and FPGA design URL http://www.arius.com > 4 King Ave 301-682-7772 Voice > Frederick, MD 21701-3110 301-682-7666 FAXArticle: 40607
Hi, for a new project I would like to use some older Xilinx FPGA´s (XC7272). Please dont tell me that I should use Virtex 2 parts because we do have excess inventory of the XC7272 FPGA´s. Im using XACT Step software and xchecker programming hardware. Simulation shows that application (decoder logic and fast statemachine)is working as expected. But, I cant download programming file into FPGA. My distributor tells me´that the FPGAs are defective. I believe they want to sell new FPGAs. Can anybody help me please? regards B. Braon / FPGA Consults ItalyArticle: 40608
Ciao, You could try to program the FPGAs with another PC. Maybe this would help. In the past I used ALtera EPM7128S devices which I programmed with a Bitblaster download cable.But: this was not possible with my notebook computer.I had to chnage the PC and it worked fine. Good Luck, MarkArticle: 40609
On Mon, 11 Mar 2002 15:39:53 -0500, rickman <spamgoeshere4@yahoo.com> wrote: >Jim Kearney wrote: >> >> "Tim" <tim@rockylogic.com.nooospam.com> wrote in message >> news:1015642799.2102.0.nnrp-12.9e9832fa@news.demon.co.uk... >> > I feel really, really stupid at having to ask this... >> > >> > What is the name of the connectors on the end of the wires >> > on Xilinx download cables? I mean the socket thingies >> > which fit over 0.025" posts - I think they crimp onto the >> > fairly thick wires. >> > >> > They may be in the DigiKey Catalog, but I cannot find >> > them ;) >> >> I had a need for these too, but Digi-key doesn't have quite the right parts. >> But I think you'll find what you want on pg. 215 of the Mouser catalog, e.g. >> part # 571-7874992 and its associated snap-in receptacles. >> >> Jim > >I haven't looked at the catalog, but this is like something like the >Molex or Amp pins for 0.1" sockets. They are nice connectors, but they >require you to buy a crimp tool that costs several hundred dollars. Of >course if this is not for production, you can get by with something >makeshift. But my experience is that you need the right crimp tool for >a reliable connection. Amp and Molex will even sell you an economy >tool, but they make no claim that it makes a good crimp. I've never had any problem when I solder the wire in the crimp channel then fold the tabs into place with a pair of needle nose pliers. BTW, if you have a 9 pin inline header on your target board, it works well to turn the flying lead adapter at the end of the Parallel Cable III around so that the flying lead ends are stationary on the Xilinx cable adapter and you then have a solid 9 pin plug to plug into the target system instead of 8 flying leads.Article: 40610
u should connect them to GND. Take a look in the (Altera) databook. Tells you exactly why you should do so. Information can be used for Lattice, Actel, Quicklogic, Triscend, Cypress,Atmel and Xilinx devices as well.Article: 40611
> I haven't looked at the catalog, but this is like something like the > Molex or Amp pins for 0.1" sockets. They are nice connectors, but they > require you to buy a crimp tool that costs several hundred dollars. Of > course if this is not for production, you can get by with something > makeshift. But my experience is that you need the right crimp tool for > a reliable connection. Amp and Molex will even sell you an economy > tool, but they make no claim that it makes a good crimp. For small quantities (I assumed from the post that the OP was building his own 'flying lead' cable), needle-nose pliers and a small bit of soldering makes for a perfectly reliable connection. JimArticle: 40612
Might as well pick one of the 2 higher level languages (VHDL or verilog). They can be used for simulation, or if you like, you can use a small part of the language and do synthesis only, the amount you'd like to learn is up to you. ABEL and the other PAL languages seem to be going the way of the gooney bird. If you're a programmer you'll appreciate the more powerful language constructs offered by the majors. "David Brown" <david_no_spam@no.spam.westcontrol.com> wrote in message news:<a6i15k$4qa$1@news.netpower.no>... > Hi, > > I am trying to convert an old project written in MachXL DSL to a more modern > Mach device. Since the current Lattice software does not support DSL, I am > going to have to convert to another design language. As far as I can see, > my choices are Verilog, VHDL and ABEL. I was recommended to learn either > Verilog or VHDL, preferably VHDL since that is more used here in Europe, but > no mention was made of ABEL. As far as I can see, however, ABEL is a much > simpler language, which should be more than sufficient for my needs. As far > as I have understood it from what I have read so far, both Verilog and VHDL > are simulation languages, and only a small part of the language is actually > synthesizable in hardware, whereas ABEL is designed as as hardware > description language. I have little experiance with PLD/FPGA design, apart > from a couple of projects several years ago. I will probably be doing a bit > more in the future, so it is useful to learn a portable language rather than > tying myself specifically to the one device family, but PLD/FPGA design will > only ever be a minor part of my job (mostly low-level microcontroller > programming, and some electronic design). I'd value any comments about what > language would be the best choice before I get too far down the wrong road.Article: 40613
That was a great idea, and after I read your message I tried it. But I got 95% the same number of LUTs. So still wondering. I'm thinking my test case may not have been a representative module as it has NO flops. "Tim" <tim@rockylogic.com.nooospam.com> wrote in message news:<1014989839.3662.1.nnrp-14.9e9832fa@news.demon.co.uk>... > You could use DC to compile to a Verilog netlist, then an FPGA-specific > compiler to reprocess the Verilog netlist into EDIF. This would > add another tool to your chain, but since you are using Xilinx 'map' > anyway, you are not really adding any more uncertainty. Whether > the FPGA-specific optimisations would survive all this... > > > Jay wrote > > I'm trying to pitch that my client use Synopsys Design Compiler > > instead of an FPGA specific synthesizer from another vendor since his > > Xilinx Vertex 2 FPGA is a proto for a standard cell part. The clock > > speed isn't important, verification of the tool flow and design > > database is. > > > > The problem I'm running into is that the Design Compiler output uses > > almost 200% the LUTs compared to the purpose built FPGA synthesizer. > > So the logic will no longer fit the proto board. > > > > Mini Example: > > Design compiler: 1760 LUTS > > FPGA synthesizer: 824 LUTS > > > > Design compiler synthesizes to cells like AND2, OR2, AND4, etc whereas > > the FPGA specific tool maps directly to special LUTs custom made for > > the logic required like LUT_AB5A and LUT_67FE, etc. Now I figured the > > Xilinx mapper would be smart enough to "map" the Design Compiler AND2, > > OR2, etc, into more compact LUT_ABCD and LUT_6534 type cells but just > > seems to be doing a 1 for one map with no optimization. > > > > It appears that Xilinx did not write the mapper optimization (option > > -oe) for the recent products Vertex E/2 an Spartan 2 in effect giving > > up support for Design Compiler. > > > > Can any one else comment on this? It seems crazy that I can't use the > > old man of sythesis (Design Compiler) at $100k seat anymore. > > > > BTW- Altera DOES still do map optimization on Design Compiler EDIF > > files.Article: 40614
xchecker wrote: > for a new project I would like to use some older Xilinx FPGA´s (XC7272). Please dont tell me that I should use Virtex 2 parts because we do have excess inventory of the XC7272 FPGA´s. > > Im using XACT Step software and xchecker programming hardware. Simulation shows that application (decoder logic and fast statemachine)is working as expected. But, I cant download programming file into FPGA. My distributor tells me´that the FPGAs are defective. I believe they want to sell new FPGAs. XC7272 is not really an FPGA. It is an old line of PALs/CPLDs which Xilinx bought in from (AFAIK) PlusLogic. Eventually replaced by the XC9500 parts. If the downnload signals look OK on the scope, start by checking whether the download software can read the XC7272 ID code (assuming this part has an ID code!). But if you do decide on an upgrade to a more modern part, the Virtex2 is probably up the challenge :-) Alternatively XC9572XL - a 3.3V part.Article: 40615
lsuser wrote > u should connect them to GND. Take a look in the (Altera) databook. Tells you exactly why you should do so. Information can be used for Lattice, Actel, Quicklogic, Triscend, Cypress,Atmel and Xilinx devices as well. After you have routed a few to testpoints :-) In practice, there is an engineering judgement in low pincount designs as to when enough ground is enough.Article: 40616
Jim Kearney wrote > > I feel really, really stupid at having to ask this... > > > > What is the name of the connectors on the end of the wires > > on Xilinx download cables? I mean the socket thingies > > which fit over 0.025" posts - I think they crimp onto the > > fairly thick wires. > > > > They may be in the DigiKey Catalog, but I cannot find > > them ;) > > I had a need for these too, but Digi-key doesn't have quite the right parts. > But I think you'll find what you want on pg. 215 of the Mouser catalog, e.g. > part # 571-7874992 and its associated snap-in receptacles. That is the one. Thanks for a smart answer to a less smart question. Following Zaphod: If I were any less hip, my bum would fall off.Article: 40617
On Mon, 11 Mar 2002 15:27:06 -0500, Theron Hicks <hicksthe@egr.msu.edu> wrote: >Isuser on drugs? I wish I could figure out how to kill file him. This is the same idiot that was trolling here a month ago, with the "all you need is 1 GAL for all designs" crap. You dont need to kill file him. Just ignore obvious trolls. Philip Philip Freidin FliptronicsArticle: 40618
It's on p. 53. It is written by someone named Jim Turley. Here is an excerpt: "I've noticed over the last few years that hardware design seems to parallel software design, just delayed by about a decade. All the virtues and vices that programmers discovered in the '80s are now being uncovered by hardware engineers. High-level languages? What a good idea-for hardware. Compilers? Gee, you mean we don't have to hand craft every single transistor? ... The hardware guys are just now catching on. ...Hardware WEENIES don't draw schematics any more. ..." Yes, it says exactly that. To start with, I find it unconscionable that a supposed professional, the author, and a supposed professional magazine would allow the use of name calling in an article. I find it offensive and arrogant that the author basically says that hardware engineering has finally "gotten a clue". The author, in my opinion, does not understand really why HDLs work today, as opposed to years ago, or even why compilers work for software today, as opposed to years ago. Though compilers have gotten much better of the past 20 years, why they were even usable in the first place is because hardware speeds increased, and memory/storage has also increased. That is the same reason HDLs work today. Gate speed has increased so much as well as available number of gates to make HDLs even plausible. I don't want this thread to turn into an HDL vs schematic/C vs assembly code...but the fact is, I don't believe this author knows what he's talking about to a great extent. Please get a copy of the article and read it for your self. The email address of the author is at the end of the article, if you feel compelled to tell him what you think of his article and views...or perhaps tell the magazine editor ;-) Regards, AustinArticle: 40619
Austin Franklin wrote: > ... Please get a copy of the article ... http://www.embedded.com/story/OEG20020221S0070 -- Phil HaysArticle: 40620
In article <3C8D0CA7.77DD536A@egr.msu.edu>,
Theron Hicks <hicksthe@egr.msu.edu> writes:
|> Hello,
|> I am trying to instantiate a startup module in a spartan2e design.
|> When I run the constraints editor I get the following message which
|> comes from the translation phase of the design.
|>
|> ERROR:NgdBuild:604 - logical block 'u0_startup' with type
|> 'startup_spartan2' is
|> unexpanded. Symbol 'startup_spartan2' is not supported in target
|> 'spartan2e'.
|>
|> I have tried just replacing the spartan2 with spartan2e and the result
|> is basicly unchanged.
|>
|> Where (specifically, I have already tried to find documentation myself)
|> can I get documentation on the startup module (especially for the
|> spartan2e parts)?
It is documented somewhere on the answers database, I stumbled over that a few
weeks ago. Simply use STARTBUF_VIRTEX and it works.
|> What happens if I don't instantiate a startup module? (Is one inferred
|> for me?)
You loose the global reset option and the the proper startup synchronized to your
system clock. If you don't need a global reset (since the bitstream already sets
your FFs right) or the sync'ed startup, it's not necessary.
--
Georg Acher, acher@in.tum.de
http://www.in.tum.de/~acher/
"Oh no, not again !" The bowl of petunias
Article: 40621Phil, Thanks for the kind words, but always, if I have offended anyone, I apologize. Even to trolls. Austin Philip Freidin wrote: > On Mon, 11 Mar 2002 15:27:06 -0500, Theron Hicks <hicksthe@egr.msu.edu> wrote: > >Isuser on drugs? I wish I could figure out how to kill file him. > > This is the same idiot that was trolling here a month ago, > with the "all you need is 1 GAL for all designs" crap. > > You dont need to kill file him. Just ignore obvious trolls. > > Philip > > Philip Freidin > FliptronicsArticle: 40622
OK, If anything that just keeps good hardware guys in business sorting out the mess created by the software types who don't have a clue about hardware constructs, timing, metastability etc. Those issues don't go away just because you do the design in an HDL. The best HDL designers still visualize their creations as hardware then code to create the hardware they envision. As fpr assembly coders being dinosaurs, ask any DSP software designer if he'd let you throw away the assembler, and dollars to donuts you'll at least spark some desire to clock you one. Phil Hays wrote: > Austin Franklin wrote: > > > ... Please get a copy of the article ... > > http://www.embedded.com/story/OEG20020221S0070 > > -- > Phil HaysArticle: 40623
In an ASIC, no, it shouldn't cause a problem, but in an FPGA where one group of flops is being reset at time zero, and the other is being reset 20nS later it could. The FPGA has special routing for the reset net, if you put logic in there, you may be off into the general purpose routing which is MUCH slower and higher skew. Since its arbitrary, why don't you just make them the same (positive or negative)? It's common to use a `define for the register always @(... clause so you can change this stuff late in the game easily. Regards shengyu_shen@hotmail.com (ssy) wrote in message news:<f4a5f64f.0203062312.420d9e9@posting.google.com>... > Hi everyone > > in my design, some module use high active reset, and other use low > active reset, and the global reset is low active, so all high active > reset is generate by pass global reset through an inverter, if this > will cause any problem?Article: 40624
If they are designated as inputs then wire them to their inactive states, maybe you'll pick up a few gates from logic reduction. Floating is bad, bad.... Regards dottavio@ised.it (Antonio) wrote in message news:<fb35ea96.0203102322.26755f30@posting.google.com>... > Using the cores there could be some pins that are not used in my > design, I would want to know if is better to let them be floating or > what else.
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