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can we implement SFI-4 interface in an FPGA ??? How many gates it will take ? Is there application notes ? Thanx !Article: 40701
"michael brown" <n5qmg@nospam.earthlink.net> wrote in message news:zGwj8.94983$dj3.3473465@typhoon.austin.rr.com... > > One of the reasons that "two wire" interfaces that are nominally IIC > > are given a different name is that they aren't fully compatible with > > the spec, even though they interwork in every practical way. > > > > Regards, > > Allan. > > That may be partially true, but the primary reason that other manufacturers > don't call their parts IIC compatible is that Philips would make them pay > royalties to do so. Pretty much whenever you hear about two-wire > interfaces, it's probably IIC compatible (more or less). > More or less - that's the key. Pay special attention to start and stop conditions - they seem pretty often messed up. It's a pity that most of the changes lose something of the original, pretty clever protocol. Tauno Voipio tauno voipio @ iki fiArticle: 40702
Kelvin Hsu wrote: > Hi, > > How would I know somebody has copied my files in Unix? > > -- > Best Regards, > ----------------------------------------------------------------- > Xu Qijun > Engineer > OKI Techno Centre (S) Pte Ltd > Tel: 770-7049 Fax: 779-1621 > Email: qijun@okigrp.com.sg I guess this isn't the right group for these type of questions. But, to answer your question: as a normal user you can't. Maybe su to root and view everyones history (if they didn't clear it). Or look at the logs of your ftp-daemon. Or maybe the system is compromised. Or ... -- To reach me by email, remove the obvious from my email-address.Article: 40703
On 12 Mar 2002 22:39:35 -0800, kindalin2002@yahoo.com (showbiz) wrote: >allan_herriman.hates.spam@agilent.com (Allan Herriman) wrote in message news:<3c870132.9726435@netnews.agilent.com>... >> On Wed, 06 Mar 2002 18:19:46 -0500, Greg Neff <gregeneff@yahoo.com> >> wrote: >> >> >On Wed, 06 Mar 2002 21:08:39 GMT, John_H <johnhandwork@mail.com> >> >wrote: >> > >> >I have not looked at the CEPT standard. We are using E1 physical >> >layer stuff for a non-telecom application. Does the CEPT standard >> >talk about mutual clock synchronization? If so, I would appreciate a >> >pointer to this standard. I though that E1/T1 systems were typically >> >clocked in a master/slave arrangement, or lived with slips. >> > >> > With regard to stability, I was thinking about the stability of the >> >democratic clock, due to multiple feedback paths to the multiple phase >> >error detectors on each PLL. >> > >> >>The references for stability... shouldn't they be contained in the >> >>ITU-T specifications regarding E1 reference timing? The clock >> >>distribution schemes, switchover conditions on signal loss, acceptable >> >>jitter transfer and tolerance are all part of the CEPT standard. Very >> >>constrained. >> >(snip) >> >> As the other posters have mentioned, a "democratic" approach to timing >> is unusual, and (to me) doesn't make sense. >> >> Regarding the ITU-T specifications, I think you should look at the >> SONET/SDH specs instead of the E1 ones. >> Try: ITU-T G.707 (SDH) and the G.810 series (SDH timing). >> Also GR-253 (SONET). >> >> Even the Network Time Protocol (RFC1305) that is used to synchronise >> time of day clocks on computers has a hierarchy of timing sources. >> But it might give you some ideas that will help you with your problem. >> http://www.ietf.org/rfc/rfc1305.txt >> >> Oh, you should probably look at the datasheets for chips that are >> designed for phone network timing, e.g. Zarlink (nee Mitel) MT90401 >> http://products.zarlink.com/partfinder/prodprofile.cgi?device=1127 >> or maybe this one from Semtech: >> http://www.semtech.com/products/sets.html >> >> Regards, >> Allan. > >I have two questions related to the timing soloutions you have >mentioned: > >1)I've found a similar chip from Agere systems which is TSWC01622. But >there is nothing more than a product brief on their website. >http://www.agere.com/netcom/docs/PB00144.pdf >I'll be grateful if someone provide me with more information (like a >complete datasheet)about it. > >2)According to MT90401 datasheet the two input references should have >the same frequency. In my application I want to switch between two >different clock rates so I can't feed both of them to the chip. After >any failure of references MT90401 enters a holdover mode(suppose the >failed clock frequency X). I WANNA KNOW if returning from holdover >mode to a diffrent clock rate Y is safe and slip free. I know the >manufacture can answer the question best but I thought you may know >the structure of such devices. If both inputs are a multiple of 8kHz, you could divide them both to this frequency and then apply them to the MT90401. If you can't manage that, you could always roll your own clock management circuit in an FPGA. (You may need an external analog PLL to get the jitter within limits, but that's dependent on your application.) Regards, Allan.Article: 40704
Hello! I'd like to implement a ROM in a Xilinx Virtex either by using a block SelectRAM or LUTs. Is there any difference concerning SEU (bit-flip due to heavy-ions etc.) resistance? Are LUTs more resistant or is the same technologie (area, speed) used as for SelectRAM. Thank you for your comments. Michael Please send any comments to my email, too.Article: 40705
Hi ! Can anyone tell whether the source code of DES implementation in Handel C is available publically or not. Thanks in advance. SaurabhArticle: 40706
when i design a project,i always use many,many eda tools(simulation/synthesis/P&R/check...). so i have to switch in eda tools,and copy some files(source file/edif/edn/sdf....etc). who have had some scripts(tcl/perl/batch/unix shell....) run from front to end so that i only run it ?that is,some switch will be finished by scripts automatic.it don't need me to intervene.in fact ,it is the same as batch(.bat) on Windows.can you share it ?Article: 40707
Zak smith <zakhama@sympatico.ca> wrote: > Do you have any data how many gates it take to implement the pointer > processor in FPGA ? > Do you have data about this design ? Can't you just run your OC48 design 4x faster? Hamish -- Hamish Moffatt VK3SB <hamish@debian.org> <hamish@cloud.net.au>Article: 40708
Hello, Do you know of any recent review/benchmark comparision of major synthesis tools for the FPGA? I'm interested in such a comparision between Synplify, LeonardoSpectrum and FPGA compiler. And is there any major perfromance difference between these tools when targetting different FPGAs from Xilinx and Altera? Best Regards ArashArticle: 40709
Eric, Try downloading the free demo from Hyperlynx. Try before you buy. Austin Eric Smith wrote: > Austin Lesea <austin.lesea@xilinx.com> writes: > > Run an IBIS simulation. > > Is there any not-too-insanely-expensive software that > can be used for this?Article: 40710
Eric, To make it easier, their site has changed around: http://www.hyperlynx.com/democontent.html Austin Eric Smith wrote: > Austin Lesea <austin.lesea@xilinx.com> writes: > > Run an IBIS simulation. > > Is there any not-too-insanely-expensive software that > can be used for this?Article: 40711
hi, Would anyone know if there are IP cores available for Baseline CDMA 2000 / IS-95 handset receiver ? Thanks, PrashantArticle: 40712
Hi. Xilinx tradionally publish only max values for the clock to out delays. I remember that there is an application note that say that the min clock to out value can be taken as 1/3 'rd of the max value (or 1/4 'th if you are a conservative person). Can someone point me to that application note ? I want to verify it. ThankX, Nahum.Article: 40713
As far as I know - you can't implement an XOR carry chain in the Xilinx devices (that's the scope of XST, right? Xilinx only) though Altera carry structers allow the greater flexibility. To do parity, you need to XOR the result from the previous stages' xor chain; this requires the ability to select either the carry or the invert of the carry. The carry invert isn't available without going external to the carry chain and totally blowing all performance gains. Maybe it's a good thing XST didn't infer the parity generator with carry chains! Kevin Brace wrote: > I will like to know if there is a way to infer a parity > generator that uses Virtex's carry-chains rather than LUTs? > The reason I am asking this question is because when I synthesize a > parity generator, XST uses LUTs rather than carry-chains even if "XOR > Collapsing" option is checked (enabled). > I will like to conserve valuable LUTs, and use carry-chains because > carry-chains are rarely used in my design. > Will I have to use Virtex specific primitives to do so, or is there a > way to do so without using Virtex specific primitives? > IF I have to use Virtex specific primitives, how do I do it? > Or is this problem XST's fault, and do other synthesis tools handle XOR > stuff differently than XST? > The parity generator here I am talking about is a one that generates the > parity of 36-inputs for PCI bus. > > Thanks, > > Kevin Brace (Don't respond to me directly, respond within the > newsgroup.)Article: 40714
______ ______ ______
clk10x _/ \______/ \______/
__ _____________ _____________ _____
toggle __X_____________X_____________X_____
_ _ _ _ _ _ _ _ _
clk35x_shift _/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_
______ _______________ ___________ __
togp ______X_______________X___________X__
________ ___________ _______________
togn ________X___________X_______________X
_ _ _
tog_diff ______/ \___________/ \___________/ \
___
samplep ______________________/ \__________
___
samplen ________/ \_______________________/
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
ddr_data X6X0X1X2X3X4X5X6X0X1X2X3X4X5X6X0X1X2X
You're right about the toggle period.
Though it's tough to show prop delays (the combinatorial tog_diff doesn't show a delay in
the diagram) it seems that the pulse that covers timeslot 3 and 4 in this phase shift
version of clk35x is independent of which clk35x transition you use to sample the
difference. You can apply the same timing diagram to the clk10x90deg signal with an
unshifted clk35x and get similar results but the timing analysis is up to you. Fun stuff!
Mark wrote:
> I think that with the toggling signals, they have a period of twice the clock period.
> It seems when using clk35x_p and clk35x_n, toggle35x_p and toggle35x_n can only resolve
> down to one clk35x resolution. The 90 degree phase shift sounds like one way to find a
> difference. I believe that I once saw an appnote that described using 90 deg phases to
> lock(?) onto an input signal.
>
> Now that you mention it, I do remember reading messages about clock skew and jitter in
> FPGAs. Also, several weeks ago, I looked into the Virtex-II skew/jitter when
> multiplying up the clock by 7x to the rate of 420 MHz.
Article: 40715Hi, I'm trying to find if there is a low cost Universal programmer for FPGAs. (Not exclusively using JTAG). If someone could help me i would be much obliged. Thanks in advance.Article: 40716
"Dionissis Efstathiou" <eyden@mhl.tuc.gr> schrieb im Newsbeitrag news:a6o6p7$q5f$1@ulysses.noc.ntua.gr... > Hi, > > I'm trying to find if there is a low cost Universal programmer for FPGAs. > (Not exclusively using JTAG). > If someone could help me i would be much obliged. Look at the Xilinx homepage->support->hardware. There you can find a schematic for the parallel-III cable, which allows you to do JTAG and Serial Slave downloads. -- MfG FalkArticle: 40717
John_H wrote: > There are techniques to develop a stable average frequency from a high > frequency reference using the 64us pulse as a correction. I'd suspect, > however, that the jitter information that would be inherent in the DPLL > could form visual patterns that detract from your true needes. > > In my opinion, good video needs good analog elements in key places like > this: timing. Nonsense. Look at video front-end (digitizer) chips for examples of all-digital video decoding. The Philips SAA7110 has been around for aeons, and the Bt848/878 are very common in PCI cards. Both use all digital circuitry to lock to the syncs and demodulate the colour info etc. Frank -- ------------------------------------------------------------------------ Frank A. Vorstenbosch <SPAM_ACCEPT="NONE"> Wimbledon, London SW19 frank-spam@kingswood-consulting-spam.co.ukArticle: 40718
>From the SAA7110 datasheet: 15 CLOCK SYSTEM 15.1 Clock generation circuit The internal CGC generates the system clocks LLC, LLC2 and the clock reference signal CREF. The internally generated LFCO (triangular waveform) is multiplied by four via the analog PLL (including phase detector, loop filter, VCO and frequency divider). The rectangular output signals have a 50% duty factor. Thanks for giving a fellow engineer the benefit of the doubt. I could swear that words like "triangular" and "analog" aren't quite digital elements. Frank Vorstenbosch wrote: > John_H wrote: > > > There are techniques to develop a stable average frequency from a high > > frequency reference using the 64us pulse as a correction. I'd suspect, > > however, that the jitter information that would be inherent in the DPLL > > could form visual patterns that detract from your true needes. > > > > In my opinion, good video needs good analog elements in key places like > > this: timing. > > Nonsense. Look at video front-end (digitizer) chips for examples of > all-digital video decoding. The Philips SAA7110 has been around for > aeons, and the Bt848/878 are very common in PCI cards. Both use all > digital circuitry to lock to the syncs and demodulate the colour info > etc. > > Frank > > -- > ------------------------------------------------------------------------ > Frank A. Vorstenbosch <SPAM_ACCEPT="NONE"> > Wimbledon, London SW19 frank-spam@kingswood-consulting-spam.co.ukArticle: 40719
John_H wrote: > From the SAA7110 datasheet: > > 15 CLOCK SYSTEM > 15.1 Clock generation circuit > The internal CGC generates the system clocks LLC, LLC2 > and the clock reference signal CREF. The internally > generated LFCO (triangular waveform) is multiplied by > four via the analog PLL (including phase detector, loop > filter, VCO and frequency divider). The rectangular output > signals have a 50% duty factor. > > > Thanks for giving a fellow engineer the benefit of the doubt. I could swear > that words like "triangular" and "analog" aren't quite digital elements. Oops! The Bt8x8's "UltraLock" is alleged to be all digital, though. Frank -- ------------------------------------------------------------------------ Frank A. Vorstenbosch <SPAM_ACCEPT="NONE"> Wimbledon, London SW19 frank-spam@kingswood-consulting-spam.co.ukArticle: 40720
I have seen other people using XST saying when Keep Hierarchy
option is checked, and if a tri-state buffer that ultimately connects to
a pin is located anywhere other than the top module (like in
instantiated submodules), things go wrong during MAP.
To verify if this happens to me, I synthesized my design (a PCI IP core
) which has tri-state buffers two submodules below the top module with
this Keep Hierarchy checked.
The result is that the synthesized design which normally has lots of
bi-directional ports (inout in Verilog) now has output ports instead.
Yes, I do understand that this problem can be worked around if I uncheck
Keep Hierarchy option, but since this Keep Hierarchy option exists in
XST, shouldn't my design synthesize correctly even if the Keep Hierarchy
option is checked?
From what I see this problem seems like a bug of XST, so I hope it gets
fixed in the next revision.
Kevin Brace
P.S. A Xilinx employee reading this posting, please forward this posting
to the XST development team.
Article: 40721
I am currently experiencing a problem with XST's Pack I/O
Registers into IOBs option.
The problem I am having is that XST duplicates OE FFs when I don't want
it to do so.
In my design (a PCI IP core), to control the Output Enable (OE) of
AD[31:0] and C/BE#[3:0], I use one FF for AD[31:0] and one FF for
C/BE#[3:0].
Some people might say the way I am handling the OE will prevent me from
merging those two OE FFs into IOB, and I understand that, and that is
what I want.
Yes, if I wanted the OE FFs to be merged into IOBs, I will manually
duplicate the OE FFs myself in my design (I used to do that.), but the
design decision I made needs only one OE FF for AD[31:0], and one OE FF
for C/BE#[3:0].
However, I do still need those output FFs for AD[31:0] and C/BE#[3:0] to
be merged into IOBs, and since IOBs don't have a feedback path, those
output FFs have to be duplicated, and must reside inside CLB.
So, when I synthesize my design with Pack I/O Registers into IOBs option
set to "True," XST duplicates the output FFs for AD[31:0] and C/BE#[3:0]
correctly so that it can be merged into IOBs.
But XST also duplicates AD[31:0] OE FF 32 times, and C/BE#[3:0] OE FF 4
times.
I don't appreciate XST overriding the design trade off I made in the
design, and do I have a way to prevent XST from duplicating the OE FF?
I am using ISE WebPACK 4.1WP3.0's XST (XST E.33), and Spartan-II XC2S150
is the target device.
I feel like this OE FF duplication thing should not happen, and hope
that the future version of XST will give its users an option to disable
OE FF duplication if the user doesn't want it.
Kevin Brace
P.S. A Xilinx employee reading this posting, please forward this posting
to the XST development team.
Article: 40722"Arash Salarian" <arash.salarian@epfl.ch> wrote in message news:3c8f4cb7$1@epflnews.epfl.ch... > Hello, > > Do you know of any recent review/benchmark comparision of major synthesis > tools for the FPGA? I'm interested in such a comparision between Synplify, > LeonardoSpectrum and FPGA compiler. And is there any major perfromance > difference between these tools when targetting different FPGAs from Xilinx > and Altera? > > Best Regards > Arash You will be hard pressed to find these comparisons, since the license agreements of these vendors say something close to "Licensee shall not .. disclose the results of any benchmarking of the SOFTWARE, or use such results for its own competing software development activities, without the prior written permission of Blah Blah." Don't blame me, I'm just the messenger! Simon Ramirez, Consultant Synchronous Design, Inc. Oviedo, FL USAArticle: 40723
Timmestein wrote:
>
> Hi,
>
> I'm fairly new to this kind of desinging circuitry. I've used VHDL at
> school to program some simple things, but what I want to do is the
> following.
>
> I want to connect my own circuitry (like a microcontroller or some other
> logic) to the PCI-bus of my computer. There are PCI interface ic's, but
> this also can be done using a fpga and an ip core from
> http://www.opencores.org . It's obvious I want to use the PCI-bridge core.
> This way my device keeps it's flexibility.
>
When I started developing my own PCI IP core, I had a similar
motivation like the one you have of wanting to connect something to my
computer, and PCI bus seemed like a way to go.
I guess I shouldn't be a nay-sayer, but I get the impression that if you
can use someone else's PCI IP core, you won't have to learn how PCI's
protocol works.
Just because someone claims that their PCI IP works doesn't mean that
you should totally trust that, and ultimately it will be your
responsibility to make sure the Opencores.org PCI IP core meets setup
timings (Which seems like it does according to their website.), and
doesn't violate PCI bus protocol.
> Can someone please help me with finding a right fpga (type and/or
> manufacturer) and how to program this device? Like the cable I have to use,
> the software for compiling the core and the software to get the code into
> the fpga.
Like the Opencores.org PCI project, I used an Insight
Electronics Spartan-II PCI Development Kit to make sure that my PCI IP
core actually works in a real computer.
http://208.129.228.206/solutions/kits/xilinx/spartan-iipci.html
The board alone without a license for Xilinx LogiCORE PCI PCI32 was only
$145, and even with two other related option boards and a parallel port
JTAG download cable, the whole thing cost me only about $370, but I was
told recently that Insight Electronics discontinued the board.
You can call the number on the website (Not sure if you can call a toll
free number from overseas, but it won't hurt to try.) to make sure if
that is true or not.
That person also said Insight Electronics supposedly is going to release
a new PCI board some time in the future.
A company called Nallatech has another Spartan-II based board that has
two Spartan-II XC2S150-5 on it, but I don't know how much it costs.
Probably not as cheap as Insight Electronics Spartan-II PCI Development
Kit.
I will guess that it will cost something like $500, but it can cost more
than that.
http://www.nallatech.com/products/dime_select/strathnuey/index.asp
Speaking of what FPGA you should use for PCI, I will say that it
should be whatever the fastest FPGA available at the time, but one thing
you should know is that most desktop computers still use 5V PCI, and
some newer FPGA no longer support 5V PCI.
For Xilinx FPGAs, Virtex/Spartan-II are the last FPGAs that support 5V
PCI without external voltage level conversion chips.
Newer FPGAs like Virtex-E/Virtex-II/Spartan-IIE support only 3.3V PCI,
and not 5V PCI by itself (Unless external voltage level conversion chips
are used.).
For Altera FPGAs, FLEX10KE/ACEX1K/APEX20K are the last FPGAs that
support 5V PCI.
Yes, there are other FPGA vendors out there, but very few people use
them, and often tools are not free or useless, so I will not discuss
them here.
Because I primarily use Xilinx software/device for my PCI IP core
development, my opinion is biased, but still I find Xilinx devices
easier to work with than Altera's devices when it comes to PCI.
So, for 5V PCI applications, I recommend Spartan-II because boards based
on it tends to be fairly low cost.
Assuming that you are poor, and cannot afford to pay for tools
like me, you should download a copy of free Xilinx ISE WebPACK 4.1.
I find Xilinx's ISE WebPACK 4.1 more generous and stable than Altera's
free Quartus II 2.0 Web Edition + LeonardoSpectrum-Altera when a Windows
98 PC is used.
When I say generous, Xilinx lets you use ModelSim XE-Starter for free
with some restrictions (Slows down quite a bit after 500 lines of code,
but will continue to run.), but Altera only offers a simple waveform
simulator.
A JTAG parallel cable should be fine to program a Configuration
PROM on the PCI card.
The necessary software (I believe it is now called iMPACT) comes with
ISE WebPACK 4.1.
> Maybe there's someone out there who's actually used thos core in one of hos
> projects who can help me.
>
> I am really new at this, but I'm always in to learn :).
> Hope someone can help me woth this. Any help is appreciated.
>
> Tim
Opencores.org PCI project forum should be able to help you.
http://www.opencores.org/forums/pci/
Going back to my opinion as a nay-sayer, the observations I made from
looking at their PCI IP core source code is that, do they (the authors)
expect other people to fix problems/update code with the way they wrote
it?
The level of abstraction of the code seems to me like something very
close to gate level, therefore it is pretty hard to follow what they are
doing in the IP core.
My guess is that they wrote it that way to get the PCI IP core to meet
7ns setup time, which the designer is not being careful, won't be met
even with Spartan-II (I had tons of problems with setup time several
months ago.), but after several months of struggle, I am now able to
meet 7ns setup time with easier to understand RTL level code after some
manual floorplanning.
If the Opencores.org PCI IP core is not buggy, that is fine, but if it
is, I will guess that it will be pretty hard for someone other than the
original authors to fix the problems.
Another problem you face in my opinion is that like almost any
other Europeans, you use VHDL, but the Opencores.org PCI IP core is
written in Verilog.
I personally don't understand why Europeans almost always use VHDL
rather than Verilog which is a simpler and easier to learn language, but
regardless, you will either have to learn Verilog, which shouldn't be a
big problem if you already know some VHDL, or you will have to do a
mixed language design.
To do a mixed language design, you will have to create a "blackbox" in
the Opencores.org PCI IP core for your backend application, and
synthesize it without the backend application.
Separately, you will synthesize the VHDL backend application likely
without I/O pads, and merge the two netlists (in ISE WebPACK, ".ngc"
files) after synthesis (In ISE WebPACK, NGDBUILD handles the merging of
netlist files.).
A few weeks ago, I did a Verilog/VHDL mixed language design with my PCI
IP core, where I merged a VHDL backend application netlist to my PCI IP
core netlist written in Verilog.
So, it is not impossible to do a mixed language design, but for a
beginner, it is probably easier to do the backend application design in
Verilog.
Kevin Brace (Don't respond to me directly, respond within the
newsgroup.)
Article: 40724The Ultralock is all digital but the application is different. By oversampling with a jitter-free clock, the analog data can be reformed to the precise timing based on a "virtual" recovered clock. What the person who started the thread appeared to be doing was generating a pixel clock directly - I may be wrong in my interpretation. If the design intent was not to produce a DPLL recovered clock output to somewhere else in the system then there are polyphase methods that can be used in sampling (decimation) or output (interpolation) of analog signals with low jitter clocks on the outside of the system. The "virtual" internal frequency that controls the polyphase filter isn't subject to the same kind of jitter issues that a DPLL clock output would generate. DDS techniques could be used to push jitter into the noise floor and get a true, clean DPLL clock output. The DDS system also costs a bit of extra cash and involves precision analog components (converters and filters) beyond the digital realm. Give ultralock a jittered clock and you'll compromise your results. Frank Vorstenbosch wrote: > Oops! The Bt8x8's "UltraLock" is alleged to be all digital, though.
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