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My mistake. I offered him some private coaching, if necessary in German...:-) Peter ========================= Peter Alfke wrote: > "F. Modderkolk" wrote: > > > Ok, I think I understand finally what you tried to tell me. I want to > > thank you for that, because I'm only a simple student trying to > > graduate. As a final solution, you suggest me to use an simple FPGA in > > combinaton of an DDS. > > Thanks again.Article: 40526
"Peter Ormsby" <faepete.deletethis@attbi.com> writes: (snip about WINE) >Any limitations that the Xilinx Windows software has under Windows will >still exist on WINE-on-Linux. Well, for limitations of the program itself, yes, but not necessarily OS limitations. While windows gives 2GB, and some server versions give 3GB, it would be possible for WINE to give 3.5GB. There may be other OS limitations that it could also get around. Definitely you won't get more than 4GB though. -- glenArticle: 40527
"Ryan Henderson" <hendersr@oit.edu> wrote in message news:newscache$vh4osg$xw9$1@phaze.fireserve.net... > What do you think the response would be if I wore a sandwich board at the > embedded systems conference that said > > HDL Designer > > Hire Me! > > > Just a thought > -Ryan Managers would probably tell you that they don't need any more HDLs designed.Article: 40528
Hello, This is a classic problem in the realm of FPGA to ASIC conversions. All or some subset of FC2 is included in Xilinx' FPGA Express that you get with the Xilinx tools. FC2 is based on DC and does not infer the Xilinx-specific technology. FC2, like DC, was designed to synthesize either the fastest run-time or smallest area for your input HDL code without being confined by a specific array of CLB's as in the Xilinx FPGA's. FC2 stumbles all over itself when it tries to fit its gates and registers into the Xilinx technology. The only two competitive HDL synthesizers for FPGA's are Mentor's/Exemplar's Leonardo and Synplify's Synplicity. Both use an inference engine of some sort to fit your HDL into the minimum possible Xilinx CLB's. In summary, use Synplicity or Mentor, I prefer the latter, to get the best fit into your FPGA then use DC to get the fastest runtime/minimum area ASIC design. You should also compare Mentor's ASIC synthesis to DC's ASIC synthesis as well to see if the cost of maintaining your DC seat is worth the $$$. However, if your primary goal is to keep the DC flow consistent then don't worry about how many LUTs/CLB's you get with FC2 and use a larger Xilinx part since your ultimate goal is to make an ASIC. By the way, Synopsys just announced dropping support for their FPGA Express tool altogether after vers. 3.7. They will continue to market FC2 however. Mark Momcilovich "Ansgar Bambynek" <a.bambynek_xxx_@avm.de> wrote in message news:<3c7f5a93$0$230$4d4ebb8e@businessnews.de.uu.net>... > Hi > > my experience with DC vs FC2 (fpga compiler II from Synopsys) is that the > results in terms of speed and area from dc are very poor compared to fc2. > This is probably true for other FPGA specific synthesizers like sinplicity, > ... > > Check with Synopsys if a dc license enables you to use fc2. > > Unfortunately fc2 uses other commands than dc, e.g. set_multicycle_path is > not available in fc2. > > I was told by Synopsys that there is a customer demand for reintegrating fc2 > into dc again so you can keep all your constraints and synthesis scripts and > just have to change the libs. I don't know if or when this will happen. > > HTH Ansgar > > -- > Attention reply address is invalid. > Please remove _xxx_ > Jay <kayrock66@yahoo.com> schrieb in im Newsbeitrag: > d049f91b.0202281030.206aeb6b@posting.google.com... > > I'm trying to pitch that my client use Synopsys Design Compiler > > instead of an FPGA specific synthesizer from another vendor since his > > Xilinx Vertex 2 FPGA is a proto for a standard cell part. The clock > > speed isn't important, verification of the tool flow and design > > database is. > > > > The problem I'm running into is that the Design Compiler output uses > > almost 200% the LUTs compared to the purpose built FPGA synthesizer. > > So the logic will no longer fit the proto board. > > > > Mini Example: > > Design compiler: 1760 LUTS > > FPGA synthesizer: 824 LUTS > > > > Design compiler synthesizes to cells like AND2, OR2, AND4, etc whereas > > the FPGA specific tool maps directly to special LUTs custom made for > > the logic required like LUT_AB5A and LUT_67FE, etc. Now I figured the > > Xilinx mapper would be smart enough to "map" the Design Compiler AND2, > > OR2, etc, into more compact LUT_ABCD and LUT_6534 type cells but just > > seems to be doing a 1 for one map with no optimization. > > > > It appears that Xilinx did not write the mapper optimization (option > > -oe) for the recent products Vertex E/2 an Spartan 2 in effect giving > > up support for Design Compiler. > > > > Can any one else comment on this? It seems crazy that I can't use the > > old man of sythesis (Design Compiler) at $100k seat anymore. > > > > BTW- Altera DOES still do map optimization on Design Compiler EDIF > > files.Article: 40529
Portable meant it was delivered as a stack of floppy disks. I'm pretty sure that was developed specifically for DOS. I still have that pile of diskettes around here somewhere. I do remember justifying a 286 to run the Xilinx software and getting away with it. Petter Gustad wrote: > > The first time I used XACT was on a 8MHz 8086, running MS-DOS 3.1. > > If this was developed on UNIX, the boys and girls at Xilinx sure > > knew a thing or two about writing portable code :-) > > That must have been long before me then. It must have been on a > SparcStation II in the early 1990's. > > Petter > -- > ________________________________________________________________________ > Petter Gustad 8'h2B | (~8'h2B) - Hamlet in Verilog http://gustad.comArticle: 40530
hello, just try to expirement little bit with the constraint i have IFD-->FD-->FD-->OFD i have set this constraint TIMESPEC TS_F0 = FROM FFS TO FFS 20ns; in the timing report. say that this constraint is met with 2 level of logics, taught should be 1 (or even 0) any explanation Thanks -- Posted via Mailgate.ORG Server - http://www.Mailgate.ORGArticle: 40531
IMHO if you're hoping to get a fair compensation package you should consider more traditional methods of seeking professional employment (e.g. head hunters, internet). Never fails to suprise me how much engineers undersell their own value. I remember a guy at Hughes arguing that we shouldn't get bonuses for invention because "it was our job". Ever hear a sales guy say he shouldn't get a commission for a sale because it was his job? Sheesh. "Ryan Henderson" <hendersr@oit.edu> wrote in message news:<newscache$vh4osg$xw9$1@phaze.fireserve.net>... > What do you think the response would be if I wore a sandwich board at the > embedded systems conference that said > > HDL Designer > > Hire Me! > > > Just a thought > -RyanArticle: 40532
In <3C89486E.AD66F5B6@andraka.com>, Ray Andraka wrote: > Portable meant it was delivered as a stack of floppy disks. I'm pretty > sure that was developed specifically for DOS. I still have that pile of > diskettes around here somewhere. I do remember justifying a 286 to run > the Xilinx software and getting away with it. > > Petter Gustad wrote: > >> > The first time I used XACT was on a 8MHz 8086, running MS-DOS 3.1. If >> > this was developed on UNIX, the boys and girls at Xilinx sure knew a >> > thing or two about writing portable code :-) >> >> That must have been long before me then. It must have been on a >> SparcStation II in the early 1990's. >> >> Petter >> -- >> ________________________________________________________________________ >> Petter Gustad 8'h2B | (~8'h2B) - Hamlet in Verilog http://gustad.com The current generation of Xilinx tools is unrelated to XACT. Xilinx bought a company (who's name escapes me now) in the mid-90s that had a place and route tool that is the ancestor of the current tools. My understanding is that the Xilinx tools are developed on Unix and then ported to Windows. The reason that the Xilinx tools run so well under wine is that they are really Unix programs, the only part of them that is Windows oriented are the GUIs, the underlying programs like map and par are clearly Unix programs.Article: 40533
"B. Joshua Rosen" <bjrosen@polybus.com> wrote in message news:pan.2002.03.08.19.49.59.237870.4736@polybus.com... > The current generation of Xilinx tools is unrelated to XACT. Xilinx > bought a company (who's name escapes me now) The company's name was NEOCAD > in the mid-90s that had a > place and route tool that is the ancestor of the current tools. My > understanding is that the Xilinx tools are developed on Unix and then > ported to Windows. The reason that the Xilinx tools run so well under > wine is that they are really Unix programs, the only part of them that is > Windows oriented are the GUIs, the underlying programs like map and par > are clearly Unix programs.Article: 40534
i generate single-port Ram of Vertix-II by coregen in ISE4.1.i find it only has one control signal WE .but i want to control read or write individual.how do i?Article: 40535
I feel really, really stupid at having to ask this... What is the name of the connectors on the end of the wires on Xilinx download cables? I mean the socket thingies which fit over 0.025" posts - I think they crimp onto the fairly thick wires. They may be in the DigiKey Catalog, but I cannot find them ;)Article: 40536
I could be very wrong. But thought will put my thoughts here. A PLL is a closed loop system. The phase error detector(PED) is a part of this loop. So only one phase error detector can be part of one PLL at a time. Let us say there are four E1 inputs to a system. I do not think, comparing the phase errors between these inputs (which will require 6 PEDs is of any use. Another thing that can be one is that phases of these are compared with that of a local oscillator using four PEDs. By this action, there is no PLL action here, just getting a comparison of the four inputs with respect to the local oscillator. Now if you were to make a selection of one of them from this then the local oscillator's frequecy stability and phase noise should be know and better than the minimum required clock stability. Once you have such an oscillator on board, at every node, then you need not worry about the synchronization. I thought the whole idea of central synchronisation was invented to avoid these high stability oscillators at every node, which can be (rather which are) very costly. Greg, As i am not sure if i understood the configuration and inputs to the several PEDs that you are talking about. So all the above words may be wrong. balaArticle: 40537
skldfb wrote: > i generate single-port Ram of Vertix-II by coregen in ISE4.1.i find it only has one control signal WE .but i want to control read or write individual.how do i? Use the EN ( enable pin ) it is the overriding control for read and write. When enabled, you always read. This is no problem, since the data out bus is separate from the data in bus. During write, you have three options: read the old data, read the new data, or leave the Dout bus unchanged. ( In Virtex you do not have this freedom, you always read the new data) What is it that you miss? Peter Alfke, Xilinx ApplicationsArticle: 40538
Thanks! i am glad to see your response! but i think that both read and write enable run simultaneity.the BlockRam is designed a table in my project.it will stored some data content.i will first check if it is in the BlockRam before writting a new data.that is,i need first read any data(from Data Out Bus) stored in the ram .if it is the same as the new data(from Data In Bus),and not write,or write. so i think the BlockRam don't meet me. am not i?Article: 40539
In fact,i am designing hash arithmetic(search table). can you help me?Article: 40540
If you are writing the data if it is not the same as what is in memory, and not writing if the new data matches what is in memory, then why not just write all the time. It would be far simpler. skldfb wrote: > Thanks! > i am glad to see your response! > but i think that both read and write enable run simultaneity.the BlockRam is designed a table in my project.it will > stored some data content.i will first check if it is in the BlockRam before writting a new data.that is,i need first read any data(from Data Out Bus) stored in the ram .if it is the same as the new data(from Data In Bus),and not write,or write. > so i think the BlockRam don't meet me. > am not i?Article: 40541
Allan Herriman wrote: > <snip> > > I always have pipelining turned off though. > > Regards, > Allan. How come ? Are there problems with it ?Article: 40542
"B. Joshua Rosen" <bjrosen@polybus.com> writes: > The current generation of Xilinx tools is unrelated to XACT. Xilinx > bought a company (who's name escapes me now) in the mid-90s that had a > place and route tool that is the ancestor of the current tools. My Thank you for the clarification. I was wrong when I assumed XACT was the ancestor of Alliance/ISE/etc. > understanding is that the Xilinx tools are developed on Unix and then > ported to Windows. The reason that the Xilinx tools run so well under This what I've heard to. Hence I was a little surprised that Xilinx is supporting the Windows version under WINE in the 4.2 release rather than porting their native UNIX (Solaris/HP-UX) version to Linux. Petter -- ________________________________________________________________________ Petter Gustad 8'h2B | (~8'h2B) - Hamlet in Verilog http://gustad.comArticle: 40543
ssy wrote: > Hi everyone > > I perform post syn simulation with modelsim5.5e, in my design , I some > module use high active reset, other use low active, so I need to > invert global reset signal(low active). > > but i find that the reset pass though an apex20ke_asynch_lcell, and in > the time zone that should got high value, it appear to be 1'bx. > > so I trace into apex20ke_asynch_lcell, and found the following > statements > > buf (icascin, cascin); > data=(long string...); && icascin; > and (combout, data, 'b1) ; > > in this apex20ke_asynch_lcell that act as inverter, the cascin is not > connected, so it must be an 1'bz, so I can not got an high active > reset signal on combout. > > why? What does the instantiation of the ...lcell look like in the simulation netlist ? What does the model for it look like ?Article: 40544
In <87y9h2w2rr.fsf@filestore.home.gustad.com>, Petter Gustad wrote: > "B. Joshua Rosen" <bjrosen@polybus.com> writes: > >> The current generation of Xilinx tools is unrelated to XACT. Xilinx >> bought a company (who's name escapes me now) in the mid-90s that had a >> place and route tool that is the ancestor of the current tools. My > > Thank you for the clarification. I was wrong when I assumed XACT was the > ancestor of Alliance/ISE/etc. > >> understanding is that the Xilinx tools are developed on Unix and then >> ported to Windows. The reason that the Xilinx tools run so well under > > This what I've heard to. Hence I was a little surprised that Xilinx is > supporting the Windows version under WINE in the 4.2 release rather than > porting their native UNIX (Solaris/HP-UX) version to Linux. > > Petter It's the GUI part of the product that they needed Wine for. The Xilinx tools have been running for years under wine so all they had to do was package them up and announce that they are supporting the Linux environment. I read a mention somewhere, either here or in the wine group, that they intend to have a fully native version next year. The GUIs are written using a tool that puts out both Windows and Unix code, I think they are waiting for that tool to support Linux.Article: 40545
SInce your return address is not valid, please send me a private email and we can discuss this. skldfb wrote: > In fact,i am designing hash arithmetic(search table). > can you help me?Article: 40546
Probably because he is doing his designs with enough attention to detail that turning it on will screw up his design. It is fine for medium performance, but at the high end of the chip's capability automatic pipelining is no match for a carefully executed design. BTW, tight control not only buys performance, it also buys lower power consumption, higher density, faster PAR times and more consistent results. Added together, and combined with hierarchical design and design for reuse, these advantages far outweigh the little bit of extra effort needed. Rick Filipkiewicz wrote: > Allan Herriman wrote: > > > <snip> > > > > > I always have pipelining turned off though. > > > > Regards, > > Allan. > > How come ? Are there problems with it ?Article: 40547
any input here!!! -- Posted via Mailgate.ORG Server - http://www.Mailgate.ORGArticle: 40548
This is really weird. I instantiated a BUFGSR and now in the ngdbuild phase (of latest Webpack for SpartanII) I get ERROR:NgdBuild:455 - logical net 'bypas3_OBUF' has multiple drivers ERROR:NgdBuild:462 - input pad net 'bypas3_OBUF' drives multiple buffers ERROR:NgdBuild:466 - input pad net 'bypas3_OBUF' has illegal connection Now here is ALL that I do with that output. assign bypas3 = 0; I also had the errors with some other random signal that was working quite happily before I introduced BUFGSR. I've had BUFGSR it in and out a few times and sure that is causing the problem. Anybody from Xilinx listening ? JonArticle: 40549
Are you talking about the IDC (Insulation Displacement Connection) Socket Connectors? http://info.digikey.com/T021/V5/016-017.pdf Jeff Stout Tim <tim@rockylogic.com.nooospam.com> wrote in message news:1015642799.2102.0.nnrp-12.9e9832fa@news.demon.co.uk... > I feel really, really stupid at having to ask this... > > What is the name of the connectors on the end of the wires > on Xilinx download cables? I mean the socket thingies > which fit over 0.025" posts - I think they crimp onto the > fairly thick wires. > > They may be in the DigiKey Catalog, but I cannot find > them ;) > > > > >
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Compare FPGA features and resources
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