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I want to create pulses with a frequency between 100kHz and 300 kHz. I want to create as many as posible frequencies between them. So, the clockfrequency must be at least 300 MHz to get a good resolution. I know it is possible to create it in DSP and FPGA. Because I'm new to this area, I would like to know your opinion, witch device I can use. What's better, DSP or FPGA? and witch FPGA? Thanks for now, F. ModderkolkArticle: 40376
Hi, I am using asynchronous FIFOs at the input stage of each core in the top core.But when I try to synthesize the whole core(top module all the individual cores) in xilinxise4.1i,interestingly I m getting postoptimization report showing nothing about clocks used in the core.Can anybody explain me why it is happening like that??.I will be waiting for ur reply. Thanks in advance, Best Regards - satya "Ken Mac" <aeu96186@yahoo.co.uk> wrote in message news:<a622lu$acl$1@dennis.cc.strath.ac.uk>... > I can wholeheartedly agree with the asynchronous FIFO statement - see the > thread "stuck in state in Spartan-II!" for some convincing evidence! > > Ken > > > It is allowed, but having less clock domains is always good. Since virtex > > has 4 global clock nets, this is no problem. When transfering datas > between > > these clock domains, do it clean, means by use of asynchronous FIFOs or > > simmilar proofen methods.Article: 40377
Nicholas Weaver wrote: > In article <3C85B110.F0FC60DE@yahoo.com>, > rickman <spamgoeshere4@yahoo.com> wrote: > > >what is special about V2Pro? Is this the V2 chip with on board PPC or > >other screaming CPU? > > 0-4 PowerPC cores (32b, integer only, 5 stage pipeline, up to 300 > MHz), with close ties into the BlockRAMs (can use the BlockRAMS for > I/D memories). Single cycle 16 bit MACs, full 32x32 hardware > multiplier. > > 4-16 (depending) 3 Gbit serial I/O channels. > > The processor cores aren't that impressive (considering this is a .13 > micron, 9 layer copper process, hell, .25 uM synthesized standard cell > sparc run at 130), but the integration looks potentially cool. > > -- > Nicholas C. Weaver nweaver@cs.berkeley.edu <moan on> Why oh why was it the PPC and not one of the 2 big players in embedded CPUs - Arm or MIPS. The embedded system s/w tools for these to CPU families are AFAIK far more advance (o.k. there's a bit of a trumpet tootle here). In particular, since `A' has Arm for Excalibur, why not MIPS ? <moan off>Article: 40378
Kevin Brace wrote: > > Not only that, in QII 1.1, NativeLink with LS-Altera (2001.1a_28) didn't > even start (crashed at Quartus_cmp.exe), and I suspect lack of testing > for the crash. I wonder how many people use Nativelink? I'm sure it's not a high priority for testing, although this isn't good, they should take it out rather than have it and it doesn't work. > Having seen these software problems, it is not surprising to me > that no wonder Altera has only 10% of a highend FPGA market, and rest of > 90% belongs to Xilinx. I'm surprised at this figure. Where did you get it, Xilinx marketing literature? > I read some time ago on EE Times that much of the reason customers > choose Virtex instead of APEX20K several years ago is because the > quality of Quartus wasn't as good as Xilinx's software offering at the > time. What, you mean when Altera had just brought Quartus out some people chose Virtex because the (mature for a year or two) Xilinx tools were more stable. This is stating the obvious. When Xilinx bring out their next big release of design software I'm sure the same thing will happen only the other way. > To me, software stability seems to be Altera's weakest point even now. > I believe my past criticisms of Altera, and the complaints I > made here are fairly valid ones, from a Xilinx ISE WebPACK user's point > of view, because it seem like Altera has lost so many users to Xilinx > that the only way it can bring them back will be to listen to customer > complaints, and fix the problems. > If they don't, they will likely keep loosing market share to Xilinx, and > I personally don't like to see Xilinx becoming too dominant (It is > always good to have a strong No. 2.). I've been using Quartus I/II for over a year on two Win98 machines and haven't had one crash, but I'm very careful about what gets loaded on the two machines. Both companies do some things well and some things not so well. Try a search in this newsgroup for the message by Jesse Kempa dated the 27th Feb in the thread on Xilinx's microblaze for an example. Nial.Article: 40379
On 6 Mar 2002 01:38:19 -0800, frankmotje@hotmail.com (F. Modderkolk) wrote: >I want to create pulses with a frequency between 100kHz and 300 kHz. I >want to create as many as posible frequencies between them. So, the >clockfrequency must be at least 300 MHz to get a good resolution. I >know it is possible to create it in DSP and FPGA. Because I'm new to >this area, I would like to know your opinion, witch device I can use. >What's better, DSP or FPGA? and witch FPGA? Hi Frank, You might like to consider a DDS chip, such as one of the ones from Analog devices, http://www.analog.com/technology/dataConverters/designTools/selectionGuides/dds.html BTW, you don't need a 300MHz clock to get fine frequency resolution in the 100 to 300kHz range. Depending on your spectral purity requirements (and the amount of output filtering you can afford) you may only need 1MHz or so. Regards, Allan.Article: 40380
Linux splits up the 32bit-address space into 2 parts, one userspace ( 3Gig) , one kernel (1Gig). So the absolute maxium memory that can be used by a linux userspace process is 3Gig, but ofcourse the c-library maps in things like shared libraries, .text, .data , and stack (or stacks for multithreaded programms ) in that address. So the memory available for malloc() is less, probablbly somewhere between 2 and 2.5 Gig depending on the type of allocation that malloc uses ( mmapped for large memory requests come from a different place in the address space than normal SBRK allocation). So unless you specialy fine tune, the linux kernel (by moving the 0xc0000000 kernel start to something higher, to winn some 512 mega bytes or so) and the c-librarys way of allocating memory and placing shared libraries you probably stuck with the 2Gig limit. The large memory extention (upto 64Gig physical memory) will allow you to have more processes into memory than would fit in a 4Gig address space. You could think of this as swapping to RAM, instead of swapping to disk, it has cost but is way faster than disk-swapping. But unlike the tools are specialy designed to deal with the memory limit (you never going to get more than 4Gig linear memory on a 32bit machine) you will have to move to a 64bit pladform like an alpha or maybe upcomming ia64 or AMD x86-64 (but that will needed porting of the tools also, cause 64bit pointers don't fit into a 32bit int :-). - Erwin Austin Lesea wrote: > I have heard from some folks: > > That even with Linux on the PC platform, that 2 Gbytes is the limit. There > are people looking into why this is. Stay tuned for the answer. This may be > related to the hardware they are using, or the build of Linux.... > > Austin > > Austin Lesea wrote: > > >>We have Linux support now.....nice low cost way to break out of the 2Gbyte >>limit of Windows on PC platforms. Dell supports a 4Gbyte memory, that >>could be used by Linux. >> >> http://www.xilinx.com/prs_rls/software/0225_Em_Linux.html >> >>Austin >> >>M Schreiber wrote: >> >> >>>all, >>> Has anybody found a good method for implementing designs using the >>>Xilinx 4.1 ISE (under windows) that require more than 2GB of memory >>>for the place and route? I have read that Xilinx now supports their >>>tools running Linux (using WINE). Does this new method allow users to >>>exceed the 2GB limitations or is this a function of application >>>executable? We are looking to complete an upcoming design that may >>>require a Virtex 2 (xc2v8000) and xilinx recommends that you need at >>>least 3 GB of memory for place and route. What are most people doing >>>to overcome this? Are there any relatively cheap unix based machines >>>($<10,000) that can accomplish this? Any recommendations would be >>>greatly appreciated. >>>Thanks in Advance, >>> Mike Schreiber >>> hardware engineer >>> >Article: 40381
I need a digital device in my power supply to switch 6 fet's on and off. The device needs to generate a frequency from the supplied voltage. If the voltage drops, the switching frequency also has to drop and when the voltage rises the frequency has to rise. This way I want to control my output current. the switching frequency of the fet must be between the 100 kHZ and the 300 kHz. To get a good resolution in the different frequencies I want to create, my clock needs at least 300 MHz. The preference is a higher frequency of the clock, because then I can create more switching frequencies so my output control gets better. To create a solutiontion for my problem, I want to use an DSP or FPGA. I don't know what's the best solution. I also have to remind the costs, they aren't allowed to get to high. Because I don't have anything to program the device I also have to buy that. What do you suggest me to use. DSP or FPGA, and witch one? Thanks!Article: 40382
Hi all, I have just got a requirement for a phase shiftable square wave, for which a Virtex-II DCM looks ideal. However, I don't need the rest of the device - or the wacky packages the seem to come in... Any plans for a standalone DCM product (in an SOIC package :-)? Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt, Solihull, UK http://www.trw.com/conektArticle: 40383
You'll have to explain further, because to me this all sounds like I don't understand your design choice. Are you planning some complex digital control loops or something? If not aren't you just describing a voltage/frequency convertor? Are you sure you need 1000th Hz resolution? Aren't variations in your fet switching time likely to be greater? Why not use a much lower system clock? Couldn't a single chip VtoF chip do the job? "F. Modderkolk" <frankmotje@hotmail.com> wrote in message news:82eb64d2.0203060324.3b54c594@posting.google.com... > I need a digital device in my power supply to switch 6 fet's on and > off. The device needs to generate a frequency from the supplied > voltage. If the voltage drops, the switching frequency also has to > drop and when the voltage rises the frequency has to rise. This way I > want to control my output current. the switching frequency of the fet > must be between the 100 kHZ and the 300 kHz. To get a good resolution > in the different frequencies I want to create, my clock needs at least > 300 MHz. The preference is a higher frequency of the clock, because > then I can create more switching frequencies so my output control gets > better. > To create a solutiontion for my problem, I want to use an DSP or FPGA. > I don't know what's the best solution. I also have to remind the > costs, they aren't allowed to get to high. Because I don't have > anything to program the device I also have to buy that. What do you > suggest me to use. DSP or FPGA, and witch one? > > Thanks!Article: 40384
Austin Lesea <austin.lesea@xilinx.com> wrote: > We have Linux support now.....nice low cost way to break out of the 2Gbyte Actually, you seem to support running the tools on Wine, which has been said to work for quite a while now. Wine might be emulating the memory models of Windows, so the same memory limit would apply. Hamish -- Hamish Moffatt VK3SB <hamish@debian.org> <hamish@cloud.net.au>Article: 40385
Leon Qin wrote:
> Altera says that QuartusII 2.0 working with Synplify 7.1 ,but I can
> only found ver 7.03 on SYNPLICITY website for download.
>
Leon,
Presently Synplicity has Synplify 7.1 Beta 2 out on the block with
certain designers evaluating it. I don't think it's available to the
general public yet. A quick telephone call to your friendly Synplicity
representative should clear this up for YOU.
Good luck and HTH.
Simon Ramirez, Consultant
Synchronous Design, Inc.
Oviedo, FL USA
Article: 40386Hi! > The best solution is to move to 64-bit processors: Sun, IBM and HP (and > some others) offer 64-bit workstations now, and there are a lot of EDA > tools available (including all Xilinx tools). This is also a pretty > expensive solution: workstations are much more expensive than PCs > (probably slower nowaday), and EDA S/W for Unix is usually much more > expensive than the same S/W for Windows (not familiar with Linux > pricing). > > Right now, we are eagerly waiting for the AMD Hammer - this appears to > be the perfect solution for us Windows users who are trying to build big > FPGAs. This is the one solution. Use 64-bit pointers. Available in Linux nowadays, upcoming for Windows in the future (but perhaps only in special versions). Or on Workstations. Another idea would be to use a cluster for P&R. So, therefore P&R must be done for some independant and seperabel parts. I don't know how P&R software works and I'm afraid, it always needs the whole memory region, but if smart programmers find a way to split P&R into several standalone processes with only few communication, the easiest solution is a cluster. On machines with more than 3GB RAM each process itself can use 3GB. Several processes so can use the whole memory. So, it isn't even necessary to distribute the processes to numerous PCs. Linux is used very often for clusters, look for Mosix or Beowulf. In an office with several FPGA designers all their PCs can be equiped with e.g. Mosix and if one of them needs to do a P&R cycle, all PCs work together. The priority system in Linux will do the rest, so all other workers don't recognize a lot of the heavy load on their machine, because local processes get fast reaction. "Fork and forget". Use more than one process for P&R and the rest is done by the OS and the cluster Software. Advantage: - each PC can be a "normal" one with a rational amount of RAM and a not too expensive processor - enormous speed up of P&R - we will get native Linux tools :-) Or, why should your processor wait for your next keypress running at 2GHz? ;-) Bye HansiArticle: 40387
Hi all, i want to send on fiber a digital pattern of approximately 50 bits with Tbit = 40ns (25MHz transmission clock). First question : NRZ or Manchester code ? Second question: UART and Manchester decoders in FPGA often use 16x oversampling to sample at mid-bit of data cell. This is impossible for me. In the design at http://www.xilinx.com/xcell/xl17/xl17-30.pdf we have a 8x oversampling manchester decoder but with my flex (Altera ACEX 1K) is very difficult to have a single global clock at 200MHz for all. Exist different ways to realize a good sampling with a low frequency ? Thanks. -- Roberto Capobianco Consorzio RFX - CNR di Padova C.so Stati Uniti, 4 35127 - Camin (PD) email: capobianco@igi.pd.cnr.it web: www.igi.pd.cnr.it tel.: +39-049-8295048 fax: +39-049-8700718Article: 40388
On 6 Mar 2002 03:24:26 -0800, frankmotje@hotmail.com (F. Modderkolk) wrote: >I need a digital device in my power supply to switch 6 fet's on and >off. The device needs to generate a frequency from the supplied >voltage. If the voltage drops, the switching frequency also has to >drop and when the voltage rises the frequency has to rise. This way I >want to control my output current. the switching frequency of the fet >must be between the 100 kHZ and the 300 kHz. To get a good resolution >in the different frequencies I want to create, my clock needs at least >300 MHz. The preference is a higher frequency of the clock, because >then I can create more switching frequencies so my output control gets >better. >To create a solutiontion for my problem, I want to use an DSP or FPGA. >I don't know what's the best solution. I also have to remind the >costs, they aren't allowed to get to high. Because I don't have >anything to program the device I also have to buy that. What do you >suggest me to use. DSP or FPGA, and witch one? I think the best solution in this case is analog. Look at the Unitrode (uh, TI) web site: http://focus.ti.com/docs/browse/productnavigation.jhtml?familyId=431&tfsection=products&templateId=2 BTW, Vicor are likely to have patents on what you are doing. (Assuming you're doing what I think you're doing.) Regards, Allan.Article: 40389
If you need the 300 MHz resolution, you won't get it with a DSP. You can do it with a very small FPGA, or even a CPLD. What you want is a direct digital synthesis, which is little more than an accumulator with a fixed increment (the increment value is changed to set the frequency). The output is take from the msb of the accumulator for a square wave, more bits if you want a phase angle to use in generating some other wave shape. The master clock sets the maximum jitter, the number of bits sets the resolution. The output frequency is F0= Fclk * N/(2^k) where k is the number of bits, N is the increment value, and Fclk is your master clock frequency. If jitter is an issue, you can use several of the MSBs to create a pahse angle then use that to generate a waveform that can be filtered to reduce the jitter. You probably don't need a 300 MHz clock. "F. Modderkolk" wrote: > I want to create pulses with a frequency between 100kHz and 300 kHz. I > want to create as many as posible frequencies between them. So, the > clockfrequency must be at least 300 MHz to get a good resolution. I > know it is possible to create it in DSP and FPGA. Because I'm new to > this area, I would like to know your opinion, witch device I can use. > What's better, DSP or FPGA? and witch FPGA? > > Thanks for now, > F. ModderkolkArticle: 40390
See my post to your previous post. Knowing now what you are doing, I am sure you can get away with a much slower clock. Jitter is not likely to be much of a problem in this application. If, for example, you use a 10 MHz clock and a 32 bit accumulator you get a frequency resolution of 0.002 Hz with jitter no greater than 100ns (1 cycle of the master clock). Your master clock determines the amount of jitter and the maximum output frequency (Fclk/2). Resolution is determined just by the number of bits. "F. Modderkolk" wrote: > I need a digital device in my power supply to switch 6 fet's on and > off. The device needs to generate a frequency from the supplied > voltage. If the voltage drops, the switching frequency also has to > drop and when the voltage rises the frequency has to rise. This way I > want to control my output current. the switching frequency of the fet > must be between the 100 kHZ and the 300 kHz. To get a good resolution > in the different frequencies I want to create, my clock needs at least > 300 MHz. The preference is a higher frequency of the clock, because > then I can create more switching frequencies so my output control gets > better. > To create a solutiontion for my problem, I want to use an DSP or FPGA. > I don't know what's the best solution. I also have to remind the > costs, they aren't allowed to get to high. Because I don't have > anything to program the device I also have to buy that. What do you > suggest me to use. DSP or FPGA, and witch one? > > Thanks!Article: 40391
It sounds like we are all barking up the wrong tree. The solution is not to go to more and more memory...There is something to be said about using low cost PCs...instead, Xilinx needs to get the modular flow working so that one can truely partition a design and run each partition through the entire process, including place and route. The individual completed parts can then be stitched together. Until the modular flow is working though, we are stuck with the memory limits of the machines we work on. Johann Glaser wrote: > Hi! > > > The best solution is to move to 64-bit processors: Sun, IBM and HP (and > > some others) offer 64-bit workstations now, and there are a lot of EDA > > tools available (including all Xilinx tools). This is also a pretty > > expensive solution: workstations are much more expensive than PCs > > (probably slower nowaday), and EDA S/W for Unix is usually much more > > expensive than the same S/W for Windows (not familiar with Linux > > pricing). > > > > Right now, we are eagerly waiting for the AMD Hammer - this appears to > > be the perfect solution for us Windows users who are trying to build big > > FPGAs. > > This is the one solution. Use 64-bit pointers. Available in Linux > nowadays, upcoming for Windows in the future (but perhaps only in special > versions). Or on Workstations. > > Another idea would be to use a cluster for P&R. So, therefore P&R must be > done for some independant and seperabel parts. I don't know how P&R > software works and I'm afraid, it always needs the whole memory region, > but if smart programmers find a way to split P&R into several standalone > processes with only few communication, the easiest solution is a cluster. > > On machines with more than 3GB RAM each process itself can use 3GB. > Several processes so can use the whole memory. So, it isn't even necessary > to distribute the processes to numerous PCs. > > Linux is used very often for clusters, look for Mosix or Beowulf. In an > office with several FPGA designers all their PCs can be equiped with e.g. > Mosix and if one of them needs to do a P&R cycle, all PCs work together. > The priority system in Linux will do the rest, so all other workers don't > recognize a lot of the heavy load on their machine, because local > processes get fast reaction. > > "Fork and forget". Use more than one process for P&R and the rest is done > by the OS and the cluster Software. > > Advantage: > - each PC can be a "normal" one with a rational amount of RAM and a not > too expensive processor > - enormous speed up of P&R > - we will get native Linux tools :-) > > Or, why should your processor wait for your next keypress running at > 2GHz? ;-) > > Bye > HansiArticle: 40392
mschreiber75@yahoo.com (M Schreiber) writes: > to overcome this? Are there any relatively cheap unix based machines > ($<10,000) that can accomplish this? Any recommendations would be A SUN Blade 1000 costs ca. $10k with a single GigaByte memory if memory serves me right. Under Solaris you can run multiple PAR jobs in parallel using the -m option in PAR. This option is not available under Windows. Petter -- ________________________________________________________________________ Petter Gustad 8'h2B | (~8'h2B) - Hamlet in Verilog http://gustad.comArticle: 40393
It is basically V2 with high speed (3+ GB) serial I/O and power PC's embedded. I think the speeds are a bit faster as well. The part I am most interested in is the high speed serial I/O rickman wrote: > Jan Gray wrote: > > > > See www.xilinx.com/virtex2pro . > > > > Congratulations to Xilinx on another blockbuster achievement. It's a bit of > > a cliche, but the arrival of V2Pro and the Altera Excallibur family marks a > > huge turning point for the programmable logic industry. Assuming they are > > priced competitively, I think these new devices, and the forthcoming cores > > libraries and system builder tools that will accompany them, will prove > > irresistable to nearly all embedded systems designers -- so that (say) three > > years from now there will be "tons" of programmable logic in all but the > > most cost constrained new designs. It's the full employment act for FPGA > > designers! :-) > > > > The debut of these parts is also exciting because it represents the > > continued "democratization" of cutting edge technologies. You don't need a > > "million unit order" to get access to fast embedded processors, fast logic, > > fast embedded RAMs, fast serial links, clock management, a rich cores > > library, etc. > > > > As for V2Pro, gigabit links and PowerPCs aside, I applaud the extra generous > > helpings of BRAM provided in these new devices. > > > > I have posted some early news links and commentary, including a small table > > comparing V2 and V2Pro devices, at www.fpgacpu.org/#020304. > > > > Jan Gray > > Gray Research LLC > > Can anyone tell me (without making me visit yet another web site today) > what is special about V2Pro? Is this the V2 chip with on board PPC or > other screaming CPU? > > -- > > Rick "rickman" Collins > > rick.collins@XYarius.com > Ignore the reply address. To email me use the above address with the XY > removed. > > Arius - A Signal Processing Solutions Company > Specializing in DSP and FPGA design URL http://www.arius.com > 4 King Ave 301-682-7772 Voice > Frederick, MD 21701-3110 301-682-7666 FAXArticle: 40394
I wrote the answers between the lines :) "Paul" <nospam@nospamplease.com> wrote in message news:<rjnh8.45999$R16.6385438@news11-gui.server.ntli.net>... > You'll have to explain further, because to me this all sounds like I don't > understand your design choice. > > Are you planning some complex digital control loops or something? Yes, when I change the load at the output of the power supply, the expected current drops or rises. As a result my output voltage drops or rise. By chanching the switching frequency, I can deliver more power at the output. I want the output-voltage to be constant. > > If not aren't you just describing a voltage/frequency convertor? It's a kind of a voltage/frequency converter only there is no straight relation, thats why I want to use a DSP or FPGA. I also want to switch the fets with an delay of 30º in one period. > > Are you sure you need 1000th Hz resolution? Aren't variations in your fet > switching time likely to be greater? No I really need that resolution, because between two different frequencies with a clock of 300MHz is a step of 0.2A. So that's already quit high, but acceptable. A lower clock is therefor no option. > Why not use a much lower system clock? > > Couldn't a single chip VtoF chip do the job? > > "F. Modderkolk" <frankmotje@hotmail.com> wrote in message > news:82eb64d2.0203060324.3b54c594@posting.google.com... > > I need a digital device in my power supply to switch 6 fet's on and > > off. The device needs to generate a frequency from the supplied > > voltage. If the voltage drops, the switching frequency also has to > > drop and when the voltage rises the frequency has to rise. This way I > > want to control my output current. the switching frequency of the fet > > must be between the 100 kHZ and the 300 kHz. To get a good resolution > > in the different frequencies I want to create, my clock needs at least > > 300 MHz. The preference is a higher frequency of the clock, because > > then I can create more switching frequencies so my output control gets > > better. > > To create a solutiontion for my problem, I want to use an DSP or FPGA. > > I don't know what's the best solution. I also have to remind the > > costs, they aren't allowed to get to high. Because I don't have > > anything to program the device I also have to buy that. What do you > > suggest me to use. DSP or FPGA, and witch one? > > > > Thanks!Article: 40395
Hi duy, try http://www.xilinx.com/xapp/xapp130.pdf "XAPP130 Using the Virtex Block SelectRAM+ Features v1.4 (12/00)" duy wrote: > > how do i write the initialize file(.coe) or edit INIT value after generated a single-port Ram? > for example:in this ram,it is 16x256. > how do i make it 256 differet value after initializtion?Article: 40396
Rick, Simple answer, we asked all of our customers what they use. They use PPC (vast majority). Austin Rick Filipkiewicz wrote: > Nicholas Weaver wrote: > > > In article <3C85B110.F0FC60DE@yahoo.com>, > > rickman <spamgoeshere4@yahoo.com> wrote: > > > > >what is special about V2Pro? Is this the V2 chip with on board PPC or > > >other screaming CPU? > > > > 0-4 PowerPC cores (32b, integer only, 5 stage pipeline, up to 300 > > MHz), with close ties into the BlockRAMs (can use the BlockRAMS for > > I/D memories). Single cycle 16 bit MACs, full 32x32 hardware > > multiplier. > > > > 4-16 (depending) 3 Gbit serial I/O channels. > > > > The processor cores aren't that impressive (considering this is a .13 > > micron, 9 layer copper process, hell, .25 uM synthesized standard cell > > sparc run at 130), but the integration looks potentially cool. > > > > -- > > Nicholas C. Weaver nweaver@cs.berkeley.edu > > <moan on> > > Why oh why was it the PPC and not one of the 2 big players in embedded CPUs - > Arm or MIPS. > The embedded system s/w tools for these to CPU families are AFAIK far more > advance (o.k. there's a bit of a trumpet tootle here). > > In particular, since `A' has Arm for Excalibur, why not MIPS ? > > <moan off>Article: 40397
Martin, Nope. How about the 2V40? Pretty tiny, cs144 package (smallest)? Austin Martin Thompson wrote: > Hi all, > > I have just got a requirement for a phase shiftable square wave, for > which a Virtex-II DCM looks ideal. However, I don't need the rest of > the device - or the wacky packages the seem to come in... > > Any plans for a standalone DCM product (in an SOIC package :-)? > > Cheers, > Martin > > -- > martin.j.thompson@trw.com > TRW Conekt, Solihull, UK > http://www.trw.com/conektArticle: 40398
Dear all, Is there anyone using MXE 5.5e ? How is its speed ? Please advise, KennyArticle: 40399
Dear All, Creating testbench in Verilog for me is always time consuming. Is there any program could help ? Please advise, Kenny
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