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> Also, I need a simple and reliable way to insure that the system does >not generate any runt clock pulses in the enable/disable count function. I >have seen circuitry that will allow the designer to switch from one clock to >another asyncronously. I need to switch from clock to no_clock without >generating any runt clocks. Can someone recommend a solution? Or perhaps I >should use a count enable input? It is not critical if the system misses >one clock pulse, as long as it does so somewhat consistently. I would >prefer to avoid any metastability. I would run your external signal through the standard 2 stage synchronizer. Now it is synchronous with your clock and you can use it as a clock enable without any problems with runt pulses. It will be delayed by 1 to 2 clocks, but that happens on both edges so the pulse duration doesn't change much. -- These are my opinions, not necessarily my employer's. I hate spam.Article: 38751
>At first I'd like to say, that the board, I start to design, is not >commercial. It is just my hobby and Atmel sends me 3-4 free samples. May be >Xilinx too, but I didn't found any page for sample request... Now I have 2x >XC2S200 and would like to use something for configuration. What is the best >type for this device? Thank you. What are you going to do with your board? If it's just a toy and you are willing to leave it connected to your PC, then you don't need any parts. Just use the printer port. Set your FPGA up for slave serial mode and write some code to read in the config file and wiggle the printer port pins. When starting, it's probably simpler to read the raw-bits file. Then you don't have to worry about which end of the byte goes out first. -- These are my opinions, not necessarily my employer's. I hate spam.Article: 38752
Hi everyone I have decide to use the instanced method, that make me very happy, I only need to reroute in Quartus with 6 mins instead of 40 min.Article: 38753
Has anybody done any benchmarking of EDA software under different hardware platforms... I'm a brand-name sucker and tend to buy Intel - but how does AMD compare. And how does a Celeron compare to a similar speed P3. I'm using ModelSim, Leonardo Spectrum & Quartus (all under Windows). I've seen loads of benchmarks on the web which talk about games, office apps and perhaps DTP - which of these applications is most simliar to EDA software ? MarkArticle: 38754
Victor Schutte wrote: > > > Requirements: A PC with Win98 or Win2000, serial port and Power supply > (2.5V, 3.3V and 5V). Victor, you might find the requirement for 3 power supplies will put people off. Could you not add regulators for the 3.3 and 2.5v supplies? Nial.Article: 38755
Hi all,
the following constraint terminates with error during parsing:
############################################################################
###
## Trying to make to Main DSP output enable faster. 24.01.2002 -mm-
TIMEGRP DSPRdDataPath = PADS(dsp_data(0).PAD :\
dsp_data(1).PAD :\
dsp_data(2).PAD :\
dsp_data(3).PAD :\
dsp_data(4).PAD :\
dsp_data(5).PAD :\
dsp_data(6).PAD :\
dsp_data(7).PAD :\
dsp_data(8).PAD :\
dsp_data(9).PAD :\
dsp_data(10).PAD);
############################################################################
###
TIMEGRP DSPRdCtrlPath = PADS(dsp_csn.PAD : dsp_rdn.PAD);
############################################################################
###
TIMESPEC TSmypads = FROM : DSPRdCtrlPath: TO : DSPRdDataPath : 6ns;
############################################################################
###
The idea should be to constraint a fast output enable once dsp_csn and
dsp_rdn are active low.
markus
Article: 38756Hi Hal, > What are you going to do with your board? I try to start something to do with VHDL and FPGA. > If it's just a toy and you are willing to leave it connected > to your PC, then you don't need any parts. Just use the > printer port. Set your FPGA up for slave serial mode and > write some code to read in the config file and wiggle the > printer port pins. This is a good idea!!! It's so simple that I forgot it. And may be also I get working the parallel mode. > When starting, it's probably simpler to read the raw-bits > file. Then you don't have to worry about which end of the > byte goes out first. Is this the difference to Xilinx conf. memories? AndrejArticle: 38757
Hi.. Can you give ideas how to interface the ADC0804 with the Altera FLEX10K ? I have planned to interface the output with DAC0808 also. I have another problem here. I have designed 8-tap FIR filter using bit serial approach. How to convert the output 8 bit from ADC to 16 bit signed extended input into the FPGA? And how to convert from 16 bit output from FPGA into 8 bit to support DAC0808? Or it is impossible at all.. Thanks alot...Article: 38758
Hal Murray <hmurray-nospam@megapathdsl.net> wrote: >>> If the two clocks are unrelated, you WILL have set-up time violations, sooner or >>> later even metastability problems. >> >>Not if the destination flip-flop is only clock enabled some time (several >>cycles) after the source signal is stable. > That doesn't avoid the metastability problem. It just pushes > it over to the logic that decided when to do the clock enable. I see your point. There is potential metastability in generating the enable signal for the high speed sampling register. In practice I don't see this as too much of an issue for this design. Hamish -- Hamish Moffatt VK3SB <hamish@debian.org> <hamish@cloud.net.au>Article: 38759
Hi, i really need help bout this, as i worked for this for a week, no result turns out. first, any one ever try reconfigure Xilinx FPGA using the chip itself? (i'm using a single XC4010XL) the problem is.. when i connect the user I/O to the /program pin, the configuration can't even complete at power start up.. when i disconnect the I/O .. the configuration working pretty well.. whats the solution for this? anyone, anyone at all, who has any idea, ple reply to me, thnaks chiibiaoArticle: 38760
Ray Andraka wrote: > > Cheapest in cost per lut, but far less a foregone conclusion when you compare the logic implemented per dollar. The > tristates are not the only thing that can eat LEs. Small delay queues need a flip-flop per bit, where all Xilinx since > the early 4K devices can use the LUTs as RAM, or even shift registers so you can get up to 17 bits of delay per > LUT+FF. Also, another LE eater is the fact that the Altera carry logic separates the 4 input LUT into a pair of > 3LUTs, one of which does the carry function. That pushes arithmetic with more than two inputs (or in the case of 10K a > clock enable) to two or more layers of logic where the same function fits in one level in any Xilinx device. Examples > here are accumulators with load, adder/subtractors, adders with muxes, etc. > You are right. For instance i am fond of SRL16 Virtex component. It expandes opportunities dramatically. Consider the FIR filter. If delay registers to exchange to SRL16s, then one can get up to 16 equal FIR filters in parallel. Altera proposes nothing of this kind. Anatoli SergyienkoArticle: 38761
> Or can anyone tell me how to test and prove that my design is working ? I
> have tried out the timing simulation and the result is correct and now I
> want to demo it . How?
May I suggest two very different directions :
- You may use a PC and RS232 to inject any waveform you
like (wav files) into your FPGA, and recover the output
(filtered) stream at the same time, and play it & compare
on your PC.
This only requires a simple UART (at 115.200 e.g.) in your
design. There is one such IP on my web site.
http://www.alse-fr.com/English/ALSE_UART_us.pdf
It is not quite "real time", but it will prove your FPGA does
the correct job. You can even do any spectrum analysis you
want on the PC.
Just be aware that using RS232 under Windows is not always trivial.
- You may use a XESS demo board which includes a 20 bits stereo
codec. It's cheap (under $100) and ready to use.
See at http://www.xess.com/prod010.php3
Both solutions should get you up and running very quickly.
Good luck !
Bert Cuzeau - Technical Manager ALSE
- ASIC & FPGA Design
- HDL Training Courses
- Consultancy ...
http://www.alse-fr.com
=D- =D- =D- =D- =D- =D- =D-
--
Posted via Mailgate.ORG Server - http://www.Mailgate.ORG
Article: 38762I am pretty sure the solution is to try this with a Virtex instead, but first read XAPP 151 and all the others on the configuration architecture. It may be possible on 4000 series but I don't think so (I am guessing that reconfiguration causes functionality to stop during reprogramming of the configuration memory, which is not the case for all scenarios with the Virtex--of course I could be dead wrong about the 4000 series and if so please excuse me). You can find out if it will work the the 4000 series for sure by digging up an in depth ap. note on its configuration architecture (if one exists--I think it does but my memory on the subject is weak right now). I have had discussions with numerous people about reconfiguring a Virtex FPGA with its own resources. It would be particularly slick in RTR (run-time-reconfigurable) applications. A :) Fong Chii Biao <ericfcb@tm.net.my> wrote in message news:3c50130f_1@news.tm.net.my... > Hi, i really need help bout this, as i worked for this for a week, no result > turns out. > first, any one ever try reconfigure Xilinx FPGA using the chip itself? (i'm > using a single XC4010XL) > > the problem is.. when i connect the user I/O to the /program pin, the > configuration can't even complete at power start up.. > when i disconnect the I/O .. the configuration working pretty well.. whats > the solution for this? > > anyone, anyone at all, who has any idea, ple reply to me, thnaks > > chiibiao > >Article: 38763
"Con Cac" <con_cac@optusnet.com.au> wrote in message news:3c4fecef$0$20438$afc38c87@news.optusnet.com.au... > I am wondering what wrong with www.fpga.org website. Is it shutdowned or > what? Just on hiatus. fpga.org used to point to fpgacpu.org. But when Mindspring moved fpgacpu.org to a new server a month ago, they neglected to move the pointer. So fpga.org currently points to a dead site. I'm working on it. Jan Gray, Gray Research LLC FPGA CPU News: www.fpgacpu.orgArticle: 38764
Even more advantageous is the fact that you can use the SRL16s instead of the LUTs, which means you can reload the filter
coefficients in a DA filter without having to reconfigure the FPGA. With Altera, you can't change coefficients in a
distributed arithmetic filter, and the alternative for programmable or adaptive filters takes a frightening number of LEs.
vt313@comsys.ntu-kpi.kiev.ua wrote:
> Ray Andraka wrote:
> >
> > Cheapest in cost per lut, but far less a foregone conclusion when you compare the logic implemented per dollar. The
> > tristates are not the only thing that can eat LEs. Small delay queues need a flip-flop per bit, where all Xilinx since
> > the early 4K devices can use the LUTs as RAM, or even shift registers so you can get up to 17 bits of delay per
> > LUT+FF. Also, another LE eater is the fact that the Altera carry logic separates the 4 input LUT into a pair of
> > 3LUTs, one of which does the carry function. That pushes arithmetic with more than two inputs (or in the case of 10K a
> > clock enable) to two or more layers of logic where the same function fits in one level in any Xilinx device. Examples
> > here are accumulators with load, adder/subtractors, adders with muxes, etc.
> >
>
> You are right.
> For instance i am fond of SRL16 Virtex component.
> It expandes opportunities dramatically.
> Consider the FIR filter.
> If delay registers to exchange to SRL16s,
> then one can get up to 16 equal FIR filters in parallel.
> Altera proposes nothing of this kind.
>
> Anatoli Sergyienko
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 38765
We've always used a small PAL outside the FPGA to assist in
self-reconfiguration. Can you give more specifics as to why you think it won't
configure? Check the program pin to make sure it isn't staying low, same with
the init pin. Also check to make sure they aren't going low at the end of
configuration.
Alex Carreira wrote:
> I am pretty sure the solution is to try this with a Virtex instead, but
> first read XAPP 151 and all the others on the configuration architecture.
> It may be possible on 4000 series but I don't think so (I am guessing that
> reconfiguration causes functionality to stop during reprogramming of the
> configuration memory, which is not the case for all scenarios with the
> Virtex--of course I could be dead wrong about the 4000 series and if so
> please excuse me).
>
> You can find out if it will work the the 4000 series for sure by digging up
> an in depth ap. note on its configuration architecture (if one exists--I
> think it does but my memory on the subject is weak right now).
>
> I have had discussions with numerous people about reconfiguring a Virtex
> FPGA with its own resources. It would be particularly slick in RTR
> (run-time-reconfigurable) applications.
>
> A :)
>
> Fong Chii Biao <ericfcb@tm.net.my> wrote in message
> news:3c50130f_1@news.tm.net.my...
> > Hi, i really need help bout this, as i worked for this for a week, no
> result
> > turns out.
> > first, any one ever try reconfigure Xilinx FPGA using the chip itself?
> (i'm
> > using a single XC4010XL)
> >
> > the problem is.. when i connect the user I/O to the /program pin, the
> > configuration can't even complete at power start up..
> > when i disconnect the I/O .. the configuration working pretty well.. whats
> > the solution for this?
> >
> > anyone, anyone at all, who has any idea, ple reply to me, thnaks
> >
> > chiibiao
> >
> >
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 38766"AP" <escorpiontale@hotmail.com> wrote in message news:TeF38.35507$fP.1921238163@newssvr21.news.prodigy.com... Angel I had exactly this problem. The reason is that the FIFO requires a free running clock and cannot be easily single stepped. Unfortunately you'll have to provide a write-enable which picks out the rising clock edge that you want. I used a state-machine which worked quite nicely. Good Luck Phil -- Posted via Mailgate.ORG Server - http://www.Mailgate.ORGArticle: 38767
i have no choice but a XC4000 series cause thats what we have in our Uni :) Im working on my undergraduate thesis actually. I read on the dynamic reconfiguration application note, it says that self reconfigure is possible, even the internal memory is gone once the reconfig was initiated, and all IO was put into tri state, its still reliable in doing so. but my problem is, it cant even configure on power up.. sad. well, thanks alot for sharing ur information, Alex. any information bout this on XC4000 series, let me know ya :) FCB Alex Carreira <aycarrei@shaw.ca> wrote in message news:a2pabv$1i02$1@nserve1.acs.ucalgary.ca... > I am pretty sure the solution is to try this with a Virtex instead, but > first read XAPP 151 and all the others on the configuration architecture. > It may be possible on 4000 series but I don't think so (I am guessing that > reconfiguration causes functionality to stop during reprogramming of the > configuration memory, which is not the case for all scenarios with the > Virtex--of course I could be dead wrong about the 4000 series and if so > please excuse me). > > You can find out if it will work the the 4000 series for sure by digging up > an in depth ap. note on its configuration architecture (if one exists--I > think it does but my memory on the subject is weak right now). > > I have had discussions with numerous people about reconfiguring a Virtex > FPGA with its own resources. It would be particularly slick in RTR > (run-time-reconfigurable) applications. > > A :)Article: 38768
Thanks Phil. I actually was able to solve this problem by registering the WE_N and then muxing it with a clock. That way when WE_N is low the WR_CLK is the delayed WE_N and when its high its a free running clock. If this is also done to the read port it solves the issue of clearing the empty flag after a simultaneous read and write. Thanks Angel "Phil Connor" <p.connorXXX@optionYYY.com> wrote in message news:fa509cd7fa6a09e7ad28154691d1912d.58911@mygate.mailgate.org... > "AP" <escorpiontale@hotmail.com> wrote in message > news:TeF38.35507$fP.1921238163@newssvr21.news.prodigy.com... > > > Angel > > I had exactly this problem. The reason is that the FIFO requires a > free running clock and cannot be easily single stepped. > > Unfortunately you'll have to provide a write-enable which picks out > the rising clock edge that you want. I used a state-machine which > worked quite nicely. > > Good Luck > > Phil > > > -- > Posted via Mailgate.ORG Server - http://www.Mailgate.ORGArticle: 38769
Burnett escribió: > > I'm working on a hobby project involving a Cirrus EP7312 > microprocessor. The design is also gointo contain an fpga with plenty > of extra gates. My problem is that on powerup the microprocessor will > enter standby mode until a few signals are triggered (following > ceratin timings) to enter normal execution and executing > instrucations. > > I'm new to programmable logic and I'm wondering if managing these > signals and their timings might be a good use for some of the extra > gates in my fpga. I'm envisioning a state machine that would wait a > few usec in a state and then transition to another state, each state > changing the logic levels on pins that are attached to the > microprocessor. Is this posible with an fpga? From my meager > understanding it sounds like this problem is better suited for a cpld, > but I don't have one of those on my design board... Hi, I'm sure that a (very small) state machine and, perhaps, a counter for the delay you need, can handle easely this question. Now you need to implement physically that state machine, and both, the FPGA and the CPLD can do it, but why use a CPLD for it if you have the FPGA. Note: a four state SM (one CLB, maybe two) and a 32-bit counter (32 LCs => 16 or 8 CLBs) is all you need. Cheers and luck, Santiago.Article: 38770
Well, i have two 512k PROM with each chip enable connected to Done pin of XC4010XL. Another edge trigger D-flip-flop for temparory register(coz all I/O go into tri state during reconfig) to select the PROM by Output Enable pin. and i use another user pin as an initiate pin to pull the program pin low. it can't configure when start up, if i had the user pin connected to this program pin. when i check on the program pin, it never goes high, its blinking actually.. the user pin is causing problem, but i have no idea why is it so. when i tied another not in use user pin to program pin, the power up configuration is working again. why is the user pin that i use in my design will cause such a problem? is this make any sense to you? thanks for giving ur opinion. :) Ray Andraka <ray@andraka.com> wrote in message news:3C50430A.1F418834@andraka.com... > We've always used a small PAL outside the FPGA to assist in > self-reconfiguration. Can you give more specifics as to why you think it won't > configure? Check the program pin to make sure it isn't staying low, same with > the init pin. Also check to make sure they aren't going low at the end of > configuration. > > > --Ray Andraka, P.E. > President, the Andraka Consulting Group, Inc. > 401/884-7930 Fax 401/884-7950 > email ray@andraka.com > http://www.andraka.com > > "They that give up essential liberty to obtain a little > temporary safety deserve neither liberty nor safety." > -Benjamin Franklin, 1759 > >Article: 38771
"Peter Ormsby" <faepete.deletethis@mediaone.net> wrote in message news:<TrG28.25000$yC.3093892@typhoon.mn.mediaone.net>... > Nios v2.0 is currently in Beta. You may want to contact your local Altera > FAE to see if you could get a copy of the beta for your project. > > -Pete- > > James Srinivasan <James_Srinivasan@nospam.yahoo.com> wrote in message > news:a2e28c$m0a$1@pegasus.csx.cam.ac.uk... > > Please can anyone from Altera comment on the availability of the Nios v2 > > softcore processor? > > > > Many Thanks, > > > > James > > > > Hello all, Nios v2.0 is in the can and should begin shipping in a week or two. I've seen the beta and can only say that it was worth the wait. Hope you all agree. ------>AlanArticle: 38772
> Nios v2.0 is in the can and should begin shipping in a week or two. > I've seen the beta and can only say that it was worth the wait. Hope > you all agree. Just managed to get hold of the beta and it looks much improved! Even managed to coexist happily with the 1.1 stuff and ran straight out of the box. Any idea if there are many changes between the shipping code and what's in the beta (build 216)? Many Thanks, JamesArticle: 38773
Sounds like you randomly selected LDC or one of the other dual use pins that
goes low during configuration. If you did that, then as soon as the chip starts
configuring, LDC goes low, pulling the program pin low, which restarts
reconfiguration. While program is low, the LDC goes high so it releases program
and the configuration starts until LDC goes low again. I kind of figured
something like that was going on. Since you only have two configurations, this
should work fine as long as you avoid pins that go low during configuration. It
may be best to use HDC to get a solid high level during configuration.
Fong Chii Biao wrote:
> Well, i have two 512k PROM with each chip enable connected to Done pin of
> XC4010XL.
> Another edge trigger D-flip-flop for temparory register(coz all I/O go into
> tri state during reconfig)
> to select the PROM by Output Enable pin.
> and i use another user pin as an initiate pin to pull the program pin low.
>
> it can't configure when start up, if i had the user pin connected to this
> program pin.
> when i check on the program pin, it never goes high, its blinking actually..
> the user pin is causing problem,
> but i have no idea why is it so.
>
> when i tied another not in use user pin to program pin, the power up
> configuration is working again.
> why is the user pin that i use in my design will cause such a problem?
> is this make any sense to you?
>
> thanks for giving ur opinion. :)
>
> Ray Andraka <ray@andraka.com> wrote in message
> news:3C50430A.1F418834@andraka.com...
> > We've always used a small PAL outside the FPGA to assist in
> > self-reconfiguration. Can you give more specifics as to why you think it
> won't
> > configure? Check the program pin to make sure it isn't staying low, same
> with
> > the init pin. Also check to make sure they aren't going low at the end of
> > configuration.
> >
> > > --Ray Andraka, P.E.
> > President, the Andraka Consulting Group, Inc.
> > 401/884-7930 Fax 401/884-7950
> > email ray@andraka.com
> > http://www.andraka.com
> >
> > "They that give up essential liberty to obtain a little
> > temporary safety deserve neither liberty nor safety."
> > -Benjamin Franklin, 1759
> >
> >
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 38774Hi, there, I'm new to Spartan-II FPGA chip. However, I need to use it in a PCI design. So I was wondering if some pins are dedicated for PCI or any pin can be used for PCI connection? BTW, can you also provide some advice on how to use Spartan FPGA as PCI controller? Thanks a lot. Regards, David
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Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z