Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
emanuel stiebler <emu@> wrote: > VR wrote: >> >> I have a new AMD "XP 1700+" (1.6GHz) > Sorry, but the "XP 1700+" is clocked at 1.47 GHz ;-) You are correct. I was also dealing with a "1900+" system which does run @ 1.6GHz. My mistake. Thanks, VR.Article: 39151
Ray Andraka <ray@andraka.com> wrote: > the design for the simulator to plug in for the black box. One option, the one > that seems the easiest, is to use the mapped output from the synthesis (in > synplicity that is the *.vhm file). It is about as readable as the edif, and I had some problems with the Synplify VHDL output. Firstly if you use any device primitives directly in your design (hard to avoid with DCMs, RAMs etc), you need to edit the generated VHDL to specify what library the simulation models are found in (ie add "library unisim" to every architecture in the output code). It'd be nice if you could tell Synplify to include some libraries for you automatically. Secondly it appeared to put 100 ps delay on all signals generated inside processes etc. I guess this is to avoid race conditions but it's a bit simplistic and I ran in to some trouble (although I can't remember the details off the top of my head). In comparison, it's easier (in my experience) to get code from Xilinx NGD2VHDL working, with or without SDF annotation. regards Hamish -- Hamish Moffatt VK3SB <hamish@debian.org> <hamish@cloud.net.au>Article: 39152
Antonio <dottavio@ised.it> wrote: > May I know why if a use this demux in a project I've a maximum > frequency > of 50MHz while if I take away the clock from this demux the maximum > frequency of the project arrive to 155MHz. > There's a well known reason ?? It could be your use of the negative edge of the clock. If the input signals (sel and in_mux) come from the flip-flops triggered by the rising edge of the clock, or the output signals (out_1, out_2, out_3) go to flip-flops triggered by the rising edge of the clock, then your maximum frequency is generally halved. > By the way here it is also the response of XST, the inferring of 30 > D-type flip-flops is due to > when others => null; > there are alternative to not use these flip flop or is better to have > them ??? You have a clocked process, so you will always have flip flops. The others statement is not the source of extra flip flops. > Found 10-bit register for signal <out_2>. > Summary: > inferred 30 D-type flip-flop(s). > Unit <demux_3x10> synthesized. > out_0, out_1, out_2 : out std_logic_vector(9 downto 0) Here are your 30 flip flops, 3 vectors of 10 bits each. > process (sel, in_mux, clk) in_mux and sel should not be in the sensitivity list, as your process is not sensitive to them (only to the clock). If you don't think this process should generate flip flops, it probably doesn't do what you want it to do. It probably shouldn't be using the negative clock edge, either. Hamish -- Hamish Moffatt VK3SB <hamish@debian.org> <hamish@cloud.net.au>Article: 39153
"Dave Brown" <dbrown12@home.com> schrieb im Newsbeitrag news:a3f6qe$el2$1@pallas.novatel.ca... > return this constant on the databus when a specific address shows up on the > address bus. I currently just use an output mux, and when the select signal > is right, I just return a constant 8 bit value. This doesn't seem to be > working reliably in the synthesized device, yet it simulates fine. Am I > missing something, or does the problem lie elsewhere? Here's a snippet to > show what I'm trying to do: The code is correct, except that you values go ta a dataBUS, means there is most probably more than one device attatched. So you need a tristate buffer, controlled by chip select (which also be derived form the address bus) data_out<=y when cs='0' else "ZZZZZZZZ"; -- low active chip select -- MfG FalkArticle: 39157
Philip Freidin wrote: > On Fri, 01 Feb 2002 01:09:32 +0000, Rick Filipkiewicz <rick@algor.co.uk> wrote: > >*BUT* > > > >I've always had one caveat about that apps note. The `metastab catching window' is quoted > >as 0.1nsec but the data book setup times for the XC4005E FFs were much larger. Does this > >mean that the hold times quoted as 0 were/are in fact negative ? > > The `metastab catching window' is also the window in which the FF actually > samples the D (and CE) input and decides what to do. If new data is valid > before the start of the window, the FF catches the new data. If the new > data changes after the window, the FF catches the data value prior to the > new data. > > The window slides around based on temp, voltage, device age, phase of moon, > Dv/Dt of the data signal, Dv/Dt of the clock signal, what the async reset > has done recently, and what the current FF state is. > The data sheet numbers for setup and hold give a bounded limit for how far > the window can wander. ( it wanders around during normal operation, but > within these limits). > > So reality is that 'setup' and 'hold' do not actually exist. By specifying > these values, and designing to them, you get reliable system behaviour > regardless as to where the window is at the time of the clock signal. > > So getting to your question, the FFs are designed so that if every thing > conspires to make the window as late as possible, the end of the window > will be no later than 0.0 ns after the clock (which gives hold time of > 0.0 ns). > > Similarly, if everything conspires to make the window as early as possible, > the beginnining of the windo will be no earlier than the setup time before > the clock. > > You could read more on this at: > > http://www.fpga-faq.com/FAQ_Pages/0017_Tell_me_about_metastables.htm > > Philip > Philip Freidin > Fliptronics I'd read that, IMO real nice, FAQ some while ago. My query was not that the `catching window' was shorter than the nominal setup time but that it was so much shorter. Re-reading the FAQ reminded me that, of course, the real window size is largely determined by the charging time of the `input' under whatever conditions are present at the time the `D' signal changes. Clearly this is going to be a lot smaller than the worst case Tsu+Thld esp. for modern fine geometry devices. If Peter's claim of a few picosec. for modern Virtex devices is correct then XAPP094 understates the MTBF (assuming K2 unchanged) by an order of magnitude or so but this largely irrelevant as the MTBF is completely dominated by the resolution time function. Going back to my PCISignal-> 100MHz clock domain case and: o Assuming that the PCI signal is not happening at PCI rate but, say, 1/6th of this. o The `catching window' has come down to 20psec from the 100 in XAPP094. o There has been a modest K2 increase to 25. o I make a 1.2nsec allowance for metastab decay [in the real system its much bigger than this]. I get an MTBF of about 62 years. Hence, while knowing full well that metstability is always with us, I do tend to align myself with Peter A's pragmatic approach to the seriousness of the problem. For example a well placed & routed double synchoniser running at 200MHz is still likely to have 2-3 nsec. of slack and the MTBF in the test case is now (for 2 nsec.) going to be 1.4*10^10 years. Exponentials are wonderful things when they're on your side. Against all this is, of course, Mr. Murphy who will ensure that, no matter how unlikely, the 1-in-10billion error happens just at the critical point of V2 for an aircraft taking off or when the surgeon really needs to know the patients blood pressure or ...Article: 39158
On 02 Feb 2002 06:26:07 GMT, hamish@cloud.net.au wrote: >Ray Andraka <ray@andraka.com> wrote: >> the design for the simulator to plug in for the black box. One option, the one >> that seems the easiest, is to use the mapped output from the synthesis (in >> synplicity that is the *.vhm file). It is about as readable as the edif, and > >I had some problems with the Synplify VHDL output. Firstly if you use >any device primitives directly in your design (hard to avoid with >DCMs, RAMs etc), you need to edit the generated VHDL to specify >what library the simulation models are found in (ie add >"library unisim" to every architecture in the output code). >It'd be nice if you could tell Synplify to include some libraries >for you automatically. > >Secondly it appeared to put 100 ps delay on all signals generated >inside processes etc. I guess this is to avoid race conditions but >it's a bit simplistic and I ran in to some trouble (although I >can't remember the details off the top of my head). I can :) In a high speed design the 100ps may overestimate the real delay and the total delay on a path may sum to greater than your clock period. This causes problems in simulation. One fix is to edit all the 100ps delays and change them to 10ps. This takes a few seconds in a text editor. >In comparison, it's easier (in my experience) to get code from >Xilinx NGD2VHDL working, with or without SDF annotation. I agree. Sometimes you will need to simulate the output of the synthesiser to work out which tool is introducing a bug into your design. Regards, AllanArticle: 39159
I've been going the *.vhm route. The only primitives I've had trouble with lately
are the ROM16 and ROM32 primitives, the others (notably the DLLs and RAMB4's) that
used to cause problems are apparently OK now without the added unisim. I've had an
open case with synplicity for some time with this issue. In the mean time, I've been
just replace all to replace every instance of library synplify with the added unisim
library lines. The advantage with using the mapped output instead of the NGD is that
you can then distribute a sim model with an edif netlist for a macro that is intended
to be used in a larger design without having to go through the xilinx tools to get
it.
hamish@cloud.net.au wrote:
> Ray Andraka <ray@andraka.com> wrote:
> > the design for the simulator to plug in for the black box. One option, the one
> > that seems the easiest, is to use the mapped output from the synthesis (in
> > synplicity that is the *.vhm file). It is about as readable as the edif, and
>
> I had some problems with the Synplify VHDL output. Firstly if you use
> any device primitives directly in your design (hard to avoid with
> DCMs, RAMs etc), you need to edit the generated VHDL to specify
> what library the simulation models are found in (ie add
> "library unisim" to every architecture in the output code).
> It'd be nice if you could tell Synplify to include some libraries
> for you automatically.
>
> Secondly it appeared to put 100 ps delay on all signals generated
> inside processes etc. I guess this is to avoid race conditions but
> it's a bit simplistic and I ran in to some trouble (although I
> can't remember the details off the top of my head).
>
> In comparison, it's easier (in my experience) to get code from
> Xilinx NGD2VHDL working, with or without SDF annotation.
>
> regards
> Hamish
> --
> Hamish Moffatt VK3SB <hamish@debian.org> <hamish@cloud.net.au>
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 39160Hi, Does anyone knows about , any research going on for a Place and route failure/success predictability for a Xilinx-Virtex architecture. Or something related to the packing constraints one shd follow and can be sure that the PAR wouldnt fail.. thanx amitArticle: 39161
hello, Really i can't see why i am getting this error message bram.clka too short setup time, missing time 2.3ns! bram.clkb too short setup time, missing time 2.3ns! i am using bram in both read and write mode. the two ports are clocked with the same clock, the master clock. one port is set always for writing the other for reading. The address are always differents! the Bram address as well as the input data are REGISTRED, clocked with the same clock clk so how can i get short setup time! i am using F3.1, sp7. i have even set the data input to zero value, the same error happen, I did timing simulation, the address values are as i expect (they change the value after the clock rising edge) the we,en, rst bram inputs are set to VCC, or GND as required , the input data are registred in the IOB, so really what i am missing ? why i am getting this error? thanks -- Posted via Mailgate.ORG Server - http://www.Mailgate.ORGArticle: 39163
want just to add the addresses values are so clean, no glitches so why i am getting this problem? -- Posted via Mailgate.ORG Server - http://www.Mailgate.ORGArticle: 39164
I have a VHDL design that I need to run off of parasitic power (standby current draw less than 300 microamps @ 3.3V). I had intended to use the Xilinx Coolrunner XPLA3, but I need the largest part (XCR3512XL) which Xilinx had chosen not to manufacture in the XPLA3, but will have samples on the Coolrunner II 512 part next August. That's a bit late for my needs! I've been looking around, but haven't found much else that looks like it's going to meet my standby current requirements. I'm also concerned about some of these SRAM/Flash FPGAs I've looked at being able to handle the slow startup necessary for a parasitic power application. I don't need speed (max clock speed will be 1 MHz at most), but I need LOW power! And of course low active power is good too! =) Any suggestions are greatly appreciated. Please copy any responses to my e-mail. Remove the NOSPAM_ header to reply. Sincerely, Dr. Michael D. FoegelleArticle: 39165
in my project,my system clock is 100Mhz,but i need 33MHZ,20MHZ,14MHZ clock,that is ,i need 3,5,7 divider.how do i implement?Article: 39166
hi all. i am wondering where one can get solutions manuals to textbooks. before everyone attacks me as being a student looking for a method to cheat, i am a practicing asic designer who is trying to learn more about different algorithms and methods to solve problems. i am interested in almost any kind of solutions manual, because it would motivate me to go out and buy the book if i am interested in the subject. working my way through problems without having a definite understanding if i am on the right path or way off is quite difficult. i am really interested in the fields of linear programming/optimization, computer architecture (hennessy and patterson book is awesome), numerical analysis, dsp(adaptive, wavelets), algorithm design, or almost anything related or of practical use to engineering. anything in the public domain, or freely available, ie: out of print books sometimes offer manuals and book online, or anything at all would be greatly appreciated. thanks strut911Article: 39167
Hi everyone, I am unable to prevent Xilinx ISE 4.1i mapper from removing a RAM in my design. It is COREGEN generated DPRAM. I am running the mapper with "map -u" option but it still insists on removing the RAM. Does anyone else have a similar problem? Is it a bug in ISE 4.1i and do I need a Service Pack for it or am I doing something wrong? Any answers will be appreciated. Thanks, HiteshArticle: 39168
Dr. Michael D. Foegelle wrote: > > I have a VHDL design that I need to run off of parasitic power (standby > current draw less than 300 microamps @ 3.3V). I had intended to use > the Xilinx Coolrunner XPLA3, but I need the largest part (XCR3512XL) > which Xilinx had chosen not to manufacture in the XPLA3, but will have > samples on the Coolrunner II 512 part next August. That's a bit late for > my needs! I've been looking around, but haven't found much else that > looks like it's going to meet my standby current requirements. I'm also > concerned about some of these SRAM/Flash FPGAs I've looked at > being able to handle the slow startup necessary for a parasitic power > application. I don't need speed (max clock speed will be 1 MHz at > most), but I need LOW power! And of course low active power is good > too! =) Any suggestions are greatly appreciated. Please copy any > responses > to my e-mail. Remove the NOSPAM_ header to reply. 512 MC is at the top end of CPLD, so bottom end FPGA are likely to be cheaper. Required is information on the StartUp ENGERY, which has not been well explained. So, far, we have seen a relatively high PEAK current is needed on FPGA startup, and that can be addressed with a snap-action regulator. What you need, is the duration of that current ( Peter/Austin ?), to determine what energy storage CAP is needed. Also, once that hurdle is over, there is a dynamic loading energy budget too ( also on the Coolrunner, but a little hidden ) This is the time to dump the NV storage block, into the config latches, and will consume FLASH Icc and a clock Icc too. After all that, then operating Icc energy will be **mA/MHz -jgArticle: 39169
"Hitesh Brahmbhatt" <hbrahmbh@san.rr.com> schrieb im Newsbeitrag news:3C5CD14B.1050703@san.rr.com... > I am unable to prevent Xilinx ISE 4.1i mapper from removing a RAM in my > design. It is COREGEN generated DPRAM. I am running the mapper with So the output of your DPRAM (or other control logic) is not connected to a signal in your design. So all logic generating unused signals will be removed. -- MfG FalkArticle: 39170
"ug" <iwrt@jdavs.iofg> schrieb im Newsbeitrag news:ee749e4.-1@WebX.sUN8CHnE... > in my project,my system clock is 100Mhz,but i need 33MHZ,20MHZ,14MHZ clock,that is ,i need 3,5,7 divider.how do i implement? Just use a counter to generate a clock enable every 3dr, 5th, 7th cycle. and use this as a clock enable for your low speed logic. You can also use a DLL to divide by 3. -- MfG FalkArticle: 39171
"Dr. Michael D. Foegelle" <NOSPAM_mfoegelle@austin.rr.com> schrieb im Newsbeitrag news:M4%68.90808$XZ1.4073857@typhoon.austin.rr.com... > most), but I need LOW power! And of course low active power is good > too! =) Any suggestions are greatly appreciated. Please copy any Xilinx is not the only vendor of CPLDs. Have a look at www.lattice.com www.actel.com -- MfG FalkArticle: 39172
"Hristo Stevic" <hristostev@yahoo.com> schrieb im Newsbeitrag news:90b177e23bcb6994a03990fbe4486893.52609@mygate.mailgate.org... > want just to add the addresses values are so clean, no glitches > so why i am getting this problem? What the frequency of your clock? What FPGA do you use? If you have a big part, the addresses must travel a long way over the chip and may be late. -- MfG FalkArticle: 39173
> What the frequency of your clock? What FPGA do you use? If you have a big > part, the addresses must travel a long way over the chip and may be late. well i am simulating the funcationality of the BRAM apart. so it is the only component in my design. i have set the period in UCF file, i got ~155 MHz i am simulating it with 80ns period -- Posted via Mailgate.ORG Server - http://www.Mailgate.ORGArticle: 39174
"Falk Brunner" <Falk.Brunner@gmx.de> schrieb im Newsbeitrag news:a3j684$18f67u$3@ID-84877.news.dfncis.de... > "Dr. Michael D. Foegelle" <NOSPAM_mfoegelle@austin.rr.com> schrieb im > Newsbeitrag news:M4%68.90808$XZ1.4073857@typhoon.austin.rr.com... > > > most), but I need LOW power! And of course low active power is good > > too! =) Any suggestions are greatly appreciated. Please copy any > > Xilinx is not the only vendor of CPLDs. Have a look at > > www.lattice.com Uuups, its www.latticesemi.com -- MfG Falk
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z