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Hi . I am going to use virtex-II for clock distribution. I have one clock input that goes to 2 seperate output pins, via 2 seperated DCM devices. The DCM will have feed back from the middle on the PCB trace, for delay compensation. Assuming no jitter on the input clock (CLKIN), and assuming that the feedback to the output DCM has the same length, what is that maximum skew between the two output clocks ?? Can it be that one DCM will have a full period jitter to one direction while the other DCM will; have full period jitter in the opposite direction ? ThankX NuritArticle: 39176
I am designing a line of DSP boards containing FPGAs and a single chip micro all on the JTAG chain. I want to be able to test the production boards using JTAG boundary scan. It looks like I can use the XDS510 emulator from TI for emulation. I can also do everything else that I want to do on this scan chain with the other chips. I have been looking for some information on the XDS510 so that I might be able to use it as my boundary scan hardware. This would make the testing and interface consistent and simple. But so far I have found none. TI support is having trouble understanding the question. The first line of help seems to focus on their "canned" answers on using the emulator for code debugging rather than to try to understand my problem. Does anyone have ideas on the best way to use the XDS510 JTAG connector on my board for boundary scan testing? Is there sufficient information on the PC interface to the XDS510 to let me write software to drive test vectors into the board? Or are there other XDS510 compatible emulators that will let me do both code debugging (Code Composer Studio) and boundary scan? -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 39177
Hello, want to install service pack8 for the F3.3i the file did unpack successfully, but nothing happen later according to http://www.xilinx.com/support/techsup/sw_updates/31i/33i_sp8/33if_sp8_readme_pc.htm i should be prompt to input the location of the foundation, but no such thing happens, moreover, the version of my tool has not been upgarded to 08i version has someone exprience a similair situation thanks -- Posted via Mailgate.ORG Server - http://www.Mailgate.ORGArticle: 39178
Ulf Samuelsson wrote: > > My real point was that I am sure Ulf (like others) would like to say > > many negative things about the competition, but there is always the > > Ain't my goal in life. If I want to say something, I generally do... > As I said, the MSP430 is an excellent product, but I do prefer the major > applications > for it to be of the road filling kind ;-) Well, maybe I am different. But I would be telling everyone why my chips were better for road filling applications than the competition's. :) -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 39179
Why do you want to use two DCMs? I would use only one, and rely on the very low skew in the clock distribution. With a common DCM you obviously have no differential jitter to worry about. The deterministic skew between the two output pins can be kept well below 100 picoseconds. Peter Alfke, Xilinx Applications ====================================== Nurit Eliram wrote: > Hi . > I am going to use virtex-II for clock distribution. > > I have one clock input that goes to 2 seperate output pins, > via 2 seperated DCM devices. > The DCM will have feed back from the middle on the PCB trace, > for delay compensation. > > Assuming no jitter on the input clock (CLKIN), > and assuming that the feedback to the output DCM > has the same length, > what is that maximum skew between the two output clocks ?? > > Can it be that one DCM will have a full period jitter to one > direction while the other DCM will; have full period jitter in > the opposite direction ? > > ThankX NuritArticle: 39180
On 2 Feb 2002 21:12:38 -0800, strut911@hotmail.com (strut911) wrote: >hi all. >i am wondering where one can get solutions manuals to textbooks. >before everyone attacks me as being a student looking for a method to >cheat, i am a practicing asic designer who is trying to learn more >about different algorithms and methods to solve problems. i am >interested in almost any kind of solutions manual, because it would >motivate me to go out and buy the book if i am interested in the >subject. working my way through problems without having a definite >understanding if i am on the right path or way off is quite difficult. >i am really interested in the fields of linear >programming/optimization, computer architecture (hennessy and >patterson book is awesome), numerical analysis, dsp(adaptive, >wavelets), algorithm design, or almost anything related or of >practical use to engineering. anything in the public domain, or freely >available, ie: out of print books sometimes offer manuals and book >online, or anything at all would be greatly appreciated. >thanks >strut911 Interesting post. You want solutions manuals to help you decide whether to buy a book,... Well, ... at least you're original. [-Rick-]Article: 39181
Steve- You should do yourself a favor and ask you local Altera support about new product due out this year that would still meet your time frame. Xilinx has announced VirtexII Pro - but that was mostly same gate densities and added features. ApexII is now the standard Altera product but there is an exciting new family you should inquire about that would likely meet your time frame and parameters you mentioned in your post. QuartusII v2.0 just released Friday and has been producing very good results for both this new family and ApexII. As far as GATE COUNTING, every vendor and family uses differnet nomenclature. For the user, you are best off descregarding gate counts and comparing 4input LUTs Available Memory counts Other dedicated Resources Multipliers etc. Best of Luck, Guy Schlacter Altera Corp. "Steve Holroyd" <spholroyd@iee.org> wrote in message news:b623f4cf.0201111039.2a16155@posting.google.com... > I am currently task of recommending the largest, fastest and most > memory FPGA that's readily available the first half of this year for a > FPGA Array Card. > > The choices have been narrowed down to two families Altera's APEX-II > (EP2A70) and XILINX Virtex-II (XC2V6000). > > Which can operate at the highest speed? > > Steve -- Posted via Mailgate.ORG Server - http://www.Mailgate.ORGArticle: 39182
I checked your web site over the weekend and found that you do support the AVR and use the Atmel eval board with an ATmega103 which I believe is somewhat similar to the chip I am evaluating, the ATmega64/128. However, this chip and even the eval board are on the list of "older tools" and parts. In fact, the ATmega103 is "not recommeded for new designs". I see that Atmel has a newer STK500 which can support all of the newer chips. How likely is it that Forth, Inc will bundle SwiftX with this newer board instead of the older board? rickman wrote: > > "Elizabeth D. Rather" wrote: > > The CD that comes with the FET also includes information about the > > SwiftX > > development system, including a link to download a free trial version > > (also > > limited in program size). SwiftX is available for only $450, including > > a royalty-free multitasking kernel, library of several hundred > > functions, > > full support for low-power mode, etc. The HLL is Forth, but assembler > > is also supported. > > > > Cheers, > > Elizabeth > > At this point I am leaning away from the MSP430 and more toward the > ATmega64 or 128 if I can get a better price. The lack of boundary scan > in the MSP430 is a problem for me. Are the ATmega parts supported by > SwiftX? > > -- > > Rick "rickman" Collins > > rick.collins@XYarius.com > Ignore the reply address. To email me use the above address with the XY > removed. > > Arius - A Signal Processing Solutions Company > Specializing in DSP and FPGA design URL http://www.arius.com > 4 King Ave 301-682-7772 Voice > Frederick, MD 21701-3110 301-682-7666 FAX -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 39183
TI does not make the XSD510, it is made by Spectrum Digital. Here a link:
http://www.spectrumdigital.com/
Mark
--
http://www.dsylva-tech.ca
BMW performance chips for E34 M5 and E36's
Chips for E30 and E34 currently in development!
"rickman" <spamgoeshere4@yahoo.com> wrote in message
news:3C5D681C.EBD7700F@yahoo.com...
> I am designing a line of DSP boards containing FPGAs and a single chip
> micro all on the JTAG chain. I want to be able to test the production
> boards using JTAG boundary scan. It looks like I can use the XDS510
> emulator from TI for emulation. I can also do everything else that I
> want to do on this scan chain with the other chips.
>
> I have been looking for some information on the XDS510 so that I might
> be able to use it as my boundary scan hardware. This would make the
> testing and interface consistent and simple. But so far I have found
> none. TI support is having trouble understanding the question. The first
> line of help seems to focus on their "canned" answers on using the
> emulator for code debugging rather than to try to understand my problem.
>
> Does anyone have ideas on the best way to use the XDS510 JTAG connector
> on my board for boundary scan testing? Is there sufficient information
> on the PC interface to the XDS510 to let me write software to drive test
> vectors into the board? Or are there other XDS510 compatible emulators
> that will let me do both code debugging (Code Composer Studio) and
> boundary scan?
>
>
> --
>
> Rick "rickman" Collins
>
> rick.collins@XYarius.com
> Ignore the reply address. To email me use the above address with the XY
> removed.
>
> Arius - A Signal Processing Solutions Company
> Specializing in DSP and FPGA design URL http://www.arius.com
> 4 King Ave 301-682-7772 Voice
> Frederick, MD 21701-3110 301-682-7666 FAX
Article: 39184If you have edited a spreadsheet before, then you should be able to get up to speed quickly. Try it and send me some feedback and requests. Just copy & paste any BOM into Excel and use Refinate. Refinate is a utility that adds functionality to Excel specifically to work with BOM. Also, when you make a change to a netlist (including EDIF), use Refinate to sort every node so you can compare it to the previous version to determine if something has changed by mistake. Here are a few reasons to use Refinate. * No need to change your document style to use it - just verify the integrity of the BOM and continue to use the original if that's all you want to do. * No need to commit to a database program to use it. * Nobody else in the process flow needs to use Refinate except you, and your worksheet file can be used by anybody else. * Counts alphanumeric reference designators (refdes). * Determines if there are duplicate or missing refdes. * Generates different assembly versions based on lists of do-not-installs. * Arranges refdes in a standard format regardless of how they are listed -- can be used to compare different BOM documents of the same assembly. * Converts existing BOM into table formatted records where each part uses only one row. * Edit the BOM while using Refinate to assist. www.adetaylor.com Thanks for your comments, Brian Taylor AnalogDigital Engineering Refinate, Copyright 2001Article: 39185
I Really need at least 15 more participants to complete this research. Please take a few minutes and fill out the attached survey. Thanks! ********** Hi, I am writing to VHDL/FPGA experts/students in the field with the hopes of having them fill out a simple survey. This survey will support a research paper I am writing to fulfill my M.S. Computer Science degree requirements at Rensselaer of Hartford. The paper itself deals with the feasibility of applying Object Oriented concepts and Software Engineering practices to VHDL/FPGA design. Please take the time to fill out and return the survey below (preferably by Feb 7). Please feel free to distribute to others as well. I appreciate your help. Regards, Rick Aikman (860) 654-3517 email: r.aikman@att.net _______________________________________________________________ VHDL - FPGA Design Survey Name: Date: Years Experience VHDL: ____0-2 years ____2-5 years _____More than 5 years Industry: _____Aerospace _____Commercial _____Defense _____Other Knowledge/ Experience in any of the following? (Check all that apply) _____Object Oriented Design _____Requirements Definition _____Verification/Validation Highest Education Completed: ___High School _____Associates ____Bachelors ____Masters ___Doctorate Major: From an Engineering standpoint, what is your view of VHDL for FPGA design? _____VHDL is Hardware Design - Electrical Engineering _____VHDL is Software Design - Software Engineering _____VHDL is a combination of Hardware/Software Design Have you heard of? (Check all that apply) _____Object Oriented Programming for VHDL(The concept of, including current language capabilities) _____Objective VHDL (Proposed Extension of the VHDL language) _____SUAVE (Proposed Extension of the VHDL language) _____Code Inspections (Peer Reviews) _____Evolutionary Prototyping _____Reuse _____Goal Setting _____Daily Build & Test Do you currently use or practice in your designs? (Check all that apply) _____Object Oriented Programming for VHDL (The concept of, including current language capabilities) _____Objective VHDL (Proposed Extension of the VHDL language) _____SUAVE (Proposed Extension of the VHDL language) _____Code Inspections (Peer Reviews) _____Evolutionary Prototyping _____Reuse _____Goal Setting _____Daily Build & Test Describe the implementation of Object-Oriented Techniques and /or Software Engineering Principles in your organization. (Check all that apply) _____Our organization uses OO techniques in our FPGA designs. _____Our organization uses SE practices in our FPGA designs. _____Our organization will likely use OO techniques in the future. _____Our organization will likely use SE practices in the future. _____Our organization believes applying OO techniques will increase design complexity. _____Our organization believes applying SE practices will increase design complexity. FPGA Designs: Please Provide the following info on your design work for up 3 designs(more if you wish). Device 1 Device Type: _____ Man-Hours spent: _____ Estimated Gate Count: _____ Estimated Device Utilization:_____ % Number of Function points: _____ Total Number of Revisions: _____ Device 2 Device Type: _____ Man-Hours spent: _____ Estimated Gate Count: _____ Estimated Device Utilization:_____ % Number of Function points: _____ Total Number of Revisions: _____ Device 3 Device Type: _____ Man-Hours spent: _____ Estimated Gate Count: _____ Estimated Device Utilization:_____ % Number of Function points: _____ Total Number of Revisions: _____ Thanks!Article: 39186
For Virtex style architectures (and probably XC4000), can comparason statements of the form o <= (a = b) o <= (a < b) even when b might be constant, glitch? ie is it async safe[1]? My gut feeling is that it isn't, even when synthesized to take advantage of fast carry chain compares. [1] Ordinarily, this question doesn't come up. In this case, I am dealing with an external device whose register port is asynchronous. -- David Miller, BCMS (Hons) | When something disturbs you, it isn't the Endace Measurement Systems | thing that disturbs you; rather, it is Mobile: +64-21-704-djm | your judgement of it, and you have the Fax: +64-21-304-djm | power to change that. -- Marcus AureliusArticle: 39187
This is a multi-part message in MIME format. ------=_NextPart_000_0026_01C1ACFB.5A419220 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable OK, several coregen parts built with 3.1i and added to overall "A" model = design. RTL sims OK. PAR and post PAR sims OK. Chip works OK (some minor, but identified problems). "B" model revisions to "A" model design. RTL sims OK. PAR and post PAR FAILS. However, Xilinx toolset upgraded to 3.3i SP8 in the interim. The coregen blockram is NOT being clocked (clka) in the POST PAR model, yet is fine in the RTL. Is this because the coregen parts, still at 3.1i, will not PAR properly = with 3.3i SP8??? Is 3.3i a load of rubbish?, the BLKRAM coregen GUI in 3.3 is very = different: I can't select either pos. or neg. clk edge as per 3.1, (clka = is -ve edge in my design). Is this the cause of the prob. TIA, NIV.Article: 39188
> Interesting post. You want solutions manuals to > help you decide whether to buy a book,... > Well, ... at least you're original. > > [-Rick-] heh. yeah, i never start a design without a spec, and i never go on a long drive without a map. i do buy books without manuals, but if i am trying to learn something new, then i would like some kind of pass/fail criteria to tell me if i am on the right track or not. having a solutions manual will not be the driving force behind buying a book, but it will make me think that i have a decent shot at learning the book material thoroughly, instead of guessing if i am correct on my answers or not. especially since the graduate texts that i enjoy perusing can sometimes be esoteric and i can't ask my nearest manager how to correctly solve the problems. ha ha...that was a joke. most of my managers are marketing people. anyways, i know many engineers that enjoy learning new things and buying techie books. having a solutions manual to go with the book would usually be icing on the cake because a manual is basically a treasure trove of useful examples. maybe to get things started, i will post some interesting solutions manuals i have found online: here are some that are great for differential equations...computing and modeling them, and also applying linear algebra to solve them: http://www.prenticehallmath.com/epmanuals/ here are some from prof bertsekas at MIT. he is the optimization/linear programming guru there, although he seems very biased towards auction algorithms: Dynamic Programming and Optimal Control: http://www.athenasc.com/dpbook.html Nonlinear Programming http://www.athenasc.com/nonlinbook.html Parallel and Distributed Computation: Numerical Methods http://www.athenasc.com/pdcbook.html i hope you all understand my meaning behind searching out these solutions. it is more to help me do the problems and improve my understanding, then anything else. like i said, any help would be appreciated. strut911Article: 39189
strut911 wrote: > > > Interesting post. You want solutions manuals to > > help you decide whether to buy a book,... > > Well, ... at least you're original. > > > > [-Rick-] > > heh. yeah, i never start a design without a spec, and i never go on a > long drive without a map. i do buy books without manuals, but if i am > trying to learn something new, then i would like some kind of > pass/fail criteria to tell me if i am on the right track or not. > having a solutions manual will not be the driving force behind buying > a book, but it will make me think that i have a decent shot at > learning the book material thoroughly, instead of guessing if i am > correct on my answers or not. especially since the graduate texts that > i enjoy perusing can sometimes be esoteric and i can't ask my nearest > manager how to correctly solve the problems. ha ha...that was a joke. > most of my managers are marketing people. anyways, i know many > engineers that enjoy learning new things and buying techie books. > having a solutions manual to go with the book would usually be icing > on the cake because a manual is basically a treasure trove of useful > examples. maybe to get things started, i will post some interesting > solutions manuals i have found online: > > here are some that are great for differential equations...computing > and modeling them, and also applying linear algebra to solve them: > http://www.prenticehallmath.com/epmanuals/ > > here are some from prof bertsekas at MIT. he is the > optimization/linear programming guru there, although he seems very > biased towards auction algorithms: > > Dynamic Programming and Optimal Control: > http://www.athenasc.com/dpbook.html > > Nonlinear Programming > http://www.athenasc.com/nonlinbook.html > > Parallel and Distributed Computation: Numerical Methods > http://www.athenasc.com/pdcbook.html > > i hope you all understand my meaning behind searching out these > solutions. it is more to help me do the problems and improve my > understanding, then anything else. like i said, any help would be > appreciated. > strut911 I'm with you, man. And besides, there are no problems in Rick's book for which the answers have been withheld. :-) Jerry -- Engineering is the art of making what you want from things you can get. -----------------------------------------------------------------------Article: 39190
Guy Schlacter wrote: > > QuartusII v2.0 just released Friday and has been producing very good > results for both this new family and ApexII. When is Quartus web edition going to include Acex 1k devices? > As far as GATE COUNTING, every vendor and family uses differnet > nomenclature. For the user, you are best off descregarding gate counts > and comparing > 4input LUTs > Available Memory counts > Other dedicated Resources Multipliers etc. > > Best of Luck, > Guy Schlacter > Altera Corp. > > "Steve Holroyd" <spholroyd@iee.org> wrote in message > news:b623f4cf.0201111039.2a16155@posting.google.com... > > > I am currently task of recommending the largest, fastest and most > > memory FPGA that's readily available the first half of this year for a > > FPGA Array Card. > > > > The choices have been narrowed down to two families Altera's APEX-II > > (EP2A70) and XILINX Virtex-II (XC2V6000). > > > > Which can operate at the highest speed? > > > > Steve > > -- > Posted via Mailgate.ORG Server - http://www.Mailgate.ORG -- ___ ___ / /\ / /\ / /__\ Russell Shaw, B.Eng, M.Eng(Research) / /\/\ /__/ / Victoria, Australia, Down-Under /__/\/\/ \ \ / \ \/\/ \__\/ \__\/Article: 39191
--------------C8015D2FAA1A3463F099345D Content-Type: text/plain; charset=us-ascii; x-mac-type="54455854"; x-mac-creator="4D4F5353" Content-Transfer-Encoding: 7bit Your gut feel is right. There is an exception, though. When you compare two Gray-coded counters, you will not get a glitch, since only one bit in each counter can change asynchronously. But otherwise, beware! You may want to read http://www.xilinx.com/support/techxclusives/MovingData-techX16.htm Peter Alfke, Xilinx Applications ========================== David Miller wrote: > For Virtex style architectures (and probably XC4000), can comparason > statements of the form > > o <= (a = b) > o <= (a < b) > > even when b might be constant, glitch? ie is it async safe[1]? > > My gut feeling is that it isn't, even when synthesized to take advantage > of fast carry chain compares. > > [1] Ordinarily, this question doesn't come up. In this case, I am > dealing with an external device whose register port is asynchronous. > > -- > David Miller, BCMS (Hons) | When something disturbs you, it isn't the > Endace Measurement Systems | thing that disturbs you; rather, it is > Mobile: +64-21-704-djm | your judgement of it, and you have the > Fax: +64-21-304-djm | power to change that. -- Marcus AureliusArticle: 39192
Actually, Spectrum Digital makes the PP510. The XDS510 is made by
TI. There is a technical document on JTAG/MPSD that might help. Go to
dspvillage.ti.com and search for "JTAG/MPSD". There should be a link for
the Emulation Technical Reference. I'm not sure if this is going to help.
People who make evaluation boards using TI chips have to make their own
drivers. TI therefore supplies them with an "emulation porting kit". Check
the dspvillage and you should be able to find something about this as
well. Hopefully this will give you the information you need if the
JTAG/MPSD document does not.
On Sun, 3 Feb 2002, Mark D'Sylva wrote:
> TI does not make the XSD510, it is made by Spectrum Digital. Here a link:
> http://www.spectrumdigital.com/
>
> Mark
> --
>
> http://www.dsylva-tech.ca
> BMW performance chips for E34 M5 and E36's
> Chips for E30 and E34 currently in development!
>
>
>
> "rickman" <spamgoeshere4@yahoo.com> wrote in message
> news:3C5D681C.EBD7700F@yahoo.com...
> > I am designing a line of DSP boards containing FPGAs and a single chip
> > micro all on the JTAG chain. I want to be able to test the production
> > boards using JTAG boundary scan. It looks like I can use the XDS510
> > emulator from TI for emulation. I can also do everything else that I
> > want to do on this scan chain with the other chips.
> >
> > I have been looking for some information on the XDS510 so that I might
> > be able to use it as my boundary scan hardware. This would make the
> > testing and interface consistent and simple. But so far I have found
> > none. TI support is having trouble understanding the question. The first
> > line of help seems to focus on their "canned" answers on using the
> > emulator for code debugging rather than to try to understand my problem.
> >
> > Does anyone have ideas on the best way to use the XDS510 JTAG connector
> > on my board for boundary scan testing? Is there sufficient information
> > on the PC interface to the XDS510 to let me write software to drive test
> > vectors into the board? Or are there other XDS510 compatible emulators
> > that will let me do both code debugging (Code Composer Studio) and
> > boundary scan?
> >
> >
> > --
> >
> > Rick "rickman" Collins
> >
> > rick.collins@XYarius.com
> > Ignore the reply address. To email me use the above address with the XY
> > removed.
> >
> > Arius - A Signal Processing Solutions Company
> > Specializing in DSP and FPGA design URL http://www.arius.com
> > 4 King Ave 301-682-7772 Voice
> > Frederick, MD 21701-3110 301-682-7666 FAX
>
>
>
---
main(){int j=1234;char t[]=":@abcdefghijklmnopqrstuvwxyz.\n",*i=
"iqgbgxmdbjlgdv.lksrqek.n";char *strchr(const char *,int); while
(*i){j+=strchr(t,*i++)-t;j%=sizeof t-1;putchar(t[j]);}return 0;}
Article: 39193I spoke with TI support and the initial answer was the DSP porting kit. But I was told this was for writing your own special emulator, not for boundary scan. I don't know if this would help, but the DPK costs $10,000. Not too good for this application since I am trying to cheap out and reuse my existing XDS510 boards and pods. I was looking back through my email I received from a post in the Yahoo! message boards where he forwards an email he received from TI support excerpted here. "For boundary scan testing, TI uses another tool. It is called Advanced Support System for Emulation and Test (ASSET). It is PC-Based, needs Windows and INCLUDES a XDS 510 card. The EMULATION in the ASSET name does NOT refer to DSP emulation but to emulating devices and clusters in general using JTAG capabilities (e.g. EXTEST). " This sounds just like what I need except for the part about including an XDS510. I am trying to avoid buying yet another expensive piece of hardware. But I will call TI about this Monday and post what I find out. I am trying hard not to become a JTAG expert, but that may be what I need to do. I will also try contacting some of the other emulator vendors. If I have to buy another board, I may as well explore my options. Darrell Grainger wrote: > > Actually, Spectrum Digital makes the PP510. The XDS510 is made by > TI. There is a technical document on JTAG/MPSD that might help. Go to > dspvillage.ti.com and search for "JTAG/MPSD". There should be a link for > the Emulation Technical Reference. I'm not sure if this is going to help. Yes, I have read this document, but it only speaks about the interface to the DSP, not to the PC. > People who make evaluation boards using TI chips have to make their own > drivers. TI therefore supplies them with an "emulation porting kit". Check > the dspvillage and you should be able to find something about this as > well. Hopefully this will give you the information you need if the > JTAG/MPSD document does not. Yes, this is likely a kit defining the interface from Code Composer to whatever board you design. I am looking for the opposit, documentation on my software to their hardware in the PC. > On Sun, 3 Feb 2002, Mark D'Sylva wrote: > > > TI does not make the XSD510, it is made by Spectrum Digital. Here a link: > > http://www.spectrumdigital.com/ > > > > Mark > > -- > > > > http://www.dsylva-tech.ca > > BMW performance chips for E34 M5 and E36's > > Chips for E30 and E34 currently in development! > > > > > > > > "rickman" <spamgoeshere4@yahoo.com> wrote in message > > news:3C5D681C.EBD7700F@yahoo.com... > > > I am designing a line of DSP boards containing FPGAs and a single chip > > > micro all on the JTAG chain. I want to be able to test the production > > > boards using JTAG boundary scan. It looks like I can use the XDS510 > > > emulator from TI for emulation. I can also do everything else that I > > > want to do on this scan chain with the other chips. > > > > > > I have been looking for some information on the XDS510 so that I might > > > be able to use it as my boundary scan hardware. This would make the > > > testing and interface consistent and simple. But so far I have found > > > none. TI support is having trouble understanding the question. The first > > > line of help seems to focus on their "canned" answers on using the > > > emulator for code debugging rather than to try to understand my problem. > > > > > > Does anyone have ideas on the best way to use the XDS510 JTAG connector > > > on my board for boundary scan testing? Is there sufficient information > > > on the PC interface to the XDS510 to let me write software to drive test > > > vectors into the board? Or are there other XDS510 compatible emulators > > > that will let me do both code debugging (Code Composer Studio) and > > > boundary scan? -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 39194
the following is my code.is it ok?
module CRC32_D8 (
Crc8_Din,
Crc32_Ok
);
/*************************************\
* *
* module all input/ouput define *
* *
\*************************************/
input [`Crc8_Din] Crc8_Din;
output Crc32_Ok;
// polynomial: (0 32)
// data width: 8
// convention: the first serial data bit is D[7]
/*************************************\
* *
* module all variable define *
* *
\*************************************/
wire [`Crc32_Out] Crc32_Out;
wire Crc32_Ok;
/*************************************\
* *
* module funtion implemention *
* *
\*************************************/
assign Crc32_Ok = (Crc32_Out==32'hc704dd7b)?1:0;
assign Crc32_Out = nextCRC32_D8(Crc8_Din,Crc32_Out);
/*************************************\
* *
* funtion implemention *
* *
\*************************************/
function [`Crc32_Out] nextCRC32_D8;
input [`Crc8_Din] Data;
input [`Crc32_Out] CRC;
reg [`Crc8_Din] D;
reg [`Crc32_Out] C;
reg [`Crc32_Out] NewCRC;
begin
D = Data;
C = CRC;
NewCRC[0] = D[0] ^ C[24];
NewCRC[1] = D[1] ^ C[25];
NewCRC[2] = D[2] ^ C[26];
NewCRC[3] = D[3] ^ C[27];
NewCRC[4] = D[4] ^ C[28];
NewCRC[5] = D[5] ^ C[29];
NewCRC[6] = D[6] ^ C[30];
NewCRC[7] = D[7] ^ C[31];
NewCRC[8] = C[0];
NewCRC[9] = C[1];
NewCRC[10] = C[2];
NewCRC[11] = C[3];
NewCRC[12] = C[4];
NewCRC[13] = C[5];
NewCRC[14] = C[6];
NewCRC[15] = C[7];
NewCRC[16] = C[8];
NewCRC[17] = C[9];
NewCRC[18] = C[10];
NewCRC[19] = C[11];
NewCRC[20] = C[12];
NewCRC[21] = C[13];
NewCRC[22] = C[14];
NewCRC[23] = C[15];
NewCRC[24] = C[16];
NewCRC[25] = C[17];
NewCRC[26] = C[18];
NewCRC[27] = C[19];
NewCRC[28] = C[20];
NewCRC[29] = C[21];
NewCRC[30] = C[22];
NewCRC[31] = C[23];
nextCRC32_D8 = NewCRC;
end
endfunction
endmodule
Article: 39195
I've a circuit where 6 parallel output of a shift register go to one
of three rom selected via the
signal rate_sel applied to a demux, regarding this demux and taking in
account the fact that I've not
necessity to change the ROM very often (...order of days) I would want
to know if is better to use a
vhdl description of a demux with a clock or without a clock and which
of the following architecture is
more suitable for this :
library ieee;
use ieee.std_logic_1164.all;
entity demux_3x10 is
port(in_mux : in std_logic_vector(9 downto 0);
clk : in std_logic;
sel : in std_logic_vector(1 downto 0);
out_0 : out std_logic_vector(8 downto 0);
out_1 : out std_logic_vector(8 downto 0);
out_2 : out std_logic_vector(9 downto 0)
);
end demux_3x10;
architecture demux_3x10_arch of demux_3x10 is
begin
process (sel, in_mux, clk)
begin
if falling_edge(clk) then
case sel is
when "00" => out_0 <= in_mux(8 downto 0) ;
when "01" => out_1 <= in_mux(8 downto 0) ;
when "10" => out_2 <= in_mux ;
when others => null;
end case;
end if;
end process;
end demux_3x10_arch ;
*********************** OR THIS ONE SUGGESTED BY MARK
*****************************
library ieee;
use ieee.std_logic_1164.all;
entity demux_3x10 is
port(in_mux : in std_logic_vector(9 downto 0);
clk : in std_logic;
sel : in std_logic_vector(1 downto 0);
out_0 : out std_logic_vector(8 downto 0);
out_1 : out std_logic_vector(8 downto 0);
out_2 : out std_logic_vector(9 downto 0)
);
end demux_3x10;
architecture demux_3x10_arch of demux_3x10 is
begin
process (sel, in_mux, clk)
begin
if falling_edge(clk) then
case sel is
when "011" => out_0 <= in_mux;
out_1 <= (others => '0');
out_2 <= (others => '0');
when "100" => out_0 <= (others => '0') ;
out_1 <= in_mux;
out_2 <= (others => '0');
when "110" => out_0 <= (others => '0') ;
out_1 <= (others => '0');
out_2 <= in_mux ;
when others => out_0 <= (others => '0') ;
out_1 <= (others => '0');
out_2 <= (others =>
'0');
end case;
end if;
end process;
end demux_3x10_arch ;
Article: 39196I coudn't understand why for a gated clock project I was fighting to obtain 150MHz and now with the clkEnable version of the same I'm fighting to obtain only 70MHz, to what this is due ?? All suggest me to use clkEnable if there are situation where clock enable is not a must, is it really necessary in my project where I've a master clock from which I obtain 3 derived clock in the gated clock version and 3 enable signal (...via a programmable counter) in the clock enable version. And to put in my thesis and based on your experience please add some lines to the following: *********************************************************************************************** Clock Enable Clock Enable Clock Enable Clock Enable Clock Enable Clock Enable Clock Enable *********************************************************************************************** PRO P1) Immunity to temperature change P2) Only CLK recognized by synthesizer VERSUS V1) slow (.. I don't know why) v2) More power dissipated because all the circuit run at f_clk *********************************************************************************************** Gated Clock Gated Clock Gated Clock Gated Clock Gated Clock Gated Clock Gated Clock Gated Clock *********************************************************************************************** PRO P1) Less power dissipated because not all the circuit run at f_clk P2) VERSUS V1) Derived clock not recognized by synthesizer v2)Article: 39197
In my project I'm using 3 set of values with different dimension, I mean 384x12 bits , 512x12 bits and 768x12 bits , to choose between them I could use a demux-BLOCKRAM-mux chain or to fit each of these block in a zero padded 1024x12 bits and use the addressing capabilities of a Virtex BLOCKRAM 3072x16. with very disappoint I found that this last solution (implemented with the CORE blockRAM single port) may run at a maximum of 60MHZ on a VIRTEX1000BG560-4 and 90MHz on VirtexE600-6 so my question is : 1) is this normal ?? 2) when I read 300 MHz on FPGA are we talking of a flip flop ?? 3) this is the most important question : how can I obtain more to solve the same problem with the VIRTEXE600-6 ?? Thanks AntonioArticle: 39198
strut911@hotmail.com (strut911) wrote in message news:<4379d3e0.0202031347.599a779f@posting.google.com>... > > Interesting post. You want solutions manuals to > > help you decide whether to buy a book,... > > Well, ... at least you're original. > > > > [-Rick-] > > heh. yeah, i never start a design without a spec, and i never go on a > long drive without a map. i do buy books without manuals, but if i am > trying to learn something new, then i would like some kind of > pass/fail criteria to tell me if i am on the right track or not. > having a solutions manual will not be the driving force behind buying > a book, but it will make me think that i have a decent shot at > learning the book material thoroughly, instead of guessing if i am > correct on my answers or not. There's a simple solution. Buy an easier book that you CAN answer the questions. Then when you can do that move on to more difficult books. Mummy won't hold your hand when you start work so I'd say it'd be better if you just had a bit more confidence in your own ability. Learning by doing is a good way of learning but if you do understand the theory not ateempting end of chapter questions won't do that much harm. You can ALWAYS find a book with answers to enough problems if you look hard enough.Article: 39199
Hi. I use 2 DCM's cause every DCM compensate on a different PCB trace length. I am using source-synchronous approach distributing on the PCB both data and clock. Every target device get a clock shifted by the his DCM that get a feedback from the middle of the relevant trace. I hope that it is clearer. ThankX Nurit. Peter Alfke <palfke@earthlink.net> wrote in message news:<3C5D72CD.21A187C9@earthlink.net>... > Why do you want to use two DCMs? I would use only one, and rely > on the very low skew in the clock distribution. With a common DCM > you obviously have no differential jitter to worry about. The > deterministic skew between the two output pins can be kept well > below 100 picoseconds. > > Peter Alfke, Xilinx Applications > ====================================== > Nurit Eliram wrote: > > > Hi . > > I am going to use virtex-II for clock distribution. > > > > I have one clock input that goes to 2 seperate output pins, > > via 2 seperated DCM devices. > > The DCM will have feed back from the middle on the PCB trace, > > for delay compensation. > > > > Assuming no jitter on the input clock (CLKIN), > > and assuming that the feedback to the output DCM > > has the same length, > > what is that maximum skew between the two output clocks ?? > > > > Can it be that one DCM will have a full period jitter to one > > direction while the other DCM will; have full period jitter in > > the opposite direction ? > > > > ThankX Nurit
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