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Do you think that the synthesizer (XST or Synplify) is enough intelligent to understand that the location having 0 inside are not used and it could optimize them (... I don't know if this is possible or just a dream ?? ) AntonioArticle: 39076
Peter's original post on the topic: >My sugestion is to build any counter you want, synchronous or ripple, but have >a one-bit prescaler toggle-flip-flop generate the clock. This prescaler must >use the Xilinx CE feature, which really is a multiplexer in the D input. >Since CE changes asynchronously, but does not affect the clock, you never get >a runt clock pulse, but you might ( once in a blue moon) get a longer Q >delay. It will be many thousands (millions?) of years between the worst >happening, when this extra metastable delay swallows one incoming clock tick. > >Peter Alfke, Xilinx Applications On Wed, 30 Jan 2002 14:50:30 -0800, Peter Alfke <peter.alfke@xilinx.com> wrote: >As usual, I agree with Phil in principle. A man of Principals! >His statements are 100% correct, but we disagree on the seriousness >of the problem. Metastability "usually" resolves itself in a small >fraction of the 10 ns period (100 MHz clock rate). >So the issue is: How often does it not resolve itself, and would you >ever see oscillations ? Tragically, in this case you need to read the your solution (above), and my reply more carefully. The output of the FF with the CE being driven by the asynchronous signal is being used as the clock for the following counter. Therefore there is NO resolution time available, and runt output pulses WILL cause problems. >Phil thinks it can happen more often than I think it might happen. >In the deplorable absence of quantitative data, the argument must remain >unresolved. Not in this case, as there is no resolution time. Things would be different if the main counter was clocked by the 100MHz, and the control FF output was used as the CE for the main counter, or the control FF was a two stage prescaler circuit, that had some metastability resolution time built in. But your recommendation (above) has the single FF prescaler output used as the clock of the main counter. >Peter Alfke and later: >There is no reason to assume that they are any different (CE or D). >But there are mitigating circumstances: >The clock rate is modest, only 100 MHz, which allows for an extra 5 ns of metastable >delay. No. No resolution time available. Q is clock to following counter >The CE changes are most likely less than 1 MHz (I assume) >The Q output only clocks one flip-flop.(Note that I shift my position a bit, now >assuming a 2-bit ripple prescaler, not just one bit). ;-) Good back peddle :-) >What is the likelyhood ( expressed as MTBF) for an extra 5 ns of metastable delay when >the clock is 100 MHz and the asynchronous input changes about 1 million times per >second? I agree that this is better. >The 1997 Xilinx app note XAPP094 documents the archaic XC4005-3 at an MTBF of 100 000 >years for metastable delay of 2 ns, ( really 1 million years at 10 MHz clock and 1 MHz >data, but that translates to 100 000 years at the ten times higher clock rate) and the >MTBF increases ten decimal orders of magnitude for every additional ns. That's three >additional ns in this case. "ten decimal orders of magnitude" ???? I seem to remember the slope is more like an improvement of a factor of 40 per each additional ns. When di the slope change to 10^30 ????? >That means an MTBF of 10exp35, which is many times the age of the universe. > >Peter Alfke, Xilinx Applications >Philip Freidin wrote: > >> The asynchronous CE signal is just as bad to a FF as an asynchronous D >> signal. The FF can go metastable, and you can get runt low or high >> pulses from the FF. Since this feeds your follow on counter as its >> clock, the results will be sub-optimal. >> >> The only safe way to use the CE is with a synchronous signal, so the >> asynchronous control signal should be passed through a multi stage >> synchronizer, before being presented to the CE pin. >> >> Philip Freidin >> >> Philip Freidin >> Fliptronics Still having fun, Philip Philip Freidin FliptronicsArticle: 39077
Hi every one I am using sopc board from altera, it hold an APEX20k400E, I am using synplicity 6.2.4 to synthesis and then use quartus II 1.1 to P&R, my design is an cpu, the cpu hold one cpu core(design by me), an interconnect network(design by other), and some slave device(design by my team member) the cpu core have two master port to fetch instruction and data the interconnect network have 8 master and 16 slave, any unuse port's output pin will not connect and input pin will assign 0, I run pre syn rtl simulation, all ok,but after burn on the board, it is error, I want to know possible cause of synthesis/simulation mismatch.Article: 39078
Hello, I'm writing a Win NT Driver for my PCI board in which I've used a FPGA to instantiate an Altera MegaCore Function for bus interfacing (bus mastering access to system memory). My question is: have I to initialize the function by writing a proper value to PCI command register in my driver? Looking at some downloaded samples the answer seems to be "NO" and it sounds a bit strange to me! I've recently read all the docs about the PCI Function: a bus master has to write to the configuration register and set the MegaCore to be a Master. Perhaps the Bios does this job, but I'm not familiar with Bios enumerating process. Are there any programming guidelines or suggestions? Thanks for help. MarcoArticle: 39079
This is a multi-part message in MIME format. --------------6912D1F0AE33766409293B9D Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Scott Thibault wrote: > > What are you're thoughts about Java and other bytecode processors? > > Is anyone out there using them? > > We are developing a bytecode processor for a high-level language (i.e. NOT > Java), and I'm curious as to what people think of these things. > > --Scott Thibault > Green Mountain Computing Systems, Inc. > http://www.gmvhdl.com Some of my collegues are/have been working in that area. Here is a paper about their project: http://www-md.e-technik.uni-rostock.de/veroeff/jsm-smartdev.pdf May be you'll find that interesting. JensArticle: 39080
Hi, A friend gave me an Xilinx XC3020-70 FPGA. The problem is that I can't find any software to compile verilog for that chip. Does anyone here know where I can get a compiler/programmer? Thanks in advance, Remco PoelstraArticle: 39081
Hal Murray wrote: > > >We are developing a bytecode processor for a high-level language (i.e. NOT > >Java), and I'm curious as to what people think of these things. Yes I'm interested in this as well. I went for a job with one of these companies before Xmas. I passed as the work wasn't for me, but I came away wondering whether, in time, I was going to find my self out of a job unless I retrained in Java (I do high level apps that just happen to run on embedded processors). > It's a great way to save memory but you pay for it in decoding > time/resources. Memory is cheap these days. I think the real motivation is the saving on development costs. Obviously they aren't going to replace the micros in washing machines but for something like a bank ATM the cost of the processor is almost an irrelevance. Question is, "is there a saving in development cost"? Or is it just that old ageism thing again, all the new kids on the block come out of school already knowing Java, us oldies don't and everybody knows that a company is much better off with a room full of 20 somethings than a room full of 40 somethings, don't they :-(. After all, the 20 somthings are going to be with the company for 40 years instead of 20, aren't they! > Do you have a lot of code? > > Compare with a RISC type system, or an even wider instruction > as used in (old) microcoded machines. FPGAs can do many things > in parallel. It's harder to take advantage of that if you > are starting from an instruction set that thinks you have a > single ALU. Are you sure about this. As Java is an OO language (I think!) it would seem to make sense for the processors to be architured to take advantange of this, do they? (Genuine question, I have no idea of the answer) > Another potential advantage is that you might be able to > get an off-the-shelf programming environment if you pick > a byte code like Java that many other people are using. Yep, as above, however I don't think it's just a case of getting an off the shelf environment, but the SAME off the shelf environment (that they already use for their Web programming for example). But this goes further. Is the motivation that you can use the SAME programmers? (as for your web development), ignoring the fact that the the two disciplines require completely different analyticaly skills, or do they? Does the processor cross this bridge for you? I've no idea, if it does I'm going to start to get worried. Tim > -- > These are my opinions, not necessarily my employer's. I hate spam. ditto (perhaps I should make myself a sigArticle: 39082
> Scott Thibault wrote: > > > > What are you're thoughts about Java and other bytecode processors? > > > > Is anyone out there using them? > > > > We are developing a bytecode processor for a high-level language (i.e. NOT > > Java), and I'm curious as to what people think of these things. > > > > --Scott Thibault Some twenty-odd years ago Western Digital made a processor called WD90. It run the UCSD Pascal P-code as its native language. Another processor resembling current bytecode processors is the HP 3000 multi-user system of the late 1970's. It was a computer too much before its time. A bait for Ms Rather: The current bytecode processors run a code very near Forth, right? A question: What is the difference between a CISC processor with peculiar instruction set and a bytecode processor? Tauno Voipio tauno voipio @ iki fiArticle: 39083
There is someone that know Proc board and the ProcWizard by Gidel? I'm having a lot of problems and I need help. -- Posted via Mailgate.ORG Server - http://www.Mailgate.ORGArticle: 39084
Hi I got a XPLA3 demo board from Insight. On the XCR3256XL there is a pre burned counter program. It is possible to download the files from: http://www.insight-electronics.com/Memec/iplanet/link1/XPLA3Reference%20Design.ZIP I created a new project an embedded the vhdl files. Then i synthesized the code, but i got errors while implementing. Annotating constraints to design from file "C:/projects/XPLA3/Counter/counter.ucf" ... WARNING:NgdBuild:383 - A case sensitive search for the INST, PAD, or NET element refered to by a constraint entry in the UCF file that accompanies this design has failed, while a case insensitive search is in progress. The result of the case insenstive search will be used, but warnings will accompany each and every use of a case insensitive result. Constraints are case sensitive with respect to user-specified identifiers, which includes names of logic elements in a design. For the sake of compatibility with currently existing .xnf, .xtf, and .xff files, Software will allow a case insensitive search for INST, PAD, or NET elements referenced in a .ucf file. WARNING:NgdBuild:385 - Found case insensitive match for NET name 'CLK'. NET is 'clk'. WARNING:NgdBuild:385 - Found case insensitive match for NET name 'LCD_COM'. NET is 'lcd_com'. WARNING:NgdBuild:385 - Found case insensitive match for NET name 'ONE_DP'. NET is 'one_dp'. WARNING:NgdBuild:385 - Found case insensitive match for NET name 'RESET'. NET is 'reset'. WARNING:NgdBuild:385 - Found case insensitive match for NET name 'TEN_DP'. NET is 'ten_dp'. ERROR:NgdBuild:397 - Could not find NET 'one_out(0)' in design 'counter'. NET entry is 'NET "one_out(0)" LOC = ":PIN91"; ' ERROR:NgdBuild:397 - Could not find NET 'one_out(1)' in design 'counter'. NET entry is 'NET "one_out(1)" LOC = ":PIN90"; ' ERROR:NgdBuild:397 - Could not find NET 'one_out(2)' in design 'counter'. NET entry is 'NET "one_out(2)" LOC = ":PIN88"; I specified the ucf file in the implementaion proberties. What is my mistake? The download of the jed file into the cpld works . ThanksArticle: 39085
Andy Peters <andy@exponentmedia.nospam.com> wrote: :> Implemented 1/2 Band 51-tap FIR using Coregen + Foundation. :> Pre-synthesis simulation looks excellent, however when the filter is :> loaded into Spartan-II the output looks like complete random junk. All :> timing is met. Probably an entirely different problem, but I am having difficulty getting the half-band decimator to work. One odd feature is that 'ngdbuild' is reporting a net within the Coregen module that "has no driver". All the inputs to the module are connected, so surely there shouldn't be an unconnected input pin inside ? Richard. http://www.rtrussell.co.uk/Article: 39086
Hi everyone I use synplicity 6.2.4 to syn and then use quartus 1.1 to P&R, the target device is APEX20k400e after synthesis, I want to run post synthesis simulation, but the value of some FF register do not change at all. why?Article: 39087
"Goteb" <goteb@katamail.com> wrote in message news:46a8c61d209992a5fd8e350ef2f72beb.9826@mygate.mailgate.org... > There is someone that know Proc board and the ProcWizard by Gidel? > I'm having a lot of problems and I need help. > I've found that the guys at Gidel are extremely helpful. Why don't you get in touch via your reseller. FWIW I'm using a Proc 20KE board with 3 600KE-1X devices. I'm using it standalone without any PCI hosting or the Gidel software. Very happy with the service of Gidel and of Parallel Systems here in the UK. BTW This board is excellent if you want large devices, a huge amount of i/o and SDRAM. A bit pricey, but probably the only board with many hundreds of IO in an intelligently arranged board. www.gidel.com for details. Can also use it as a hosted coprocessor accessed via C++ programming. Email me at pauljnospambaxter@hotmail.com if you would like further correspondence about specific problems... removing the nospam part of the email address. Or post here if you think it has general relevance. PaulArticle: 39088
"Tim Sinkins" <timothy.sinkins@alcatel-ke.de> wrote in message news:3C591458.204081B7@alcatel-ke.de... > > > Hal Murray wrote: > > > > >We are developing a bytecode processor for a high-level language (i.e. NOT > > >Java), and I'm curious as to what people think of these things. > > Yes I'm interested in this as well. I went for a job with one of > these companies before Xmas. I passed as the work wasn't for me, > but I came away wondering whether, in time, I was going to find my > self out of a job unless I retrained in Java (I do high level apps > that just happen to run on embedded processors). > > > It's a great way to save memory but you pay for it in decoding > > time/resources. Memory is cheap these days. > > I think the real motivation is the saving on development costs. > Obviously they aren't going to replace the micros in washing > machines but for something like a bank ATM the cost of the > processor is almost an irrelevance. > > Question is, "is there a saving in development cost"? This is the main goal in our case, at least. We've focused on a high-level scripting language to simplify software development. Code density does become important when it comes to selecting a compilation vs. bytecode processor approach. Using compilation may lead to very bulky code. > Or is it just that old ageism thing again, all the new kids on > the block come out of school already knowing Java, us oldies > don't and everybody knows that a company is much better off with > a room full of 20 somethings than a room full of 40 somethings, > don't they :-(. > After all, the 20 somthings are going to be with the company for > 40 years instead of 20, aren't they! > > > Do you have a lot of code? > > > > Compare with a RISC type system, or an even wider instruction > > as used in (old) microcoded machines. FPGAs can do many things > > in parallel. It's harder to take advantage of that if you > > are starting from an instruction set that thinks you have a > > single ALU. > > Are you sure about this. As Java is an OO language (I think!) > it would seem to make sense for the processors to be architured > to take advantange of this, do they? (Genuine question, I have > no idea of the answer) I think that is what Hal was driving at. Take for instance the Pentium. Although, the instruction set has been modified it is still fundamentally tied to the 8086 instruction set that was not designed for superscalar execution. This makes implementing instruciton level parallelism in the Pentium much more complex than necessary. So much so, that it has driven Intel to experiment with the Itanium. --Scott Thibault Green Mountain Computing Systems, Inc.Article: 39089
You haven't lived!
Rick Filipkiewicz wrote:
>
>
> Karnaugh - what's that ? :-).
>
> I got into digital design with the PAL/ABEL generation &, since those nice people
> at Berkley supplied Expresso and Presto reduction for me, I've never done a K-map
> in my life [no self-timed design] and have rarely had to DeMorganise by hand.
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 39090
Yes Synplify is brain dead enough to mess up a ROM by optimizing zero
locations in an inferred ROM.
Antonio wrote:
> Do you think that the synthesizer (XST or Synplify) is enough
> intelligent to understand that the location having 0 inside are not
> used and it could optimize them (... I don't know if this is possible
> or just a dream ?? )
>
> Antonio
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 39091> Slightly more serious now - if your application is not a mass product, > you may find various dedicated PCI chips more convenient (AMCC,PLX). > You don't have to worry about timing, you can use a significantly smaller > PLD and the thing doesn't have to be fully configured at system start. I think you're right. So I program a FPGA to obtain data, store it to RAM and subsequently offer it to a dedicated PCI chip. Is somebody familiar with any of these chips? Please give me some details and/or suggestions. regards, PeterArticle: 39092
Anyone, Is there someone who is willing to share their verilog code for a 72,64 bit extended hamming code decoder (error corrector)? We are looking at error correction, and would appreciate any URL to some actual working code. Thanks, AustinArticle: 39093
Hello, Not long ago I started to evaluate and get acqainted with FPGA programming using VHDL design flow (Xilinx ISE). Recently I've been told that the VHDL programming style can have significant effects on timing. Does somebody have any advices regarding a convenient style of programming, or tell me where I can get "to the point" documents on internet about meeting time critical conditions. Also comments about improving timing with floorplanner and timing constraints are welcome. Thanx, PeterArticle: 39094
Remco Poelstra wrote: > > Hi, > > A friend gave me an Xilinx XC3020-70 FPGA. The problem is that I can't > find any software to compile verilog for that chip. > Does anyone here know where I can get a compiler/programmer? > > Thanks in advance, > > Remco Poelstra Try "WebPack" from the Xilinx site. It's free, and the simulator license you will have to get is free as well. Works nicely for smaller designs. -- ------------------------------ "Science is the game we play with god to find out his rules." ------------------------------Article: 39095
axel wrote: > Remco Poelstra wrote: > >>Hi, >> >>A friend gave me an Xilinx XC3020-70 FPGA. The problem is that I can't >>find any software to compile verilog for that chip. >>Does anyone here know where I can get a compiler/programmer? >> >>Thanks in advance, >> >>Remco Poelstra >> > Try "WebPack" from the Xilinx site. It's free, and the simulator license > you will have to get is free as well. Works nicely for smaller designs. > Forgotten to mention, I've webpack for the Xilinx Spartan II we get from uni. It does not support the XC3020-70. Thanks for the reply, Remco PoelstraArticle: 39096
> > > Btw Ulf, What's your idea about MSP430 series suggested by Jim > Granville? > > > > Ulf is an Atmel representative, so it is not likely he will say much > > about a TI product. He would be ill advised to say anything good for the > > sake of his job and won't say anything bad for being thought of as > > badmouthing the competition. :) Even if we ask... > > Yes, I can, There are many applications where the MSP430 is excellent including but not limited to "road-filling" in China. Especially the larger packages are suitable :-) -- Best Regards Ulf at atmel dot com These comments are intended to be my own opinion and they may, or may not be shared by my employer, Atmel Sweden.Article: 39097
On Thu, 31 Jan 2002 10:40:10 +0100, Remco Poelstra <remco@beryllium.net> wrote: >Hi, > >A friend gave me an Xilinx XC3020-70 FPGA. The problem is that I can't >find any software to compile verilog for that chip. >Does anyone here know where I can get a compiler/programmer? > >Thanks in advance, > >Remco Poelstra None of the current sw , or any version for the last 5 years handles these chips. The effort required to get sw to handle this old chip exceeds the cost of just getting something current like a spartan or spartan-2 and using the current free sw from Xilinx. Use it as a paper weight, or a tie clip, or if your chair is unstable, place it under the leg with the largest gap :-) Philip Philip Freidin FliptronicsArticle: 39098
As the warning say, your names do not match perfectly. For example, change the UCF entry from 'clk' to 'CLK'. "Gunther" wrote > I got a XPLA3 demo board from Insight. > On the XCR3256XL there is a pre burned counter program. > It is possible to download the files from: > http://www.insight-electronics.com/Memec/iplanet/link1/XPLA3Reference%20Design.Z IP > > I created a new project an embedded the vhdl files. > Then i synthesized the code, but i got errors while implementing. > > Annotating constraints to design from file > "C:/projects/XPLA3/Counter/counter.ucf" ... > WARNING:NgdBuild:383 - A case sensitive search for the INST, PAD, or NET element > refered to by a constraint entry in the UCF file that accompanies this design > has failed, while a case insensitive search is in progress. The result of the > case insenstive search will be used, but warnings will accompany each and > every use of a case insensitive result. Constraints are case sensitive with > respect to user-specified identifiers, which includes names of logic elements > in a design. For the sake of compatibility with currently existing .xnf, > .xtf, and .xff files, Software will allow a case insensitive search for INST, > PAD, or NET elements referenced in a .ucf file. > WARNING:NgdBuild:385 - Found case insensitive match for NET name 'CLK'. NET is > 'clk'. > WARNING:NgdBuild:385 - Found case insensitive match for NET name 'LCD_COM'. NET > is 'lcd_com'. > WARNING:NgdBuild:385 - Found case insensitive match for NET name 'ONE_DP'. NET > is 'one_dp'. > WARNING:NgdBuild:385 - Found case insensitive match for NET name 'RESET'. NET is > 'reset'. > WARNING:NgdBuild:385 - Found case insensitive match for NET name 'TEN_DP'. NET > is 'ten_dp'. > ERROR:NgdBuild:397 - Could not find NET 'one_out(0)' in design 'counter'. NET > entry is 'NET "one_out(0)" LOC = ":PIN91"; > ' > ERROR:NgdBuild:397 - Could not find NET 'one_out(1)' in design 'counter'. NET > entry is 'NET "one_out(1)" LOC = ":PIN90"; > ' > ERROR:NgdBuild:397 - Could not find NET 'one_out(2)' in design 'counter'. NET > entry is 'NET "one_out(2)" LOC = ":PIN88"; > > I specified the ucf file in the implementaion proberties. > > What is my mistake? > > The download of the jed file into the cpld works . >Article: 39099
With dear old XACT you could play with Karnaugh maps directly. "Ray Andraka" wrote > You haven't lived! > > Rick Filipkiewicz wrote: > > > > > > > Karnaugh - what's that ? :-). > > > > I got into digital design with the PAL/ABEL generation &, since those nice people > > at Berkley supplied Expresso and Presto reduction for me, I've never done a K-map > > in my life [no self-timed design] and have rarely had to DeMorganise by hand.
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z