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COOL! A great conference at my Alma Mater! GO RIT!! rauletta@orci.com (Richard Auletta) wrote in message news:<b57a54ba.0201150808.10795814@posting.google.com>... > .. > > CALL FOR PAPERS > > 15th Annual IEEE International ASIC/SOC Conference > > September 25-28, 2002 > RIT Inn and Conference Center, Rochester, New York > > Driven by the rapid growth of the Internet, communication > technologies, pervasive computing, and wireless and portable consumer > electronics, Systems-on-Chip (SoC) have become a dominant issue in > today's ASIC industry. The transition from traditional Application- > Specific Integrated Circuits (ASIC) to SoCs has created new > challenges in Design Methods, Design Tools, Design Automation, > Manufacturing, Technology and Test. The ASIC/SOC Conference provides > a forum for sharing advances in ASIC and SoC technology and > applications. The 2002 Conference will offer three days of technical > papers and a full day of technical workshops. > > GENERAL INFORMATION > This year's ASIC/SOC Conference will be held at the Rochester Institute of > Technology Inn and Conference Center. Rochester New York is served by the > Greater Rochester International Airport and is within easy driving distance > of the Buffalo International Airport and most of New England. > Accommodations will be available for $79.00 a night at the RIT Inn. > Rochester, the third largest urban area in New York State, offers a wide > range of cultural, historic, and recreational activities within the relaxed > atmosphere of upstate New York. > > TECHNICAL SCOPE > Papers are invited which address new and previously unpublished results in > the following categories or in related areas. Proposals for tutorial > papers, tutorials, workshops, and panel sessions are also invited. The > best paper will be acknowledged with a best paper award. > > System on Chip Manufacturing Test and Verification > Design Tools Embedded Systems Novel Circuits & Structures > Design Methods Analog and Mixed Signal Computing Systems > Design Automation Applications Intellectual Property > > PAPER SUBMISSION > Electronic paper submission requires a 25 word condensed abstract for the > Advance Program, and the full paper, limited to five double-column IEEE > format pages, including figures and references. Please refer to the > conference web page at http://asic.union.edu for paper formatting and paper > submission as an Adobe PDF file. > > DEADLINE FOR PAPER SUBMISSION: APRIL 12, 2002 > NOTIFICATION OF PAPER ACCEPTANCE: MAY 31, 2002 > FINAL CAMERA-READY PAPERS DUE: JUNE 28, 2002 > > Please visit the Conference web site at http://asic.union.edu or contact > the ASIC/SOC Conference office at 301-527-0900 x104 for paper submission, > registration, and current conference information. > > ORGANIZING COMMITTEE > > General Chair Technical Program Chair Technical Program Co-Chair > P. R. Mukund John Chickanosky Dong Ha > RIT IBM Microelectronics Virginia Tech > prmeee@rit.edu chickano@us.ibm.com ha@vt.edu > > Publications Chair Steering Committee Chair Workshop Chair > Richard Auletta Thomas Bochner Ram Krishnamurthy > LSI Logic IBM Boblingen Lab Intel > rauletta@lsil.com tbuechner@de.ibm.com ramk@hf.intel.com > > > Sponsored by the IEEE Circuits and Systems Society > > ~ > ~Article: 38551
How can I force ngdBuild (in the Xilinx Foundation environment) to continue implementation if design has too many "errors". These errors are resulting from unconnected bus taps. I want to leave these taps unconnected, but NgdBuild complains that they have no load... results in 44 errors and premature ending of implementation. thanks adrianArticle: 38552
This is only for atmega323... Damir "Geir Atle Ward" <gaward@online.no> wrote in message news:oYY08.104$0W1.1652@news4.ulv.nextra.no... > Here: > ftp://www.atmel.com/pub/atmel/bsdl.zip > Geir A > > "DG_1" <dgacina@san.rr.com_no.spam> wrote in message > news:6YN08.101893$AI.27135658@typhoon.san.rr.com... > > Thanks Damir. > > Where I can get that file? > > (HR: Postovanje! Gdje mogu 'podici' taj filek?) > > -- D.G. > > > > "Damir Danijel Zagar" <dzagar@srce.hr> wrote in message > > news:a1urs3$ub8$1@sunce.iskon.hr... > > > Just to mention... BSDL file for ATmega128 is available. > > > > > > Damir > > > > > > "DG_1" <dgacina@san.rr.com_no.spam> wrote in message > > > news:lbp08.100459$AI.26190323@typhoon.san.rr.com... > > > > Thanks 'rickman'. > > > > The only problem I 'foresee' is the fact that IAR Kickstart doesn't > > > > have any capability of adding/editing BSDL files (or I missed > > something). > > > > Therefore, I don't see the way how to use debugging features > > > > of IAR Kickstart when _more_ than one chip is in the same chain. > > > > I guess, designers of IAR's tool-set didn't (intentionally?) > > > > though-out that possibility. Also, I guess, from Xilinx's perspective, > > > > having MSP430 in the same chain is no big deal, just add BSDL > > > > file for TI's part to Xilinx's 'JTAG programmer' tool. > > > > In the past I've used JTAG to chain-up devices (Xilinx, Lattice) > > > > but always from the same manufacturer, I've never mixed-up > > > > different chips, from different manufacturers, neither I added MPUs > > > > into the chain. now I guess the only way to check it up is to make > > > > the actual circuitry and then 'everything is in God's hands'. > > > > (Well, the same problem is applicable to Atmel AVmega128 > > > > to be chained-up with other JTAG-capable chips) > > > > > > > > > > > > "rickman" <spamgoeshere4@yahoo.com> wrote in message > > > > news:3C414ACF.EA8194EA@yahoo.com... > > > > > DG_1 wrote: > > > > > > > > > > > > Hi there, > > > > > > Has anybody tried to chain-up a MSP430 with any of JTAG-capable > > > > > > Xilinx chips and be able to programm both of them without > problem(s) > > > > > > (MSP430 via IAR KickStart, Xilinx via JTAG programmer)? > > > > > > Or (re-arranged question):: > > > > > > Does IAR Kick-Start still recognizes MSP430 and/or allows other > > > > > > devices (other than MSP430) to be chained-up via JTAG? > > > > > > > > > > > > Thanks in advance, > > > > > > -- D.G. > > > > > > > > > > > > > > > I will be doing exactly this in a month or two. I am building a > board > > > > > with a TMS320C6711, an MSP430F148/9, an XC2S150E and an XCR3256XL > all > > in > > > > > one JTAG chain. Actually, I may leave the MSP430F148/9 out of the > > chain > > > > > depending on the answers to the questions I will be asking the > > vendors. > > > > > But I really want the rest of it in a single chain so that I can do > > > > > boundry scan testing on it all. The MSP430F148/9 will not be quite > so > > > > > integrated into the rest of the board, so it does not have to be > > tested > > > > > that way. It is also important to be able to burn software into it > > > > > regarless of the state of the board. This will be used for initial > > board > > > > > test too. I am even considering using the MSP430F148/9 as a JTAG > > > > > interface for the JTAG chain. But we will see if I can get it all to > > > > > work together. > > > > > > > > > > If you have any results yourself, please let me know. Thanks! > > > > > > > > > > -- > > > > > > > > > > Rick "rickman" Collins > > > > > > > > > > rick.collins@XYarius.com > > > > > Ignore the reply address. To email me use the above address with the > > XY > > > > > removed. > > > > > > > > > > Arius - A Signal Processing Solutions Company > > > > > Specializing in DSP and FPGA design URL http://www.arius.com > > > > > 4 King Ave 301-682-7772 Voice > > > > > Frederick, MD 21701-3110 301-682-7666 FAX > > > > > > > > > > > > > > > > > > > > > > > > > > > >Article: 38553
Hi, I found the solution to the big "string" problem in the Exemplar X-Files. The following commands solved this problem: #Turn off eqn property in EDIF file set edif_function_property "" #Turn on INIT property in EDIF file set xi_write_init_on_luts TRUE #Process database set rename_rule XILINX attach_equations I have defined the part component and the library in leo using: set part v800hq240 set process 4 set wire_table xcv800-4_avg load_library xcv but when I tried to load the EDIF using dsgnmgr it didn't got the device from the EDIF description. The NgdBuild libraries I have are (for -l option): fpga_compiler_ii fpga_express synopsys viewlog xc9500 xc9500xl xc9500xv xilinxun Should I have something like exemplar library? Thanks again, Rodolfo Ray Andraka wrote: > > Mike, > > I don't recall ever seeing settings in the Xilinx tools for the edif reader. > Sounds to me like a problem with the way leo is writing the edif. I think there > may be settings in leo for the edif output format. Also, the tri_state warnings > indicate that it couldn't find a matching component. If it is not a primitive > for the device you are using, it better have an edif file for the component or > you get the error. > > Mike Treseler wrote: > > > Mike Treseler wrote: > > > > > Check the Xilinx GUI for EDIF writer settings. > > > > Make that EDIF *reader* settings. -- The Xingo Project | Rodolfo Jardim de Azevedo Code Optimization for Embedded Systems | Computer Science PhD Student An Open Software Initiative of IC-UNICAMP | rjazevedo@ic.unicamp.brArticle: 38554
Peter van Beek wrote: > > Thanks for replying, > > We want to stick to the 32 bit, 33 Mhz bus. Our data is not sustained > but consist of bursts that can vary between 16 Kbyte and 64 KByte. We > consider using extern memory to avoid time critical situations. Any > suggestions regarding this matter? > > Regards, > Peter If that's all, you can probably add a 64K RAM to your board and buffer the data. Later you can transfer it via Parallel Port / Serial Port / Flashing LED to a PC... Slightly more serious now - if your application is not a mass product, you may find various dedicated PCI chips more convenient (AMCC,PLX). You don't have to worry about timing, you can use a significantly smaller PLD and the thing doesn't have to be fully configured at system start. Have a nice day, IwoArticle: 38555
I want to generate a 128x32 ROM for Spartan II using CoreGen. Will CoreGen work with Xilinx Webpack tools? If not, could someone post the code for a blank ROM that I could fill in with my own data? FWIW, I'm using Verilog. -- Brad EckertArticle: 38556
You are welcome, Please visit http://www.nallatech.com/ for hardware and software to make the DSP development in FPGAs much much easier. Austin Amit Thakar wrote: > Thanks a lot Austin and Ray, your responses were really helpful. > > -Amit > > "Amit Thakar" <athakar@uwaterloo.ca> wrote in message > news:z7l18.253991$KT.59135022@news4.rdc1.on.home.com... > > Hi, > > > > I was hoping someone could answer questions I had regarding digital signal > > processors vs. FPGAs for implementing computationally intensive signal > > processing algorithms: > > > > 1. Can FPGAs (especially newer ones) achieve better performance than DSPs? > > 2. If so, then why do ppl use DSPs as opposed to FPGAs? > > 3. Which is more flexible in terms of reprogrammability (I would think > they > > would be the same in this regard). > > 3. What are other (dis)advantages of using FPGAs vs. DSPs. > > > > In general, I understand that DSPs provide a low cost solution due to high > > volume of generic products, but performance tends to fall short for many > > applications. > > > > Any input would be greatly appreciated. > > Thanks! > > > > -Amit > > > > > >Article: 38557
Christian, Yes, that is what the ICAP primitive is for. We added it to support the internal reconfiguration, and self modifying efforts of many groups. With the addition of the floorplanner in 4.1i, one can now assign areas to functions (necessary for using ICAP so you don't step on yourself). Look for more applications notes using this capability. If you are interested in using it now, contact your FAE for the necessary technical support, or just give it a try (it has been verified to work in the silicon). Basically it is quite simple, it is a 2:1 multiplexer that allows access to all external configuration pins inside the logic plane. So, basically, anything you could do outside the part, you can now do inside the part. The posting on using the -r bitstream option to generate differences between bitstreams as re-configurable snippets would be one way to use this: configure once with the first pattern, load the changes into a block RAM (might be part of the first pattern), and then use the BRAM and the ICAP to re-program the change at the point it is needed. Austin Christian Plessl wrote: > Hi > > Incidentally, I just stumbled over the Virtex2 ICAP (Internal configuration > access port) primitive. Just looking at the name of the component this > sounds very interessting. Is it possible to access/modify the Virtex2 > configuration from a circuit within the FPGA itself using this component? > > Unfortunately I could not find any documentation ICAP on the Xilinx webpage. > > Does anybody know, what this component is good for? Is there any > documentation on this? > > Thanks for any hints. > > ChristianArticle: 38558
I think all of synthesizer software will treat coregen as blackbox. ps: I am using Leonardo Spectrum. Buzz :-----Original Message----- :From: a_darabiha@yahoo.com (a_darabiha) [mailto:a_darabiha@yahoo.com] :Posted At: Thursday, 17 January, 2002 3:35 AM :Posted To: fpga :Conversation: Core Generator :Subject: Re: Core Generator : : :Thanks a lot for your guide, :It really helped to solve my problem, :As you said synplicity looks at the core as a black box. : :Ahmad Darabiha : :"Angel Pino" <escorpiontale@hotmail.com> wrote in message :news:<EBq%7.30659$_j6.3312171080@newssvr14.news.prodigy.com>... :> You need to make sure that the .edn file generated by :CoreGen is in the same :> directory as the .edf file generated by Symplicity. Simplicity only :> considers the core as a black box and ignores whats in it. :In ourder to :> place and route you need both the .edf ( netlist from :Symplicity ) and .edn :> ( netlist from CoreGen ). :> Hope this helps :> Angel PinoArticle: 38559
> Basically it is quite simple, it is a 2:1 multiplexer that allows access > to all external configuration pins inside the logic plane. So, basically, > anything you could do outside the part, you can now do inside the part. > > The posting on using the -r bitstream option to generate differences > between bitstreams as > re-configurable snippets would be one way to use this: configure once > with the first pattern, load the changes into a block RAM (might be part > of the first pattern), and then use the BRAM and the ICAP to re-program > the change at the point it is needed. Wow. Im looking forward to a JBits version that supports Virtex2. This will make this new ICAP feature really usefull.. Best regards, ChrisArticle: 38560
> and in the pre-optimized version, I got the message: > ERROR:NgdBuild:201 - An EDIF value has exceeded the maximum string limit > of 500 > characters, or a closing double-quote was never found for this > string, which > starts on line 2190 in file "leon1_preopt.edf". This likely means > that the > EDIF netlist was improperly written. Please contact the vendor of > the > program that produced this EDIF. For what it's worth, I also got this type of error when using FPGA-Express as the synthesizer. I was passing a bunch of generic integers to a component, and apparently exceeded the string limit. My workaround was to shorten all the named items to get below the string limit. NewmanArticle: 38561
"Ray Andraka" <ray@andraka.com> schrieb im Newsbeitrag news:3C45FC8B.A2E1B898@andraka.com... > The biggest disadvantage to using FPGAs is the relative scarcity of expertise > needed for the performance gains I noted above. FPGAs also cost more per device > than typical DSP micros, but when you consider dollars for a specific > performance then the PFGAs get cheaper as soon as performance drives you over > one or two DSPs. The is a nice article in thwe new issue of Xcell. Its about a design for a 2D FFT of a 2048x2048x16bit image with 120 frames/second. The use two XC2V6000 one for the row transformation, one for the column transformation. So a 2048 Point (16 bit) FFT takes 2.8 us. The whole system costs about 20k $. The System that was used before (dozens of PowerPC cards) was about 480k $. Hmm, not bad ;-) -- MfG FalkArticle: 38562
Brad,
ROM's are just simple case statements with the address as selects and data
as outputs like,
module (address,data)
input address;
output data;
case (address)
0: data = 0;
1: data =1;
endcase
endmodule
hope this helps,
Dave
"Brad Eckert" <brad@tinyboot.com> wrote in message
news:4da09e32.0201170728.4206ba97@posting.google.com...
> I want to generate a 128x32 ROM for Spartan II using CoreGen. Will
> CoreGen work with Xilinx Webpack tools? If not, could someone post the
> code for a blank ROM that I could fill in with my own data? FWIW, I'm
> using Verilog.
>
> --
> Brad Eckert
Article: 38563I've got a RAM-less solution! Back in the Day, when a delay was needed such as for a reverb circuit, they didn't have digital storage so they used long springs. A transducer would put the sound waves on one end of the spring and another transducer would get the sound from the other end of the spring after a the delay. A metal spring doesn't have a flat passband and I think is also has a nonconstant group delay, but how many products can advertise: "uses cutting-edge titanium spring delay line"? It's worth the extra cost, effort, and strong degradation in quality. (To modify the delay, just change spring tension.) They also used to use mercury delay lines for RAM back in the ENIAC day, but I'm not sure how that worked. Anybody? "Simon Fisher" <Simon.Fisher@hitachi-eu.com> wrote in message news:2cbcf39d.0201160940.7eec6579@posting.google.com... > Hi, I'm new to all this, so please bear with me. > > I need to implement a variable time delay for digital audio signals of > several hundred milliseconds. The data comes in and out of an I2S > interface using 32khz sample rate, stereo 16 bit samples. The device > also needs to be controlled (ie precise time delay selected) via an > I2C slave interface. > > Any ideas please? > > Cheers > Simon FisherArticle: 38564
You can find tested ADPCM cores from Xilinx, Amphion at www.amphion.com, and Adelante Technologies at www.adelantetechnologies.com. I am currently using Adelante's core and have tested and verified it works as per ITU. GregArticle: 38565
"Kevin Neilson" <kevin_neilson@removethis-yahoo.com> wrote in message news:WlH18.42619$uA.413604@rwcrnsc51.ops.asp.att.net... > I've got a RAM-less solution! [deleted] > > They also used to use mercury delay lines for RAM back in the ENIAC day, but > I'm not sure how that worked. Anybody? > I remember seeing these on the old English Electric DEUCE valve (tube) computer that was still operational when I worked at the English Electric Co. Ltd. at Kidsgrove in 1962. They had an ultrasonic transducer at both ends. The pulses were transmitted into the mercury at one end and were received at the other end, amplified and reshaped, and re-transmitted. They looked like large grey mushrooms sticking out of the floor. The earlier Cambridge University EDSAC computer used them as registers. Leon -- Leon Heller, G1HSM leon_heller@hotmail.con http://www.geocities.com/leon_heller Low-cost Altera Flex design kit: http://www.leonheller.comArticle: 38566
Rodolfo Jardim de Azevedo wrote: > but when I tried to load the EDIF using dsgnmgr it didn't got the > device from the EDIF description. > The NgdBuild libraries I have are (for -l option): > fpga_compiler_ii > fpga_express > synopsys > viewlog > xc9500 > xc9500xl > xc9500xv > xilinxun > Should I have something like exemplar library? I think so. Call mentor or xilinx or try a simpler example. Try using the pushbutton gui and file list. If your part shows up on leo's target list, this stuff should just work. --Mike TreselerArticle: 38567
I haven't used the latest version of system generator yet, so this may have been
fixed. The biggest problem with the old system generator is that it is very
difficult to incorporate your own blocks into the system generator unless they
are comprised totally of the coregen macros that are supported by system
generator or the very simple extra functions built into system generator. This
makes it very awkward to use if you are doing things that don't fit in the
rather limited set of standard components.
That said, it is enough for someone to put something together in system
generator and get it to run in the FPGA. You usually won't see the orders of
magnitude performance increases, and your design is probably going to be bigger
than it needs to be using system generator, but at least it lets the
non-hardware DSP savvy guy in. I like the system simulation capability it has,
but it isn't too useful to me until they come up with an easy way to import
custom macros.
a_darabiha wrote:
> Hi All,
>
> I'm trying to implement a Computer Vision Algorithm
> on Xilinx Vitex2000E fpgas. I am now using CoreGen for some blocks
> of my system. We are thinking of switching to System Generator to do
> the simulation in the highest level and then translate the system
> to VHDL. I hope it would make the life much easier!
>
> So does anybody have experience of using SysGen for Image Processing
> applications? how easy is that compared with the standard method of
> writing the whole VHDL myself? what are the major problems that
> might be in the way? ...
>
> Any coment would be helpful,
>
> Thanks,
> Ahmad Darabiha
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 38568"Kevin Neilson" <kevin_neilson@removethis-yahoo.com> writes: > Back in the Day, when a delay was needed such as for a reverb circuit, they > didn't have digital storage so they used long springs. A transducer would > put the sound waves on one end of the spring and another transducer would > get the sound from the other end of the spring after a the delay. A metal > spring doesn't have a flat passband and I think is also has a nonconstant > group delay, but how many products can advertise: "uses cutting-edge > titanium spring delay line"? It's worth the extra cost, effort, and strong > degradation in quality. (To modify the delay, just change spring tension.) A similar method has been used for digital data storage. Rather than a spring, they used a very long wire, usually coiled up. A piezoelectric transducer sent torsion pulses down the wire, which was then detected by another piezoelectric transducer at the far end. I have a Frieden EC-132 desktop calculator using this form of memory. It was manufactured in 1964. It's a four-function RPN calculator with square root and a CRT display. Uses a heck of a lot of germanium transistors.Article: 38569
Eric Smith wrote: > A similar method has been used for digital data storage. Rather than > a spring, they used a very long wire, usually coiled up. A piezoelectric > transducer sent torsion pulses down the wire, which was then detected > by another piezoelectric transducer at the far end. Back in 1965 I was supposed to stuff much of the logic and all of the memory for an electronic cash register into such a torsional delay line. We managed to squeeze in 15,000 bits and run that reliably, but the project never saw the light of day. So I packed up my slide rule and emigrated to the US. Smart move ! Peter AlfkeArticle: 38570
go to the following URL: www.andraka.com They have explaination about your Q's BUZZ :-----Original Message----- :From: Amit Thakar [mailto:athakar@uwaterloo.ca] :Posted At: Thursday, 17 January, 2002 4:11 AM :Posted To: fpga :Conversation: Signal processing using FPGAs :Subject: Signal processing using FPGAs : : :Hi, : :I was hoping someone could answer questions I had regarding :digital signal :processors vs. FPGAs for implementing computationally intensive signal :processing algorithms: : :1. Can FPGAs (especially newer ones) achieve better :performance than DSPs? :2. If so, then why do ppl use DSPs as opposed to FPGAs? :3. Which is more flexible in terms of reprogrammability (I :would think they :would be the same in this regard). :3. What are other (dis)advantages of using FPGAs vs. DSPs. : :In general, I understand that DSPs provide a low cost solution :due to high :volume of generic products, but performance tends to fall :short for many :applications. : :Any input would be greatly appreciated. :Thanks! : :-Amit : : :Article: 38571
Peter Alfke <peter.alfke@xilinx.com> writes: > Back in 1965 I was supposed to stuff much of the logic and all of the > memory for an electronic cash register into such a torsional delay > line. How do you stuff logic into the delay line? > We managed to squeeze in 15,000 bits and run that reliably, Quite impressive! What was the physical length of the delay line? I have a Monroe 990 calculator that stores only around 120 bits into a delay line made by NEC, and fails to do that reliably. I assume it was reliable back in 1971 though. The Friden seems to work reliably though. It was made in 1964, and stores around 280 bits. Actually more channel bits, because they use a strange encoding rather than straight binary.Article: 38572
Implemented 1/2 Band 51-tap FIR using Coregen + Foundation. Pre-synthesis simulation looks excellent, however when the filter is loaded into Spartan-II the output looks like complete random junk. All timing is met. Does anyone have a similar experience or an idea for a potential problem area? Thanks.Article: 38573
If recall it correctly, niether Spartan-II nor SpartanXL mode pins have any effect during the Boundary scan (JTAG) based configuration. And yes, you should be able to connect the JTAG compliant devices in a chain the way you described it.Article: 38574
I was at Sweda cash registers, Swedish junior sister of Monroe, who loved drums, so we first tried to use the delay line like a drum. But it was not stable enough to pack it full, like a ring, as you do on a drum. So we left a gap, and made sure the gap would neither grow nor shrink. It was a stored instruction design, but the details are getting foggy... Transistors were very expensive, and read-out was a real problem before the advent of Nixie tubes. Makes you appreciate today's plethora of solutions. Peter Alfke Eric Smith wrote: > Peter Alfke <peter.alfke@xilinx.com> writes: > > Back in 1965 I was supposed to stuff much of the logic and all of the > > memory for an electronic cash register into such a torsional delay > > line. > > How do you stuff logic into the delay line? > > > We managed to squeeze in 15,000 bits and run that reliably, > > Quite impressive! What was the physical length of the delay line? > > I have a Monroe 990 calculator that stores only around 120 bits into a > delay line made by NEC, and fails to do that reliably. I assume it was > reliable back in 1971 though. > > The Friden seems to work reliably though. It was made in 1964, and > stores around 280 bits. Actually more channel bits, because they > use a strange encoding rather than straight binary.
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