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Hi, I'm designing using Leonardo Spectrum (2001d) and passing the EDIF files to Xilinx tools. But I'm having problems using vectors. All the tools are for Solaris. The synthesis goes right, but when I run the NGD using the constraints file mainly for pinout specification. I get messages like this: ERROR:NgdBuild:397 - Could not find NET 'ram_address1(10)' in design 'xsv800'. NET entry is 'NET ram_address1(10) LOC = 108; I don't know what is happening. I get this message for all vector signals. Can anyone help me? Thanks in advance, RodolfoArticle: 38426
Bryan wrote: > The buttons don't work in the main window, they do work in the editor > windows. > Coincidentally, a day or two before your posting, I started to look into the wine code to see if I could fix this. We will see whether my limited programming skills are up to the task. Hey Xilinx, here is an idea. How about allowing one of your programmers to spend a little time fixing wine bugs that affect Xilinx programs? The programs generally work pretty good under wine already. If you don't want to have any visible connection to wine, to avoid the support issues, ask the person to post patches to wine from their personal (non Xilinx) email account. The wine project will happily accept "stealth" patches. -- My real email is akamail.com@dclark (or something like that).Article: 38427
"Martin Fischer" <Martin.Fischer@fzi.de> schrieb im Newsbeitrag news:a1u88b$bd@absalom.fzi.de... > Hello, > > I don't understand why an Signal toggles at the rising > edge, because I want to toggle it at an falling edge. > Can someone help me ? > > Thanks > > Martin.Fischer@fzi.de > > > Phasen : process (MSP_CLK, Befehl_Empfangen) > Begin > if (Befehl_Empfangen='0' and Empfangs_Buffer(3 downto 0)="0000") then > Zustand <= Zustand0; Speicherdummy(3 downto 0)<="0000"; > > elsif falling_edge(Befehl_Empfangen) then Are you sure that "Befehl empfangen" is your clock signal?? The process looks like MSP_CLK should be your clock signal. And dont use the same signal for clocking and asynchronous reset. -- MfG FalkArticle: 38428
"Antonio" <dottavio@ised.it> schrieb im Newsbeitrag news:fb35ea96.0201140021.7780667e@posting.google.com... > Good Morning, > I'm using the following code to arrange a pair of two CLKDLL one that > divide the clock by two and the other that divide it by 3 to obtain > the final result of a clock divided by 6 , the problem is that I could > have the clock divided by two while the output at the following clock > divider is always 0, there's a special reason for this ?? I've to > arrange this cascade in another way ?? In general this cascade works. Make sure you reset the DLLs, especial the second. Have a look at the Xapps, there are good examples (including VDHL). > By the way also another question, I still haven't understand if vhdl > have this degree of freedom : > I would want to change at runtime the value of the divider factor of > the two CLKDLL depending for example on the value of an input port. > Thanks for your help and here's the code : This is not possible. Its no limitation of VHDL, its a limitation of the FPGAs. IF you want a runtime selectable divideer, just use a programmable counter and generate a clock enable for your logic. -- MfG FalkArticle: 38429
I got some question about radiation resistance of FLASH and EEPROMs. I would like to use an AVR microcontroller from Atmel near an electron accellerator. Since the whole thing is inside a radiation shielded room, Iam interested in the resistance of normal FLASH (the programm memory of the AVR) and EEPROM. Any hints, links or other ressources? -- MfG FalkArticle: 38430
Christian Plessl wrote: > > > The pieces mentioned as missing are only really missing if you are > > trying to do all this at design time using mainstream tools. If you > > defer routing to run-time and use JBits, then the fact that routes run > > through the section you want to use doesn't really matter - it's like > > implementing your design on an FPGA with more limited routing > > resources. The router will find a way. > > Ok, I admitt, if you go all way using JBits and no conventional design > tools, you won't have this problem. But what if you want to use > conventional tools? For implementing large circuits, which are not > primarily dataflow oriented, but have also a larger controler part, you > might be forced to use conventional tools. Otherwise you will have to do > all statemachine implementation (state encoding, implementationo and > minimization of transition- and output-functions) yourself.. which is very > tedious even for small statemachines.. > > Is there a way to let the VHDL/Verilog design tools synthesize your > circuit, and than read back the resulting netlist into JBits and use JBits > for implementation and routing? For instance by instantiating the netlist > primitives and using JRoute2 for routing? Has anybody done this in an > automated way? What about timing? The standard synthesis tools can check > for meeting all timing constraints. If I do all routing using JBits, how > can I guarantee, that the timing constraints are met? Some work has been done in this area. At FCCM last year, Dr Satnam Singh and I presented an automated route from high-level Lava (an experimental HDL) through JBits, basically by the mechanism you describe. I can send the paper to anyone interested, just email me. I agree 100% about the tediousness of forcing you to go structural when the task is control-oriented. As for timing, we do not do any kind of timing-driven routing. The task of the router is to find a lump of shiny metal linking this point to that point, and that's it. The router does not go out of its way to find bad routes, so as long as you are not to near your timing boundary, and you have a decent floorplan, on a routing-rich architecture such as Virtex or Virtex-II, the router will do a good job. XDL generation allows you to perform static timing analysis after routing if you are concerned. Phil -- --------------------------------------------------------------------- __ / /\/ Dr Phil James-Roxby Direct Dial: 303-544-5545 \ \ Staff Software Engineer Fax: Unreliable use email :-) / / Loki/DARPA Email: phil.james-roxby@xilinx.com \_\/\ Xilinx Boulder ---------------------------------------------------------------------Article: 38431
Hi; Maybe you can find useful the schematics (not VHDL, sorry) of 2Mb/s (E1) PDH muxes and demuxes from my web page, http://www.arrakis.es/~jl.r/pfc/index.htm E2 and E3 frame structures are less complex than E1. Hope this helps. Juan-Luis Lopez Spain <dainis@safequipment.com> escribió en el mensaje de noticias a1cjf9$eih$1@news.netmar.com... > I am looking for PDH MUX (E2,E3) VHLD cores and > any sync frame based device VHLD examples. > Thanks. > > > ----- Posted via NewsOne.Net: Free (anonymous) Usenet News via the eb ----- > http://newsone.net/ -- Free reading and anonymous posting to 60,000+ groups > NewsOne.Net prohibits users from posting spam. If this or other posts > made through NewsOne.Net violate posting guidelines, email abuse@newsone.netArticle: 38432
Falk, Use "google.com" to search for: single event upset single event error pmos single event error cmos single event error nmos Lots of good pdf's to wander through. Lots of good tests done at Sandia, NASA, ESA, etc. Generally speaking, inside a shielded room is probably a good place to be, unless the shielding is huge lead blocks (which tend to emit low level alpha particles to to the latent radioactive contaminants in lead). Xilinx also has test results for rad hard eeprom. http://www.xilinx.com/partinfo/ds082.pdf Austin Falk Brunner wrote: > I got some question about radiation resistance of FLASH and EEPROMs. I would > like to use an AVR microcontroller from Atmel near an electron accellerator. > Since the whole thing is inside a radiation shielded room, Iam interested in > the resistance of normal FLASH (the programm memory of the AVR) and EEPROM. > Any hints, links or other ressources? > > -- > MfG > FalkArticle: 38433
In addition, their non-linear distortions and their very limited bandpass make their use with ASR very problematic. Look for Clarity. They have a commercial product that works pretty well. Doing this well without distorting the speech is much more than a senior project. "Leon Heller" <leon_heller@hotmail.com> wrote in message news:a1oobf$ers$1@knossos.btinternet.com... > > "Jerry Avins" <jya@ieee.org> wrote in message > news:3C3FA303.1B3A019E@ieee.org... > > > > Contact throat microphones were used in fighter planes 50 years ago. > > They discriminate against ambient noise very nicely indeed. 50 dB SNR > > improvements were cited, but I didn't make measurements myself. > > I looked into throat microphones when I worked on military radio human > factors. > > They deal with ambient noise OK, but the speech quality is generally very > poor. They are also uncomfortable to wear (especially when they get wet, as > often happens with special services personnel), and generally need to be > pressed against the larynx with a finger to work properly. Users hate them!Article: 38434
Actually, they should be slightly off the corner of the mouth, out of the nose and mouth breath stream. "Ray Andraka" <ray@andraka.com> wrote in message news:3C40AAF1.84FC623@andraka.com... > Jerry, > > These are not throat mikes, rather they are on a boom that you position > immediately in front of your lips. If you can't kiss it, it is too far away.Article: 38435
Hello all, can anyone tell me about the optimization option "merge duplicate register" in FPGA Express. Also I need some more information about the "preserve hierarcy" and "do not insert I/O pads" options, I checked Xilinx site but more help would be very welcome. Best Regards HarrisArticle: 38436
Rodolfo Jardim de Azevedo wrote: > I'm designing using Leonardo Spectrum (2001d) and passing the EDIF > files to Xilinx tools. But I'm having problems using vectors. All the > tools are for Solaris. > The synthesis goes right, but when I run the NGD using the constraints > file mainly for pinout specification. I get messages like this: > ERROR:NgdBuild:397 - Could not find NET 'ram_address1(10)' in design Consider leaving the pinout stuff out of your code. Run the Xilinx place and route and then edit the Xilinx pin assignment file directly. --Mike TreselerArticle: 38437
"Peter Ormsby" <faepete.deletethis@mediaone.net> wrote in message news:<o6l08.22134$yC.2552933@typhoon.mn.mediaone.net>... > David, > > Putting processors in FPGAs is becoming more common all the time. Actually, > creating the processor is the easy part of making a useable > microprocessor/microcontroller system. It's creating the 'C' > compilers/linkers and the Debuggers and the OSes and the development > environments that are really the trick. However, having someone create a > processor in a FPGA has got to be one of the best ways to teach a person > about computer architectures. > > Just as an example of how far some of the FPGA-specific processors have > gotten is to look at the Nios processor from Altera and the Microblaze from > Xilinx. I can't speak to the Microblaze much since I haven't seen anything > other than marketing stuff, but the Nios processor has quite a collection of > the support tools. In addition to the "free" (comes with the kit) GNU Pro > compiler/linker/debugger, there's a bunch of third-part stuff like the > Arriba (Viosoft) IDE, the Nucleus Plus (ATI) and Kros (Shugyo) RTOS. > There's even a version of Linux (Microtronix's uCLinux distro) that runs on > Nios as well as TCP/IP stacks and a web server application that come with > Altera's Ethernet Development Kit. > > Anyway, if you don't need Pentium/Athlon type performance, FPGAs really are > a viable platform for computing. Check out the Nios information here... > > http://www.altera.com/products/devices/excalibur/exc-nios_index.html > > -Pete- > > David Findlay <david_j_findlay@yahoo.com.au> wrote in message > news:pan.2002.01.13.20.44.34.131584.2125@yahoo.com.au... > > Is it possible to build a homebrew computer of some description using > FPGA's? I know it won't be > > as powerful as a PC, but I'm more interested in designing and building my > own. Also does anyone > > know of an FPGA simulator for Linux? Thanks, > > > > David Or how about the LEON SPARC clone? http://www.gaisler.com/ It wont have the performance of the Altera or Xilinx softcores but it is free, well supported and provides an implementation of the AMBA bus for high speed peripherals. I'll bet the compiler tools are better than the Altera/Xilinx ones as well...Article: 38438
I'm trying to use the i/o's of the Virtex2 as inputs. To do this, in VHDL i
connect a user pin (input) directly to a pin that is connected with a
segment of the board's led display. After programming the FPGA, i use a
loose wire to connect the input to GND or +3.3V and expect the led segment
to light up accordingly.
To go short; some pins work this way, other's don't do anything. How is this
possible, what am i doing wrong? Do the i/o banks need any configuration?
Have i already blown up these pins by experimenting this way? how robust are
the i/o pins of the Virtex2 anyway?
thanx 4 yer thoughts guys
regards,
Seb
Article: 38439grohss <fgt@iutg.trg> wrote in message news:<ee7432f.-1@WebX.sUN8CHnE>... > i do a divider,(a/b),the result is c.should i declare the c is wire or reg or integer? One things for sure - you'll never synthesize your code. Can you do something like a * (1/b) where 1/b is taken from a lookup table? This you can synthesize. Alternatively you will have to write a bitserial divider - no fun at all. I assume you are using verilog which I dont know very well but I would guess that if c is a wire then you are describing combinatorial logic whereas with a register it is clocked. The choice is yours and depends on how you intend it to fit with the rest of your circuit.Article: 38440
hamish@cloud.net.au writes: > Here's a diagram (use a monospaced font to view): > > FROM:TO needed here > <---------> > > Changing HS Signal HS Sample LS Sample > every +-------+ +-------+ +-------+ > cycle ----|D Q|-----|D Q|------|D Q| > | | +---|CE | +----|CE | > +-->CK | | +->CK | | +-->CK | > | +-------+ | | +-------+ | | +-------+ > | | | | | > HSCLK -+--------------+ | | > | | | > LSCLK ------------------------------+ > | | > Pulse edge detect --+ | > | > Delayed pulse --------------------+ If they are not related, how do you know time from HSCLK goes high to LSCLK goes high? What is the value of your FROM:TO constraint? Homann -- Magnus Homann, M.Sc. CS & E d0asta@dtek.chalmers.seArticle: 38441
hamish@cloud.net.au writes: > Here's a diagram (use a monospaced font to view): > > FROM:TO needed here > <---------> > > Changing HS Signal HS Sample LS Sample > every +-------+ +-------+ +-------+ > cycle ----|D Q|-----|D Q|------|D Q| > | | +---|CE | +----|CE | > +-->CK | | +->CK | | +-->CK | > | +-------+ | | +-------+ | | +-------+ > | | | | | > HSCLK -+--------------+ | | > | | | > LSCLK ------------------------------+ > | | > Pulse edge detect --+ | > | > Delayed pulse --------------------+ You have two cross-domain signals here, but I guess you knew that. Do you have a constraint there too? It's hard to understand what you are doing. Couldn't you just clock the middle FF with LSCLK? If your Pulse is one LSCLK period long you get metastability problems when CE comes in the metawindow of HSCLK. Swapping HSCLK for LSCLK you instead get metastability problem when D changes in the metawindow of LSCLK. You said coherent, I'm assuming you have a several values (e.g. counter) you want to sample at the same time? Homann -- Magnus Homann, M.Sc. CS & E d0asta@dtek.chalmers.seArticle: 38442
I would look in the edif file and make sure that your names exactly matc= h. Make sure they aren't listed with NET ram_address1<10> as apposed to N= ET ram_address1(10). Some tools use different brackets for the vector numbers. Good luck, Tom Dillon Dillon Engineering, Inc. http://www.dilloneng.com >>>>>>>>>>>>>>>>>> Original Message <<<<<<<<<<<<<<<<<< On 1/14/02, 11:10:44 AM, Rodolfo Jardim de Azevedo <rjazevedo@N_O_S_P_A_M.ic.uincamp.br> wrote regarding Leonardo + Xilinx = tools help: > Hi, > I'm designing using Leonardo Spectrum (2001d) and passing the ED= IF > files to Xilinx tools. But I'm having problems using vectors. All the= > tools are for Solaris. > The synthesis goes right, but when I run the NGD using the constraints > file mainly for pinout specification. I get messages like this: > ERROR:NgdBuild:397 - Could not find NET 'ram_address1(10)' in design > 'xsv800'. > NET entry is 'NET ram_address1(10) LOC =3D 108; > I don't know what is happening. I get this message for all vecto= r > signals. > Can anyone help me? > Thanks in advance, > RodolfoArticle: 38443
Anyone out there familiar with this language ? I am trying to convert a PAL to VHDL and can't find any reference for it. Thanks in advanceArticle: 38444
Ray Andraka wrote:
>
> You are kind of stuck if you are unwilling to use any vendor specific coding. You could use
> keep buffers in your synthesis to force the synthesizer to assign logic to specific LUTs.
> The mapper should pretty much leave those alone as long as the synthesizer outputs LUT
> primitives. Unfortunately, the keep buffers have different syntaxes between vendors.
>
Ray, thanks for the suggestion.
XST allows the user to use a separate constraint file for synthesis, so
following your suggestion, I added several lines of code in a synthesis
constraint file to add "keep" attribute to the wire connections I wanted
perserved.
Here is the synthesis constraint file I wrote.
________________________________________________________________________
begin Parity_Generator
attribute keep of Fast_Path_Parity_Input[3] : signal is "true";
attribute keep of Fast_Path_Parity_Input[2] : signal is "true";
attribute keep of Fast_Path_Parity_Input[1] : signal is "true";
attribute keep of Fast_Path_Parity_Input[0] : signal is "true";
attribute keep of Parity_Input_1[3] : signal is "true";
attribute keep of Parity_Input_1[2] : signal is "true";
attribute keep of Parity_Input_1[1] : signal is "true";
attribute keep of Parity_Input_1[0] : signal is "true";
attribute keep of Parity_Input_2[3] : signal is "true";
attribute keep of Parity_Input_2[2] : signal is "true";
attribute keep of Parity_Input_2[1] : signal is "true";
attribute keep of Parity_Input_2[0] : signal is "true";
attribute keep of Parity_Input_3[3] : signal is "true";
attribute keep of Parity_Input_3[2] : signal is "true";
attribute keep of Parity_Input_3[1] : signal is "true";
attribute keep of Parity_Input_3[0] : signal is "true";
attribute keep of Parity_Input_4[3] : signal is "true";
attribute keep of Parity_Input_4[2] : signal is "true";
attribute keep of Parity_Input_4[1] : signal is "true";
attribute keep of Parity_Input_4[0] : signal is "true";
attribute keep of Parity_Input_5[3] : signal is "true";
attribute keep of Parity_Input_5[2] : signal is "true";
attribute keep of Parity_Input_5[1] : signal is "true";
attribute keep of Parity_Input_5[0] : signal is "true";
attribute keep of Parity_Input_6[3] : signal is "true";
attribute keep of Parity_Input_6[2] : signal is "true";
attribute keep of Parity_Input_6[1] : signal is "true";
attribute keep of Parity_Input_6[0] : signal is "true";
attribute keep of Parity_Input_7[3] : signal is "true";
attribute keep of Parity_Input_7[2] : signal is "true";
attribute keep of Parity_Input_7[1] : signal is "true";
attribute keep of Parity_Input_7[0] : signal is "true";
attribute keep of Parity_Input_8[3] : signal is "true";
attribute keep of Parity_Input_8[2] : signal is "true";
attribute keep of Parity_Input_8[1] : signal is "true";
attribute keep of Parity_Input_8[0] : signal is "true";
attribute keep of First_Intermediate_Parity[7] : signal is "true";
attribute keep of First_Intermediate_Parity[6] : signal is "true";
attribute keep of First_Intermediate_Parity[5] : signal is "true";
attribute keep of First_Intermediate_Parity[4] : signal is "true";
attribute keep of First_Intermediate_Parity[3] : signal is "true";
attribute keep of First_Intermediate_Parity[2] : signal is "true";
attribute keep of First_Intermediate_Parity[1] : signal is "true";
attribute keep of First_Intermediate_Parity[0] : signal is "true";
attribute keep of Second_Intermediate_Parity[1] : signal is "true";
attribute keep of Second_Intermediate_Parity[0] : signal is "true";
attribute keep of Third_Intermediate_Parity : signal is "true";
attribute keep of Final_Parity : signal is "true";
end Parity_Generator;
________________________________________________________________________
The problem I had was that because of a bug of XST (synthesis tool), it
doesn't synthesize my design when I try to constraint the following
wires with the following constraint code.
________________________________________________________________________
wire[7:0] First_Intermediate_Parity;
wire[1:0] Second_Intermediate_Parity;
________________________________________________________________________
________________________________________________________________________
attribute keep of First_Intermediate_Parity[7] : signal is "true";
attribute keep of First_Intermediate_Parity[6] : signal is "true";
attribute keep of First_Intermediate_Parity[5] : signal is "true";
attribute keep of First_Intermediate_Parity[4] : signal is "true";
attribute keep of First_Intermediate_Parity[3] : signal is "true";
attribute keep of First_Intermediate_Parity[2] : signal is "true";
attribute keep of First_Intermediate_Parity[1] : signal is "true";
attribute keep of First_Intermediate_Parity[0] : signal is "true";
attribute keep of Second_Intermediate_Parity[1] : signal is "true";
attribute keep of Second_Intermediate_Parity[0] : signal is "true";
________________________________________________________________________
When I get rid of the above keep attribute constraint, the code
synthesizes, but even if I do so, still c_be_n[3:0] doesn't seem to map
to the final level of the parity generator.
Another problem is that even when the code synthesizes, XST
still doesn't seem to generate a 5-input LUT for the final level of the
parity generator.
________________________________________________________________________
// Final level
assign Final_Parity =
Fast_Path_Parity_Input[3] ^ Fast_Path_Parity_Input[2] ^
Fast_Path_Parity_Input[1] ^ Fast_Path_Parity_Input[0] ^
Third_Intermediate_Parity;
________________________________________________________________________
XST recognizes the final level of the parity generator as "xor5," but I
guess that is not enough to generate a 5-input LUT.
> An option, if this part is not changed from instance to instance, is to compile the parity
> component separately to an edif using vendor specific code, then distribute as and
> instantiate it as a black box in the design. The PAR tools will look for the edif to merge
> the black box component with the rest of the design. You can include the code when compiling
> it for simulation so that the simulation is correct and remove it from the compile script so
> that it gets black boxed.
>
I think I will stick with the keep attribute method for the time
being (Hopefully the bug will get fixed soon.)
Thanks,
Kevin Brace (Don't respond to me directly, respond within the
newsgroup.)
>
> --
> --Ray Andraka, P.E.
> President, the Andraka Consulting Group, Inc.
> 401/884-7930 Fax 401/884-7950
> email ray@andraka.com
> http://www.andraka.com
>
> "They that give up essential liberty to obtain a little
> temporary safety deserve neither liberty nor safety."
> -Benjamin Franklin, 1759
Article: 38445There is one 32bit register.The [31:18] of register is divided 64.The register value is variable.i write:is it OK? *********************************** wire [31:0 ]register; wire Quotient; wire Remainder; assign Quotient=register[31:18]>>6'b100000; assign Remainder=register[31:18]%6'b100000; when i synthesis,it says: Error: Operands to mod must be constant in routine % called from PT_EOP_GalNet_DMA line 109 in file 'E:/gt48350/PT_EOP_GalNet_DMA.v' (HDL-65) Implementation Errors can you help me?Article: 38446
Why do you want to use the DLL for such a simple job? It only takes three flip-flops to perform this operation, and you can be run-time programmable to your heart's desire. Peter Alfke =============== Antonio wrote: > Good Morning, > I'm using the following code to arrange a pair of two CLKDLL one that > divide the clock by two and the other that divide it by 3 to obtain > the final result of a clock divided by 6 , the problem is that I could > have the clock divided by two while the output at the following clock > divider is always 0, there's a special reason for this ?? I've to > arrange this cascade in another way ?? > > By the way also another question, I still haven't understand if vhdl > have this degree of freedom : > I would want to change at runtime the value of the divider factor of > the two CLKDLL depending for example on the value of an input port. > Thanks for your help and here's the code : > > library IEEE; > use IEEE.std_logic_1164.all; > > -- other libraries declarations > -- synopsys translate_off > library VIRTEX; > library IEEE; > use IEEE.vital_timing.all; > -- synopsys translate_on > > entity b is > port( > clk : in std_ulogic; > reset : in std_ulogic; > clk_div_2 : out std_ulogic; > clk_div_6 : out std_ulogic > ); > end b; > > architecture b of b is > > ---- Component declarations ----- > > component BUFG > -- synopsys translate_off > generic( > InstancePath : STRING := "*"; > MsgOn : BOOLEAN := TRUE; > TimingChecksOn : BOOLEAN := false; > Xon : BOOLEAN := TRUE; > tipd_I : VitalDelayType01 := (0 ns,0 ns); > tpd_I_O : VitalDelayType01 := (0 ns,0 ns) > ); > -- synopsys translate_on > port ( > I : in std_ulogic; > O : out std_ulogic > ); > end component; > component CLKDLL > -- synopsys translate_off > generic( > CLKDV_DIVIDE : REAL := 2.000000; > DUTY_CYCLE_CORRECTION : BOOLEAN := TRUE; > InstancePath : STRING := "*"; > MAXPERCLKIN : TIME := 100 ns; > MsgOn : BOOLEAN := false; > TimingChecksOn : BOOLEAN := TRUE; > Xon : BOOLEAN := TRUE; > tipd_CLKFB : VitalDelayType01 := (0 ns,0 ns); > tipd_CLKIN : VitalDelayType01 := (0 ns,0 ns); > tipd_RST : VitalDelayType01 := (0 ns,0 ns); > tpd_CLKIN_LOCKED : VitalDelayType01 := (0 ns,0 ns); > tperiod_CLKIN : VitalDelayType := 0.01 ns; > tpw_CLKIN_negedge : VitalDelayType := 0.01 ns; > tpw_CLKIN_posedge : VitalDelayType := 0.01 ns; > tpw_RST_posedge : VitalDelayType := 0.01 ns > ); > -- synopsys translate_on > port ( > CLKFB : in std_ulogic := '0'; > CLKIN : in std_ulogic := '0'; > RST : in std_ulogic := '0'; > CLK0 : out std_ulogic := '0'; > CLK180 : out std_ulogic := '0'; > CLK270 : out std_ulogic := '0'; > CLK2X : out std_ulogic := '0'; > CLK90 : out std_ulogic := '0'; > CLKDV : out std_ulogic := '0'; > LOCKED : out std_ulogic := '0' > ); > end component; > > ---- Signal declarations used on the diagram ---- > > signal clk_2 : std_ulogic; > signal NET616 : std_ulogic; > > ---- Configuration specifications for declared components > > -- synopsys translate_off > for U1 : CLKDLL use entity VIRTEX.CLKDLL; > -- synopsys translate_on > -- synopsys translate_off > for U2 : CLKDLL use entity VIRTEX.CLKDLL; > -- synopsys translate_on > -- synopsys translate_off > for U3 : BUFG use entity VIRTEX.BUFG; > -- synopsys translate_on > > begin > > ---- Component instantiations ---- > > U1 : CLKDLL > -- synopsys translate_off > generic map ( > CLKDV_DIVIDE => 2.0 > ) > -- synopsys translate_on > port map( > CLKDV => NET616, > CLKIN => clk, > RST => reset > ); > > U2 : CLKDLL > -- synopsys translate_off > generic map ( > CLKDV_DIVIDE => 3.0 > ) > -- synopsys translate_on > port map( > CLKDV => clk_div_6, > CLKIN => clk_2, > RST => reset > ); > > U3 : BUFG > port map( > I => NET616, > O => clk_2 > ); > > ---- Terminal assignment ---- > > -- Output\buffer terminals > clk_div_2 <= clk_2; > > end b;Article: 38447
I am looking for SDH Pointer generator and interpreter(AU3,AU4) VHDL cores and VHDL examples Can someone help me, please ? ThanksArticle: 38448
i am using synplify v7.0 right now and i am trying to assign syn_hier=hard to certain modules. this attribute is going inside the sdc file. anyways, i am getting the software to crash on me with some kind of mapper error. this only occurs when i am using syn_hier=hard in the sdc file. by the way, the other options i have checked are: resource sharing, retiming, and pipelining. any help would be appreciated. thanks. strut911Article: 38449
Thanks Damir. Where I can get that file? (HR: Postovanje! Gdje mogu 'podici' taj filek?) -- D.G. "Damir Danijel Zagar" <dzagar@srce.hr> wrote in message news:a1urs3$ub8$1@sunce.iskon.hr... > Just to mention... BSDL file for ATmega128 is available. > > Damir > > "DG_1" <dgacina@san.rr.com_no.spam> wrote in message > news:lbp08.100459$AI.26190323@typhoon.san.rr.com... > > Thanks 'rickman'. > > The only problem I 'foresee' is the fact that IAR Kickstart doesn't > > have any capability of adding/editing BSDL files (or I missed something). > > Therefore, I don't see the way how to use debugging features > > of IAR Kickstart when _more_ than one chip is in the same chain. > > I guess, designers of IAR's tool-set didn't (intentionally?) > > though-out that possibility. Also, I guess, from Xilinx's perspective, > > having MSP430 in the same chain is no big deal, just add BSDL > > file for TI's part to Xilinx's 'JTAG programmer' tool. > > In the past I've used JTAG to chain-up devices (Xilinx, Lattice) > > but always from the same manufacturer, I've never mixed-up > > different chips, from different manufacturers, neither I added MPUs > > into the chain. now I guess the only way to check it up is to make > > the actual circuitry and then 'everything is in God's hands'. > > (Well, the same problem is applicable to Atmel AVmega128 > > to be chained-up with other JTAG-capable chips) > > > > > > "rickman" <spamgoeshere4@yahoo.com> wrote in message > > news:3C414ACF.EA8194EA@yahoo.com... > > > DG_1 wrote: > > > > > > > > Hi there, > > > > Has anybody tried to chain-up a MSP430 with any of JTAG-capable > > > > Xilinx chips and be able to programm both of them without problem(s) > > > > (MSP430 via IAR KickStart, Xilinx via JTAG programmer)? > > > > Or (re-arranged question):: > > > > Does IAR Kick-Start still recognizes MSP430 and/or allows other > > > > devices (other than MSP430) to be chained-up via JTAG? > > > > > > > > Thanks in advance, > > > > -- D.G. > > > > > > > > > I will be doing exactly this in a month or two. I am building a board > > > with a TMS320C6711, an MSP430F148/9, an XC2S150E and an XCR3256XL all in > > > one JTAG chain. Actually, I may leave the MSP430F148/9 out of the chain > > > depending on the answers to the questions I will be asking the vendors. > > > But I really want the rest of it in a single chain so that I can do > > > boundry scan testing on it all. The MSP430F148/9 will not be quite so > > > integrated into the rest of the board, so it does not have to be tested > > > that way. It is also important to be able to burn software into it > > > regarless of the state of the board. This will be used for initial board > > > test too. I am even considering using the MSP430F148/9 as a JTAG > > > interface for the JTAG chain. But we will see if I can get it all to > > > work together. > > > > > > If you have any results yourself, please let me know. Thanks! > > > > > > -- > > > > > > Rick "rickman" Collins > > > > > > rick.collins@XYarius.com > > > Ignore the reply address. To email me use the above address with the XY > > > removed. > > > > > > Arius - A Signal Processing Solutions Company > > > Specializing in DSP and FPGA design URL http://www.arius.com > > > 4 King Ave 301-682-7772 Voice > > > Frederick, MD 21701-3110 301-682-7666 FAX > > > > > > > > > >
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