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Jon Elson wrote: > > Peter Alfke wrote: > > > Contemplate only the -XL versions, since 5-V is now a dead-end street. > > Arrgh! Yes, of course, in PCs and other computer gear, 3.3 (and lower) > voltages are the thing. But, there are a LOT of us out here still forced > (by existing equipment or non-digital components we are interfacing > with) to work at 5 V. Please don't abandon us! The Spartan line is > going to be good for us for many projects, as long as we can still get > them! I agree that 5v is far from dead! But you would not know that from talking to the FPGA vendors. Of course, they are looking at the potential revenue and, let's face it, not many bucks will be spent on the smaller, 5 volt compatible FPGAs compared to the big, expensive low voltage parts they try their hardest to burn them selves up. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 38276
Martin Darwin wrote: > <snip> > > Well you need a simulator no matter what. The ASIC design house > typically does the layout for you (thats what part of the NRE is for) so > there is no need for layout tools. Now the synthesiser you are right, > synopsys is not cheap. A static timing tool is usally required as well. > > MD > For an FPGA ModelSim on a PC is enough, say $5K. For an ASIC though you need something that's accepted for ``sign-off'' by your vendor - normally very much more expensive - Verilog-XL, VCS, ...Article: 38277
rickman wrote: > Jon Elson wrote: > > > > Peter Alfke wrote: > > > > > Contemplate only the -XL versions, since 5-V is now a dead-end street. > > > > Arrgh! Yes, of course, in PCs and other computer gear, 3.3 (and lower) > > voltages are the thing. But, there are a LOT of us out here still forced > > (by existing equipment or non-digital components we are interfacing > > with) to work at 5 V. Please don't abandon us! The Spartan line is > > going to be good for us for many projects, as long as we can still get > > them! > > I agree that 5v is far from dead! But you would not know that from > talking to the FPGA vendors. Of course, they are looking at the > potential revenue and, let's face it, not many bucks will be spent on > the smaller, 5 volt compatible FPGAs compared to the big, expensive low > voltage parts they try their hardest to burn them selves up. > > Maybe they are in league with the makers of 100R resistor packs.Article: 38278
I've used Altera FPGA's with CMOS area sensors. The nice thing abut using CMOS imagers is that they are essentially digital parts at the I/O's. The complicated clocking and bias is handled on-chip. In general, you supply a digital clock, 3.3V supply, and an I2C interface and you get Bayer pattern out on a parallel bus. Since you have so much signal (outdoor application), the relative insensitivity of CMOS sensors as compared to CCD should not be a problem. A bunch of people make them; I've used several of Conexant's sensors. Regards Gacquer William <wgacquer@yahoo.fr> wrote in message news:<3C3C5C80.5080702@yahoo.fr>... > Hello > has anybody tried to connect a FPGA to several CCDs ( for imaging > purpose, of course ? ) > I am new to FPGA programming. > Regards, > William GacquerArticle: 38279
The largest delays are usually going to be the cell interconnect so don't kill yourself over the gate delay time, just try to reduce levels of logic. richard.padovan@wktest.com (Richard Padovan) wrote in message news:<90f772c9.0201090424.d805e9c@posting.google.com>... > Where can I find a list explaining all the delay types detailed in the > Timing Analyser report file ? Sure most are self-explanatory but some > not: eg Tf_fgm.Article: 38280
What about just typing a "*" and let your synthesizer turn it into 2 adders? This way nobody has to try to figure out why you're adding 2 shifted numbers when they're reading the code. Kenily <aiurh@iuehr.erug> wrote in message news:<ee74130.-1@WebX.sUN8CHnE>... > i want to implement a multiplier.one > multiply 0x600(Hex).how do i implement?Article: 38281
Hello Matthias, One trick to prevent PAR from using specific resources is to create a located routed hard macro (.nmc file created in FPGA Editor) that uses the resources that you want to prohibit. In your case, you would then have to use JBits to remove the macro as well as add the new logic. I'm no JBits expert, but I think this would work. Regards, Bret Matthias Dyer wrote: > Hi, > > I'm working for my final project at the Swiss Federal Institute of > Technology (ETH Zuerich). The main goal of the project is to develop a > reconfigurable system on an single FPGA (XCV800 on a XESS-Board) > consisting of a processor core and several virtual components which > can be added and removed to the system dynamically. We use JBits for > the partial reconfiguration. > > We want to do this with the following steps: > > 1) > Generating (standard flow with Xilinx-Tools) a static design with > the processor core and a place-holder for the virtual component (empty > area or maybe an anti-core). > > 2) Replacing the place-holder with the desired virtual component and > connecting it to the static part using partial configuration with JBits. > > We managed to floor-planning the design in the first step that the > place-holder is at a defined position. Our problem now is, that there > are some disturbing lines (nets from the processor core to IOBs) > through this area. > > One way to get rid of them is to manually reroute them with FPGA-Editor, > what we did with an effort for the first approach. But we'll have to do > this every time the static design changes (still isn't so static). We > are looking for a more flexible solution which can be automated. > > Is there another way to avoid routing through a certain area? To my > knowledge there aren't any area-constraints for routing not either in > JRoute. The anti-cores on the other hand reserve only a part of the > routing resources, so there isn't either a guarantee that no route will > go through. > > Used Hard-/Software: > FPGA: Xilinx XCV800HQ240 > Board: XESS XSV800 V1.1 > Software: Xilinx Foundation Series 3.1i (3.3-08i) > Synthese: FPGA Express 3.5 > JBits: v 2.8 > > Thanks > > ========================================================================== > Matthias Dyer EMail: mdyer@ee.ethz.ch > Swiss Federal Institute of Technology Zurich > Computer Engineering and Networks Laboratory > ==========================================================================Article: 38282
Anyone heard of EXPAL ? I have a couple of pals that need to convert into VHDL and the only source is in EXPAL. It looks like the original code was written in PALSM and then ran trough a converter of EXPAL. This was done by ATT. I need some sore or reference that will help me translate this. Any help would be appreciated Regards AngelArticle: 38283
You need to make sure that the .edn file generated by CoreGen is in the same directory as the .edf file generated by Symplicity. Simplicity only considers the core as a black box and ignores whats in it. In ourder to place and route you need both the .edf ( netlist from Symplicity ) and .edn ( netlist from CoreGen ). Hope this helps Angel Pino "a_darabiha" <a_darabiha@yahoo.com> wrote in message news:88a1211d.0201081317.13f3a1f1@posting.google.com... > Hi all, > can one Xilinx ISE tools experts help me please! > I have gone through the Core Generator guide but > still confused! :( here is the story: > > As a new user of Xilinx Core Generator I am trying > generate a very simple core (16bit comparator) and then > instantiate it in my vhdl design and finally synthesize and > implement it on a virtexII platform. > > The Core Generator works fine and produces .vho, .edn and > .vhd files. I then cut and paste from the .vho file to instantiate > the component in my own design with the proper port map names... > > I synthesize the desing by Synplicity VHDL compiler v6.2.0 and it seems > there is not any problem but after that in ngdbuid I get this error message: > > **************************************************************** > . > . > . > WARNING:NgdBuild:329 - Line number 5: Invalid PART record value "4003pc84" > ignored. Please consult the Xilinx Programmable Logic Data Book for valid > part/package/speed conbinations. > Writing NGO file "my_adder_coregen_ports.ngo" ... > Loading design module > "/jayar/q/q6/ahmadd/tm3/coregen/test_5/tm3a/xilinx/fpga0/my_adder_coregen_po rts. > ngo"... > > Annotating constraints to design from file "virtex0.ucf" ... > > Checking timing specifications ... > > Checking expanded design ... > ERROR:NgdBuild:604 - logical block > 'wrapped_my_adder_coregen_inst/my_adder_coregen_inst/your_instance_name' with > type 'new_comp' is unexpanded. Symbol 'new_comp' is not supported in target > 'virtexe'. > WARNING:NgdBuild:454 - logical net 'GND' has no load > WARNING:NgdBuild:454 - logical net 'VCC' has no load > > NGDBUILD Design Results Summary: > Number of errors: 1 > Number of warnings: 2 > > . > . > . > **************************************************************** > > Has any friend had this problem before? > > I have some guesses in my mind that might also help you > to figure out the problem: > > 1- I have not compiled the XilinxCore Lib. Is that the problem ? > There were several reasons for that: > - it seems compiling VHDL behavioral library requires > MTI ModelSim and in our package ModelSim is only supported > for PC and not for Solaris... > > - in fact at this time I do not need to do any simulation > and want to synthesize it directly, so I dont feel > any need for simulation. and It should be possible > to generate a core and synthesize it without any simulation in > between... > > So, is it really neccessary to compile XilinxCoreLib for synthesis? > if so, could someone help how to do that? (the info in Xilix Core > Generator guide for compile_hdl.pl is too short not clear :( ) > > 2- in page 4-33 of Core generator guide for Synplicity synthesis tool it says: > "do not read in a separate .vhd file or EDIF file for Core Generator mudule" > what dose that mean !? > > > > I would really appreciate any help, > and please let me know if the problem is not described clearly, > thanks, > a_darabiha@yahoo.comArticle: 38284
I had not had a chance to take a look at their web site. Do they publish any high speed I/O limits ? I/O speed , delays and things of that nature ? RGDSArticle: 38285
Hello all, I have to program a Virtex-E FPGA at 155MHz. For this purpose I use 8 vhdl entities,a MUX BUS and a Block RAM from the CORE GENERATOR (I use XILINX ISE 4.1 with SP2). I use for synthesis FPGA EXPRESS 3.6.1 , so I create a fpga express project where I add the vhdl sources and the 2 edn files (the one for the mux bus and the one for the block ram), is this the correct procedure? I manage to export the netlist for my design but in the PAR process I get too many timing errors!!! Thanks a lotArticle: 38286
Don't fear. We will be offering those 5-V devices for years. But they are not state-of-the-art, neither in size, performance, capability, nor price. So avoid them if you can. If not, they will still be around for a while... Peter Alfke ====================================== Jon Elson wrote: > Peter Alfke wrote: > > > Contemplate only the -XL versions, since 5-V is now a dead-end street. > > Arrgh! Yes, of course, in PCs and other computer gear, 3.3 (and lower) > voltages are the thing. But, there are a LOT of us out here still forced > (by existing equipment or non-digital components we are interfacing > with) to work at 5 V. Please don't abandon us! The Spartan line is > going to be good for us for many projects, as long as we can still get > them! > > JonArticle: 38287
rickman wrote: > JI agree that 5v is far from dead! But you would not know that from > talking to the FPGA vendors. Of course, they are looking at the > potential revenue and, let's face it, not many bucks will be spent on > the smaller, 5 volt compatible FPGAs compared to the big, expensive low > voltage parts they try their hardest to burn them selves up. Wrong statement. Some of the newer Spartan-II and even Virtex-II parts are far cheaper than their logic-equivalent predecessors. You get far more bang for the buck with the newer low-voltage parts. The old 5-V parts we just make and sell, and there is no price reduction because the cost just does not go down. How could it? Peter Alfke ===================================== > > > -- > > Rick "rickman" Collins > > rick.collins@XYarius.com > Ignore the reply address. To email me use the above address with the XY > removed. > > Arius - A Signal Processing Solutions Company > Specializing in DSP and FPGA design URL http://www.arius.com > 4 King Ave 301-682-7772 Voice > Frederick, MD 21701-3110 301-682-7666 FAXArticle: 38288
My experience is similar to that of the previous poster. You will get several times the speed out of a standard cell ASIC of the same process technology. Of course there are FPGA tricks you can use like heavy pipelining, but these are often over kill for the ASIC and will only increase the power disipation and size of your ASIC. Usually your FPGA emulation is a reduced speed (e.g 1/4 speed), but logic compatible version of the ASIC. If you've been able to get a clock period of 10nS for your FPGA, and your target is only 125MHz for your ASIC, you are WAY ahead of where you needed to be. Regards. Muzaffer Kal <muzaffer@dspia.com> wrote in message news:<c0cd3u4d2jdcp7dut03au6k55oab9n2jsq@4ax.com>... > On 4 Jan 2002 17:07:50 -0800, yujun@huawei.com (Yu Jun) wrote: > > >We are planning to develop a ASIC chips for a highspeed router. The > >majoy frequency may be 125M. Now at a verification stage, we made a > >FPGA version to check if the basic functions can work properly. But > >the FOUNDATION(virtex-II 4000-5) reports a timing contraints > >failure--the maximum logical delay is up to 9.7ns. After a very > >long-time optimization, the result is improved to 8.7ns, still not > >meet the timing requirement(8ns). > > > >we wonder if this problem exists when it goes to ASIC. I have no idea > >about ASIC's speed. I was told ASIC is faster than FPGA, if yes, how > >much faster? Seems VirtexII is already much faster than the old virtex > >or virtexE. I also notice somebody declare ASIC is NOT inherently > >faster than FPGA. Who is right? > > > >Your suggestion is very appreciated if you can help me or point me to > >the right direction to learn some basic ASIC knowledge. Thank you very > >much. > > > >----------------------- > >Yu Jun > >yujun@huawei.com > > In my experience with three designs which have seen both standard cell > and FPGA implementations, I have observed a 3 to 5 times speed up with > the ASIC implementation. The context was .25u standard cell desing and > maximum frequency in the designs was 500 MHz. One design was an 8 bit > microcontroller with lots of memory, one a 16 bit processor with > embedded 10bt implementation and the last one a small block in a > mixed signal design. These were all mostly control logic dominant > designs and the ASIC implementations were done using static cmos, DFF > registers. I think the 3-5 speed up only goes up to 500~600 MHz (i.e. > if your design times 100 MHz on an FPGA you can expect 300 to 500 MHz) > because above that speed, the clocking overhead with static cmos > becomes too high. In my latest .25u design, the worst case > setup+clk->q is around 1.5 ns so anything nearing 500 MHz leaves you > only 500 ps to work with. With domino circuit techniques you can go > much higher with a full custom design. > > Muzaffer Kal > > http://www.dspia.com > DSP algorithm implementations for FPGA systemsArticle: 38292
I'm not sure I understand your question but I'll try my hand at it because nobody else has. The Altera clock multiplication is done using hard macro PLL's on the die. The feedback circuitry is encapsulated inside the function, you just tell it what multiplication factor you want, and let Altera do the rest. "Dimitry Yegorov 1598864168" <dmyegorov@geolink-group.com> wrote in message news:<a0kbgd$97h$1@josh.sovintel.ru>... > I know that it must be an easy question, but I can't find the answer - it is > not published in the Help. Seems that some loop should be added to max2plus > PLL megafunction to implement the F*N multiplier. > Any comments are welcome, I am the beginner. > Thanks!Article: 38293
BIST = Built In Self Test Boundary Scan = A test methdology and infrastructure for performing interconnect test between devices on a PCB BIST incorporates as the acronym suggests, special purpose logic built-in to a system whose function is to perform some level of testing of the device, the connections between devices or the system. This logic is generally customized. Several CAE vendors offer applications that help in the design and insertion of this logic in existing systems. Boundary-Scan is most often referred to as JTAG or IEEE Std 1149.1. Specialized hardware is built into devices that conform to this standard. This hardware incorporates a controller and special logic at every pin connected together as a serial shift register known as a boundary-scan register. The special pin logic is access only when the controller is in test mode. The special pin logic can be used to both drive and sense logic values at the pins. This facilitates interconnect test. Fortuitously, the people who defined 1149.1 designed the controller such that it could be used to control more than just interconnect test. Rather, its functionality could be extended to allow the inclusion of instructions to control BIST, device debug and other operations. Many designers and device vendors have taken advantage of this. This has also blurred the meaning of boundary-scan as designers and vendors who use the controller for the non-interconnect test operations tend to say they are using boundary-scan to accomplish those ends. It should be noted that programmable device configuration can also be accomplished through the IEEE Std 1149.1 controller (and it has been standardized through IEEE Std 1532). I don't know if this answers your question or not. Let me know if you need further clarification. Martin Fischer wrote: > Hello, > > What is the difference between Boundary Scan and > BIST ? And what can I do with them ? > With Boundary Scan I can read out the checksum from > an PLD, how can I read the cheksum out with an > Mikrocontroller ? You can connect the microcontroller to the boundary-scan port (TAP) and shift in the necessary instructions and data to perform a checksum operation. If you are using Xilinx devices you might look at this applications note for details: http://www.xilinx.com/isp/microprocessor.htm > > > Thanks > > Martin.Fischer@fzi.deArticle: 38294
If you're only using 30% then pick a smaller part, it will be faster. And of course, using the newest generation will be faster, if sometimes only incrementally faster. If you can fit your algorithm to some special circuitry in the part such as the multipliers in the Vertex 2, etc. Josh dottavio@ised.it (Antonio) wrote in message news:<fb35ea96.0112132356.7f43b3fe@posting.google.com>... > I'm preparing a QPSK modulator, > until now I arrange it for a VIRTEX 1000 -4 , but it seem that could > be impossible to use it at a maximum clock speed of 165MHz especially > 'cause I've to put in and out that speed and this seems not possible > (..or I'm wrong ??) I'm using less than 30% of VIRTEX 1000 so my > question is which FPGA is actually the one with best speed > performance, it could be not only Xilinx 'cause my scope is to verify > that there's actually a technology where my project could be > implemented. Thanks > > AntonioArticle: 38295
In the ASIC you might not even need to use a ROM to do that decode it would be fast enough that you don't have to play those tricks and mess around with another macro (the ROM). But to answer your question, I'd venture to guess that the per bit size of a compiled ROM is about 1/8 the size of a standard cell flop, so how about the answer being 32? brad@tinyboot.com (Brad Eckert) wrote in message news:<4da09e32.0112261613.7ba94d6e@posting.google.com>... > Hi all, > > I'm going to use block RAM as a 128x32 decoder ROM in a FPGA-based CPU > model. I think if the design were converted to ASIC, the ROM would be > fairly small. Comparing gates, does anyone know about how many 16-bit > registers would fit in the die area used by a typical 128x32 ROM?Article: 38296
Angel Pino wrote: > > Anyone heard of EXPAL ? > I have a couple of pals that need to convert into VHDL and the only source > is in EXPAL. It looks like the original code was written in PALSM and then > ran trough a converter of EXPAL. This was done by ATT. > I need some sore or reference that will help me translate this. > Any help would be appreciated Most tools have a human-readable report file, and if it's PALASM, it's easy enough to read and manually recode in a higher HDL. Is EXPAL human readable ? Do you want to merge these pals into a larger device ? -jgArticle: 38297
"Ray Andraka" <ray@andraka.com> wrote in message news:3C3DB8F1.48F10CD1@andraka.com... > 155 MHz is not hard to achieve in a VirtexE (any speed grade), but you do have > to be careful about how the design is implemented, particularly making sure that > you don't have lots of levels of logic. In the timing errors the max levels of logic is 6, is this good? You will likely need to do some > floorplanning to get the speed, especially when reading from the BRAMs. If you > are accessing the BRAMs at 155 MHz, you will need registers immediately adjacent > to the BRAM with no LUTs between the BRAM and the registers, and you will have > to floorplan those to place them there. Depending on how wide the BRAMs are, > you may not be able to read them at 155MHz in a -6 or if 16 bits wide, even a -7 > part. One solution may be to run the BRAM at half the clock rate and read/write > two locations per clock by using a set of staging registers. I use 3 BRAMS (128x32) at 155MHz , I have 3 modules that access them so I use BUS MUXs for the memory arbitration (the BUS MUXs is LUT based and registered with latency 1), all 3 modules use a fsm to read and write to the BRAMs. Do you think that the logic is total wrong? In the functional simulation all seem well (if that counts :)) ) In the timing errors I get that the total delay is mostly owing to route (70% route - 30% logic), do you think that with floorplanning I will be able to decrease the delays? Thank you very much for the help , I am new into these :) > > The first step, of course, is to look at the timing report to see where your > design is not meeting the timing. Once you do that, you'll know where you need > to focus your attention. > > > > "H.L" wrote: > > > Hello all, > > > > I have to program a Virtex-E FPGA at 155MHz. For this purpose I use 8 vhdl > > entities,a MUX BUS and a Block RAM from the CORE GENERATOR (I use XILINX ISE > > 4.1 with SP2). I use for synthesis FPGA EXPRESS 3.6.1 , so I create a fpga > > express project where I add the vhdl sources and the 2 edn files (the one > > for the mux bus and the one for the block ram), is this the correct > > procedure? I manage to export the netlist for my design but in the PAR > > process I get too many timing errors!!! > > > > Thanks a lot > > -- > --Ray Andraka, P.E. > President, the Andraka Consulting Group, Inc. > 401/884-7930 Fax 401/884-7950 > email ray@andraka.com > http://www.andraka.com > > "They that give up essential liberty to obtain a little > temporary safety deserve neither liberty nor safety." > -Benjamin Franklin, 1759 > >Article: 38298
I am taking a look at the option of using a XC2Se part interfaced to a 5 volt bus and I can't seem to find an app note on the Xilinx web site. Can you point me to one? Austin Lesea wrote: > > Doug, > > The recommendation is to use a 100 ohm resistor in series with the 5V > driver output to the 3.3V powered IO bank on the Spartan IIE. This way, > if the driver can pull all the way to 5V, the forward clamping of the > input diode to Vcco limits the voltage at the input pin to Vcco+0.5V (the > diodes are intrinsic to the pmos output fets which are present in the IOB, > so they are ~ 0.5V drop). > > If you first simulate the connection in IBIS, you may find that the 5V > outputs are classic TTL (not CMOS), and can not pull above Voh(max) of a > voltage that does not exceed Vcco+0.5V (i.e. less than 3.8 V). If this is > the case, no resistor is needed to limit the input current into the > Spartan IIE. > > Many TTL parts that are CMOS used nmos pull-up transistors in the output > stage, so the Voh(max) was always ~ 0.7 V below the Vcc of 5V, or lower. > > If placing a 100 ohm resistor in series slows down the signal too much, > one can also simulate it in IBIS with a resistor to ground. A 75 ohm > resistor, for example, will load down the driver without slowing down the > signal, resulting in a lower Voh(max). > > Remember to simulate the fast/strong corner in IBIS, as that is the > cold/strong transistor/high vcc case that will be the worst case. Also > then simulate the slow/weak corner to be sure the voltages are still > within spec for the input to see 0's and 1's. > > Innoveda's Hyperlynx has a free download version that can be used for > these kinds of what if's. The demo version can not import new IBIS files, > and has other restrictions, but I highly recommend trying it out. Once > you get using it, you will be hooked, and just buy the real version. The > cost will save board respins due to bad SI, so you will end up saving > money the first time you use it. > > For those of you with the Cadence, or Mentor IBIS simulator tools, those > are also excellent, and I highly recommend them. Avant! Hspice also > imports IBIS as a subcircuit model, so it can be used for those who like > spice. > > Austin Lesea > ICDES > Xilinx > > Doug wrote: > > > I need to interface some old-fashioned 5V logic to a Spartan-IIE FPGA, > > which has 3.3V I/O. > > > > I know I could use something like a 74LVX3245, but apparently it can > > be safely done with resistors as well. In the appnote "Spartan-IIE > > Family: Frequently Asked Questions" (Xilinx document #FAQ100), it > > says: > > > > "The Spartan-IIE is 3.3V I/O compatible and will only support 5.0V > > I/Os when an external pull-up resistor is used." > > > > ...and that's all the info I've been able to find so far. > > > > Before I proceed, I would like to see more specific recommendations > > (preferably from Xilinx!) about how best to do this. Is anyone out > > there aware of any other documents detailing Xilinx' recommended > > method, specifically for the Spartan-IIE family? > > > > Thanks in advance, > > > > Doug Jones -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 38299
While that is true (the pick a smaller part it will be faster) with the Altera parts, it is not true in
the Xilinx parts with some minor variations in the setup and clock to out at the IOBs due to the size of
the clock network. Unlike Altera, the Xilinx structure features remain the same, as does the timing as
you move up the device size within the family. The virtex -4 is the earliest and slowest family of the
virtex architecture. If you are doing arithmetic logic, using block RAM or using the shift register
elements, you won't get those elements running at 165 MHz (with the exception of short carry chains) in
the -4 part. Unless you have a good reason (already have the parts on a board, forced to use -4 because
it is a Q-pro part, etc), move up to the Virtex-E family, it is faster and cheaper plus it has more BRAM
more clock DLLs and more options on the IO standards. You can make 165 MHz in pretty easily there. A
Virtex E-8 can run (with very careful design) at around 250 MHz, and the newer virtexII family is quite a
bit faster.
Jay wrote:
> If you're only using 30% then pick a smaller part, it will be faster.
> And of course, using the newest generation will be faster, if
> sometimes only incrementally faster. If you can fit your algorithm to
> some special circuitry in the part such as the multipliers in the
> Vertex 2, etc.
>
> Josh
>
> dottavio@ised.it (Antonio) wrote in message news:<fb35ea96.0112132356.7f43b3fe@posting.google.com>...
> > I'm preparing a QPSK modulator,
> > until now I arrange it for a VIRTEX 1000 -4 , but it seem that could
> > be impossible to use it at a maximum clock speed of 165MHz especially
> > 'cause I've to put in and out that speed and this seems not possible
> > (..or I'm wrong ??) I'm using less than 30% of VIRTEX 1000 so my
> > question is which FPGA is actually the one with best speed
> > performance, it could be not only Xilinx 'cause my scope is to verify
> > that there's actually a technology where my project could be
> > implemented. Thanks
> >
> > Antonio
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
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