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Because the synthesizer may not recognize that it can be done with an adder.
Often a template is used which in turn instantiates the vendor core for the
multiplier. I believe if you do this in synplicity, you'll get a LUT based sum
of partial products construction based on the Xilinx coregen constant coefficient
multiplier. The synthesis is not smart enough to distill that down to an adder
(it would if the multiplier template produced a full array multiplier, but that
is usually a very inefficient construct in an FPGA).
Jay wrote:
> What about just typing a "*" and let your synthesizer turn it into 2
> adders? This way nobody has to try to figure out why you're adding 2
> shifted numbers when they're reading the code.
>
> Kenily <aiurh@iuehr.erug> wrote in message news:<ee74130.-1@WebX.sUN8CHnE>...
> > i want to implement a multiplier.one
> > multiply 0x600(Hex).how do i implement?
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 38301
A 32 bit barrel shift with 32 bits in and out should occupy 160 LEs.
Since the proper construction does not use the cascade/carry chains, it
can be laid out with 2 bits per LAB, so that it takes up 16 LABs.
Depending on how they are laid out, There may not be enough row routes
to squeeze it all into a single megalab. Unfortunately, Altera does not
provide information on the row route connections available at each LAB
(it is a sparse connection matrix), so doing hand placement can actually
hurt performance and density by forcing wires to go through an
intermediate lab to make connections. That said, the routing time is
fairly uniform at each level of hierarchy in Altera, so you may find
that you get little additional performance trying to do the placement
yourself.
ssy wrote:
> Hi everyone
>
> I am looking for a fast 32 bit barrel shifter for APEX20K400E, I use
> the LPM from Altera, but after P&R, I found it ocuppy three MegaLAB,
> and many wire run between them.
>
> so I think if somebody have hand place the shifter?
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 38302Hi, Rick Filipkiewicz <rick@algor.co.uk> wrote: > Martin Darwin wrote: >> <snip> >> >> Well you need a simulator no matter what. The ASIC design house >> typically does the layout for you (thats what part of the NRE is for) >> so there is no need for layout tools. Now the synthesiser you are >> right, synopsys is not cheap. A static timing tool is usally required >> as well. >> >> MD >> > > For an FPGA ModelSim on a PC is enough, say $5K. For an ASIC though you > need something that's accepted for ``sign-off'' by your vendor - > normally very much more expensive - Verilog-XL, VCS, ... Totaly wrong. ModelSim is fine for ASIC. But you need a full version to get full speed and the ability to do designs with more gates. A Full version will cost as much as other simulators (Think about 50k plus 15% yearly maintance). BTW I had to use the crippled version of synthesiser that come with FPGAs (nearly) for free and got a lot of problems. If you do a lot of FPGAs its worthy to buy a full synthesiser. bye Thomas -- Thomas Stanka TE/EMD4 Space Communications Systems Tesat Spacecom GmbH & Co KG thomas.stanka@tesat.deArticle: 38303
On Fri, 11 Jan 2002 06:57:52 GMT, Ray Andraka <ray@andraka.com> wrote: >Because the synthesizer may not recognize that it can be done with an adder. >Often a template is used which in turn instantiates the vendor core for the >multiplier. I believe if you do this in synplicity, you'll get a LUT based sum >of partial products construction based on the Xilinx coregen constant coefficient >multiplier. The synthesis is not smart enough to distill that down to an adder >(it would if the multiplier template produced a full array multiplier, but that >is usually a very inefficient construct in an FPGA). Hi Ray, I think y <= (x * 4) + (x * 2); would be ok, and it is still fairly easy to read (easier than the shifts, anyway). Would you agree? Next year the synthesisers will be a little more clever, and they'll reduce this down to y <= x * 6; before doing code generation, so we're back to where we started. Thanks for the Christmas card. Allan. >Jay wrote: > >> What about just typing a "*" and let your synthesizer turn it into 2 >> adders? This way nobody has to try to figure out why you're adding 2 >> shifted numbers when they're reading the code. >> >> Kenily <aiurh@iuehr.erug> wrote in message news:<ee74130.-1@WebX.sUN8CHnE>... >> > i want to implement a multiplier.one >> > multiply 0x600(Hex).how do i implement? > >-- >--Ray Andraka, P.E. >President, the Andraka Consulting Group, Inc. >401/884-7930 Fax 401/884-7950 >email ray@andraka.com >http://www.andraka.com > > "They that give up essential liberty to obtain a little > temporary safety deserve neither liberty nor safety." > -Benjamin Franklin, 1759 >Article: 38304
The full PE version for modelsim is about $6K, and is plenty of simulator for
FPGA design. There is a watered down version available with vendor tools that
is crippled and costs less. The full PE seat is not crippled in any way.
Frankly though, if I had to pick a simulator for FPGAs, I'd take Aldec over
Modelsim unless the boss (the customer) insisted on having modelsim. Aldec is
about the same costs for an equivalent seat and comes with a much more user
friendly interface, plus a first class entry environment, plus superb
documentation.
AFAIK, the PE version of modelsim really doesn't cut it for ASIC work because
of the sign off requirements there. If you are looking at an SE seat, then you
are going to be up in the much higher price range, but then that is really
overkill for FPGA design.
I do FPGAs day in and day out, at a current rate of about a dozen large designs
a year. I use both modelsim and aldec. I use modelsim when the customer
demands it, or when I want to run a long sim in the background while I am
working on something else in Aldec.
Thomas Stanka wrote:
> Hi,
>
> Rick Filipkiewicz <rick@algor.co.uk> wrote:
> > Martin Darwin wrote:
> >> <snip>
> >>
> >> Well you need a simulator no matter what. The ASIC design house
> >> typically does the layout for you (thats what part of the NRE is for)
> >> so there is no need for layout tools. Now the synthesiser you are
> >> right, synopsys is not cheap. A static timing tool is usally required
> >> as well.
> >>
> >> MD
> >>
> >
> > For an FPGA ModelSim on a PC is enough, say $5K. For an ASIC though you
> > need something that's accepted for ``sign-off'' by your vendor -
> > normally very much more expensive - Verilog-XL, VCS, ...
>
> Totaly wrong. ModelSim is fine for ASIC. But you need a full version to get
> full speed and the ability to do designs with more gates. A Full version
> will cost as much as other simulators (Think about 50k plus 15% yearly
> maintance).
>
> BTW I had to use the crippled version of synthesiser that come with FPGAs
> (nearly) for free and got a lot of problems. If you do a lot of FPGAs its
> worthy to buy a full synthesiser.
>
> bye Thomas
>
> --
> Thomas Stanka TE/EMD4
> Space Communications Systems
> Tesat Spacecom GmbH & Co KG
> thomas.stanka@tesat.de
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 38305Hi! The smallest reconfiguration unit of a Xilinx Virtex is a column. So if I want to change a single bit in a frame, I have to read/write all frames in a column. Read/write is done serially (shift register). Are there any transients, in the configuration during the shift process with every clock? Or is the "final" configuration buffered by FFs for every configuration bit and only changed through a final clock? Assuming the column bit stream of a new configuration is the same as the existing bit stream: Are there any transients in the configuration at the time the FPGA is reconfigured? Maybe someone can comment on the runtime reconfiguration process of other than Xilinx devices, too. Thanks for your help. MichaelArticle: 38306
Hi Ray Thanks for your help first but I have some different idea from you everytime before I compile in quartus, I assign the shifter to a custom region that hold three Megalab, it actually took almost every le in that 3 megalab(about 450 le), this is my first question, you say it ocuppy only 160 le, how to achive this? BTW, my shifter is 32 bit rotate left shifter, and every compilation get different route result, so I think the place and route information is not contain in the lib from altera, the P&R of the shifter is perform on the fly with the other logic of the design, is that right? hope for further help from you Ray Andraka <ray@andraka.com> wrote in message news:<3C3E8F95.C4CD51B2@andraka.com>... > A 32 bit barrel shift with 32 bits in and out should occupy 160 LEs. > Since the proper construction does not use the cascade/carry chains, it > can be laid out with 2 bits per LAB, so that it takes up 16 LABs. > Depending on how they are laid out, There may not be enough row routes > to squeeze it all into a single megalab. Unfortunately, Altera does not > provide information on the row route connections available at each LAB > (it is a sparse connection matrix), so doing hand placement can actually > hurt performance and density by forcing wires to go through an > intermediate lab to make connections. That said, the routing time is > fairly uniform at each level of hierarchy in Altera, so you may find > that you get little additional performance trying to do the placement > yourself. > > ssy wrote: > > > Hi everyone > > > > I am looking for a fast 32 bit barrel shifter for APEX20K400E, I use > > the LPM from Altera, but after P&R, I found it ocuppy three MegaLAB, > > and many wire run between them. > > > > so I think if somebody have hand place the shifter? > > -- > --Ray Andraka, P.E. > President, the Andraka Consulting Group, Inc. > 401/884-7930 Fax 401/884-7950 > email ray@andraka.com > http://www.andraka.com > > "They that give up essential liberty to obtain a little > temporary safety deserve neither liberty nor safety." > -Benjamin Franklin, 1759Article: 38307
Bret Wade wrote: > One trick to prevent PAR from using specific resources is to create a > located routed hard macro (.nmc file created in FPGA Editor) that uses the > resources that you want to prohibit. In your case, you would then have to > use JBits to remove the macro as well as add the new logic. I'm no JBits > expert, but I think this would work. There is a document on cores and anti-cores in the JBits documentation, and an additional papaer from Phil-James Roxby which appeared at RAW2001. These papers explain, how it is possible to prevent placement of componente in a certain FPGA area. Basically this can be done, by eating up all logic ressources in a CLB, such that no other element can be placed in this CLB. This can be done by instantiating SRL16 elements in all CLBs in the area. BUT, this method can only be used for preventing the placement of _logic_ elements and registers in a certain area. It has no influence on _routing_. Is there a way to create a hard macro, that could be placed in a design that either prohibits routing through this area, or use all routing ressources in this area, that no additional routs can pass this area? Is there a documentation on the Xilinx .nmc file format out there, that one could these files automatically, without FPGA editor? Best regards, ChristianArticle: 38308
"Christian Plessl" <plessl@remove.........thz.ch> wrote > Is there a way to create a hard macro, that could be placed in a design > that either prohibits routing through this area, or use all routing > ressources in this area, that no additional routs can pass this area? > > Is there a documentation on the Xilinx .nmc file format out there, that one > could these files automatically, without FPGA editor? Maybe the routing could be blocked by generating a chunk of XDL?Article: 38309
Jay I would be interested im playing with such a design. Could you e-mail me more info, ie schematics parts lists and code. Thanks mpbrown@magma.ca On 10 Jan 2002 15:26:25 -0800, kayrock66@yahoo.com (Jay) wrote: >I've used Altera FPGA's with CMOS area sensors. The nice thing abut >using CMOS imagers is that they are essentially digital parts at the >I/O's. The complicated clocking and bias is handled on-chip. In >general, you supply a digital clock, 3.3V supply, and an I2C interface >and you get Bayer pattern out on a parallel bus. Since you have so >much signal (outdoor application), the relative insensitivity of CMOS >sensors as compared to CCD should not be a problem. A bunch of people >make them; I've used several of Conexant's sensors. > >Regards > > >Gacquer William <wgacquer@yahoo.fr> wrote in message news:<3C3C5C80.5080702@yahoo.fr>... >> Hello >> has anybody tried to connect a FPGA to several CCDs ( for imaging >> purpose, of course ? ) >> I am new to FPGA programming. >> Regards, >> William GacquerArticle: 38310
Rick Filipkiewicz wrote: > > Martin Darwin wrote: > > > <snip> > > > > Well you need a simulator no matter what. The ASIC design house > > typically does the layout for you (thats what part of the NRE is for) so > > there is no need for layout tools. Now the synthesiser you are right, > > synopsys is not cheap. A static timing tool is usally required as well. > > > > MD > > > > For an FPGA ModelSim on a PC is enough, say $5K. For an ASIC though you need something > that's accepted for ``sign-off'' by your vendor - normally very much more expensive - > Verilog-XL, VCS, ... Yup like Modelsim. That's all we use around here for ASICs & FPGAs. Modelsim works just fine. Vendors don't usually care about your simulator (so long as they have the libraries). Static timing and formal verification results are used for signoff. MD -- Martin Darwin ASIC Design Engineer Tel +1 (613) 784-8873 Alcatel CanadaArticle: 38311
I recently acquired a PalPro-2 by Logical Devices without software in order to burn 16L8 PAL's for vintage computers that I restore. I have had zero success with contacting Logical Devices. Does anyone out there have a copy of the software for this device? (Please don't suggest I got out and buy/build another burner..... :) Since I'm not a regular in this newsgroup, feel free to email me directly. Regards, Dan BensonArticle: 38312
Well, You really need to simulate YOUR pcb with YOUR connected devices, and then decide which IO standard will meet your needs. Some considerations are: single or double data rate, SSOs, clock forwarded, or system clock, single ended IO required, or if differential can be used. Typical performance numbers are ~180 MHz (360 Mbs) for hstl, sstl, and up to 840 Mbs for LVDS. The newer LVDCI (digitally controlled impedance) provides for balanced drivers (nearer to 50% dutyc cycle control) so it can be used for DDR applications at higher frequencies than LVTTL or LVCMOS. Please go to the web site, and visit: http://www.xilinx.com/xlnx/xil_prodcat_landingpage.jsp?title=Signal+Integrity And look at the IBIS simulation pages. That is where you need to go to find the answer to the question. Austin BM wrote: > I had not had a chance to take a look at their web site. Do they > publish any high speed I/O limits ? I/O speed , delays and things of > that nature ? > RGDSArticle: 38313
Hello, I'm looking for people who had problems targeting ProAsic with Libero. We could share our experience. Thank you, Eric Lukac-Kuruc Klavis Technologies s.a.Article: 38314
Just a quick comment, If you compare the same techology ASIC with the same technology FPGA, the ASIC is always faster. This is a "no-brainer." But, the latest technology ASIC is always late. For example, how many 0.15u ASICs are here today with advanced .12u gates? Virtex II was introduced and sampled a year ago, and is in production NOW. So, Virtex II is faster than many available ASIC/ASSP foundry processes today, as ASICs are in .25u, followed by some in .18u (followed by many in development for smaller processes with a handful sampling). In fact, I would bet there are more .35u and larger ASICs being manufactured than all other ASIC processes combined. We are ususally one or two generations ahead with a standard FPGA product compared to a custom ASIC. Just think, if you start today designing your ASIC, you will not only be late to market, but slower than the FPGA solution! Austin Jay wrote: > My experience is similar to that of the previous poster. You will get > several times the speed out of a standard cell ASIC of the same > process technology. Of course there are FPGA tricks you can use like > heavy pipelining, but these are often over kill for the ASIC and will > only increase the power disipation and size of your ASIC. Usually > your FPGA emulation is a reduced speed (e.g 1/4 speed), but logic > compatible version of the ASIC. If you've been able to get a clock > period of 10nS for your FPGA, and your target is only 125MHz for your > ASIC, you are WAY ahead of where you needed to be. > > Regards. > > Muzaffer Kal <muzaffer@dspia.com> wrote in message news:<c0cd3u4d2jdcp7dut03au6k55oab9n2jsq@4ax.com>... > > On 4 Jan 2002 17:07:50 -0800, yujun@huawei.com (Yu Jun) wrote: > > > > >We are planning to develop a ASIC chips for a highspeed router. The > > >majoy frequency may be 125M. Now at a verification stage, we made a > > >FPGA version to check if the basic functions can work properly. But > > >the FOUNDATION(virtex-II 4000-5) reports a timing contraints > > >failure--the maximum logical delay is up to 9.7ns. After a very > > >long-time optimization, the result is improved to 8.7ns, still not > > >meet the timing requirement(8ns). > > > > > >we wonder if this problem exists when it goes to ASIC. I have no idea > > >about ASIC's speed. I was told ASIC is faster than FPGA, if yes, how > > >much faster? Seems VirtexII is already much faster than the old virtex > > >or virtexE. I also notice somebody declare ASIC is NOT inherently > > >faster than FPGA. Who is right? > > > > > >Your suggestion is very appreciated if you can help me or point me to > > >the right direction to learn some basic ASIC knowledge. Thank you very > > >much. > > > > > >----------------------- > > >Yu Jun > > >yujun@huawei.com > > > > In my experience with three designs which have seen both standard cell > > and FPGA implementations, I have observed a 3 to 5 times speed up with > > the ASIC implementation. The context was .25u standard cell desing and > > maximum frequency in the designs was 500 MHz. One design was an 8 bit > > microcontroller with lots of memory, one a 16 bit processor with > > embedded 10bt implementation and the last one a small block in a > > mixed signal design. These were all mostly control logic dominant > > designs and the ASIC implementations were done using static cmos, DFF > > registers. I think the 3-5 speed up only goes up to 500~600 MHz (i.e. > > if your design times 100 MHz on an FPGA you can expect 300 to 500 MHz) > > because above that speed, the clocking overhead with static cmos > > becomes too high. In my latest .25u design, the worst case > > setup+clk->q is around 1.5 ns so anything nearing 500 MHz leaves you > > only 500 ps to work with. With domino circuit techniques you can go > > much higher with a full custom design. > > > > Muzaffer Kal > > > > http://www.dspia.com > > DSP algorithm implementations for FPGA systemsArticle: 38315
rickman wrote: > > Matthias Dyer wrote: > > > > Hi, > > > > I'm working for my final project at the Swiss Federal Institute of > > Technology (ETH Zuerich). The main goal of the project is to develop a > > reconfigurable system on an single FPGA (XCV800 on a XESS-Board) > > consisting of a processor core and several virtual components which > > can be added and removed to the system dynamically. We use JBits for > > the partial reconfiguration. > > > > We want to do this with the following steps: > > > > 1) > > Generating (standard flow with Xilinx-Tools) a static design with > > the processor core and a place-holder for the virtual component (empty > > area or maybe an anti-core). > > > > 2) Replacing the place-holder with the desired virtual component and > > connecting it to the static part using partial configuration with JBits. > > > > We managed to floor-planning the design in the first step that the > > place-holder is at a defined position. Our problem now is, that there > > are some disturbing lines (nets from the processor core to IOBs) > > through this area. > > > > One way to get rid of them is to manually reroute them with FPGA-Editor, > > what we did with an effort for the first approach. But we'll have to do > > this every time the static design changes (still isn't so static). We > > are looking for a more flexible solution which can be automated. > > > > Is there another way to avoid routing through a certain area? To my > > knowledge there aren't any area-constraints for routing not either in > > JRoute. The anti-cores on the other hand reserve only a part of the > > routing resources, so there isn't either a guarantee that no route will > > go through. > > > > Used Hard-/Software: > > FPGA: Xilinx XCV800HQ240 > > Board: XESS XSV800 V1.1 > > Software: Xilinx Foundation Series 3.1i (3.3-08i) > > Synthese: FPGA Express 3.5 > > JBits: v 2.8 > > > > Thanks > > I have not seen any way to do this. The two missing pieces in design for > partial reconfiguration are "keep routes in this area" and "keep routes > out of this area". To the best of my knowledge, Xilinx does not support > either one in any way. > > I like the idea of an "anti-core". I assume you are defining blocks of > the chip that are "pre-routed", but will be removed from the actual > routed file before it is finallized. It might be possible to tie up all > of the routing resources on the periphery of the "anti-core". For a wire > to get into the block, it must pass through the edge. But then I guess > there are any number of wires that lead into a block at different levels > so this is still not an easy task. > > If you find a way to get this working, I would be very interested in how > to do it. The pieces mentioned as missing are only really missing if you are trying to do all this at design time using mainstream tools. If you defer routing to run-time and use JBits, then the fact that routes run through the section you want to use doesn't really matter - it's like implementing your design on an FPGA with more limited routing resources. The router will find a way. The anti-core I wrote that is mentioned in Christian's post does indeed tie up the routing resources required on the interface. The interface does not need to be the geometric edge of the block, but the idea is if you have a static wire that needs to get to the F3 input of such and such a look up table, then this is done at design time. All other wires in the anti-core are ripped up, and the new logic dropped into the space reserved. The routing within the new logic is then performed using whatever resources are free. It works suprisingly well. Phil -- --------------------------------------------------------------------- __ / /\/ Dr Phil James-Roxby Direct Dial: 303-544-5545 \ \ Staff Software Engineer Fax: Unreliable use email :-) / / Loki/DARPA Email: phil.james-roxby@xilinx.com \_\/\ Xilinx Boulder ---------------------------------------------------------------------Article: 38316
check out: http://www.xilinx.com/xlnx/xil_prodcat_landingpage.jsp?title=Signal+Integrity under IBIS simulations Austin rickman wrote: > I am taking a look at the option of using a XC2Se part interfaced to a 5 > volt bus and I can't seem to find an app note on the Xilinx web site. > Can you point me to one? > > Austin Lesea wrote: > > > > Doug, > > > > The recommendation is to use a 100 ohm resistor in series with the 5V > > driver output to the 3.3V powered IO bank on the Spartan IIE. This way, > > if the driver can pull all the way to 5V, the forward clamping of the > > input diode to Vcco limits the voltage at the input pin to Vcco+0.5V (the > > diodes are intrinsic to the pmos output fets which are present in the IOB, > > so they are ~ 0.5V drop). > > > > If you first simulate the connection in IBIS, you may find that the 5V > > outputs are classic TTL (not CMOS), and can not pull above Voh(max) of a > > voltage that does not exceed Vcco+0.5V (i.e. less than 3.8 V). If this is > > the case, no resistor is needed to limit the input current into the > > Spartan IIE. > > > > Many TTL parts that are CMOS used nmos pull-up transistors in the output > > stage, so the Voh(max) was always ~ 0.7 V below the Vcc of 5V, or lower. > > > > If placing a 100 ohm resistor in series slows down the signal too much, > > one can also simulate it in IBIS with a resistor to ground. A 75 ohm > > resistor, for example, will load down the driver without slowing down the > > signal, resulting in a lower Voh(max). > > > > Remember to simulate the fast/strong corner in IBIS, as that is the > > cold/strong transistor/high vcc case that will be the worst case. Also > > then simulate the slow/weak corner to be sure the voltages are still > > within spec for the input to see 0's and 1's. > > > > Innoveda's Hyperlynx has a free download version that can be used for > > these kinds of what if's. The demo version can not import new IBIS files, > > and has other restrictions, but I highly recommend trying it out. Once > > you get using it, you will be hooked, and just buy the real version. The > > cost will save board respins due to bad SI, so you will end up saving > > money the first time you use it. > > > > For those of you with the Cadence, or Mentor IBIS simulator tools, those > > are also excellent, and I highly recommend them. Avant! Hspice also > > imports IBIS as a subcircuit model, so it can be used for those who like > > spice. > > > > Austin Lesea > > ICDES > > Xilinx > > > > Doug wrote: > > > > > I need to interface some old-fashioned 5V logic to a Spartan-IIE FPGA, > > > which has 3.3V I/O. > > > > > > I know I could use something like a 74LVX3245, but apparently it can > > > be safely done with resistors as well. In the appnote "Spartan-IIE > > > Family: Frequently Asked Questions" (Xilinx document #FAQ100), it > > > says: > > > > > > "The Spartan-IIE is 3.3V I/O compatible and will only support 5.0V > > > I/Os when an external pull-up resistor is used." > > > > > > ...and that's all the info I've been able to find so far. > > > > > > Before I proceed, I would like to see more specific recommendations > > > (preferably from Xilinx!) about how best to do this. Is anyone out > > > there aware of any other documents detailing Xilinx' recommended > > > method, specifically for the Spartan-IIE family? > > > > > > Thanks in advance, > > > > > > Doug Jones > > -- > > Rick "rickman" Collins > > rick.collins@XYarius.com > Ignore the reply address. To email me use the above address with the XY > removed. > > Arius - A Signal Processing Solutions Company > Specializing in DSP and FPGA design URL http://www.arius.com > 4 King Ave 301-682-7772 Voice > Frederick, MD 21701-3110 301-682-7666 FAXArticle: 38317
What were your problems? "Eric Lukac-Kuruc" <eric.lukac-kuruc@iname.com> wrote in message news:3c3f09af.94671560@news.pandora.be... > Hello, > > I'm looking for people who had problems targeting ProAsic with Libero. > We could share our experience. > > Thank you, > > Eric Lukac-Kuruc > Klavis Technologies s.a.Article: 38318
It is readable but the syntax is not very straight forward. I will like to have a reference card that will assure me that my interpretation is correct. Yes, I am trying to put all those pals in one FPGA. Thanks Angel "Jim Granville" <jim.granville@designtools.co.nz> wrote in message news:3C3E4FF7.1B04@designtools.co.nz... > Angel Pino wrote: > > > > Anyone heard of EXPAL ? > > I have a couple of pals that need to convert into VHDL and the only source > > is in EXPAL. It looks like the original code was written in PALSM and then > > ran trough a converter of EXPAL. This was done by ATT. > > I need some sore or reference that will help me translate this. > > Any help would be appreciated > > Most tools have a human-readable report file, and if it's PALASM, > it's easy enough to read and manually recode in a higher HDL. > Is EXPAL human readable ? > > Do you want to merge these pals into a larger device ? > > -jgArticle: 38319
"BM" <bm007@pacbell.net> schrieb im Newsbeitrag news:b5215890.0201101650.651206e8@posting.google.com... > I had not had a chance to take a look at their web site. Do they > publish any high speed I/O limits ? I/O speed , delays and things of > that nature ? They do. 622 Mbit per second are achievable with LVDS IOs using DDR clocking. With carefull design, even 840 Mbit per second are possible (according to Xilinx) -- MfG FalkArticle: 38320
Hello Christian, Please see my comments below. Regards, Bret Christian Plessl wrote: > Bret Wade wrote: > > > One trick to prevent PAR from using specific resources is to create a > > located routed hard macro (.nmc file created in FPGA Editor) that uses the > > resources that you want to prohibit. In your case, you would then have to > > use JBits to remove the macro as well as add the new logic. I'm no JBits > > expert, but I think this would work. After rethinking this I realized that there is no need remove the macro using JBits. Simply delete the macro in FPGA Editor after place and route. > > > There is a document on cores and anti-cores in the JBits documentation, and > an additional papaer from Phil-James Roxby which appeared at RAW2001. These > papers explain, how it is possible to prevent placement of componente in a > certain FPGA area. Basically this can be done, by eating up all logic > ressources in a CLB, such that no other element can be placed in this CLB. > This can be done by instantiating SRL16 elements in all CLBs in the area. > > BUT, this method can only be used for preventing the placement of _logic_ > elements and registers in a certain area. It has no influence on _routing_. > > Is there a way to create a hard macro, that could be placed in a design > that either prohibits routing through this area, or use all routing > ressources in this area, that no additional routs can pass this area? Yes, that was my point, that a macro could be created that uses the routing resources that need to be reserved. This technique has been used successfully in the past to prevent the router from using known bad resources, usually cases where the software device representation didn't match the hardware. In that case, there was no need to later remove the macro. > > Is there a documentation on the Xilinx .nmc file format out there, that one > could these files automatically, without FPGA editor? The .nmc macro is an old feature dating back to the NeoCAD tools and EPIC and is well documented. Here is a link to our online docs: http://toolbox.xilinx.com/docsan/3_1i/data/common/fpg/chap04/fpg04000.htm. Regarding automatic macro creation, since any .ncd file can be converted to an .nmc, it would be possible to use JBits to create an .ncd and then convert the .ncd to an .nmc using FPGA Editor (File-->Save as macro). Since no external pins would be needed for an interface, the only remaining operation is to set a reference component (Select component, Edit-->Set Macro Reference Comp). > > > Best regards, > ChristianArticle: 38321
Phil James-Roxby wrote: > > rickman wrote: > > I have not seen any way to do this. The two missing pieces in design for > > partial reconfiguration are "keep routes in this area" and "keep routes > > out of this area". To the best of my knowledge, Xilinx does not support > > either one in any way. > > > > I like the idea of an "anti-core". I assume you are defining blocks of > > the chip that are "pre-routed", but will be removed from the actual > > routed file before it is finallized. It might be possible to tie up all > > of the routing resources on the periphery of the "anti-core". For a wire > > to get into the block, it must pass through the edge. But then I guess > > there are any number of wires that lead into a block at different levels > > so this is still not an easy task. > > > > If you find a way to get this working, I would be very interested in how > > to do it. > > The pieces mentioned as missing are only really missing if you are > trying to do all this at design time using mainstream tools. If you > defer routing to run-time and use JBits, then the fact that routes run > through the section you want to use doesn't really matter - it's like > implementing your design on an FPGA with more limited routing > resources. The router will find a way. > The anti-core I wrote that is mentioned in Christian's post does indeed > tie up the routing resources required on the interface. The interface > does not need to be the geometric edge of the block, but the idea is if > you have a static wire that needs to get to the F3 input of such and > such a look up table, then this is done at design time. All other wires > in the anti-core are ripped up, and the new logic dropped into the space > reserved. The routing within the new logic is then performed using > whatever resources are free. It works suprisingly well. > Phil Phil, Thanks for your reply. I think I understand what you are saying, that you don't have to control the routing at compile time, but rather just as long as there is sufficient routing available, it can be done at "run-time". There are two possible problems that I see. The first is that my "run-time" does not include a PC. So running Jbits when my board boots up is not an option. Even if it was, this is not significantly different from rerunning the compiler since any time you change routing, you must reverify timing. So it would take significant clock time and must be reviewed by a human. So the practicality for many embedded apps is not there. The second issue is the reduced routability that may result. This may not be a big problem in a chip that is not used fully, but again, in an embedded design it could cause a problem at "run-time" that would require intervention by a human. BTW, I am not very familiar with Jbits other than to know that it is often recommended for this approach. I assume that Jbits has the ability to do auto routing? For my application it might be possible to use Jbits in a mid level where a PC must be attached anytime the HW is changed. A new bit file is generated and saved in the flash. But it would still be much easier to configure "stand-alone" blocks of logic that do not overlap except at the edges. Oh, yes, I forgot that this is another required function that is not currently available in the P&R tools, partial routes to defined endpoints. But then I guess the end points could be logic blocks. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 38322
Bret Wade wrote: > > Hello Christian, > > Please see my comments below. > > Regards, > Bret > > Christian Plessl wrote: > > > Bret Wade wrote: > > > > > One trick to prevent PAR from using specific resources is to create a > > > located routed hard macro (.nmc file created in FPGA Editor) that uses the > > > resources that you want to prohibit. In your case, you would then have to > > > use JBits to remove the macro as well as add the new logic. I'm no JBits > > > expert, but I think this would work. > > After rethinking this I realized that there is no need remove the macro using > JBits. Simply delete the macro in FPGA Editor after place and route. Bret, are you saying that a macro like this can be treated as a single object and removed with a single command in the FPGA Editor? > > Is there a way to create a hard macro, that could be placed in a design > > that either prohibits routing through this area, or use all routing > > ressources in this area, that no additional routs can pass this area? > > Yes, that was my point, that a macro could be created that uses the routing > resources that need to be reserved. This technique has been used successfully in > the past to prevent the router from using known bad resources, usually cases > where the software device representation didn't match the hardware. In that > case, there was no need to later remove the macro. > > > > > Is there a documentation on the Xilinx .nmc file format out there, that one > > could these files automatically, without FPGA editor? > > The .nmc macro is an old feature dating back to the NeoCAD tools and EPIC and is > well documented. Here is a link to our online docs: > http://toolbox.xilinx.com/docsan/3_1i/data/common/fpg/chap04/fpg04000.htm. > > Regarding automatic macro creation, since any .ncd file can be converted to an > .nmc, it would be possible to use JBits to create an .ncd and then convert the > .ncd to an .nmc using FPGA Editor (File-->Save as macro). Since no external pins > would be needed for an interface, the only remaining operation is to set a > reference component (Select component, Edit-->Set Macro Reference Comp). What if external pins are needed? In my application, I will be defining five blocks of logic all connected to a common bus and to external pins. One block would have a lot of IO. The remaining four blocks are all equivalent with only about 30 IOs. These four blocks are each loaded with a design for 1 of N possible interfaces that match the HW that is plugged into the board. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 38323
While I cant write with total authority on this subject, here are my beliefs on your questions: On Fri, 11 Jan 2002 11:26:45 +0100, Michael Boehnel <boehnel@iti.tu-graz.ac.at> wrote: >Hi! > >The smallest reconfiguration unit of a Xilinx Virtex is a column. So if >I want to change a single bit in a frame, I have to read/write all >frames in a column. Read/write is done serially (shift register). The smallest reconfiguration unit of a Xilinx Virtex is a frame. So you only have to send the frames you want to change. >Are there any transients, in the configuration during the shift process >with every clock? Or is the "final" configuration buffered by FFs for >every configuration bit and only changed through a final clock? The data is shifted into the frame register, then transferred in parallel to the actual frame within the main array. >Assuming the column bit stream of a new configuration is the same as the >existing bit stream: >Are there any transients in the configuration at the time the FPGA is >reconfigured? Dont know. It is either just over written (no glitch), or there may be a reset cycle that sets the frame to all 0 (the equiv of the housecleaning that is done for complete chip configuration, but just for the selected frame), and then writes the frame register to the frame, setting the bits as needed. My guess is that there is probably no glitch. >Maybe someone can comment on the runtime reconfiguration process of >other than Xilinx devices, too. All RAM based FPGAs have the ability to be reconfigured. The devices from Atmel also have partial reconfiguration, and can do it at a finer granularity than the Xilinx parts. >Thanks for your help. >Michael Philip Freidin FliptronicsArticle: 38324
I am finalizing my FPGA selection for a line of DSP boards that we will be making for a number of years. I have always been more familiar with Xilinx but had a chance to work with the Altera 10K parts this past year. They seem ok, but the nearly identical ACEX 1K family is better in most regards. But the gate size is limited if we are looking at having future growth and I am not finding as good a price as with the Xilinx SpartanII parts. The only vendors I can find are Arrow and Newark, and Newark does not show much on their web site. Anyone know how to get good price numbers on the Altera parts without having a handfull of specific parts? If I call the vendors, they always want me to give the a few part numbers and I am window shopping and need pricing on all the parts so I can make my choices. The other problem I have with the Altera FPGAs is the lack of LUT RAM. There are only a small number of RAM (EAB/ESB) in these parts and I need a lot more blocks of it than are available. They don't have to be big, the 16 words available in a bank of Xilinx LUTs is perfect. For example, I will need 64 blocks of RAM if four modules of the 8 channel ADC/DAC are on board. This is not hard using the Xilinx LUTs. Anyone know of a way to do something similar in an Altera FPGA? BTW, just to mention why I like the Altera parts... THEY DON'T HAVE A STARTUP CURRENT SURGE!!! Was I at all unclear about that? :) -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAX
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