Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Jim Granville <jim.granville@designtools.co.nz> writes: >Peter Alfke wrote: (snip) >> When I measured it with random input times ( incoherent clock and data ) I >> counted the times metastability exceeded a certain value. I think you can >> calculate the width of the input window from that. It is extremely narrow. >The 'incoherent' clock/data approach I always feel uneasy about >- just HOW inchoerent are they, and in the real world they may not be. >Plus, the 'hit rate' decreases with improving process, as you have >observed. There is a TTL device that is a dual oscillator. I have heard that it is almost impossible to use both, as they will phase lock even if you don't want them to. The old story about Huygens hanging multiple pendulum clocks on the same wall and noticing that they would phase lock. I would agree that it is very difficult to remove all coupling between two devices and believe that they are incoherent. -- glenArticle: 29701
I have an application that uses a 95144XL as an interface from firmware to program a XCS40XL and a XC2S150 in Slave serial mode. The Spartan XL is the lead device in the daisy chain to the Spartan II. The bitstreams for the two devices are combined using the prom generator. After the firmware has sent all of the configuration data the DONE line stays low, and the INIT stays high. To verify that the logic in the CPLD and the functionality of the firmware, I removed the Spartan II from my PCB. We re-ran the program to only send the bitstream for the Spartan XL. This works perfectly. The problem seems to be that when the Spartan II is on the PCB it keeps the DONE low. The configuration for the Spartan II is set so that the DONE has the Active pullup option selected. Any suggestions that you may have would be appreciated.Article: 29702
<steve (Steve Rencontre)> wrote in message
news:memo.20010305184510.1344D@steve.rsn-tech.co.uk...
> In article <NLto6.31387$68.5690704@typhoon.tampabay.rr.com>,
> sramirez@deletethis.cfl.rr.com (S. Ramirez) wrote:
>
> > "Embedded Head" <chilln@gte.net> wrote in message
> > news:OKco6.3179$sC4.237266@paloalto-snr1.gtei.net...
> > > Mixed Signal Engineer
> > > Will work as a member of our Test Engineering team to design, test and
> > > troubleshoot our next generation of test equipment. We are a rapidly
> > > expanding, progressive company with excellent benefits and friendly
> > > atmosphere.
> > > Qualifications
> > > BSEE (required)
> > > 2+ years experience in C/C++ and VHDL or FPGA (required)
> > > 2+ years experience with analog hardware (required)
> > > Schematic design software experience (required)
> > > DSP experience preferred
> > > Send or Fax resume to:
> > > "Mixed Signal Engineer Web"
> > > 3629 Vista Mercado
> > > Camarillo, CA 93012
> > > FAX: (805) 383-1838
> > > EMAIL: humanresources@a-m-c.com
> >
> >
> >
> > Your BULLET_P.gif is quite enlightening.
>
> That's why they don't want no smart-arse consultants :-)))
>
> Now, back to learning the company song...
>
Smart-assed consultants do it faster and better. They will
sing your company song for a price and be in key!!
Article: 29703Our client is the leading provider of highly integrated silicon solutions that enable broadband digital transmission of voice, video, and data. Using proprietary technologies and advanced design methodologies, the company designs, develops and supplies integrated circuits for a number of the most significant broadband communications markets, including the markets for cable set-top boxes, cable modems, high-speed local, metropolitan and wide area networks, home networking, Voice over Internet Protocol (VoIP), residential broadband gateways, direct broadcast satellite and terrestrial digital broadcast, optical networking, digital subscriber lines (xDSL) and wireless communications. They are currently seeking ASIC Designers with the following... Required Skills and Experiences: BSEE or equivalent; MSEE preferred, plus 5+ years' of VLSI hardware design experience. Position requires working knowledge of Verilog and Synopsys. Experience with back-end CAE, layout tools, 3D, video, and DSP is a plus. Responsibilities: Responsibilities include: definitions of the molecules specifications based on the system specification; RTL development and debugging, test bench development; design validation as part of an overall system, system integration; synthesis of the RTL at a certain clock speed; Implementation of the test strategy, scan insertion, ATPG test vectors generation. PROCOM: Established in 1978, Professional Computer Consultants Group Ltd. (Procom) is a national leader in the provision of Computer personnel on a contract and full-time basis. Our clients are comprised of the largest national and international corporations that utilize technical resources extensively across a wide range of disciplines. In the Financial Post (March 1999) Procom was ranked as the 6th largest professional Services Company in Canada. In November of 1999, Procom was named a Regional finalist in Canada' s 50 Best Managed Private companies. Our track record is proven with more than 180 consultants servicing Ottawa's high tech community and more than 1600 Procom consultants currently on assignment throughout. North America. For further information on this and other opportunities please visit our web site at www.procom.ca. Interested candidates are invited to forward their resumes or questions in confidence to: Derek Weber PROCOM 300 March Rd Suite 600 Kanata, Ontario K2K-2E2 613-270-9339 x231 613-270-9449 (FAX) derekw@procom.ca www.procom.caArticle: 29704
I'm looking for a way to get data into a PC (probably a laptop) from an FPGA based frame grabber type of thing of my own design. I need a sustained data rate of about 5MByte/sec. Does somebody do an FPGA on a PCMCIA card ? That would be ideal. JonArticle: 29705
jschneider@cix.CEEOWE.EWEKAY wrote: > I'm looking for a way to get data into a PC (probably a laptop) from an > FPGA based frame grabber type of thing of my own design. I need a > sustained data rate of about 5MByte/sec. > > Does somebody do an FPGA on a PCMCIA card ? That would be ideal. > > Jon I believe Annapolis Microsystems used to make a PCMCIA card with an FPGA on it. I don't know what type of I/O came off the card to the outside world. -- || Dr. Dave Van den Bout XESS Corp. (919) 387-0076 || || devb@xess.com 2608 Sweetgum Dr. (800) 549-9377 || || http://www.xess.com Apex, NC 27502 USA FAX:(919) 387-1302 ||Article: 29706
Thankyou for this information, I am getting the guys to have a look, unfortunatly we use an expansion rom, this might be a problemArticle: 29707
Peter Alfke wrote: > Rick Filipkiewicz wrote: > > > > > > > I agree basically with Simon. What we have for an FF whose input has change has > > violated the su/hld spec is a probability distribution p(t) which give the > > probability that the output will be in a legal state at time t after the clock > > edge. > > I have a problem with this "legal state" expression. > Aside from the crazy oscillations in bipolar circuits, the output is always at a > legal state. Even at an acceptable state, since by definition either a 0 or a 1 is > equally acceptable when you are right at the edge. > The bad thing with a metastable flip-flop is not its logic state, but the fact > that it will ( might ) change this state at a time that you have no control over, > strictly statistically determined. > That's what you have to fight: timing, not right or wrong levels. > There is no right or wrong... > > Peter Alfke Are you saying that a Xilinx FF is always a 1 or 0 but it just might be slow getting there? No runt pulses, very slow rise times, ragged edges, and all the other horrible TTL phenomema ? The worst one I ever saw was a sort of jagged parabolic curve that got to just under 2V before sliding back down to 0.Article: 29708
Company song, hmmm, yes I can see it now......while they're doing their ergo exercises "Shift to the left, shift to the right" "Push down, pop up" "Byte, byte, byte" Thanks for the idea, see, you consultants really are smart fellers "Eric Braeden" <braeden@erinet.com> wrote in message news:3aa4126a$0$46005$4c5ecdc7@news.erinet.com... > > <steve (Steve Rencontre)> wrote in message > news:memo.20010305184510.1344D@steve.rsn-tech.co.uk... > > In article <NLto6.31387$68.5690704@typhoon.tampabay.rr.com>, > > sramirez@deletethis.cfl.rr.com (S. Ramirez) wrote: > > > > > "Embedded Head" <chilln@gte.net> wrote in message > > > news:OKco6.3179$sC4.237266@paloalto-snr1.gtei.net... > > > > Mixed Signal Engineer > > > > Will work as a member of our Test Engineering team to design, test and > > > > troubleshoot our next generation of test equipment. We are a rapidly > > > > expanding, progressive company with excellent benefits and friendly > > > > atmosphere. > > > > Qualifications > > > > BSEE (required) > > > > 2+ years experience in C/C++ and VHDL or FPGA (required) > > > > 2+ years experience with analog hardware (required) > > > > Schematic design software experience (required) > > > > DSP experience preferred > > > > Send or Fax resume to: > > > > "Mixed Signal Engineer Web" > > > > 3629 Vista Mercado > > > > Camarillo, CA 93012 > > > > FAX: (805) 383-1838 > > > > EMAIL: humanresources@a-m-c.com > > > > > > > > > > > > Your BULLET_P.gif is quite enlightening. > > > > That's why they don't want no smart-arse consultants :-))) > > > > Now, back to learning the company song... > > > Smart-assed consultants do it faster and better. They will > sing your company song for a price and be in key!! > > > >Article: 29709
This is the VHDL code I wrote recently for a homework assignment(I'm also
learning the language now:-)
I use a library(BITLIB) which came along with my textbook("Digital system
design using VHDL" by Charles Roth) to define bit, bit_vector etc instead of
using the IEEE std_logic etc.
Hope it helps:)
Balaji
> Can anyone please post a VHDL implementation of a ROM-based FSM
> implementation,or point me to links on the web where I might get some
help. I
> Have the Block Diagram, but I am having trouble realizing that in VHDL.
begin 666 prob3_1.vhd
M;&EB<F%R>2!"251,24(["G5S92!"251,24(N8FET7W!A8VLN86QL.PH*96YT
M:71Y(%)/33%?,B!I<PH@('!O<G0H6"Q#3$LZ(&EN(&)I=#L*(" @(" @(%HZ
M(&]U="!B:70I.PIE;F0@4D]-,5\R.PH*87)C:&ET96-T=7)E(%)/33$@;V8@
M4D]-,5\R(&ES"G-I9VYA;"!1+"!1<&QU<SH@8FET7W9E8W1O<B@Q('1O(#(I
M(#H]("(P,"(["G1Y<&4@4D]-(&ES(&%R<F%Y("@P('1O(#<I(&]F(&)I=%]V
M96-T;W(H,B!D;W=N=&\@,"D["F-O;G-T86YT($9335]23TTZ("!23TT@.CT@
M"B @(" @(" @(" @(" @(" H(C Q,"(L(C$P,2(L(C$P,2(L(C P,2(L"B @
M(" @(" @(" @(" @(" @(C P,2(L(C Q,"(L(C P,"(L(C P,"(I.PIB96=I
M;@H@('!R;V-E<W,H42Q8*2 @(" @(" @(" M+2!D971E<FUI;F5S('1H92!N
M97AT('-T871E(&%N9"!O=71P=70*("!V87)I86)L92!23TU686QU93H@8FET
M7W9E8W1O<B@R(&1O=VYT;R P*3L*("!B96=I;@H@(" @4D]-5F%L=64@.CT@
M1E--7U)/32AV96,R:6YT*%$@)B!8*2D[(" @+2T@<F5A9"!23TT@;W5T<'5T
M"B @("!1<&QU<R \/2!23TU686QU92@R(&1O=VYT;R Q*2!A9G1E<B Q,"!N
M<SL*(" @(%H@/#T@4D]-5F%L=64H,"D@869T97(@,3 @;G,["B @96YD('!R
M;V-E<W,["@H@('!R;V-E<W,H0TQ+*2 @(" @(" @"B @8F5G:6X*(" @(&EF
M($-,2STG,"<@=&AE;B *"5$\/5%P;'5S(&%F=&5R(#$U(&YS.PH@(" @96YD
M(&EF.R @("TM('5P9&%T92!S=&%T92!R96=I<W1E<@H@(&5N9"!P<F]C97-S
-.PIE;F0@4D]-,3L@"@``
`
end
Article: 29710Falk Brunner wrote: > <Snip> > > > Technique : > > > Construct a coarse delay line in Logic > > > Construct a fine delay, by a sliding physical contact on a stripline, > > > ideally slid under vernier control. > > Sounds a little bit ancient ;-)) > > Why not using a PLL and doing a phase modulation?? This would give VERY > reliable and repeatable results. > And its free of mechanical wearout. Ancient but hard to beat :-) ( reminds us how far we have really come..) PLL's think they are doing well with sub-ns jitters, a stripline will deliver femto seconds, with no jumps, snaps, or discontinuties appart from the contact point. DLL's are good for ~ 40ps, still too coarse for what Peter is chasing. A Mechanical system can also read-off directly in pico-seconds - try that with any PLL :-) Another alternative, for those who dislike the physical, is electrical - using a Split Vcc dual Buffer scheme. Best is probably same-batch tiny logic, as you want to avoid ANY gnd bounce coupling between the two signals, but have matched delay paths. This uses Tpd/Vcc variation as a differential delay line. Moving the CLK Vcc up relative to DATA Vcc advances Clock, and the opposite advances data. Lacks the inherent calibration of a strip line, but should be good for pico second control precisions.Article: 29711
Simon,
One feature Actel has in their antifuse parts that no SRAM parts have to
my knowledge is the ability to look at ANY node in the design during normal
system operation. This is done via Silicon Explorer. There is absolutely no
need to bring signals out to unused pins. As for the BGA/OTP relationship
you described (chasing interconnect problems)... does that potential problem
not apply to any other technology implemented in a BGA? Xilinx would be as
difficult, if not more diffcult, to chase down interconnect problems when
using BGAs than any of the Actel antifuse parts.
Also, the ProASIC (used to be Gatefield) parts are fully functional and have
in fact been shipping to select customers for quite some time. The delay in
delivery had nothing to do with function... yield has been the issue.
ProASIC will be hitting distributors very soon (not just marketing BS).
Tim
"S. Ramirez" <sramirez@cfl.rr.com> wrote in message
news:1XBo6.33047$68.6150627@typhoon.tampabay.rr.com...
>
> "Timothy R. Sloper" <trs@mpinet.net> wrote in message
> news:3lxo6.44388$nL5.2679174@news3.aus1.giganews.com...
> > I'm an FAE for a distributor of Actel. As Philip stated the devices are
> OTP.
> > There are no inherent problems with the SX/SXA families but if you want
to
> > be successful on the first pass (this applies to any vendor/technology)
> > budget time for proper simulation.
> >
> > Tim
>
> Tim,
>
> Simulation with OTP devices is even more important than with SRAM
> based, reprogrammable devices. This is especially true of higher density
> OTP devices involving BGAs, where success on the first pass is paramount.
> To get more IO density, BGAs are required, and this is an anathema to OTP
> devices, at least in the "first time around" type of design. I remember
> socketing Actel FPGAs many years back, but this is next to impossible with
> BGAs and sockets. Reliability decreases as interconnections increase, and
> this means you may be chasing interconnection problems instead of
> functiional problems. I'll be glad when Actel gets the Gatefield line
> working.
> Good luck to you in your FAE role.
> Simon Ramirez, Consultant
> Synchronous Design, Inc.
> Oviedo, FL 32765
>
>
>
Article: 29712This is a multi-part message in MIME format. --------------F9DA7908A1BBE80B9719466E Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Is there a tool that I could use to evaluate number of SlectMAP transfers to partially program Virtex device with my configuration ? For example: my project uses only upper right quarter of the chip. I'd like to shorten the configuration phase and download only that part of configuration bitstream. Before making a design, however, I'd like to know how long the configuration phase will last. Or is there any simple algorithm, that can give even the coarse approach to answer to my question ? -- Regards, Pawel J. Rajda ----------------------------------------------------------------------------- Pawel J. Rajda, MSc. E.E. mail: pjrajda@uci.agh.edu.pl Dept. of Electronic Engineering www: http://galaxy.uci.agh.edu.pl/~pjrajda AGH Technical University tel: (+48-12) 617 3980 Al. Mickiewicza 30 fax: (+48-12) 633 2398 30-059 Cracow, POLAND ----------------------------------------------------------------------------- --------------F9DA7908A1BBE80B9719466E Content-Type: text/x-vcard; charset=us-ascii; name="pjrajda.vcf" Content-Transfer-Encoding: 7bit Content-Description: Card for Paweł J. Rajda Content-Disposition: attachment; filename="pjrajda.vcf" begin:vcard n:Rajda;Pawel J. x-mozilla-html:FALSE org:AGH Technical University version:2.1 email;internet:pjrajda@uci.agh.edu.pl title:M.Sc. E.E. tel;fax:+48 12 633 2398 tel;home:+48 12 634 0653 tel;work:+48 12 617 3980 adr;quoted-printable:;;Dept. of Electronics=0D=0AAl. Mickiewicza 30;Krakow;;30-059;POLAND x-mozilla-cpt:;0 fn:Rajda, Pawel J. end:vcard --------------F9DA7908A1BBE80B9719466E--Article: 29713
Hi Jon, I have designed a card having XC2S150-FG256 FPGA, MAX1246 ADC, two 65LVDS179DGK drivers etc on it. The card has two LVDS input, one analog input and one LVDS output, CardBus interface on the other side. Jaan.Article: 29714
"Jaan Sirp" <jaan.sirp@mail.ee> writes: > I have designed a card having XC2S150-FG256 FPGA... > > Jaan. Is that available as a product I can buy, a design, a free design or what ? The Annapolis card looks fine but I'm really really on a shoestring here. JonArticle: 29715
"Marc Reinert" <reinert@tu-harburg.de> wrote > I' like to use a CPLD/FPGA (Xilinx) to receive data from the parallel > port (EPP-mode) of my PC. > > Is it a good style to react direct on the edges of the port signals (e. > g. adress/data strobes) or would it be better to use a fast PLD-Clock to > sample the port and then to evaluate the signals in a clocked logic? I've done this in a Spartan device. You should synchronize the inputs to an internal clock and 2 flip-flops. (See the ongoing thread on Metastability). Then just use a state machine. It works well but I coudn't make the EPP going faster than 750Kb/s under W2K (Dell I5000e PIII 700). MarcArticle: 29716
Hi everyone! This is an absolute newbie question.... I tried to implement a simple port test. (Relevant part of code at the end of the msg.) Now it seems like I am not allowed to wait for an event on a normal port line. The foundation software forces me to use one of the 4 GLCK inputs for "SW1" in the constraints editor, otherwise I get the following implementation error: ERROR:MapLib:93 - Illegal LOC on symbol "SW1.PAD" (pad signal=SW1) or BUFGP symbol "C15" (output signal=SW1_BUFGPed), IPAD-IBUFG should only be LOCed to GCLKIOB site. I know that it is basically good to use the DLLs for clock distribution, but I think it should be possible to wait for events on any port/signal, shouldn't it? Surely my mistake is obvious for you... :) Thanks in advance! Stephan --- vhdl code --- entity shift1 is port ( SW1: in STD_LOGIC ); end shift1; architecture shift1_arch of shift1 is signal sw1_int: STD_LOGIC; begin sw1_int <= SW1; process (sw1_int) begin if sw1_int'event and sw1_int='1' then -- ... end if; end process; end shift1_arch;Article: 29717
Hi Jon, >> I have designed a card having XC2S150-FG256 FPGA... >> >> Jaan. > > >Is that available as a product I can buy, a design, a free design or what ? Official answer: The design is property of my customer - a telecommunication company. The card is used for product testing. You need also CardBus core and SW driver if you want to use this card. PCMCIA bus is easier solution. Its THEORETICAL bandwith is 20MBytes/sec. Practically 5MBytes/sec is still very critical, if lossless reception is needed (depends on laptop and programs running). But I'm happy to help you, if you'll have problems when designing the card (better by email). Jaan.Article: 29718
Hello everybody,
my friend has to realize the implementation of an OCR algorithm in
schematics or VHDL,
with fondation or any other FPGA software.
As a student he is in internship in the USA, and does not have easy
access (beside work) to computer and internet.
If somebody could give him (us) some clue for him to get started ?
apparently a demo version of software is enough, but here are the
questions :
1. Where can he download a free demo version of a good software ?
2. Where can he find a description of an OCR algorithm ?
3. Where can he find good documentation to program in VHDL ?
Thank to evryone !
(more detail description of the subject :
Make under fondation or other software for FPGA a development of
a simulation in schematics or VHDL for the following problem :
OCR algorithm for one character on a matrix, dimensions from
10*10 to 500*500 points)
Article: 29719Hello, Does anyone know where I can order small quantities (2-5) of Xilinx fpga`s in the Benelux? Thanx in advance! StevenArticle: 29720
Stephan Schirrmann wrote: > > Hi everyone! > > This is an absolute newbie question.... > I tried to implement a simple port test. (Relevant part of code > at the end of the msg.) > Now it seems like I am not allowed to wait for an event on a > normal port line. > The foundation software forces me to use one of the 4 GLCK > inputs for "SW1" in the constraints editor, otherwise I get the > following implementation error: > > ERROR:MapLib:93 - Illegal LOC on symbol "SW1.PAD" (pad > signal=SW1) or BUFGP symbol "C15" (output signal=SW1_BUFGPed), > IPAD-IBUFG should only be LOCed to GCLKIOB site. Hi The problem is that somewhere in the design flow a clock buffer has been inserted (bufgp). You can not source such a buffer from anything but a GCLK pad. I think your synthesis tool (FPGA Express ?) automatically inserted the global buffer on the clock line. There is a switch somewhere to disable this. -- Nicolas MATRINGE IPricot European Headquarters Conception electronique 10-12 Avenue de Verdun Tel +33 1 46 52 53 11 F-92250 LA GARENNE-COLOMBES - FRANCE Fax +33 1 46 52 53 01 http://www.IPricot.com/Article: 29721
Hi! You wrote: > 3. Where can he find good documentation to program in VHDL ? At the moment I'm on the way to vhdl too. The vhdl resources I found are already linked together very well, so you will quickly come from one doc to each other. Some starting points: http://www.vhdl.org/comp.lang.vhdl/ http://www.vhdl-online.de/~vhdl/ http://tech-www.informatik.uni-hamburg.de/vhdl/vhdl.html http://www180.hrz.tu-chemnitz.de/~chu/vhdl/vhdl.html (german) StephanArticle: 29722
Actually, it is exceedingly easy to chase down interconnect problems with SRAM based arrays. You simply reconfigure with a configuration designed to exercise the IO without having to deal with the rest of your internal design. THis methodology also lets you exhaustively test external (to the fpga) memories at system speeds. By using reconfiguration, you can isolate board level test from your algorithm debug...a huge advantage as far as I can see. Can't do that with non-volatile media. There is more detail on this test methodology in my paper entitled "An FPGA Based Processor Yields a Real Time High Fidelity Radar Environment Simulator" which is available on my website. "Timothy R. Sloper" wrote: > > Simon, > > One feature Actel has in their antifuse parts that no SRAM parts have to > my knowledge is the ability to look at ANY node in the design during normal > system operation. This is done via Silicon Explorer. There is absolutely no > need to bring signals out to unused pins. As for the BGA/OTP relationship > you described (chasing interconnect problems)... does that potential problem > not apply to any other technology implemented in a BGA? Xilinx would be as > difficult, if not more diffcult, to chase down interconnect problems when > using BGAs than any of the Actel antifuse parts. > > Also, the ProASIC (used to be Gatefield) parts are fully functional and have > in fact been shipping to select customers for quite some time. The delay in > delivery had nothing to do with function... yield has been the issue. > ProASIC will be hitting distributors very soon (not just marketing BS). > > Tim > > "S. Ramirez" <sramirez@cfl.rr.com> wrote in message > news:1XBo6.33047$68.6150627@typhoon.tampabay.rr.com... > > > > "Timothy R. Sloper" <trs@mpinet.net> wrote in message > > news:3lxo6.44388$nL5.2679174@news3.aus1.giganews.com... > > > I'm an FAE for a distributor of Actel. As Philip stated the devices are > > OTP. > > > There are no inherent problems with the SX/SXA families but if you want > to > > > be successful on the first pass (this applies to any vendor/technology) > > > budget time for proper simulation. > > > > > > Tim > > > > Tim, > > > > Simulation with OTP devices is even more important than with SRAM > > based, reprogrammable devices. This is especially true of higher density > > OTP devices involving BGAs, where success on the first pass is paramount. > > To get more IO density, BGAs are required, and this is an anathema to OTP > > devices, at least in the "first time around" type of design. I remember > > socketing Actel FPGAs many years back, but this is next to impossible with > > BGAs and sockets. Reliability decreases as interconnections increase, and > > this means you may be chasing interconnection problems instead of > > functiional problems. I'll be glad when Actel gets the Gatefield line > > working. > > Good luck to you in your FAE role. > > Simon Ramirez, Consultant > > Synchronous Design, Inc. > > Oviedo, FL 32765 > > > > > > -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com or http://www.fpga-guru.comArticle: 29723
"Paweł J. Rajda" wrote: > > Is there a tool that I could use to evaluate number of SlectMAP > transfers to partially program Virtex device with my configuration ? > For example: my project uses only upper right quarter of the chip. > I'd like to shorten the configuration phase and download only that > part of configuration bitstream. Before making a design, however, > I'd like to know how long the configuration phase will last. > Or is there any simple algorithm, that can give even the coarse > approach to answer to my question ? The Xilinx app note XAPP151 covers configuration for Virtex devices in detail. One thing to be aware of is that your project logic might only use the upper right quarter, but what about its routing? If its routing is spread over the whole chip, you will have difficulties trying to do anything other than reconfigure the whole device. Phil -- --------------------------------------------------------------------- __ / /\/ Dr Phil James-Roxby Direct Dial: 303-544-5545 \ \ Staff Software Engineer Fax: Unreliable use email :-) / / Loki/DARPA Email: phil.james-roxby@xilinx.com \_\/\ Xilinx Boulder ---------------------------------------------------------------------Article: 29724
On Tue, 6 Mar 2001 02:27:39 -0800, "Jaan Sirp" <jaan.sirp@mail.ee> wrote: >Hi Jon, > >>> I have designed a card having XC2S150-FG256 FPGA... >>> >>> Jaan. >> >> >>Is that available as a product I can buy, a design, a free design or what ? > >Official answer: > >The design is property of my customer - a telecommunication company. The card is used for product testing. > >You need also CardBus core and SW driver if you want to use this card. PCMCIA bus is easier solution. Its THEORETICAL bandwith is 20MBytes/sec. Practically 5MBytes/sec is still very critical, if lossless reception is needed (depends on laptop and programs running). > >But I'm happy to help you, if you'll have problems when designing the card (better by email). > >Jaan. Hi Jaan I'm looking for ressources that explain, how to build a PCMCIA or even better a Compact Flash Card that is FPGA based. Do you have any pointers to good ressources as free designs for inspirations, books, webpages, FAQs.. I would be glad for any hint, Chris
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z