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I´ve been looking all over the net for some suplier!
I need Xilinx FPGA demo board, where can i get it?
Thank you!
Article: 29451"Max L." wrote: > > Hello, > > The question refers to dual ported memory inferring using > Leonardo Spectrum for synthesis and targeting Xilinx' Spartan XL device: > > How to infer both outputs of a dual ported memory's element > (namely SPO and DPO of RAM16X1D) from plain Verilog. About a year ago I tried something similar in VHDL. It turns out Leonardo Spectrum can only understand single port RAM not dual port RAM. In the old version I used before, they couldn't even do single port ram. The only easy way to do this is to use a black box (eg. RAM16X1D) and let the downstream tools substitue in the ram cell. Use my ram code only for simulation part. K. C. LeeArticle: 29452
Hi guys. You might want to check out Atmel's web sight. They have ROMs up to 2Mbit, that are reconfigurable using an spi(-like?) interface. So if you have a CPU on board, you can download to the EEPROM via the CPU or something. 2Mbit is the biggst they have, and it's more than twice the cose of the 1Mbit, yso you mayb wan tot use 2x 1MBit devices. I've never used them, so take anything I say with a grain of salt. they look like they're completely compatable with Xilinx FPGA's, however, and even have a CEO/ output so that they can be cascaded. My 2 cents worth, -Kent "C.Schlehaus" <carlhermann.schlehaus@t-online.de> writes: > > If You like to save the space for a prom use an FPGA of Actel. They use > > antifuse tech. Problem is that you can program it only once. > > I already asked ACTEL for the comparable ACTEL FPGA which could replace > my EP1K100, but the device they told me is more expensive. And as you > already wrote, it's a one-way-ticket. I need reprogrammability. > > CU, CarlhermannArticle: 29453
Has anyone had success implementing a USB interace with the Xilinx Virtex series chips? I imagine you would need a transceiver chip, but which one is best to use? And has anyone gotten it working? And more specifically, does anyone have design docs or schematic files for it? Otherwise it looks like I'm going to have to start from scratch using the PDIUSBP11A.Article: 29454
On Thu, 22 Feb 2001 04:35:32 GMT, George P. Burdell <gpburdell1@yahoo.com> wrote: >Has anyone had success implementing a USB interace with the Xilinx >Virtex series chips? I imagine you would need a transceiver chip, but >which one is best to use? And has anyone gotten it working? And more >specifically, does anyone have design docs or schematic files for it? >Otherwise it looks like I'm going to have to start from scratch using >the PDIUSBP11A. I have been involved in design of this chip http://www.controlchips.com/UsbRam.htm and verification of this chip http://www.ubicom.com/hardware/IP2022.html. The first one got prototyped with a Phillips transceiver and an Altera 10K. The second one with the same transceiver and Virtex 300K. I should say that going from a transceiver to a functioning USB 1.1 device is not a trivial undertaking. You should at least review these documents http://www.usb.org/developers/data/crcdes.pdf, http://www.usb.org/developers/data/siewp.pdf. hope this is some help, Muzaffer FPGA DSP Consulting http://www.dspia.comArticle: 29455
Hi Jon, As far as I've seen you need an Altera MPU programmer. I would recommend getting an EPM7032S device that can be programmed in circuit. Brian Goudy "Jon S." wrote: > Could someone tell me how to program a MAX7032 (which does not have JTAG > capability), i.e. what signals to apply where, when? Altera's documentation > seems to only discuss JTAG programming.Article: 29456
Just idea.
You can use booth rising and falling edges from master clock. You need
to build clock doubler - just use exclusive or with clock, and delayed
clock. Then just divide by 3.
Alexander
Goran <goran_metlic@yahoo.com> wrote in message
news:ee6fc2d.-1@WebX.sUN8CHnE...
> Im beginer in vhdl and i need to create a clock divider by 1.5.I have
found such one in edn magazine (on the web) but it didnt help me.Does
someone have better idea then the one in edn magsine.
>
> If someone wants to look at the design in edn :
http://www.ednmag.com/ednmag/reg/1996/101096/21di_05.htm
Article: 29457Goran, you might want to take a look at Alteras APEX 20KE architecture. These devices have on-chip PLLs, that allow to multiply incoming clocks by m/(n*k). With the Altera Megawizard you would paramterize your PLL and generate a black box which you could then put into your clock path by instantiating it within your VHDL code. It's usualy better design technique to use something like a PLL rather than combinatorial, asynchronous logic or even combinatorial feedback loops within a clock path. Regards Wolfgang Goran <goran_metlic@yahoo.com> wrote in message news:ee6fc2d.-1@WebX.sUN8CHnE... > Im beginer in vhdl and i need to create a clock divider by 1.5.I have found such one in edn magazine (on the web) but it didnt help me.Does someone have better idea then the one in edn magsine. > > If someone wants to look at the design in edn : http://www.ednmag.com/ednmag/reg/1996/101096/21di_05.htmArticle: 29458
Goran wrote: > Im beginer in vhdl and i need to create a clock divider by 1.5.I have found such one in edn magazine (on the web) but it didnt help me.Does someone have better idea then the one in edn magsine. > > If someone wants to look at the design in edn : http://www.ednmag.com/ednmag/reg/1996/101096/21di_05.htm Peter Alfke from Xilinx has an clock divide by 1.5 implementation in Xilinx technology: http://www.xilinx.com/xcell/xl33/xl33_30.pdf UtkuArticle: 29459
One web site: www.optimagic.com Laurent for Amontec www.amontec.com ----------------------------------- Amontec introduces a new easy PCI development system. Build your own PCI board in 2 weeks! A reality with Amontec. Jorge Neves wrote: > I´ve been looking all over the net for some suplier! > I need Xilinx FPGA demo board, where can i get it? > Thank you!Article: 29460
Try ATMEL. Giorgio "Tom" <te@wiese.de> wrote in message news:970k7n$q2l$1@bohr.tzl.de... > Does someone know a second source for the ALTERA EPC1 configuration PROM ? > > -Tom > > >Article: 29461
"Jorge Neves" <jorge.correio@netc.pt> wrote in message news:3a9450d1$1@212.18.160.197... > I´ve been looking all over the net for some suplier! > I need Xilinx FPGA demo board, where can i get it? > Thank you! Jorge, There are lists of suppliers of FPGA demo / eval / design boards at both http://www.optimagic.com/boards.html http://www.xilinx.com/xlnx/xil_prodcat_product.jsp?title=protoboards_protobo ards_page My company ad here :)... Burch Electronic Designs sells the BED-SPARTAN2+ kit. See http://www.burched.com.au/ Features include: - 200,000 gates! - free Xilinx Webpack software CD - price: US$120! Great for some serious prototyping, or for education. http://www.burched.com.au/bedspartan2.html for full specs and secure online shop. International orders are very welcome. Best regards Tony Burch Burch Electronic Designs http://www.burched.com.au/Article: 29462
We have developed a PCI 33/32 device, works correctly on all systems we have tested on, except 3 different ASUS motherboards. On these systems the motherboard never starts the power on self tests. The core is loaded but system halts.Article: 29463
Hi, Does anybody have any information on the expected availability of the Virtex II family, especially the 6000 part?Article: 29464
Well, I need the pins that are assigned to be JTAG pins in the "S" chips to be user I/O. So then if I configure an "S" device that way, does that mean that I lose the JTAG programmability? Brian Goudy wrote in message <3A94BFAF.965F8172@earthlink.net>... >Hi Jon, > >As far as I've seen you need an Altera MPU programmer. I would >recommend getting an EPM7032S device that can be programmed >in circuit. > >Brian GoudyArticle: 29465
Get yourself a board from Burched http://www.burched.com.au/ I bought a Spartan II board online which was delivered within one week to me (in France) without paying enormous amounts for shipping. ClemensArticle: 29466
"George P. Burdell" wrote: > > Has anyone had success implementing a USB interace with the Xilinx > Virtex series chips? I imagine you would need a transceiver chip, but > which one is best to use? And has anyone gotten it working? And more > specifically, does anyone have design docs or schematic files for it? > Otherwise it looks like I'm going to have to start from scratch using > the PDIUSBP11A. You're probably better off putting the USB functions into one of the dozen or so USB microcontrollers you can buy. Most of them are based on an 8051 core. For instance, I'm doing a USB audio project and I'm using the TI TUSB3200 part. It literally does everything I need it to do, with very little programming (mostly setting up endpoints). And it's like $5.50 in 1K quantities. Cypress has their EZ-USB-FX parts which cost more (maybe $15 each) but they're also easy to program. I think doing USB in a big Virtex part is exactly the wrong thing to do. just my opinion, of course. -aArticle: 29467
Looks like LED is not driven, and was optimized away. Helen Long wrote: > > Hi I am trying to generate bit file and download to XS40 board > I use XC40005XLPC84, but I can successfully implement it without > my own ucf file, it I connet my ucf file it fails > What is wrong? My code and my ucf file and error message are listed > below thanks a lot! > > Qian > > Here is my code > library IEEE; > use IEEE.std_logic_1164.all; > use IEEE.std_logic_unsigned.all; > > entity noGSR is > port( > CLOCK: in STD_LOGIC; > --RESET: in STD_LOGIC; > --HEX: in STD_LOGIC_VECTOR(3 downto 0); > LED: out STD_LOGIC_VECTOR(6 downto 0)); > end noGSR; > > architecture SIMPLE of noGSR is > signal HEX: STD_LOGIC_VECTOR(3 downto 0); > > begin > HEX<="0000"; > UP_COUNTER:process(CLOCK) > begin > -- if(RESET='1') then > > if(CLOCK'event and CLOCK='1') then > HEX <= HEX + 1; > end if; > end process; > SHOW:process(HEX) > begin > .... > end process; > > end SIMPLE; > > Here is my ucf file > NET CLOCK LOC=P13; > NET LED LOC=25,26,24,20,23,18,19; > > And I use Xilinx Foundation 2.1l to implement it > it shows error > > Annotating constraints to design from file "led.ucf" ... > ERROR:NgdHelpers:18 - Could not find NET "CLOCK" in design "led". NET entry > is > "NET CLOCK LOC=P13; > " > ERROR:NgdHelpers:18 - Could not find NET "LED" in design "led". NET entry > is > "NET LED LOC=25,26,24,20,23,18,19; > > " > ERROR:Parsers:11 - Encountered unrecognized constraint while parsing. > ERROR:NgdBuild:19 - Errors found while parsing constraint file "led.ucf". > > One or more errors were found during NGDBUILD. No NGD file will be written. > > Writing NGDBUILD log file "led.bld"... > > ==================================================Article: 29468
It is, because you are asking for the fastest speed grade. The -6 would be about half that price... Peter Alfke ==================== Neo WT wrote: > Can anyone advice me of a reasonable sample price for XCV1000E-8HQ240? I was quoted about US$1900 per piece for 5 pcs. Is this the market rate? > > Neo WTArticle: 29469
I've wanted to start playing with FPGAs for a long time, but never got to start a real project with these due to home-computers limitations : none of my computer have the resources/hard disk space to get win9x running (ie I do not want to dedicate one of my higher grade computers to fpga development by installing win9x on it as I would have no other use for that OS). I did develop basic circuitry for a ISA based counter on an EPLD in the previous lab I worked in, and enjoyed it a lot (Altera tools). But since I moved institutions I have no longer access to FPGA development tool while I'd still like to play with the idea re-programmable processors. While thinking about all I could do with an FPGA, I becam quite fluent with microcontrolers and "classical" processors, and have ended up building my 68HC11, Z80 and 6502 development tools (http://mmyotte.free.fr for a preliminary descritpion). Now I'd like to go back to FPGA but have 2 problems: 1/ compiling a VHDL program for a given FPGA and 2/ programming the actual FPGA 1/ how does one get from a VHDL document to a "binary" (or whatever it is called in the FPGA world) file ? With the altera tool, one had part AHDL subroutines, part graphical interface for connecting these subroutines tougether, click on "build" and there you get your compiled file. Is there anything similar in the open-source world ? I seem to understand alliance will compile early Xilinx 4000 series EPLD, but I don't even know if these are still available. 2/ once I get by "binary" file, I used to send it to the EPLD via the JTAG port. I suppose I could program an HC11 to get the files sent from the PC through RS232 and send whatever signal is required by the JTAG protocol => a/ is the JTAg protocol documented and easy to understand (I did find documents but most were users guide, not development guides) b/ is it just a matter of reading the bytes from the previous "binary" file and send them through JTAG or is there a complex intermediate step (such as "this cell is programmed this way and this other cell this other way"). I know this sound like inventing the wheel again, but I'm just doing this for a hobby (for now at least) and I enjoy developing all the tools I use. It's just that in the case of FPGAs I don't know where to start. Thank you, Jean-Michel FRIEDT (friedtj@imec.be)Article: 29470
In article <3a93e727$0$32754$45beb828@newscene.com>, ads@begone.com (Jon S.) wrote: > Could someone tell me how to program a MAX7032 (which does not have JTAG > capability), i.e. what signals to apply where, when? Altera's > documentation > seems to only discuss JTAG programming. Like most such products, it's a proprietary algorithm which they only license to the DataIOs of this world. -- Steve Rencontre http://www.rsn-tech.co.uk //#include <disclaimer.h>Article: 29471
"Mark" <mark@plumjob.net> writes: > Does anybody have any information on the expected availability of the Virtex > II family, especially the 6000 part? Oooh, you have lots of money! Sales critters love to hear that! :-)Article: 29472
Peter Alfke <peter.alfke@xilinx.com> writes: > It is, because you are asking for the fastest speed grade. > The -6 would be about half that price... Speaking of which, why are the speed grades -5 and -6?Article: 29473
Hi Helen From your code I see that you have mutiple assignments to the signal HEX. You have a concurrent assingment HEX <= "0000"; and then a clocked process which should increment HEX. I guess you want describe a defined start value, but remember that the concurrent statement is "executed" all the time. HEX will always be assigned "0000". I'm suprised that your synthesis tool haven't reported this as an error: "multiple assignment of a non-tristate signal" or something. Maybe the synthesis tool has just optimised HEX to a constant value "0000", and as a consequence optimised all signals out of the design, because there is no need for them. Maybe that is why ngdbuild reports the error. What you should do is to remove the concurrent assignment. Do not worry, HEX will be initiated to "0000" when the device is configured. Hope this helps /Thomas Helen Long <madisonfff@usa.net> skrev i diskussionsgruppsmeddelandet:96t62l$i2u$1@news.doit.wisc.edu... > Hi I am trying to generate bit file and download to XS40 board > I use XC40005XLPC84, but I can successfully implement it without > my own ucf file, it I connet my ucf file it fails > What is wrong? My code and my ucf file and error message are listed > below thanks a lot! > > Qian > > Here is my code > library IEEE; > use IEEE.std_logic_1164.all; > use IEEE.std_logic_unsigned.all; > > entity noGSR is > port( > CLOCK: in STD_LOGIC; > --RESET: in STD_LOGIC; > --HEX: in STD_LOGIC_VECTOR(3 downto 0); > LED: out STD_LOGIC_VECTOR(6 downto 0)); > end noGSR; > > architecture SIMPLE of noGSR is > signal HEX: STD_LOGIC_VECTOR(3 downto 0); > > begin > HEX<="0000"; > UP_COUNTER:process(CLOCK) > begin > -- if(RESET='1') then > > if(CLOCK'event and CLOCK='1') then > HEX <= HEX + 1; > end if; > end process; > SHOW:process(HEX) > begin > .... > end process; > > end SIMPLE; > > > Here is my ucf file > NET CLOCK LOC=P13; > NET LED LOC=25,26,24,20,23,18,19; > > And I use Xilinx Foundation 2.1l to implement it > it shows error > > Annotating constraints to design from file "led.ucf" ... > ERROR:NgdHelpers:18 - Could not find NET "CLOCK" in design "led". NET entry > is > "NET CLOCK LOC=P13; > " > ERROR:NgdHelpers:18 - Could not find NET "LED" in design "led". NET entry > is > "NET LED LOC=25,26,24,20,23,18,19; > > > " > ERROR:Parsers:11 - Encountered unrecognized constraint while parsing. > ERROR:NgdBuild:19 - Errors found while parsing constraint file "led.ucf". > > One or more errors were found during NGDBUILD. No NGD file will be written. > > Writing NGDBUILD log file "led.bld"... > > ================================================== > > > > >Article: 29474
Hi Jean-Michel, > I've wanted to start playing with FPGAs for a long time, but never got > to start a real project with these due to home-computers limitations : > none of my computer have the resources/hard disk space to get win9x > running (ie I do not want to dedicate one of my higher grade computers > to fpga development by installing win9x on it as I would have no other > use for that OS). Well, you can run Xilinx back-end tools under WINE on Linux, if that is what you are running, see http://www.polybus.com/xilinx_on_linux.html. Xilinx has fairly hefty tools, WEBPack, available for free (somewhere at http://www.xilinx.com/). I'm not sure the HDL synthesis works under WINE; you could try hacking Icarus Verilog (http://icarus.com/eda/verilog/) to target Virtex/Spartan-II for synthesis instead (it targets XC4k now). Somehow, getting a bigger disk (that's cheap nowadays), installing Windows, and dual-booting to run WEBPack seems less work (even though it s*cks)... > 1/ how does one get from a VHDL document to a "binary" (or whatever > it is called in the FPGA world) file ? With the altera tool, one had > part AHDL subroutines, part graphical interface for connecting these > subroutines tougether, click on "build" and there you get your compiled > file. Is there anything similar in the open-source world ? I seem to > understand alliance will compile early Xilinx 4000 series EPLD, but I > don't even know if these are still available. I don't really follow you here. You need a HDL synthesis tool to turn your HDL xource into a netlist, and a place&route back-end to map it onto the physical device. The final device programming data goes into some bitstream file, your 'binary' if you like. Note that Altera's (free) tools also run on Windows. Alliance runs on Solaris (SPARC) and HP-UX, last time I checked; no synthesis front-ends included. > 2/ once I get by "binary" file, I used to send it to the EPLD via the > JTAG port. I suppose I could program an HC11 to get the files sent from > the PC through RS232 and send whatever signal is required by the JTAG > protocol Xilinx FPGAs support a dead simple serial protocol. I'll post a download utility for Linux tomorrow or so. Have fun, - Reinoud ---- Spam goes to wanabe, mail to wanadoo.
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