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Dear Zhen, We have the solution for such request : Our PCI and CompactPCI FPGA based boards support PMC connectors for plugging any daughterboard. Either you plug a RAM PMC daughter board from amanufacturer such as the ones you mentionned, either we design for you a small custom daugghter board with the required memory. Please have a look at http://www.plda.com or contact me directly by email or phone. Best regards, ------------------------------------------------------ Arnaud SCHLEICH - PLD Applications Sales & Marketing Manager 32,ZAC de Bompertuis 13120 Gardanne - France Tel: +33 442 654 388 Fax: +33 442 654 443 Email: aschleich@plda.com Web: http://www.plda.com ------------------------------------------------------ > I am looking for an FPGA board with a PCI interface (or PMC). I hope the > FPGA would have access to at least 4 banks of memory (preferably SRAM) of > 32-bit data. And I hope each bank of memory would have large capacities (>= > 4M bytes). Does anyone know any board of this type? > > I did a search myself and the closest one I could find are the RC1000 board > from Alpha Data (4 banks, 32-bit interface, 2M bytes for each bank) and > SMT406 from Sundance (4 banks, 36-bit interface, 2.25M bytes for each bank). > I wonder if there is anything bigger than that. > > Thanks, > > -- Zhen Luo > > >Article: 29026
In article <3a7a137f$1@news.starhub.net.sg>, "Kang Liat Chuan" <kanglc@agilis.st.com.sg> writes: |> Besides the front-end design language, what are the major |> difference between FPGA design and IC design? If you make a mistake in your IC design it may cost more than your yearly salary to correct and take several months. IC designers tend to sweat the details and spend a lot of time verifying their designs before committing them to silicon. Have fun! Joe -- --------------------------------------------------------------------------- == K. Joseph Hass == Microelectronics Research Center == == http://www.mrc.unm.edu/~jhass == 801 University Blvd SE, Suite 206 == == (505) 272-7055 == Albuquerque, NM 87106-4340 USA ==Article: 29027
I have been given the task of resurrecting the Xilinx software used at my place of work. A few years ago we were quite active in designing various bespoke electronic modules but the majority of our desingers have since left. Our existing "out of date" set-up uses two types of design entry methods: ABEL Version 5.12 and Orcad ESP V4.40 and the designs are implemented using Xilinx XACT Version 5.1.0. As I understand it there are three available families of software: Alliance, Foundation ISE and Foundation. I need to find out whether any or all of these families will be able to support our old existing designs. I assume they probably do but can anyone confirm this or point me to where I can find out this information. Regards AlanArticle: 29028
I have a design (multiple vhdl files thru Synplify into xilinx 3.1 design
mgr) that now refuses to map, after mapping many times prior during
incremental testing. The map error message is given below, where the only
reference to this signal name is the pin declaration in Synplicity
constraint file (P99) and Xilinx UCF file (also P99). Any ideas can be
sent to my email address dana*at*xetron.com
Section 1 - Errors
------------------
ERROR:Pack:679 - Unable to obey design constraints (LOC = P99) which require
the combination of the following symbols into a single I/O component:
PAD symbol "rxtcnsel.PAD" (Pad Signal = rxtcnsel)
BUF symbol "rxtcnsel_obuf" (Output Signal = rxtcnsel)
LUT symbol "rxtcnsel" (Output Signal = rxtcnsel_c)
Symbol rxtcnsel is not a kind of symbol that can join an I/O component.
Please correct the design constraints accordingly.
Article: 29029I've successfully programmed the Insight demo board with JTAG. A common oversight is to forget to make the Startup Clock the JTAG clock. Otherwise, please provide more information about what you're seeing. Karim LIMAM wrote: > Hi, > > we've bought a SpartanII Demo board (XC2S100) and we're trying without > success to configure the FPGA via the JTAG port using Alliance FPGA > programmer . > Has someone experience with Insight demo cards. > > Thanks for the time. > > Karim. -- Marc Baker Xilinx Applications (408) 879-5375Article: 29030
If you're just interested in CPLD's. You should try the Webpack ISE software. It's completely for free, and you can use all types of design entry (abel, vhdl, verilog, schematic). You can even address the spartan2-series and Virtex-E300 FPGA's.... As I have heard, both foundation and alliance will dissapear, however not immediatelly (say 1/2-1 years).. The "new" way is using foundation ISE : a superset of webpack ISE. For feature detailes, I can only refer to www.xilinx.com ... according to me (and compared to www.altera.com) an excellent website... best regards, Jan "Alan Horton" <arh@jet.uk> schreef in bericht news:95ellk$rv3$1@soap.pipex.net... > I have been given the task of resurrecting the Xilinx software used at my > place of work. A few years ago we were quite active in designing various > bespoke electronic modules but the majority of our desingers have since > left. Our existing "out of date" set-up uses two types of design entry > methods: ABEL Version 5.12 and Orcad ESP V4.40 and the designs are > implemented using Xilinx XACT Version 5.1.0. > > As I understand it there are three available families of software: > Alliance, Foundation ISE and Foundation. > > I need to find out whether any or all of these families will be able to > support our old existing designs. I assume they probably do but can anyone > confirm this or point me to where I can find out this information. > > Regards > Alan > > >Article: 29031
This is a multi-part message in MIME format. --------------B488CC690C996B0ECD7B20C0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit There is a difference between variable and signal declarations as it seems you have noticed. There is a brief description and example comparing signal and variable declarations in the Xilinx Synthesis and Simulation Guide at: http://toolbox.xilinx.com/docsan/2_1i/data/common/sim/sim2_2.htm Perhaps this can shed a little light as to what might be happening in your case. -- Brian Lenny wrote: > I found a problem:while implementing a VHDL design I declared all the variables I need as variable statement on a process : > > variable temp : std_logic_vector(Bu-1 downto 0); variable t : integer; variable dato : dati; variable coeff : coefficienti; > > where dati and coefficienti are type. The timing report of this design after flow engine run is : > > Design statistics: Minimum period: 51.279ns (Maximum frequency: 19.501MHz) Maximum net delay: 9.185ns > > Changing the declaration of the variables as signal statement outside the process...: > > signal temp : std_logic_vector(Bu-1 downto 0); signal t : integer; signal dato : dati; signal coeff : coefficienti; > > ..I found this result: > > Design statistics: Minimum period: 18.102ns (Maximum frequency: 55.243MHz) Maximum net delay: 7.240ns > > Please,does anybody tell me why? The design with signal statement does not give a right simulation. > > Thanks in advance --------------B488CC690C996B0ECD7B20C0 Content-Type: text/x-vcard; charset=us-ascii; name="brian.philofsky.vcf" Content-Transfer-Encoding: 7bit Content-Description: Card for Brian Philofsky Content-Disposition: attachment; filename="brian.philofsky.vcf" begin:vcard n:Philofsky;Brian tel;work:1-800-255-7778 x-mozilla-html:TRUE url:http://www.xilinx.com org:Xilinx, Inc.;Software Marketing adr:;;2300 55th Street;Boulder;CO;80301;USA version:2.1 email;internet:brianp@xilinx.com title:Sr. Technical Marketing Engineer fn:Brian Philofsky end:vcard --------------B488CC690C996B0ECD7B20C0--Article: 29032
Dominet Systems is an early stage startup developing "Ethernet in the first mile" products. These cutting edge Ethernet products will enable new levels of performance and service for residential and business customers throughout the world, while lowering the service provider's costs. We will change the way integrated voice, video and high speed internet access services are provided. Currently, we are looking for a Board-level Design Engineer to join our rapidly growing team. Work with ASIC engineers to design and develop the first generation of Ethernet switches based on a new architecture. Responsibilities include board level architecture and conceptual design, detailed logic and circuit design, component selection, schematic entry, supervision of PCB layout, supervision of prototype fabrication and prototype bring-up and debug. Requires a BSEE with 7+ years of related experience or MSEE with 5+ years or related experience. MS preferred. Requires experience with high-speed PCB board designs. LVDS signaling experience is a plus. Requires experience with board level design tools. Prior experience with Viewlogic tools is a plus, as wells as HSPICE, XTK, and Verilog/FPGA design. Strong hardware debug and lab skills with logic analyzers and oscilloscopes are essential. Experience with Ethernet networking components and protocols and knowledge of high-speed signal integrity design techniques is highly desirable. Must have pro-active, self-starter style with good communication skills and exceptional technical skills. Please check out our web site at http://www.dominetsystems.com to find out more information about our company and our distinguished founders. Best regards, Michael Malone, Recruiter Dominet Systems 408-436-6665 mmalone@dominetsystems.com Sent via Deja.com http://www.deja.com/Article: 29033
I have just posted the article "Hold Everything" to the Netrino
website. It can be found at the following URL:
http://www.netrino.com/Connecting/2000-05/
I once ran into a difficult problem involving run-time calibration of
real world (that is, imperfect) components. A client was developing a
piece of exercise equipment that was to provide a variable number of
pounds of force feedback to a human operator. To support the complete
range of possible force settings with a given worst-case accuracy, the
product was correctly designed around a microcontroller. The embedded
software that ran on this microcontroller was principally responsible
for regulating the voltage going to a brake such that the brake's
calipers would "slip" precisely at the selected force. Due to a range
of differences in each physical brake, calibration was a challenge.
Here's what I learned that might be of use to others.
This article was first published in the March 2000 issue of Embedded
Systems Programming. For more information about the magazine, or to
sign up for a free subscription, please visit:
http://www.embedded.com/
The Netrino Consultants Network encourages its partners and associates
to share their technical expertise by writing magazine articles and books
and by speaking at industry conferences. Whenever possible we retain the
right to publish these materials on our website. An complete index of our
publications can be found at the following URL:
http://www.netrino.com/Publications/
I hope you will find these resources valuable, and relevant to these
newsgroups.
Sincerely,
Michael Barr
Article: 29034For old designs you are likely stuck with the old XACT software since newer Xilinx tools do not support the 2K, 3K, and plain (non-E) 4K devices. I think there might have been one or two releases after 5.1 (5.2/6.0?) before the switch to Foundation etc. regards, Tom Burgess Alan Horton wrote: > > I have been given the task of resurrecting the Xilinx software used at my > place of work. A few years ago we were quite active in designing various > bespoke electronic modules but the majority of our desingers have since > left. Our existing "out of date" set-up uses two types of design entry > methods: ABEL Version 5.12 and Orcad ESP V4.40 and the designs are > implemented using Xilinx XACT Version 5.1.0. > > As I understand it there are three available families of software: > Alliance, Foundation ISE and Foundation. > > I need to find out whether any or all of these families will be able to > support our old existing designs. I assume they probably do but can anyone > confirm this or point me to where I can find out this information. > > Regards > AlanArticle: 29035
Registration information will become available shortly.
Christof Paar
====================================================================
Workshop on Cryptographic Hardware and Embedded Systems 2001
(CHES 2001)
www.chesworkshop.org
Paris - France
May 13 - 16, 2001
Third and Final Call for Papers
General Information
The focus of this workshop is on all aspects of cryptographic
hardware and embedded system design. The workshop will be a forum of
new results from the research community as well as from the industry.
Of special interest are contributions that describe new methods for
efficient hardware implementations and high-speed software for
embedded systems, e.g., smart cards, microprocessors, DSPs, etc. We
hope that the workshop will help to fill the gap between the
cryptography research community and the application areas of
cryptography. Consequently, we encourage submission from academia,
industry, and other organizations. All submitted papers will be
reviewed.
This will be the third CHES workshop. The first workshop, CHES '99,
was held at WPI in August of 1999 and was very well received by
academia and industry. There were 170 participants, more than half of
which were from outside the United States. The second workshop, CHES
2000, was also held at WPI in August of 2000 and had an attendance of
180.
The third workshop, CHES 2001, will be held in Paris in May of 2001.
The topics of interest include but are not limited to:
* Computer architectures for public-key cryptosystems
* Computer architectures for secret-key cryptosystems
* Reconfigurable computing and applications in cryptography
* Cryptographic processors and co-processors
* Modular and Galois field arithmetic architectures
* Tamper resistance on the chip and board level
* Smart card attacks and architectures
* Efficient algorithms for embedded processors
* Special-purpose hardware for cryptanalysis
* Fast network encryption
* True and pseudo random number generators
* Cryptography in wireless applications
Instructions for Authors
Authors are invited to submit original papers. The preferred
submission form is by electronic mail to submission@chesworkshop.org.
Papers should be formatted in 12pt type and not exceed 12 pages (not
including the title page and the bibliography). The title page should
contain the author's name, address (including email address and an
indication of the corresponding author), an abstract, and a small
list of key words. Please submit the paper in Postscript or PDF. We
recommend that you generate the PS or PDF file using LaTeX, however,
MS Word is also acceptable. All submissions will be refereed.
Only original research contributions will be considered. Submissions
must not substantially duplicate work that any of the authors have
published elsewhere or have submitted in parallel to any other
conferences or workshops that have proceedings.
Important Dates
Submission Deadline: February 15th, 2001.
Acceptance Notification: March 31st, 2001.
Final Version due: April 21st, 2001.
Workshop: May 13th - 16th, 2001.
NOTE: The CHES dates May 13th - 16th are Sunday - Wednesday
succeeding Eurocrypt 2001 which ends on Thursday, May 10th.
Invited Speakers
Ross Anderson, University of Cambridge, U.K.
"Protecting Embedded Systems - the Next Ten Years"
Adi Shamir, Weizmann Institute, Israel (tentative)
TBA
Mailing List
If you want to receive emails with subsequent Call for Papers and
registration information, please send a brief mail to:
mailinglist@chesworkshop.org
Program Committee
Ross Anderson, Cambridge University, England
Jean-Sebastien Coron, Gemplus, France
Kris Gaj, George Mason University, USA
Jim Goodman, Chrysalis-ITS, Canada
Anwar Hasan, University of Waterloo, Canada
Peter Kornerup, Odense University, Denmark
Bart Preneel, Katholieke Universiteit Leuven, Belgium
Jean-Jacques Quisquater, Universite Catholique de Louvain, Belgium
Patrice L. Roussel, Intel Corporation, USA
Christoph Ruland, University of Siegen, Germany
Erkay Savas, rTrust Technologies, USA
Joseph Silverman, Brown University and NTRU Cryptosystems, Inc., USA
Jacques Stern, Ecole Normale Superieure, France
Colin Walter, Computation Department - UMIST, U.K.
Michael Wiener, Entrust Technologies, Canada
Organizational Committee
All correspondence and/or questions should be directed to either of the
Organizational Committee Members:
Cetin Kaya Koc
(Publications Chair)
Dept. of Electrical & Computer Engineering
Oregon State University
Corvallis, Oregon 97331, USA
Phone: +1 541 737 4853
Fax: +1 541 737 8377
Email: Koc@ece.orst.edu
David Naccache
(Program Chair and Local Organization)
Gemplus Card International
34 Rue Guynemer
92447 Issy les Moulineaux Cedex, FRANCE
Phone: +33 1 46 48 20 11
Fax: +33 1 46 48 20 04
Email: David.Naccache@gemplus.com
Christof Paar
(Publicity Chair)
Dept. of Electrical & Computer Engineering
Worcester Polytechnic Institute
Worcester, MA 01609, USA
Phone: +1 508 831 5061
Fax: +1 508 831 5491
Email: christof@ece.wpi.edu
Workshop Proceedings
The post-proceedings will be published in Springer-Verlag's Lecture
Notes in Computer Science (LNCS) series. Notice that in order to be
included in the proceedings, the authors of an accepted paper must
guarantee to present their contribution at the workshop.
Article: 29036Austin Lesea wrote: > > http://www.xilinx.com/support/programr/cables.htm > > for the "new" cables that use USB for faster configuration. > > It is called Multilinx III. Don't do it through JTAG (takes longer). Actually, it is either MultiLINX or parallel cable III. Unless there is a newer rev., then that's the one I have tried. It is about 6X slower than parallel cable III using JTAG mode. Unfortunately JTAG mode is the only option available in the circuit board we have in the lab. > Austin K. C. LeeArticle: 29037
Software/Analog Hardware Engineer
Will work as a member of our test engineering team to design, test and
troubleshoot our next generation of test equipment.
Qualifications
BSEE (required)
2+ years experience in C/C++, VHDL, FPGA (required)
2+ years experience with analog hardware (required)
DSP and digital experience preferred
Send or Fax resume to:
"Software/Analog Hardware Engineer Web"
3629 Vista Mercado
Camarillo, CA 93012
FAX: (805) 383-1838
EMAIL: humanresources@a-m-c.com
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Article: 29038Steve Rencontre wrote: > In article <3A7A385B.C979A413@earthlink.net>, palfke@earthlink.net (Peter > Alfke) wrote: > > > Steve Rencontre wrote: > > > > > I'm not sure I'd be very happy with a product that was guaranteed to > > > die > > > after 15 years even with a 'perfect' battery. > > > > > > > Most watches use batteries, as do cameras and many PalmPilots. > > Smoke alarms need a battery, kind of every year. > > Cars need a new battery, new tires and a new muffler now and then. > > Oh, I agree entirely. However, I fear that 15 years is well over the > horizon for many engineering and all marketing departments, and > that providing battery-monitoring circuitry, and/or the case mechanics to > allow safe battery changing with power applied will be seen as unnecessary > expense in too many instances. Sounds like another Y2K on a continuous basis... > > > -- > Steve Rencontre http://www.rsn-tech.co.uk > //#include <disclaimer.h>Article: 29039
Terry Hicks wrote: > > Sounds like another Y2K on a continuous basis... C'mon, let's put this in perspective. For the past 15 years hundreds of millions of S-RAM based FPGAs have been sold by Xilinx, Altera, Lucent and perhaps a few others. None of these FPGAs ever offered the option of bitstream encryption. Somehow tens of thousands of users have bought and used these chips in their equipment. And paid us good money, thank you! Now Xilinx offers, in a new family, the option of encrypting the bitstream. And all I hear is the whining that batteries don't last, need to be changed, causing a service problem. Y2K, my foot ! Let me predict that a few years from now, 95% of all FPGA designs will still be un-encrypted, and the remaining 5% are so obsessed about design security that they gladly change the battery every 10 years, 5 years before they have lost their charge. I did not expect a loud "thank you" for offering a new valuable and, in certain cases, priceless feature. But I had not expected all this whining either. Encrypted bitstreams are encrypted for a reason. Changing the battery every decade is a minor nuisance, well worth the protection it offers, if you need the protection. Nobody forces you to use this unique option. End of soapbox. Peter AlfkeArticle: 29040
I am looking to start coding fpga's but have a little trouble getting the first very basic info. Such as how many gates on a chip is many, which starterkits would be recomendable, what the potential of fpga is... such as how fast they will actually function ect ect. Is there a faq for this group coving some of this?Article: 29041
I am an amateur circuit designer. It seems that the FPGA world may now be inexpensive enough for me to give it a try. Could you please recommend a book and board combo that would get me going. Although I have a good understanding of TTL style logic design, I have no experience with this more advanced stuff. Thanks, KevinArticle: 29042
> I am an amateur circuit designer. It seems that the FPGA world may now be > inexpensive enough for me to give it a try. Could you please recommend a > book and board combo that would get me going. Although I have a good > understanding of TTL style logic design, I have no experience with this > more advanced stuff. ------- Generic Answer -------- This question gets asked a lot on this newsgroup. Your quickest, most extensive answer will be found by going to www.deja.com and searching this newsgroup with the keywords "fpga starter kit". About 40 hits last time I checked. You can also go to http://www.optimagic.com. They have a list of programmable logic board vendors and a bunch of links to tutorials and software you can use. -------- Company-Specific Answer ---------- My company has a document (http://www.xess.com/manuals/webpack-3_1.pdf) that shows you how to get, install, and use the free XILINX WebPACK software to do programmable logic designs. You can also look at our list of programmable logic boards (http://www.xess.com/ho04000.html). -- || Dr. Dave Van den Bout XESS Corp. (919) 387-0076 || || devb@xess.com 2608 Sweetgum Dr. (800) 549-9377 || || http://www.xess.com Apex, NC 27502 USA FAX:(919) 387-1302 ||Article: 29043
Sorry, I was just trying to inject a little humor. I didn't mean to impune Xilinx's intentions or quality. If I understand correctly, the bitstream encription will allow the battery to keep the data "alive" without the use of a prom which can be copied. Is that right? If so I think it is great for those who can deal with the problem of lost memory. Or does it merely keep the key (in RAM) to de-cript the bitstream such that without the key the device is useless. Either way if the user/designer is willing to deal with the limitations of battery technology great. If not, as Peter as said don't use it. Peter Alfke wrote: > Terry Hicks wrote: > > > > > Sounds like another Y2K on a continuous basis... > > C'mon, let's put this in perspective. > For the past 15 years hundreds of millions of > S-RAM based FPGAs have been sold > by Xilinx, Altera, Lucent and perhaps a few > others. None of these FPGAs ever > offered the option of bitstream encryption. > Somehow tens of thousands of users > have bought and used these chips in their > equipment. And paid us good money, > thank you! > > Now Xilinx offers, in a new family, the option of > encrypting the bitstream. > And all I hear is the whining that batteries don't > last, need to be changed, > causing a service problem. Y2K, my foot ! > > Let me predict that a few years from now, 95% of > all FPGA designs will still be > un-encrypted, and the remaining 5% are so obsessed > about design security that > they gladly change the battery every 10 years, 5 > years before they have lost > their charge. > > I did not expect a loud "thank you" for offering a > new valuable and, in certain > cases, priceless feature. > But I had not expected all this whining either. > Encrypted bitstreams are encrypted for a reason. > Changing the battery every > decade is a minor nuisance, well worth the > protection it offers, if you need > the protection. Nobody forces you to use this > unique option. > End of soapbox. > > Peter AlfkeArticle: 29044
Dave,
Thanks for taking the opportunity to answer this question without using it as
a soapbox to push your particular product. I really respect that behavior. It
shows a great deal of personal integrity. I have a potential need for a simple
_fast_ FPGA board. Perhaps I will give you a try.
Thanks,
Theron Hicks
Dave Vanden Bout wrote:
> > I am an amateur circuit designer. It seems that the FPGA world may now be
> > inexpensive enough for me to give it a try. Could you please recommend a
> > book and board combo that would get me going. Although I have a good
> > understanding of TTL style logic design, I have no experience with this
> > more advanced stuff.
>
> ------- Generic Answer --------
> This question gets asked a lot on this newsgroup. Your quickest, most
> extensive answer will be found by going to www.deja.com and searching this
> newsgroup with the keywords "fpga starter kit". About 40 hits last time I
> checked.
>
> You can also go to http://www.optimagic.com. They have a list of
> programmable logic board vendors and a bunch of links to tutorials and
> software you can use.
>
> -------- Company-Specific Answer ----------
> My company has a document (http://www.xess.com/manuals/webpack-3_1.pdf) that
> shows you how to get, install, and use the free XILINX WebPACK software to do
> programmable logic designs. You can also look at our list of programmable
> logic boards (http://www.xess.com/ho04000.html).
>
> --
> || Dr. Dave Van den Bout XESS Corp. (919) 387-0076 ||
> || devb@xess.com 2608 Sweetgum Dr. (800) 549-9377 ||
> || http://www.xess.com Apex, NC 27502 USA FAX:(919) 387-1302 ||
Article: 29045To be safe, the cell would need to be of known high quality and be replaced more often than every decade. Every 5 years would be safer, and moreover the designer would have to build in something (a large cap) to hold the VCC up while it is being changed. That cap cannot be any sort of electrolytic (which includes tants); it would have to be a ceramic. Plus a mechanism to make sure the battery is changed before the time is up. A real time clock chip? A "change by date" sticker on the outside of the product? The point is that after 5 years most products will be unsupported and the mfg may even have gone bust. Then I am risking the operation of my product (which presumably wasn't something very cheap) on a successful change of a battery. Moreover I don't think battery backed up CMOS SRAM (which is basically what we are talking about here) is a good technology to use in any sort of harsh environment. Very few people would use that technology to store any critical data, e.g. in an industrial control application. I have designed many products, 1978 onwards, which used this, and no matter how much engineering one puts into it, somebody somewhere always manages to trash the thing. EEPROM/FLASH is the way forward for storing anything that really matters, and there is no fundamental difference in security because if you remove VCC from SRAM the data will probably mostly remain. Presumably SRAM was used because putting EEPROM/FLASH on the same chip is a more complicated process. This is a very badly thought out idea, IMHO. >> Sounds like another Y2K on a continuous basis... > >C'mon, let's put this in perspective. >For the past 15 years hundreds of millions of >S-RAM based FPGAs have been sold >by Xilinx, Altera, Lucent and perhaps a few >others. None of these FPGAs ever >offered the option of bitstream encryption. >Somehow tens of thousands of users >have bought and used these chips in their >equipment. And paid us good money, >thank you! > >Now Xilinx offers, in a new family, the option of >encrypting the bitstream. >And all I hear is the whining that batteries don't >last, need to be changed, >causing a service problem. Y2K, my foot ! > >Let me predict that a few years from now, 95% of >all FPGA designs will still be >un-encrypted, and the remaining 5% are so obsessed >about design security that >they gladly change the battery every 10 years, 5 >years before they have lost >their charge. > >I did not expect a loud "thank you" for offering a >new valuable and, in certain >cases, priceless feature. >But I had not expected all this whining either. >Encrypted bitstreams are encrypted for a reason. >Changing the battery every >decade is a minor nuisance, well worth the >protection it offers, if you need >the protection. Nobody forces you to use this >unique option. >End of soapbox. Peter. -- Return address is invalid to help stop junk mail. E-mail replies to zX80@digiYserve.com but remove the X and the Y. Please do NOT copy usenet posts to email - it is NOT necessary.Article: 29046
In article <3A7B9C79.2D6E31DC@earthlink.net>, Peter Alfke <palfke@earthlink.net> wrote: ... >Now Xilinx offers, in a new family, the option of >encrypting the bitstream. ... >Nobody forces you to use this unique option. > As a consumer yes they do. I admit I am atypical but I still use an old 486 as a Linux web server/firewall etc (had to replace memory backup battery but could re-enter all data backed up by it myself), a laserjet III and other old consumer equipment at home along with the new stuff. Please no followup post on why people would want to use this junk, nothing will be accomplished by it, private email is fine. I know some companies will make the decision that their WizBanger 2000 will need protection but due to cost, replaceable batteries are out and only 5 year estimated battery life is fine since it won't change warranty repair rates and people should have bought the WizBanger 6000 by then anyway. I will be annoyed if I bought the product but there may not be enough of us to matter. I understand why Xilinx added this solution and for many of the groups involved this is a good thing. If my company was in the correct market segment I might even recommend using it. We will be using those neat new Virtex II's on our next project. But like many solutions to problems it is bad for some (and arguing the subject further probably won't accomplish much either). >I just don't believe the story about many lithium batteries being >short-lived. > It doesn't qualify for "many" but Garmin had a bad batch for their GPS's. Since this was back in 98 not much is available online about it and dejanews doesn't go back long enough anymore to see the discussion in the newsgroup. Only reference I could find is http://joe.mehaffey.com/li_bats.htm Others also have been dealing with failing memory backup batteries in equipment they want to run, for example Suns. http://www.squirrel.com/squirrel/sun-nvram-hostid.faq.html I also try to keep even older equipment running just because I find it interesting. David Gesswein http://www.pdp8.net/ -- Run an old computer with blinkenlightsArticle: 29047
Piggy wrote: > > I have ORCA OC2C06 serie FPGA. > I want to program using PROTEL 99 SE. > The device is not native to Protel PLD library. On Protel web site, > it say that I have to set device to 'Virtual', which I did. > I also downloaded fitter files. > > I compile the file but I get only a PLD/PLA/... but after that, how > can I generate the file for the specific target I want (ORCA > OR2C06...)? I do not know anything about Protel, but I doubt that they provide the end to end capability to design FPGAs. FPGAs require a much more complex "fitter" which is typically only provided by the chip manufacturer. However, Lucent has a very inexpensive package that will let you design a OR2C06 part in VHDL, Verilog or Viewlogic schematic. I got my copy for free since I was designing a board using their parts. Give a call to your Lucent FAE. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design Arius 4 King Ave Frederick, MD 21701-3110 301-682-7772 Voice 301-682-7666 FAX URL http://www.arius.comArticle: 29048
Austin Lesea wrote: > > .... I can't watch while misleaading information is spread around: > > > If you want to know what the 20KE PLL really does, measure it with > other things happening in the part. > > [Image] > > This is what Altera doesn't want you to see. It is their "perfect" ...snip... > > Austin Austin, Just a reminder. This is not a binary group. If you have an image to post, it should be done with a link or a reference, not as part of the message. My understanding is that if a lot of binaries get posted to a non-binary newsgroup, it can result in the group being dropped from some servers. Then there will be people don't get to read any of your posts! -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design Arius 4 King Ave Frederick, MD 21701-3110 301-682-7772 Voice 301-682-7666 FAX URL http://www.arius.comArticle: 29049
Hi there, Could you, PLEASE, advice me a good VHDL reference book. I would like a book with emphasize practical issues: VHDL language, how to write VHDL TestBenches, pitfalls etc. I am particularly interested in targetting FPGAs. Cheers.
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