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> There are other SI tools available, that are more (from Mentor, Cadence, Avanti, > etc.) but I find Hyperlynx to be completely adequate for a lot of designs. It > has a spice extraction mode to extract spice models from the pcb layout that is > particularly useful, too. Maybe I just like its user interface. Any SI tool is > a worthwhile investment. Thanks. What sort of "pcb layout" database/file can it read? -- These are my opinions, not necessarily my employeers. I hate spam.Article: 34276
> Let me have a Fax number and I'll see what I can do. I certainly have > a data sheet somewhere in the paper archive that litters my office :-) Unfortunatly I cant recieve faxes. Do you have access to a scanner? Perhaps you could scan it in and email it to me...Article: 34277
Hi All, Anyone knows what will happen to the Xilinx Spartan2 if I have accidentally connected the "not connected" (e.g. P55, P56 on a PQ208) pins externally on the PCB? My PCB maker has actually connected all the pins that I marked as NC (no connection)... Thanks for any advice. HaydenArticle: 34278
*** post for FREE via your newsreader at post.newsfeeds.com ***
Hello everyone!
I'm a member of a PCI team at Opencores (www.opencores.org). We are
developing a 32 bit WISHBONE to PCI bridge.
We have an Insight development board with Spartan2 -5 FPGA. I've defined
constraints for PCI ports, such as IOB register usage and PCI33_5 type of IO
port.
Now the question - in initial timing analysis PAR reports 8.9ns delay for
output signals which are packed in IOB register together with its output
enable register. How is that possible? Do I have to define any other
constraint to reduce this delay or is this the best Spartan2 can do on 5V
PCI bus?
Regards,
Miha Dolenc
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Article: 34279My main problem is that the system is critical and I really need to know what logic is being placed on the chip so it can be verified that it meets the spec. MattArticle: 34280
>This is possible too. You can also drive your 2x Clock with falling >edges (in the HDL description) >Or drive it on the same edge and just insert a synchronizer (running on >the falling edge). Please Falk could you tell me how to implement this synchronizer, i am interested in high speed design, or at least describe its function thanks >Ok, this will increase latency but is required for highest speeds >anyway. > >-- >MFG >Falk > >Article: 34281
In article <aa5d502.0108161654.146ee3ec@posting.google.com>,
jonwil@tpgi.com.au (Jonathan Wilson) writes:
> I am trying to get a datasheet on a 18P8 PAL.
> If anyone can help that would be good.
> None of the manufacturers sites I tried had one.
>
No registration, search for ampal18p8 at
http://www.e-insite.net/
Better search (can do a contains match for 18p8) but requires registration.
http://www.freetradezone.com/
Both seem to use same database and have PDF scans of datasheets.
David Gesswein
http://www.pdp8.net/ -- Run an old computer with blinkenlights
Have any PDP-8 stuff you're willing to part with?
Article: 34282"Hayden So" <haydenso@yahoo.com> wrote in message news:<ee7207c.-1@WebX.sUN8CHnE>... > Hi All, > > Anyone knows what will happen to the > Xilinx Spartan2 if I have > accidentally connected the "not > connected" (e.g. P55, P56 on a > PQ208) pins externally on the PCB? I think that 'not-connected' means they are not bonded, rather than *do not connect*. You could always make sure by checking the NC pins' resistances to ground, on an unmounted chip. It should be open-circuit, if my theory is correct. LeonArticle: 34283
Hi all, using JTAG programmer 3.307i from Xilinx I just wanted to configure my Spartan-II XC2S150 device. Here is what the log file is saying, any idea? JTAGProgrammer:Release 3.3.07i - JTAG Boundary-Scan Download D.26 Copyright:1991-1999 JTAG Programmer Started 2001/08/18 17:10:52 Loading Boundary-Scan Description Language (BSDL) file 'C:/Xilinx/spartan2/data/xc2s150_fg256.bsd'.....completed successfully. Checking boundary-scan chain integrity...done. Verifying device positions in boundary-scan chain... Instance 'du_core(Device1)' at position '1'...verified. Verification completed. Boundary-scan chain validated successfully. 'du_core(Device1)': Checking boundary-scan chain integrity...done. 'du_core(Device1)': Reading bit-stream file...done. 'du_core(Device1)': Programming device.........done. 'du_core(Device1)': Checking boundary-scan chain integrity...done. 'du_core(Device1)': Reading bit-stream mask file...BIT FILE READ FAILURE from load_mask_object().ERROR:JTag - Unable to open file 'E:\dokument.all\work_aldec\du_fpga\xilinx\xproj\ver1\rev1\du_core.msk'. Check if file exists and has read permission to all. Modify using 'chmod', if necessary. 'du_core(Device1)': Cannot definitively confirm status of chip, Verify that DONE went high manually. markus -- ******************************************************************** ** Meng Engineering Telefon 056 222 44 10 ** ** Markus Meng Natel 079 230 93 86 ** ** Bruggerstr. 21 Telefax 056 222 44 10 ** ** CH-5400 Baden Email meng.engineering@bluewin.ch ** ******************************************************************** ** Theory may inform, but Practice convinces. -- George Bain **Article: 34284
On Thu, 16 Aug 2001 23:28:37 -0400, "Austin Franklin" <austin@darkroom99.com> wrote: > >No, it is not a requirement to implement configuration, if you are only >responding to a specific hard coded address as far as I am concerned. You >aren't operating specifically as a PCI device in your description (POST Code >Display), so you really need nothing PCI configuration offers. You are >doing nothing but "sniffing" the bus. Now, the only issue that could come >up is if some bridge chip decides to only allow addresses it knows are for >that particular PCI segment through... Is it true that in a normal PC system, the bridge will claim all the address which are not claimed by other PCI devices on bus? If that is the case, it should be fine. > >> Now,I am converting a lagacy ISA I/O card to PCI card (no need for >> plug-n-play). But It uses Interrupt. Do I have to implement >> Configurarion and let the system to assign a ramdon interupt or I can >> assign it myself? It would be great if I can fix #INTA to a specific >> IRQ. Because I would like to keep the exsiting software driver >> untouched and let it handle the interrupt. Is there a way of doing so. > >It is BIOS dependant. Some BIOSs allow you to specify what interrupt goes >to what PCI slot...but you can not count on that unless you have control of >the motherboard. > > As long as I can get a motherboard which allows me to map the interrupt to a given PCI slot, it serves my purpose. The existing drive can remain unchanged(It is not written by me). I don't know how to write a driver. The good old DOS days are long gone. I/Os can no longer be accessed simply by issuing "IN" and "OUT" commands. The ISA board I am asked to convert is integrated with a dedicated PC as a part of control system. It has been sold for many years and works great. From performance point of view, there is really no need to change it. The only problem is that PC boards with ISA slots are diminishing and eventually, there will be nowhere to plug in a ISA card. Seems all I need to do now is: 1. Find a PC board which let me lock a certain IRQ interrupt to a certain PCI slot. 2. Make a FPGA PCI snooping device which use the same I/O address and interrupt. What about Xilinx9500 CPLD? Does it support PCI I/O stardard. Lattice have a free PCI core. But I don't know if it let users to hardwire the address and interrupt. Anyone have this information?Article: 34285
John wrote: > > Do any of you kown some good starting point for finding FPGA development boards. I have quite > specific requirement such as PCI interface (or preferably PMC interface), onboard (or SODIM) SDRAM > (> 32MB) and lots of user IO (in the range of 150 I/O). And I perfer using Xilinx. > The Virtex-E development board from Avnet has it all. See www.ads.avnet.com for details. I have purchased one board for $1,495:- and it is great value for money! Jiri Gaisler. -- ----------------------------------------------------------------------- Gaisler Research, Plantageg. 5, 41305 Goteborg, Sweden, +46-73-9927100 email: jiri@gaisler.com, home page: http://www.gaisler.com -----------------------------------------------------------------------Article: 34286
M Pedley wrote: > > My main problem is that the system is critical and I really need to > know what logic is being placed on the chip so it can be verified that > it meets the spec. > > Matt So it's a version control/verification problem ? In that case, rather than reverse the JED, why not create test vectors - that way you confirm not only the Fuse patterns, but also the logic resulting from those fuses. The silicon can then be proven after programming. The FIT eqn reports will confirm the logic, one layer above the Fuses, and the vector test confirms it in silicon, so you have everything covered :-) -jgArticle: 34287
Hello, There are a number of things that could be wrong. You could violate your timespecs because: 1. Your timespecs are wrong. 2. The clock delay is too high. 3. The flops aren't packed like you think. For case 1, verify that you have constrained the paths with the correct timespecs. The PCI 2.2 specification for 33 MHz operation suggests that the clock to valid maximum for bussed signals is 11 ns. For point to point signals, it is 12 ns. I don't know what type of constraint you specified (to:from or an offset) that had an 8.9 ns result, but it doesn't sound unreasonable. As for your question "is that the best it can do" it doesn't need to do any better because a 5.0 v bus will not run at 66 MHz, so you will never need anything faster. For case 2, you should verify that you are using the right input pin for the global clock that is clocking the IOB. It needs to be on a global clock input and use the right IBUFG standard, and also requires the use of a BUFG for distribution. Other configurations may increase the "clock" portion of the "clock to out" causing your design to fail. For case 3, you should verify that all OFD and all TFD are indeed packed in the offending IOBs. You can do this by checking the mapper report or opening the design with fpga_editor and inspecting the IOBs in question. If you have used the correct "IOB=TRUE" constraints in the UCF or the mapper "-pr o|b" option, and the flops still are not in the IOB, it may be a result of your logic design. If you are implementing the source sampling bypass rules in the PCI 2.2 specification using the output of the flops you want in the IOB, it will not pack properly because there will be more than one load on the output net. You must create duplicate (shadow) copies of all OFDs and TFDs for use by the bypassing logic. Another potential snafu that is often overlooked is that your design must have an individual TFD flop for each OFD. If you instantiate them, it works great. If you are using a synthesis tool, you must code up the appropriate number and then be sure to disable duplicate register merge or whatever your favorite synthesis tool calls it... Otherwise it will tend to optimize all but one of them away, and the packing will fail. Hope that helps, Eric Crabill Miha Dolenc wrote: > We have an Insight development board with Spartan2 -5 FPGA. I've defined > constraints for PCI ports, such as IOB register usage and PCI33_5 type of IO > port. > Now the question - in initial timing analysis PAR reports 8.9ns delay for > output signals which are packed in IOB register together with its output > enable register. How is that possible? Do I have to define any other > constraint to reduce this delay or is this the best Spartan2 can do on 5V > PCI bus?Article: 34288
****************************************************************************
***
THERE'S STILL TIME TO SUBMIT A PAPER TO ACSAC'2002 - Melbourne, Australia
****************************************************************************
***
Asia-Pacific Computer Systems Architecture Conference
Call For Papers
The Asia-Pacific Computer Systems Architecture Conference (ACSAC'2002)
will be held at Monash University, Melbourne, Australia from 28 January -
30 January, 2002. Original papers on all aspects of computer systems
architecture are invited, including, but not restricted to:
* arithmetic circuits
* processor design and architecture
* reconfigurable architectures
* instruction-level parallelism
* hardware support for operating systems and languages
* multiprocessor architectures
* interconnection networks
* software structures designed to utilise special hardware features
* operating systems
* embedded systems
* compilers
* virtual machines
All papers will be fully refereed. Full details of the conference are
available from
http://ciips.ee.uwa.edu.au/~morris/ACAC2002/index.html
Don't miss this opportunity to visit Australia and interact with
the computer systems architects from "down-under" and the Asia-Pacific
region.
Feipei Lai, National Taiwan University (flai@cc.ee.ntu.edu.tw)
John Morris, University of Western Australia (morris@ee.uwa.edu.au)
Programme Committee Co-Chairs
Article: 34289Eric Smith wrote: > > Reinoud <dus@wanabe.nl> writes: > > A circuit like you have drawn above will oscillate at a fairly high > > frequency. If there are many loops, or if a lot of logic is driven > > at high frequency by such loops, this may draw a lot of power. Many > > boards out there with large FPGAs were not designed to handle such > > power. This is not a flaw of Virtex (actually, Xilinx documents > > power issues quite clearly), it's more a board/system design issue > > with current generation (high power density) chips. > > I appreciate the insight. However, I'm still curious as to whether > such things are likely to damage the chip. I suppose the answer > may depend on how many such circuits one manages to configure. It depends on how hot the chip can get when downloading such problematic designs. This depends on FPGA technology, die size, packaging and cooling - and the capacity of the power supply. The combination of a huge modern FPGA, strong power supply, and no heatsink has high potential for smoke emissions. With a tiny FPGA or weak power supply, no sweat. Otherwise, cooling or power/temperature monitoring can keep things within safe limits. You can get an idea of these power issues by playing with the power estimator on the Xilinx website, and calculating die temperatures with the package thermal data. - Reinoud (Spam goes to wanabe, mail to wanadoo.)Article: 34290
I would be very interested to see the resolution to this problem as I am having a very similar issue. I have 2 Virtex-E devices in a daisy chain configuration and I try to configure them using the multilinx cable. When I do, I get the same messages you get (minus the one about the .msk file... I do however get this when I try to verify the devices...) When I check done manually of course it is low and never goes high. From reading the documentation and talking to the xilinx app engineer, the two things I found that were supposed to fix this probem were: 1. You must use the JTAG clock as your startup clock for boundary scan configuration (in bitgen command use " -g StartUpClk:JTAGClk") 2. Also in your bitgen file, set the secuirity bits to NONE. (in bitgen command use "-g Security:NONE"). This is supposed to allow the readback of the status of the DONE pin. Like I said, I thought these would help but they didn't, but feel free to give them a try. The last thing that the xilinx engineer told me to try (which I haven't had time to yet so I don't know if it will work) is to verify that the .bit file was generated using the latest service pack of the toolset (Service Pack 8 in my case for alliance...) I would appreciate anymore ideas anyone may have... Hope this helps you Marcus... P.S. I have since programmed the flash on my board and successfully configured using SelectMAP mode so I am pretty sure this is a multilinx/software problem. "Markus Meng" <meng.engineering@bluewin.ch> wrote in message news:3b7e8a80$1_2@news.bluewin.ch... > Hi all, > > using JTAG programmer 3.307i from Xilinx I just wanted to > configure my Spartan-II XC2S150 device. Here is what the > log file is saying, any idea? > > JTAGProgrammer:Release 3.3.07i - JTAG Boundary-Scan Download D.26 > Copyright:1991-1999 > JTAG Programmer Started 2001/08/18 17:10:52 > Loading Boundary-Scan Description Language (BSDL) file > 'C:/Xilinx/spartan2/data/xc2s150_fg256.bsd'.....completed successfully. > Checking boundary-scan chain integrity...done. > Verifying device positions in boundary-scan chain... > Instance 'du_core(Device1)' at position '1'...verified. > Verification completed. > Boundary-scan chain validated successfully. > 'du_core(Device1)': Checking boundary-scan chain integrity...done. > 'du_core(Device1)': Reading bit-stream file...done. > 'du_core(Device1)': Programming device.........done. > 'du_core(Device1)': Checking boundary-scan chain integrity...done. > 'du_core(Device1)': Reading bit-stream mask file...BIT FILE READ FAILURE > from load_mask_object().ERROR:JTag - Unable to open file > 'E:\dokument.all\work_aldec\du_fpga\xilinx\xproj\ver1\rev1\du_core.msk'. > Check if file exists and has read permission to all. Modify using 'chmod', > if necessary. > 'du_core(Device1)': Cannot definitively confirm status of chip, > Verify that DONE went high manually. > > markus > > -- > ******************************************************************** > ** Meng Engineering Telefon 056 222 44 10 ** > ** Markus Meng Natel 079 230 93 86 ** > ** Bruggerstr. 21 Telefax 056 222 44 10 ** > ** CH-5400 Baden Email meng.engineering@bluewin.ch ** > ******************************************************************** > ** Theory may inform, but Practice convinces. -- George Bain ** > > > > > > >Article: 34291
Oh, ok. It has a nozzle like an exhaust. "-:Install:-" <no_spam@dingoblue.net.au> wrote in message news:3b7df01b$0$20921$7f31c96c@news01.syd.optusnet.com.au... > Thats the intake !.. > > "Tom Del Rosso" <no.spam.please-t.delrosso@att.net> wrote in message > > > > I like the way he has the jet exhaust aimed straight at the control > > panel.Article: 34293
On Sat, 18 Aug 2001 11:27:14 +0200, "Miha Dolenc" <mihad@opencores.org> wrote: >*** post for FREE via your newsreader at post.newsfeeds.com *** > >Hello everyone! > > I'm a member of a PCI team at Opencores (www.opencores.org). We are >developing a 32 bit WISHBONE to PCI bridge. >We have an Insight development board with Spartan2 -5 FPGA. I've defined >constraints for PCI ports, such as IOB register usage and PCI33_5 type of IO >port. >Now the question - in initial timing analysis PAR reports 8.9ns delay for >output signals which are packed in IOB register together with its output >enable register. How is that possible? Do I have to define any other >constraint to reduce this delay or is this the best Spartan2 can do on 5V >PCI bus? > In addition to checking Eric's points ... - look at the "map.mrp" file to check that both OUTFF and ENBFF are listed for the pins in question. If not - something is preventing their being mapped into the IOBs. This will have to be found and fixed. - if the "FAST" slew rate constraint is not specified (e.g. in the ucf file) for these pins, they will indeed be slow! - BrianArticle: 34294
Anyone who has read or examined the book _Principles of Verifiable RTL Design_ (2nd edition) by Bening and Foster: Comments about the usefulness and or relevance of the book to their work? Thanks.Article: 34295
> So, if you have an ISA card (legacy or PnP), and want to convert it to > a PCI card, and assuming that the card doesn't use the I/O or memory > address IBM defined, then it seems to me that you should implement > Configuration Address Space (and implement Base Address Register > inside the Configuration Address Space), so that BIOS or Windows can > assign I/O or memory address automatically. My understanding was he was using dedicated addresses, and as such, can't let the BIOS or Windows assign them. I do believe there are PCI boards that hardcode the addresses... > Since you are using interrupt, that makes it a requirement to > implement Configuration Address Space because interrupt handlers of > PCI devices use Configuration Register 3CH (Interrupt Line) and 3DH > (Interrupt Pin). Not really in PC based PCI implementations. They only use INTA. I believe there used to be a caveat about that in the spec. > You will likely have to rewrite your device driver to accommodate the > I/O or memory address that can get assigned to any location, and also > IRQ can get assigned to any IRQ (Configuration Register 3CH will hold > the IRQ number assign by BIOS or Windows). If the BIOS allows you to set the interrupt from each PCI slot to a particular INT, then that is not true. I believe he can do exactly what he wants, if he can find a BIOS that allows setting the INT.Article: 34297
On Sat, 18 Aug 2001 10:57:11 GMT, K.O <nospam@newsranger.com> wrote:
>
>Please Falk could you tell me how to implement this synchronizer, i am
>interested in high speed design, or at least describe its function
>
>thanks
You may also want to read:
http://www.fpga-faq.com/FAQ_Pages/0017_Tell_me_about_metastables.htm
and
I have discussed this at some length with the author of the following page,
and he has some nice simple synchronizer schematics for you to look
at.
http://www.interfacebus.com/Design_MetaStable.html
Philip Freidin
Philip Freidin
Fliptronics
Article: 34298Hello group! Does anyone know of a way to do JTAG TAP controller within FPGA? Gr, HansArticle: 34299
On Fri, 17 Aug 2001 18:00:20 +1000, "David L. Jones" <dljones@ozemail.com.au> wrote: >Russell Shaw <rjshaw@iprimus.com.au> wrote in message >news:3B7B401E.E90A0168@iprimus.com.au... >> http://www.asciimation.co.nz > >Someone has way too much free time on their hands! > >BTW, the relevance to electronics is? (oh that's right - it's ASCII) I think its more relevant to engineering, beer that is!
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