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This isn't a technical issue but probably effects the readers of this newsgroup more that 101st tool bug he's trying to solve at work. It concerns Opencores and the license under which the cores are offered for use. While I'm a big "information needs to be free" kind of guy, it seems kind of strange to me that the primary contributers are individuals, and the main beneficiaries (financially) are business entities. Aren't these kinds of projects usually handled under a "use limited to not for profit" arrangement? Kind of like shareware WS-FTP, if you're using it at school go ahead, but if you're making money using it, you shell out your $30. Otherwise all that we've accomplished is reducing corporate NRE at engineers' expense. I suppose you might argue that this in turn reduces the cost of consumer electronics goods for the whole world, but still, why on my ticket? Put another way, why should Motorola (for example) be able to my XYZ core back to me in the form of a cell phone ASIC? What do you think?Article: 45876
Don't give up so quick on the prefered solution of using the PCI clock. Before you kill yourself doing crazy async stuff, investigate the clock spec more carefully in the context of what Intel does in real life. Don't be afraid to probe the clock on a few PCs and see for yourself. Its comforting to follow specs, but sometimes they're wrong, outdated or not directly applicable. I know, I've written specs before. Regards FullyArticulate@yahoo.com (Mike Neuman) wrote in message news:<d617f3db.0208061251.791a2be3@posting.google.com>... > Hello! > > I'm working on a PCI to local bus bridge (using the Xilinx IP). I > need some recommendations on "best practices" (esp. if Verilog > specific). > > Everything dealing with the PCI "side" is nicely synchronous to the > PCI clock. However, there is no local bus clock. Every peripheral on > the local bus is a slave to chip select, output enable, and write > enable signals. > > A Xilinx reference bridge essentially synchronizes the local bus to > the PCI clock. I could probably do this, except the PCI spec says the > clock can be anywhere from 0-33Mhz, which means there are conditions > at which my design would simply stop working. In addition, there would > seem to be race conditions (i.e. my write_enable must be 30ns in order > to guarantee catching one positive clock edge, but if it's slightly > longer for some reason, I could potentially catch two) > > I can't use the Xilinx CORE asynchronous FIFO (it apparently > requires several "do nothing" clock cycles in order to move data > around. Since I have no "do nothing" clock cycles, this doesn't work). > > I'm currently doing things like: > > assign register_decode = CHIP_SELECT & (ADDR == REGISTER); > assign register_write = register_decode & WRITE_ENABLE; > assign register_read = register_decode & OUTPUT_ENABLE; > > always @(posedge register_write) > ... > > The problem is, combinatorial clocks give the compiler a headache. > In addition, I'm running into a timing problem (even in behavioral > simulation with no delays) where the bus lines get there after the > register_write edge. As a result, the above construct latches bad > data. > > Augh! Help! What is the best method for arbitrating between a > synchronous clock and asynchronous signals?Article: 45877
You don't have to because, unfortunately, it doesn't check them by default. FPGA timing analysis software is only just now getting to the level of sophistication required for multi-clock, non-handshaked, non-fifo's interface. In the past they relied mainly on single clock designs, explicit (examples given above) synchronization, and "hold time guaranteed by architecture" rather than timing calculations. Regards chen.songwei@mail.zte.com.cn (Apollo) wrote in message news:<913ddf38.0208061713.536debe4@posting.google.com>... > I think the TIG of xilinx constrain is a little simlar > "Set_False_Path" of Design Compiler .For example,i have 3 > clock(clk1/clk2/clk3) in my project. > Do i need add the following constrain so that both P&R and Timing > analyzer of xilinx ISE don't care them like Synopsys DC? > *********************************** > TIMESPEC "TS_clk1" = FROM "clk1" TO "clk2" TIG; > TIMESPEC "TS_Clk2" = FROM "clk2" TO "clk3" TIG; > TIMESPEC "TS_clk1" = FROM "clk1" TO "clk3" TIG; > TIMESPEC "clk3" = FROM "clk1" TO "MDC_c_c" TIG; > TIMESPEC "clk3" = FROM "clk2" TO "MDC_c_c" TIG;Article: 45878
"Jay" <kayrock66@yahoo.com> schrieb im Newsbeitrag news:d049f91b.0208081101.1256d131@posting.google.com... > You don't have to because, unfortunately, it doesn't check them by > default. FPGA timing analysis software is only just now getting to > the level of sophistication required for multi-clock, non-handshaked, > non-fifo's interface. In the past they relied mainly on single clock Is this the way to go? Iam doubtful. The problems of multi-clock domains with all the metastability issue are known for decades. So why always reinventing the wheel? Keep you design as single clock as possible. Use proven methods to cross clock domains clean. Why not using asynchronous FIFOs? As the PLDs are getting bigger, a FIFO doesnt really matter in size, even in the smallest devices (Iam not talking about CPLDs here ;-) I would not like to waste my time trying to reinvent the whhel to creat fancy, probably not full failsafe multiclock methods. Its like the debate between synchronus and asynchronus (selftimed) circuits. Yes there are also safe methods to design asynchronous logic, but there are almost no devices to do this. So I prefer doing synchronous designs and get things done. When this will start to get boring, I may write a PHD thesis about asynchronus design tequnices. ;-) -- MfG FalkArticle: 45879
"Jay" <kayrock66@yahoo.com> schrieb im Newsbeitrag news:d049f91b.0208081028.309454bd@posting.google.com... > I suppose you might argue that this in turn reduces the cost of > consumer electronics goods for the whole world, but still, why on my > ticket? Put another way, why should Motorola (for example) be able to > my XYZ core back to me in the form of a cell phone ASIC? In my opinion, this question is THE question of the WHOLE business today. MP3 was just the beginning. MPG4 (AKA DivX) is not the end. Technology now provides us the possibility to copy informations (not just Audio/Video also Software, databases etc) without any quality loss. Broadband access to the internet allows transportation of these contents all over the world almost for free in just an blink of an eye. Business in all ares heavyly depends on IT structure, just think about what we would do without our CAD tools? The industry (a often used, but strange term, that sound like an alien race but is not, since we all are emploees of the industry) tries to intoduce digital right management stuff into electronics. This is like removing the batteries from you walkman ;-) For year, the internet was thought of the next generation businessplace (with all the ugly internet-hype stuff). But the BIG breakthrough did not happen. Sure, there are no MANY which can be bought via internet, but this is only a fraction of the announced volume. So one big question is, how do measure the work of individuals and in turn how much is this worth (=money)? Or are we facing a big change in the business structure? Will the vision of StarTrek come true, the the economics of the future is no more based on money, to aquire welth. Is our future the seach for ourself, to better ourself, to boldly go, where no one has gone before? Hmmm, we will see. Is getting interesting . . . . . . . -- MfG Falk P.S. Also in StarTrek, there are a lot of problems in the future. The Kardassians, the Ferengi, malfunctioning warp cores. So engineers, dont worry, the future needs us ;-)Article: 45880
Just think of a reloc package as part of the total offered compensation. When the market is down, your offered compensation will be too. What if they offered a $20k sign on bonus but no reloc, would that make a difference what they called it? As far as discrimination, what about the guy that already lives in the area so doesn't get offered that perk, is that fair? Just throw all the dollars in a pot and see which one has more in it taking into account the well put points mentioned by the previous poster about personal conviction, happiness, and balance in life and work. My advice, waive reloc, take the phone interview, see what they offer, and if you can't reach an agreement you're both happy with, do something else with your time and energy. Everybody wins. Regards jamesb7us@yahoo.com (James Bonanno) wrote in message news:<3869c28a.0208072200.5d89e153@posting.google.com>... > I am here in SoCal where I have relocated over one year ago and am in > a very FPGA centric job with dedicated hw signal processing for > control > system applications. It's a cutting edge field with regards to digital > controls, and I was seduced by all of the glitz and glamour. I > relocated > from the midwest. The relo package was good. However, I would offer > that > not having a relo package as a potential positive in the sense that > you aren't bound to the company, which is often the case in terms of > a relo package (1-2 years). I think Xilinx is great, we are using > their chips, but you never know until you are there. I know that the > relo decision is factored on many criteria. But going from a house to > an Apartment and the fact that the housing out here (in SoCal) is at > the top of huge bubble makes me regard my change in living status > as a downgrade. The deriviative is the measure > of rate of change; and I can tell you the housing price derivative is > quite high. There is a distinct difference in the middle class out > here > in Cali, so my words of wisdom are this: Even if they are a great > company, > you still have to live your life, and it's a one way ticket. Inner > convictions and happiness are in the long run dominant over a company > name and any experience, but hey, that's my opinion. If I were in my > (your) position and knew what I know now, I would demand a relo > package with no strings attached. Be bold. After all, I don't care > what any headhunter or industry pundit or human resources person > utters out of their mouth, there are only so many good engineers. If > you are confident in your abilities, and believe in delivering the > best, then ask for the best. Good luck in your > decision. > > > spam_hater_7@email.com (Spam Hater) wrote in message news:<3d4ff8e2.5456646@64.164.98.7>... > > It's the "Law of Supply and Demand". The current supply of FPGA > > experts exceeds the demand in the Silicon Valley. (Ask me how I > > know...) > > > > You are "geographically undesireable". Sorry, it's not any form of > > discrimination. > > > > > > On 6 Aug 2002 04:35:51 -0700, johnjakson@earthlink.net (John Jakson) > > wrote: > > > > >I saw that Xilinx was hiring for VLSI guys with some substantial > > >experience, not just Verilog coders, but transistor level, HSpice, > > >layout, the works etc. > > > > > >I just happen to fit the bill and being an FPGA nut as well, but I am > > >out of state & MA based. > > > > > >As I was just about to expect a pre screen call, I was told that I > > >would not be interviewed unless I waived the benefit of a relocation > > >package as the budget is really tight. Of course I was working with a > > >head hunter so it must be even more really tight. > > > > > >I was somewhat dumbstruck, flabbergasted, and somewhat pissed off. > > > > > >This would seem to be a blatant form of either age or distance related > > >discrimination as I believe that many older engineers will have left > > >the valley. But Si valley is where the action is as any job search > > >will show so I was willing to go back even if the cost of living was > > >much much higher than MA, and salary likely much lower and now > > >apparently I have to buy the job. > > > > > >Is this true Peter, Austin, is it common that relocation is gone in > > >the valley. > > > > > >I am sure that Peter didn't just walk from Denmark? to SJ to start > > >work for what I thought was a remarkable company. > > > > > >John JaksonArticle: 45881
Thanks a lot guys. I think my question has been answered. I guess giving away the bit stream is not a good idea. And for that matter even a device with the program can be broken into. So keep my code to myself. Thanks, Prashant Kevin Brace <killspam4kevinbraceusenet@killspam4hotmail.com> wrote in message news:<ais3ag$38u$1@newsreader.mailgate.org>... > Prashant wrote: > > > > Hi, > > > > I would like to give someone the programming bits for an FPGA for my > > design. Is there anyway the programming bits could be used to reverse > > engineer to my design ? What is the safest way to let someone use your > > design without them being able to figure out your FPGA design ? > > > > Thanks, > > Prashant > > > If what you are trying to do is to safe guard your design, then > giving someone the FPGA bit stream image of your design sounds risky to > me because that person can make unlimited copies of it. > However, I believe it will be pretty tough to figure out what you are > doing on in your design, since that user will be getting very low level > device information (a bit stream file), and FPGA device vendors, in > general, don't make the internal bit stream fuse map information public. > So, as long as you don't mind that the person getting it can make > unlimited copies of it, you shouldn't have to worry too much about your > design being modified. > A little off topic, but it is not impossible to figure out the > internal bit stream fuse map, as long as that person or company is very > wealthy, because a company called Clear Logic (http://www.clear-logic) > did figure out Altera's MAX CPLD and FLEX10K internal bit stream fuse > map information, and cloned them. > However, a few weeks ago there was a preliminary injunction against > Clear Logic barring them from using Altera's bit stream image within > Clear Logic devices because the Altera software licensing clause (The > legal stuff you see when you install MAX+PLUS II or Quartus II.) says > that Altera software can be used solely for Altera devices only. > If you are so concerned about your design, perhaps you may want > to consider using OTP (One Time Programmable) antifuse FPGAs from Actel > or Quicklogic, or flash-based FPGAs from Actel. > As long as you program the chip, and give it to someone (I know that's > the case.), it should be reasonably safe against someone else figuring > out the design inside. > > > > Kevin Brace (In general, don't respond to me directly, and respond > within the newsgroup.)Article: 45882
Jay (kayrock66@yahoo.com) wrote: : This isn't a technical issue but probably effects the readers of this : newsgroup more that 101st tool bug he's trying to solve at work. It : concerns Opencores and the license under which the cores are offered : for use. : While I'm a big "information needs to be free" kind of guy, it seems : kind of strange to me that the primary contributers are individuals, : and the main beneficiaries (financially) are business entities. : Aren't these kinds of projects usually handled under a "use limited to : not for profit" arrangement? Kind of like shareware WS-FTP, if you're : using it at school go ahead, but if you're making money using it, you : shell out your $30. Otherwise all that we've accomplished is reducing : corporate NRE at engineers' expense. : I suppose you might argue that this in turn reduces the cost of : consumer electronics goods for the whole world, but still, why on my : ticket? Put another way, why should Motorola (for example) be able to : my XYZ core back to me in the form of a cell phone ASIC? : What do you think? I am an asic designer for a large company and also keep tabs on the opencores movement. There is very little free stuff that is ready to drop into a production asic and ship. In most cases the designers have done the 20% of the work that produces 80% of the results. It works but you would still need to fully document it and do a COMPLETE test suite and provide support. When we buy IP we do so so primarily so we won't have to do all that. The biggest advantage to contributing to opensource is if you can parlay that into some consulting or other work. Having a few opencores projects on your resume can be very rewarding. John EatonArticle: 45883
"Jason Berringer" <jberringer@trace-logic.com> schrieb im Newsbeitrag news:Ruj29.2469$9g7.527520@news20.bellglobal.com... > Hello FPGA and VHDL experts, > > I require a little assistance. I have done some searches and read through a > few texts to see if the topic is covered and can't find the information that > I'm looking for. I have two counter banks which are counting away. At 1 kHz > I take the counts in both of the banks, generate an interrupt and pass off > the values to a CPU where the floating point division of the counts BANK A > divided by BANK B occurs along with some fancy DSP filtering. I use an ISA > interface for the data transfer. What I'm looking to do is move the division > inside of the FPGA. Can anyone point out a couple of examples so I can learn > how to do this. I'm looking for floating point division with at least 5 > digits of precision in my result. Then I can perform some fancy DSP > filtering inside of the FPGA. > Note, the counter banks are 24 bits each. > > Questions: > > 1. Can this be done as a VHDL module or do I have to embed a CPU type core > for the division? A small statemachine can control the divider. The divider is build with an adder/subtractor, a shifter and some registers. > 2. Does anyone know of an app note that might cover, and provide a small > example of this type of VHDl code? The reference shown is not VHDL, it is just an explanation of how division can be performed with a fair amount of logic. http://www.e-insite.net/ednmag/archives/1997/050897/10df_05.htm#Figure%203 Best Regards HelmutArticle: 45884
Hi, I want to learn more about IC layout. Any resource in the internet? Thank you. RealaArticle: 45885
Use LOGIBLOX, search it in the menu and check CONSTANT. Narcís NadalArticle: 45886
Krishna, I have written a Rijndael encryption/decryption core which supports VirtexE parts. The core can operate in pipelined and semi-pipelined modes, (giving different performance/area gains). The pipelined version can give a throughput of over 6 GBits/sec on a VirtexE-6, and the semi-pipelined version runs at 776 MBits/sec but is a fraction of the size. The core comes with wrappers to help integrate it into your design. If you need any more info, give me a shout. best regards Andrew Dunlop Design Engineer Celoxica Ltd. andrew.dunlop@celoxica.com www.celoxica.com "kkps" <kkps@rapid5.com> wrote in message news:c6efc5c9.0208050742.187cb4de@posting.google.com... > Hi all, > > I need to choose an AES (rijndael) IP core to use in Xilinx VirtexE. > There is a wide perplexing selection of core providers on the > internet. Does anybody have any recommendation regarding who is the > best (performance & cost)? > > Also, I would highly appreciate it if anybody who has used an AES core > from some core provider can share their experience on: > > 1. Did it work? > 2. Was it easy to use? > 3. How was the technical support? > 4. Do you recommend it? > > Any information will be highly appreciated, > KrishnaArticle: 45887
Hi, I'm using WebPack4.2 and I already developed some VHDL codes without any problem. Now I want to implement and simulate a VHDL block using Block RAM (virtex-E 300). The synthesis phase seems to be good but the simulation (with modelsim) in order to verify the content of the RAM don't work and signal output when I try to read RAM always return 'U' although RAM is initialized before. Could someone give me a solution to resolve this problem ? thanks in advance for your help! Regards PhilippeArticle: 45888
Does anyone here have any speed info on Xilinx CoreGen FIFOs in a real design? I have a client company that wants me to do a design where I will have to synchronize data across clock boundaries. 32w x16d FIFOs are the natural link, but the fastest clock is 170 MHz. Spartan-IIes are the chip of choice. I can register signals at IOBs to minimize the time to the FIFOs. Thanks. Simon Ramirez, Consultant Synchronous Design, Inc. Oviedo, FL USAArticle: 45889
--------------060801010800020204070405 Content-Type: text/plain; charset=us-ascii; format=flowed Content-Transfer-Encoding: 7bit Andrew, Is it correct to say that those throughputs are for ECB/Counter modes? Do you have anything that runs in CFB or the newest AES mode of operation? Adam Andrew wrote: >Krishna, > >I have written a Rijndael encryption/decryption core which supports VirtexE >parts. The core can operate in pipelined and semi-pipelined modes, (giving >different performance/area gains). The pipelined version can give a >throughput of over 6 GBits/sec on a VirtexE-6, and the semi-pipelined >version runs at 776 MBits/sec but is a fraction of the size. The core comes >with wrappers to help integrate it into your design. > >If you need any more info, give me a shout. > >best regards >Andrew Dunlop >Design Engineer >Celoxica Ltd. >andrew.dunlop@celoxica.com >www.celoxica.com > > >"kkps" <kkps@rapid5.com> wrote in message >news:c6efc5c9.0208050742.187cb4de@posting.google.com... > >>Hi all, >> >>I need to choose an AES (rijndael) IP core to use in Xilinx VirtexE. >>There is a wide perplexing selection of core providers on the >>internet. Does anybody have any recommendation regarding who is the >>best (performance & cost)? >> >>Also, I would highly appreciate it if anybody who has used an AES core >>from some core provider can share their experience on: >> >>1. Did it work? >>2. Was it easy to use? >>3. How was the technical support? >>4. Do you recommend it? >> >>Any information will be highly appreciated, >>Krishna >> > >Article: 45890
Paul, If you are part of a University program, please contact the Xilinx University support folks at: http://www.xilinx.com/univ/index.htm Austin Paul Smith wrote: > Anyone actually managed to get one of these yet? Doesn't show up > at findchips.comArticle: 45891
Hi, You can refer to "Computer Arithmetic Algorithms" by Israel Koren. It gives some very good division algorithms. Prashant "Jason Berringer" <jberringer@trace-logic.com> wrote in message news:<Ruj29.2469$9g7.527520@news20.bellglobal.com>... > Hello FPGA and VHDL experts, > > I require a little assistance. I have done some searches and read through a > few texts to see if the topic is covered and can't find the information that > I'm looking for. I have two counter banks which are counting away. At 1 kHz > I take the counts in both of the banks, generate an interrupt and pass off > the values to a CPU where the floating point division of the counts BANK A > divided by BANK B occurs along with some fancy DSP filtering. I use an ISA > interface for the data transfer. What I'm looking to do is move the division > inside of the FPGA. Can anyone point out a couple of examples so I can learn > how to do this. I'm looking for floating point division with at least 5 > digits of precision in my result. Then I can perform some fancy DSP > filtering inside of the FPGA. > Note, the counter banks are 24 bits each. > > Questions: > > 1. Can this be done as a VHDL module or do I have to embed a CPU type core > for the division? > 2. Does anyone know of an app note that might cover, and provide a small > example of this type of VHDl code? > 3. Am I crazy to try this (ie should I just let the CPU do the work)? > > If my question seems rather niave I appologize, I've only been working with > VHDL and FPGAs for about a year so my knowledge is somewhat limited (so go > easy with the shots please!). Any help is greatly appreciated. > > Thanks > > Jason BerringerArticle: 45892
Does anyone have information about 80386 compatible IP core which can be used on FPGA? Are there any problem, if I implement a subset of ia32 and distribute it? Should I concerned about patent, royalty, license or anything else? Anyone, please tell me. Thanks in advance.Article: 45893
Mike Rosing <rosing@neurophys.wisc.edu> wrote in news:3D4DCEF8.50006@neurophys.wisc.edu: > I'm having a problem understanding how to use primitives with > Web pack (or Foundation, doesn't matter). I'm sure it's a > generic VHDL question, and it's obvious to everyone here. > -snip- > > architecture storage of bit_matrix16x16 is > > component RAM16X1S > > begin > > matrix: process (wclk) is > > begin > > -- Distributed SelectRAM Instantiation > column15: RAM16X1S > port map ( > I think it's a copy/paste artefact, but is your component instantiated inside the 'matrix' process? I don't think it's a legal in vhdl, and is probably misinterpreted by ths synthetizer. hth SylvainArticle: 45894
Hi there! I am involved with a project regarding bluetooth protocol stack and I want to move protocols of this stack to hardware (FPGA or even mController) -till now I only have some very very complicated implementations in C++. I am looking for references for such a task since I have little experience on the subject yet (how to transfer a protocol layer effectively in vhdl for instance). I also don't seem to find very explanatory details of the interface provided by the bluetooth stack so as to interconnect it correctly with hardware. If you have any knowledge of such hardware, sample codes or references please please tell me! HW rulez! :-)Article: 45895
> Yes, that's where I'm trying to put it. I guess that's not allowed? > So I need to declare the entities outside the process, and in this > case I'm just creating a storage object, so there's no process to > really do. I'll try that, thanks!! > > Patience, persistence, truth, > Dr. mike > I often refer to this page, when I have a doubt about vhdl constructs http://www.ami.bolton.ac.uk/courseware/adveda/vhdl/vhdlbnf.html S.-Article: 45896
In article <d049f91b.0208081028.309454bd@posting.google.com>, kayrock66@yahoo.com says... > I suppose you might argue that this in turn reduces the cost of > consumer electronics goods for the whole world, but still, why on my > ticket? Put another way, why should Motorola (for example) be able to > my XYZ core back to me in the form of a cell phone ASIC? > > What do you think? I could be wrong but I doubt companies are really putting these cores into products. -- Rich Iachetta iachetta@us.ibm.com I do not speak for IBM.Article: 45897
A good pointer would be http://www.research.compaq.com/wrl/projects/magic/magic.html Magic is a free layout tool. -Vikash "Reala" <manfield.chow@scoreconcept.com> wrote in message news:aiv69a$gcp5@imsp212.netvigator.com... > Hi, > > I want to learn more about IC layout. > Any resource in the internet? > Thank you. > > Reala > >Article: 45898
The Reuse Methodology Manual (RMM), Third Edition is a MUST have book for anyone involved in the requirements/design/verification/methodologies of chips. Even though the title seems to emphasize "reuse", this book is much more than because it emphasizes best design definition and practices for systems using ASICs and FPGAs. This edition addresses changes in the methodologies as a result of technology and experience in the design methodologies. Thus it re-address topics covered in the second edition, but with additional guidelines and intuitions (see url below for TOC). I strongly recommend this edition because it provides very useful guidelines and points to consider in the design definition and verification processes using Verilog and VHDL. Methodologies and guidelines are fickle issues because they reflect style. I have minor issues that the authors may address in a supplement, or in the next edition: 1. Pg 97: RMM recommends using IEEE standard types. This is great! However, the RMM should also recommend the use of IEEE standard packages, including the Numeric_Std package. Instead, it provides as an example the use of ieee.std_logic_arith package, which is a Synopsys package, not approved by IEEE. 2. Pg. 98: RMM recommends the use of `define to specify constant values. Instead, I prefer Cliff Cummings' recommendation to use parameters instead because `define macros are global macro definitions, and are poor style. Parameters are local to each module and can be redefined at module instantiation. In fact, the whole concept of parameterization is keyed to reusability. 3. Pg. 59: RMM recommends port ordering of clocks, resets, enables, control, data and address lines. This is a minor point, but I like Cliff's recommendation of the port ordering defined in the Verilog LRM for primitives. Specifically: outputs, inputs, controls, clock. Reuse Methodology Manual for System-on-a-Chip Designs Third Edition, Hardbound, ISBN 1-4020-7141-8, June 2002, 330 pp. edited by Michael Keating Synopsys, Inc., Mountain View, CA, USA Pierre Bricaud Synopsys, Inc, CA, USA http://www.wkap.nl/book.htm/1-4020-7141-8 p.s. My "Component Design by Example" book demonstrates by example how tro write a requirement/architectural/verification specs, which are in line with the RMM. ---------------------------------------------------------------------------- Ben Cohen Publisher, Trainer, Consultant (310) 721-4830 http://www.vhdlcohen.com/ vhdlcohen@aol.com Author of following textbooks: * Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 0-9705394-2-8 * Component Design by Example ", 2001 isbn 0-9705394-0-1 * VHDL Coding Styles and Methodologies, 2nd Edition, 1999 isbn 0-7923-8474-1 * VHDL Answers to Frequently Asked Questions, 2nd Edition, isbn 0-7923-8115 ------------------------------------------------------------------------------Article: 45899
Hello, I am working with an existing design that uses an EPC2 device to configure a Flex 6024 FPGA. The logic was done using MaxPlus, even though Altera no longer supports the use of an EPC2 with Flex 6000 devices -- MaxPlus could be tricked into using an EPC2 with a 6000 by editing the .acf file. Now, we are trying to switch to Quartus, but it seems more strict. It won't allow you to choose the EPC2 device for a Flex 6000 target, and when I edit the .csf file to try and trick it into using an EPC2, the compiler gives an error. So, does anyone know of a way to use an EPC2 configuration device with a Flex 6000-series FPGA while using Quartus? Thanks, Mike Neufeld
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