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Rick Filipkiewicz <rick@algor.co.uk> wrote: > Esp. in view of Ray Andraka's comments that in the change from 4.1i -> > 4.2i the routing has got worse for a given placement. I think this is true > of 3.xi->4.1i as well. Hmmm... we found that 4.1 was bad for some Virtex-E designs but 4.2 was quite reasonable. Hamish -- Hamish Moffatt VK3SB <hamish@debian.org> <hamish@cloud.net.au>Article: 46301
I believe FPGA can work as an I2C device. However, you might have to implement the I2C interface on FPGA by yourself. I remember somebody also posted message looking for I2C core here. Jianyong Niu -- "SUDIP SAHA" <sudip.saha@philips.com> wrote in message news:ee7893c.-1@WebX.sUN8CHnE... > Hi all, > Do you know whether any FPGA/CPLD supports I2C bus configuration or not? Means Can I connect any I2C device like a microcontroller to the FPGA via I2C bus and The FPGA will act as a master/slave I2C device? > Sudip Saha > sudip.saha@philips.comArticle: 46302
"BasePointer" <mfide@softhome.net> schrieb im Newsbeitrag news:ee78937.-1@WebX.sUN8CHnE... > Hi > > How can I connect XTAL to XCS10XL by using minimum external component ? Is there any sample available for this ? Not reliable. Use an external oscillator. -- MfG FalkArticle: 46303
There is no really reliable way of doing this. You can buy a canned oscillator for almost the same prices as a crystal (<$1.00) and that saves you a lot of trouble with the oscillator not starting reliably ( e.g. as a function of Vcc rise time or temperature) or oscillating on a harmonic frequancy. FPGAs ar excellent digital circuits, they do not function so well a analog high-frquecy amplifiers. Peter Alfke, Xilinx Applications BasePointer wrote: > Hi > > How can I connect XTAL to XCS10XL by using minimum external component ? Is there any sample available for this ? > > ThanksArticle: 46304
Hi!
I have some basic thoughts about floorplanning, that I was hoping you
might shed some light upon.
I have learnt all I know about floorplanning by fiddling with the
floorplanner(Xilinx) myself, I haven't attended any courses. To gain some
real life experience points as well, I'm using one of our designs(from a
Spartan 40 XL).
The first part is easy, the goal is - well, in a simplified way - to pack
clb:s, etc. that belong to the same part of the design close together in an
optimized way, right? When you get advanced, there are probably exceptions
to this, it might be better to optimize the interblock flow instead of the
intrablock one, etc. Each design is unique. But that's then ;).
With this "optimize-block-giving-them-a-nice-shape(square?)" approach it's
easier to place blocks that talk to eachother as close as possible. But:
* Doing this for a complete fpga takes time! I know that now, at least ;).
* I instantiate some blocks several times. And I haven't found a way to
copy
the "pattern" from an optimized instance to an unoptimized one. So I
thought
about RLOC's. I have seen them mentioned in this group before, though
I'm
still not sure what they do. Do they set the relative locations of
clb:s,
etc. within a submodule(verilog ;)) so that p&r knows how to put them.
(Using the .ucf file?)
If so, how do I extract the RLOC:s from the floorplanner? I know I can
save them to a .ucf file, but I think this saves RLOC's for the whole
design! One could perhaps remove the unwanted one using a texteditor,
but
is this a foolproof way? Can you see which signal/block a rloc is
attached
to when you read the line in the .ucf? No "module1_notri.clbxxx.t" style
stuff?
Or can I mark one submodule in the floorplanner and tell it to save
the
rloc:s for this block only? The more I think about it this sounds like a
Xilinx support question. You don't have to answer this.
I'd like to know more about if I should place things
horizontally/vertically, etc. Maybe it's basically about learning the
structure of the chip you're working on, i.e. read the *** manual so to
speak :)? Are there any floorplanning tutorials out there? If possible with
some example(s) for a real tool, not just the general theory. I tried to
find a faq or so for this group, as I think these questions aren't that new,
but I didn't find anything. So I ask them here, hope this is ok and thank
you for reading this.
/Regards, Big Swede
Article: 46305I have a design where either an oscillator can be supplied externally on an IOB input or I can generate it internally. Today I am struggling a bit with the question of how to sense whether the external oscillator is connected and if it is not, then to run some logic circuitry off the internal oscillator. Currently, I am thinking that counting some number of oscillator cycles from both inputs with an always statement (in Verilog) and setting a terminal count of say 10000 cycles for the external and 100,000 cycles for the internal. They are both the same frequency. If the external doesnt reach terminal count before the internal one does, then I would run the logic circuitry off the internal oscillator. The only reason the external one would not reach terminal count first would be if it is not active. So, the question for Sunday is, "Is this a reasonable way to sense an external/internal oscillator or is there a better way?" -- Charles Krinke http://home.pacbell.net/cfk cfk@pacbell.netArticle: 46306
For stuff that is auto-placed, 4.2 does a reasonable job, and frankly I think it
does the placement better than 3.3 did. For a highly floorplanned design, the
router in 3.3 does a significantly better job when timing is tight than 4.2
does, although it also takes a little bit longer.
hamish@cloud.net.au wrote:
> Rick Filipkiewicz <rick@algor.co.uk> wrote:
> > Esp. in view of Ray Andraka's comments that in the change from 4.1i ->
> > 4.2i the routing has got worse for a given placement. I think this is true
> > of 3.xi->4.1i as well.
>
> Hmmm... we found that 4.1 was bad for some Virtex-E designs but
> 4.2 was quite reasonable.
>
> Hamish
> --
> Hamish Moffatt VK3SB <hamish@debian.org> <hamish@cloud.net.au>
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 46307
The FPGA is electrically fine for an I2C connection. You'll have to design a circuit to go in it in order to implement the controller though. That isn't a terribly hard design to do. This applies to the FPGA
AFTER it is configured. None of the configuration interfaces I am aware of are I2C, although a little bit of clever work with a CPLD will get you that.
SUDIP SAHA wrote:
> Hi all,
> Do you know whether any FPGA/CPLD supports I2C bus configuration or not? Means Can I connect any I2C device like a microcontroller to the FPGA via I2C bus and The FPGA will act as a master/slave I2C device?
> Sudip Saha
> sudip.saha@philips.com
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 46308
As far as I know, there isn't much out there as far as tutorials for
floorplanning. Much of floorplanning is more of an art than a science... it is
sort of like a jig saw puzzle with many possible solutions. Playing with it is
the best way to learn it.
The floorplanner can output to a UCF, but that is not RLOCs, rather it is LOCs
on the flattened design. All the instances are placed in specific CLBs rather
than relative to one another. To work with RLOCs, you need to add them to your
source. The floorplanner can be a valuable tool in helping to assign those
RLOCs as well as for verifying your work, but it can't directly assign them.
Floorplanning does take time, however you can cut that time down considerably by
putting RLOCs in your pieces of code that you will be reusing. For example,
we've invested a fair amount of time in creating placed VHDL components for
stuff we use lots of like several flavors of adders, D registers, delay queues,
multipliers and filter sections. Since these components are made to have
parameterized attributes for width, reset value, signed or unsigned etc, we get
an opportunity to use the very often so the floorplanning effort spent at the
beginning continues to reap rewards. When we use thes components in a design,
we can then RLOC them together to form bigger placed macros, so that when we get
to the floorplanner lots of the detail work is already taken care of. At that
point it is mostly a matter of putting in the big pieces and then adjusting the
layout to minimize the routes.
If that is too much effort for you, you can sometimes use the floorplanner
capture pattern and impose pattern if you are dealing with identical groups of
components to replicate a pattern. Sort your component list before you start
though.
As far as the best way to layout the blocks, you are correct you need to learn
the structure of the device. Carry chains enforce a particular orientation, so
if you have lots of them in your design it will more or less constrain the
orientation of your data flow horizontally and controls vertically.
Big Swede wrote:
> Hi!
> I have some basic thoughts about floorplanning, that I was hoping you
> might shed some light upon.
> I have learnt all I know about floorplanning by fiddling with the
> floorplanner(Xilinx) myself, I haven't attended any courses. To gain some
> real life experience points as well, I'm using one of our designs(from a
> Spartan 40 XL).
> The first part is easy, the goal is - well, in a simplified way - to pack
> clb:s, etc. that belong to the same part of the design close together in an
> optimized way, right? When you get advanced, there are probably exceptions
> to this, it might be better to optimize the interblock flow instead of the
> intrablock one, etc. Each design is unique. But that's then ;).
> With this "optimize-block-giving-them-a-nice-shape(square?)" approach it's
> easier to place blocks that talk to eachother as close as possible. But:
> * Doing this for a complete fpga takes time! I know that now, at least ;).
> * I instantiate some blocks several times. And I haven't found a way to
> copy
> the "pattern" from an optimized instance to an unoptimized one. So I
> thought
> about RLOC's. I have seen them mentioned in this group before, though
> I'm
> still not sure what they do. Do they set the relative locations of
> clb:s,
> etc. within a submodule(verilog ;)) so that p&r knows how to put them.
> (Using the .ucf file?)
> If so, how do I extract the RLOC:s from the floorplanner? I know I can
> save them to a .ucf file, but I think this saves RLOC's for the whole
> design! One could perhaps remove the unwanted one using a texteditor,
> but
> is this a foolproof way? Can you see which signal/block a rloc is
> attached
> to when you read the line in the .ucf? No "module1_notri.clbxxx.t" style
> stuff?
> Or can I mark one submodule in the floorplanner and tell it to save
> the
> rloc:s for this block only? The more I think about it this sounds like a
> Xilinx support question. You don't have to answer this.
>
> I'd like to know more about if I should place things
> horizontally/vertically, etc. Maybe it's basically about learning the
> structure of the chip you're working on, i.e. read the *** manual so to
> speak :)? Are there any floorplanning tutorials out there? If possible with
> some example(s) for a real tool, not just the general theory. I tried to
> find a faq or so for this group, as I think these questions aren't that new,
> but I didn't find anything. So I ask them here, hope this is ok and thank
> you for reading this.
> /Regards, Big Swede
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 46309On Sun, 25 Aug 2002 17:41:22 +0200, "Big Swede" <tstabo@passagen.killthispart.se> wrote: >Hi! > I have some basic thoughts about floorplanning, that I was hoping you >might shed some light upon. > > etc .... > >/Regards, Big Swede Maybe the following will help you: http://www.fliptronics.com/floorplanning1.html Philip Philip Freidin FliptronicsArticle: 46310
If this is the problem you want to solve, go ahead. But why thousands of clock cycles? I would count to 16. Peter Alfke, Xilinx Applications cfk wrote: > I have a design where either an oscillator can be supplied externally on an > IOB input or I can generate it internally. Today I am struggling a bit with > the question of how to sense whether the external oscillator is connected > and if it is not, then to run some logic circuitry off the internal > oscillator. > > Currently, I am thinking that counting some number of oscillator cycles from > both inputs with an always statement (in Verilog) and setting a terminal > count of say 10000 cycles for the external and 100,000 cycles for the > internal. They are both the same frequency. If the external doesnt reach > terminal count before the internal one does, then I would run the logic > circuitry off the internal oscillator. The only reason the external one > would not reach terminal count first would be if it is not active. > > So, the question for Sunday is, "Is this a reasonable way to sense an > external/internal oscillator or is there a better way?" > > -- > Charles Krinke > http://home.pacbell.net/cfk > cfk@pacbell.netArticle: 46311
Hi all, I had to make a 32 states and 20 I/Os FSM recently in ABEL, Foundation 2.1I for an spartan xcs05 and I realize the number of CLBs is strongly dependent on the state codification. That is if I numbered the states as 0,1,2,3...31 the resulting numer of CLBs is different than when I change the order. In the other hand I suspect there are parts of that FSM that were better optimized in one hot and others not, and due the speed is not critical I also suspect there is a lot of room for area optimisation. Is there any tool to optimize FSMs across huffman encoding to minimize CLBs? or other method less optimum? Thanks Narcís NadalArticle: 46312
hello I remember i have read once that even for a complez design >70 Mhz is expected with Virtex-E, is there any similar figure for Virtex 2?Article: 46313
This seems reasonable, however I agree that you only need to delay a short
enough time to detect the external clock and large values like 100000 is a
waste of internal registers and logic. I'm curious how you change clocks on
the fly in the FPGA. I assume that all your 'other' logic is held in a
'reset' or known state until the decision is made and a logic combination is
applied to a global clock driver. Could you elaborate?
Steve
Peter Alfke <palfke@earthlink.net> wrote in message
news:3D694B51.98200113@earthlink.net...
> If this is the problem you want to solve, go ahead.
> But why thousands of clock cycles? I would count to 16.
> Peter Alfke, Xilinx Applications
>
> cfk wrote:
>
> > I have a design where either an oscillator can be supplied externally on
an
> > IOB input or I can generate it internally. Today I am struggling a bit
with
> > the question of how to sense whether the external oscillator is
connected
> > and if it is not, then to run some logic circuitry off the internal
> > oscillator.
> >
> > Currently, I am thinking that counting some number of oscillator cycles
from
> > both inputs with an always statement (in Verilog) and setting a terminal
> > count of say 10000 cycles for the external and 100,000 cycles for the
> > internal. They are both the same frequency. If the external doesnt reach
> > terminal count before the internal one does, then I would run the logic
> > circuitry off the internal oscillator. The only reason the external one
> > would not reach terminal count first would be if it is not active.
> >
> > So, the question for Sunday is, "Is this a reasonable way to sense an
> > external/internal oscillator or is there a better way?"
> >
> > --
> > Charles Krinke
> > http://home.pacbell.net/cfk
> > cfk@pacbell.net
>
Article: 46314
Depends on the design. We've more or less routinely run virtexE-6's at
160 Mhz with dense arithmetic designs, but that does require some
patience in the design and floorplanning. For the same designs, we've
found the virtexII-4 to be slightly slower than the virtexE because there
is a huge penalty in getting on and off the carry chains in VirtexII.
For a non-arithmetic design, VirtexII is noticibly faster. >70 MHz can
be achieved readily even with the slowest grade original Virtex and
SpartanII's.
hristo wrote:
> hello
>
> I remember i have read once that even for a complez design >70 Mhz is
> expected with Virtex-E, is there any similar figure for Virtex 2?
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 46315Yes, holding the logic clocked by this external IOB in reset was the plan. Certainly, I can count to a lower number. I was just asking if using a counter that counts to any number seems like a reasonable way to determine if a clock is connected or not. I have to admit that I did not think the implications of the number of flip-flops involved in counting to 100,000 would be while I was trying to come up with the idea to tell the difference between an external clock that is not connected and how I run the logic off an internal clock if that is so. And again, this is only a portion of the logic in the FPGA, so the portion that runs the always statement and does the decision is running from a clock that is on from reset. "steve bessette" <sbessette@stny.rr.com> wrote in message news:GGea9.129481$vg.21964965@twister.nyroc.rr.com... > This seems reasonable, however I agree that you only need to delay a short > enough time to detect the external clock and large values like 100000 is a > waste of internal registers and logic. I'm curious how you change clocks on > the fly in the FPGA. I assume that all your 'other' logic is held in a > 'reset' or known state until the decision is made and a logic combination is > applied to a global clock driver. Could you elaborate? > > Steve > > > > Peter Alfke <palfke@earthlink.net> wrote in message > news:3D694B51.98200113@earthlink.net... > > If this is the problem you want to solve, go ahead. > > But why thousands of clock cycles? I would count to 16. > > Peter Alfke, Xilinx Applications > > > > cfk wrote: > > > > > I have a design where either an oscillator can be supplied externally on > an > > > IOB input or I can generate it internally. Today I am struggling a bit > with > > > the question of how to sense whether the external oscillator is > connected > > > and if it is not, then to run some logic circuitry off the internal > > > oscillator. > > > > > > Currently, I am thinking that counting some number of oscillator cycles > from > > > both inputs with an always statement (in Verilog) and setting a terminal > > > count of say 10000 cycles for the external and 100,000 cycles for the > > > internal. They are both the same frequency. If the external doesnt reach > > > terminal count before the internal one does, then I would run the logic > > > circuitry off the internal oscillator. The only reason the external one > > > would not reach terminal count first would be if it is not active. > > > > > > So, the question for Sunday is, "Is this a reasonable way to sense an > > > external/internal oscillator or is there a better way?" > > > > > > -- > > > Charles Krinke > > > http://home.pacbell.net/cfk > > > cfk@pacbell.net > > > >Article: 46316
Kenneth wrote: > Dear All, > > Currently I have a design which is quite simple and am planning to > implement it in a CPLD. However, the target operating speed is > around 300MHz. > > After searching, I found that some CPLDs from Xilinx and Lattice > are claimed to be able to operate at more than 300MHz. However, > it seems that there is no PLL/DLL inside their CPLDs. So how can > they operate at this high frequency? Does it mean that I need to > input a 300MHz clock signal into CPLD directly? If so, i think it > may cuase some problems in the PCB design, and i will change the > design avoiding this to be happened. If you go thru only a few gates you can go in and out that fast. If you want things to happen at 300 MHz continously, you'll need an external clock that runs that fast. > Please advise, thanks in advance. put a clock right next to the cpld? external pll's might do the trick. Good luck! Patience, persistence, truth, Dr. mike -- Mike Rosing www.beastrider.com BeastRider, LLC SHARC debug toolsArticle: 46317
In pre-Virtex families of Xilinx, speed grades used to be exact CLB delays, which obviously meant a -3 would be faster than -4 (which also meant 4ns CLB delay). Later, due to process migrations, even the XC4000 family started having CLB delays as low of 0.9ns, wherein the speed grade used to be -09, -08 and so on. (I remember an XC4085XLA-08). Starting Virtex, this was reversed, and speed grades became relative. So now, a -4 speed grade does not tell you the exact delay, but tells you that it is slower than a -5 part. For exact delays you need to refer to the datasheet. The new speed nomenclature applies to Virtex, Spartan-II, Virtex-E, Spartan-IIe, Virtex-II and Virtex-II-Pro only. HTH. --Neeraj Daryl <e@eastday.com> wrote in message news:<ak4731$1fdoj1$1@ID-155928.news.dfncis.de>... > Hi all, > A question, what the fpga "speed level" as "...-5" means exactly? > "-5" device runs at more high speed than "-6" speed device or the > opponent? > How about the same speed level devices from different manufacturer? > > Thanks in advance? > > DarylArticle: 46318
Hi Charles, > Currently, I am thinking that counting some number of oscillator cycles from > both inputs with an always statement (in Verilog) and setting a terminal > count of say 10000 cycles for the external and 100,000 cycles for the > internal. They are both the same frequency. If the external doesnt reach > terminal count before the internal one does, then I would run the logic > circuitry off the internal oscillator. The only reason the external one > would not reach terminal count first would be if it is not active. > > So, the question for Sunday is, "Is this a reasonable way to sense an > external/internal oscillator or is there a better way?" Whatever you do (and I think that your method is OK, but counting to 10000 is a bit of overkill - 3 or 4 clock transitions should do just fine), don't forget to use a pull-up or pull-down resistor with the external clock pin. I've had a lot of trouble with floating input pins on a broken connector once - it picked up just enough RF to fake the presence of the pin but in the end only transmitted garbage. Best regards, BenArticle: 46320
doe's anyone has an example for writing "shifter" in vhdl
"shifter" - means takeing a nember with 8 bit and "placing" it into a
32 bit vector , in a place choosen by anther integer , streching the
other bits
example :
input :
data:8 std_logic_vector;
move: integer;
output :
data_out : 32 std_logic_vector;
for input: data = 11110000
move = 0
output : 111111...11110000 ( takes the msb of the input and strach it
all over )
for input: data = 11110000
move = 2
output : 111111...1111000000 ( takes the msb of the input and strach
it all over, add zeros for lsb as move indicates )
for input: data = 01010101
move = 3
output : 000...01010101000 ( takes the msb of the input and strach it
all over, add zeros for lsb as move indicates )
Article: 46321Hi all, I'm trying to debug a digital filter. What I'd like to do is export simulation results from ModelSim to Excel or Matlab or something. Let's say signals a and b are updated at the same time. Exactly when they are updated doesn't really matter. It is happening on a steady clock, though. What I want to do is convert ModelSim's plot looking like a .. 100 X 200 X 300 X 400 b .. 101 X 202 X 303 X 404 to Excel cells a | 100 | 200 | 300 | 400 b | 101 | 202 | 303 | 404 Do you know if this is possible? Regards, BørgeArticle: 46322
The standard Excel import feature allows you to specify the column separater character. Can you just read in the text file and preview results in the Excel import wizard. Failing that have your sim write to file in a format that Excel is happy with. "Børge Strand" <borge.strand.remove.if.not.spamming@sintef.no> wrote in message news:1030352252.324918@halvan.trd.sintef.no... > Hi all, > > I'm trying to debug a digital filter. What I'd like to do is export > simulation results from ModelSim to Excel or Matlab or something. Let's say > signals a and b are updated at the same time. Exactly when they are updated > doesn't really matter. It is happening on a steady clock, though. What I > want to do is convert ModelSim's plot looking like > > a .. 100 X 200 X 300 X 400 > b .. 101 X 202 X 303 X 404 > > to Excel cells > > a | 100 | 200 | 300 | 400 > b | 101 | 202 | 303 | 404 > > Do you know if this is possible? > > Regards, > > Børge > >Article: 46323
Thanks for your responses. Can you advise a component/company for canned oscillator?Article: 46324
I was hoping that there would be a cut/paste solution between graph and excel vector. But that was hoping for a bit too much. Thanks for the tip, I got it working with $monitor in Verilog and cut/paste into a textfile which I then imported. Børge "Paul Baxter" <pauljnospambaxter@hotnospammail.com> wrote in message news:3d69f3ef$0$8511$cc9e4d1f@news.dial.pipex.com... > The standard Excel import feature allows you to specify the column separater > character. Can you just read in the text file and preview results in the > Excel import wizard. > > Failing that have your sim write to file in a format that Excel is happy > with. > > "Børge Strand" <borge.strand.remove.if.not.spamming@sintef.no> wrote in > message news:1030352252.324918@halvan.trd.sintef.no... > > Hi all, > > > > I'm trying to debug a digital filter. What I'd like to do is export > > simulation results from ModelSim to Excel or Matlab or something. Let's > say > > signals a and b are updated at the same time. Exactly when they are > updated > > doesn't really matter. It is happening on a steady clock, though. What I > > want to do is convert ModelSim's plot looking like > > > > a .. 100 X 200 X 300 X 400 > > b .. 101 X 202 X 303 X 404 > > > > to Excel cells > > > > a | 100 | 200 | 300 | 400 > > b | 101 | 202 | 303 | 404 > > > > Do you know if this is possible? > > > > Regards, > > > > Børge > > > > > >
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