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On Wed, 21 Aug 2002 04:58:40 GMT, Ray Andraka <ray@andraka.com> wrote: >I have seen this happen before in non-Xilinx stuff as well. The problem is >the if clk'event and clk='1' (which is what rising_edge(clk) does too), looks >for an event on the clock and a current value of '1', so any transition that >ends in a '1' is going to be interpreted as a clock rising edge by the sim, >and that includes the initial transition from 'U' to '1'. If the delta >delays in your particular model are such that the clock has more delta delays >than the data, you are fine. If not, then you have a problem. It just so >happens that the old BRAM model had an additional delay into the clock >relative to the data inside the model that is no longer there. I don't think >that this is a xilinx bug per se, although it could certainly be eliminated >by putting initial values or on the data path or extra delta delays >(connecting to local clock signal names) inside the model. > >As I said, this is certainly not unique to xilinx, and you are probably >fortunate not to have run into it before. Hi Ray, There is a semantic difference between rising_edge(clk) and (clk'event and clk = '1') Rising_edge(x) returns (x'event and (to_x01(x) = '1') and (to_x01(x'last_value) = '0')) which usually avoids the problem at time 0, although it is still possible to make it fail if the initial values on various signals are set to provide a delta glitch. You have to try pretty hard to make it fail though. I haven't seen this before in my simulations because my clocked processes always use rising_edge() (rather than clk'event and clk='1') and always have an async reset (with higher priority than the clock), and this reset is always active at time zero. As you say, I've been fortunate. I'll have to check all my old test benches now :( If Xilinx are listening: it would be really nice if you could fix the block ram model. Regards, Allan. > > > > > >Allan Herriman wrote: > >> On Mon, 19 Aug 2002 15:35:58 GMT, Patrik Eriksson >> <patrik.eriksson@netinsight.net> wrote: >> >> >When I simulates the following code this warning message is displayed at >> >time 0ns. >> > >> ># ** Warning: Invalid ADDRESS: XXXXXXXXXX. Memory contents will be set >> >to 'X'. >> ># Time: 0 ps Iteration: 3 Instance: /theram >> >> I just found that this feature was recently introduced with the >> unisim_vcomp.vhd that shipped with a recent service pack of 4.2i. >> >> I had a test bench that had been working fine, and I recently >> recompiled my copy of unisim_vcomp (using the SP3 source) and my >> testbench stopped working :( >> >> I had the clocks starting at '1', and Ray's suggested fix of having >> them start at '0' made the problem go away. (Thanks Ray.) >> >> This points to a bug in the unisim library. I feel that the rambx >> components should not see an initial clock of '1' as a rising edge. >> >> Regards, >> Allan. > >-- >--Ray Andraka, P.E. >President, the Andraka Consulting Group, Inc. >401/884-7930 Fax 401/884-7950 >email ray@andraka.com >http://www.andraka.com > > "They that give up essential liberty to obtain a little > temporary safety deserve neither liberty nor safety." > -Benjamin Franklin, 1759 > >Article: 46176
> > I believe when you buy a chip that has an "interface" that you have to > > interface to, you implicitly have the right to interface to it, period, and > > no additional license is needed. Again, simply MY opinion. > > So you would say that if I buy a chipset from Via that implements the > Intel P4 front side bus interface, and a Foobarco J37 processor that > implements the same bus, that I can build them into my product (with no > Intel P4), and implicitly receive a license from Via and Foobarco to use > the Intel P4 front side bus? <Disclaimer: The following is my understanding of german law, but most of it is pretty much common sense, and should apply elsewhere> If someone sells you a chip and hands you a datasheet that tells you how to use the chip I think that you can safely assume that price of the chip covers the use of all techniques described in the datasheet, as long as you use them in conjunction with the chip. This of course only applies to techniques that the seller of the chip onws. But if the seller does not have the right to license the techniques to you -e.g. because of a license agreement with intel - you can hold him liable for the illegal transaction. The first sale principle should prevent licenses along the lines: "This chip may only be used in conjunction with an intel processor" But there are many local excptions to the first sale principle, so who knows? The above only applies to techniques that are required to use the chip. So you can assume that you licensed the memory bus, but if there is an MP3 application not for the processor you do not own an MP3 license. Kolja SulimmaArticle: 46177
In article <ajb0l6$org$1@news-int.gatech.edu>, Buddy Smith
<nullset@dookie.net> wrote:
> I'm a (soon graduating!) student at Georgia Tech studying computer
> engineering. GT uses altera products for several classes, so I've used
> those plenty....but I've seen very little of how FPGAs are really used in
> industry. Also I've had no experience with non-altera FPGAs because I
> believe my school has some sort of deal with altera.....
>
> Can someone point me to a text, or website that contains information about
> real world applications of FPGAs?
>
> Thanks,
>
> --buddy
From a practical standpoint, no one wants to work harder than they have
to. So, when you graduate, and someone asks you to design something, the
first thing you'll do is reuse other people's designs. If the problem
you are solving can be handled with ASICs from Motorola or IBM or AMCC
etc., you'll throw those on the board, and leave it to your software
team to make it work :-)
However, many ASICs have most of the functionality you want, but the
interface on them is just plain wrong. Some of the designs done
by groups I've worked in, consisted of ASIC --> FPGA --> ASIC --> FPGA
and so on. The FPGA was used as a protocol translator.
So, the simplest use for FPGAs is as "glue" logic.
At one time, if you visited the Texas Instruments web site, you could
find just about any primitive you could ever want. As programmable logic
has advanced, TI and other logic companies have seen their sales of this
discrete logic shrink. Today, you'll find an assortment of bus
buffers/registers, but a lot of the other logic is nowhere to be found.
This is also a place where you will resort to FPGAs or CPLDs, to make
counters and decoders and the like.
At a more ambitious level, FPGAs allow the construction of retargetable
hardware designs, where you can send a new file to a customer and
change the function of an already designed board.
Certainly, the price of the devices can have an extreme influence on
the use of programmable logic. When a small part costs $10, you wouldn't
waste a lot of time making a decision to use such a device. But, the
top of the line >$1000 a piece devices are reserved for "price is no
object" designs. An example would be a telecom optical line card, where
the customer pays $100,000 for the hardware. If the job takes 5 or 6
of the $1000 parts, you still make a profit.
Things you still have to figure out - how to make logic functions that
work during powerup (as a decent size FPGA takes 1 second to initialize
after the power stabilizes). Also, you may need some JTAG logic, so
think carefully about what happens to the device that is being put in
JTAG test.
Now, when you put an FPGA on a board - someone has to design the
innards of the device. As a new graduate, you will have to make a
career decision, as to whether you want to design boards, or whether
you want to follow the FPGA designer / ASIC designer career path.
These days, the ASIC designers still make the big bucks, and in
my view, there is much stronger demand for experienced FPGA/ASIC
designers, than there is for board designers.
BTW - There are still some single gate logic devices available.
See http://www.onsemi.com/productSummary/0,4317,MC74VHC1G00,00.html
for an example of a single 2 input NAND gate, a device with 5 leads
on the package. These can be used for gating reset signals and the like.
Hope that helps,
Paul
Article: 46178Can anyone share his/her experiences with this board? I'm especially interested in the quality of the supplied software and ease of use of pci-data transfer (virtex <-> pc) thank you in advance! best regards, SebastianArticle: 46179
Hi all, Any one experienced with multiple Nios running on embedded linux ? Any comments / suggestions ? DinArticle: 46180
Do a google search as this question has been asked recently. I *think* the answer was that its possible with newer versions of the core. Also look here http://twistedminds.org/nios/index.php PaulArticle: 46181
Hi All, I have read in a roadmap from ITRS the item "tall, thin engineer". Can someone explain me the meaning of this ? It seems to be a "step" in the history of integrated circuits ?! Best Regards GeorgArticle: 46182
See, even a seasoned veteran can learn something off the newsgroups. I never
realized rising_edge was different than clk'event and clk='1', so had been still
using the latter for consistency's sake. Way back when, I had a problem with
rising_edge not being recognized by a simulator, and since then I hadn't used it.
Allan Herriman wrote:
> There is a semantic difference between rising_edge(clk) and (clk'event
> and clk = '1')
>
> Rising_edge(x) returns
>
> (x'event and
> (to_x01(x) = '1') and
> (to_x01(x'last_value) = '0'))
>
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 46183"Georg Heinrich" <Georg.Heinrich@eas.iis.fhg.de> wrote in message news:3D6384B4.EBAF4EA6@eas.iis.fhg.de... > Hi All, > > I have read in a roadmap from ITRS the item "tall, thin engineer". > > Can someone explain me the meaning of this ? > I think it refers to specialisation. I.e. before a certain point, engineers did a bit of everything (drew layouts in pencil, built prototypes out of transistors, designed the system etc). Eventually everything got so specialised that you needed engineers who specialised in layout i.e. had a lot of knowledge about a small area of electronics (tall and thin) rather than a bit of knowledge about everything (short and wide??). But who knows... Alan P.S. It reminds me of the saying "a salesman knows almost nothing about almost everything; an engineer knows almost everything about almost nothing" :-) > It seems to be a "step" in the history of integrated circuits ?! > > Best Regards > > Georg > > > -- Alan Fitch [HDL Consultant] DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project Services Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK Tel: +44 (0)1425 471223 mail: alan.fitch@doulos.com Fax: +44 (0)1425 471573 Web: http://www.doulos.com This e-mail and any attachments are confidential and Doulos Ltd. reserves all rights of privilege in respect thereof. It is intended for the use of the addressee only. If you are not the intended recipient please delete it from your system, any use, disclosure, or copying of this document is unauthorised. The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 46184
Alan Fitch wrote: > P.S. It reminds me of the saying > > "a salesman knows almost nothing about almost everything; an > engineer knows almost everything about almost nothing" :-) Another formulation: "An expert is someone who knows more and more about less and less." - Ron Cline XilinxArticle: 46185
"Reala" <-> wrote in message news:<ajsgss$57k1@imsp212.netvigator.com>...
> Hi,
>
> For the design with input and output only, I collect input of design to
> output of test generater and vice versa. However, when the design have INOUT
> port, How can i collect this to test generate mode?
>
> Thanks you.
> Reala
----------------------------------------------------------
Reala,
I'm not sure what you're trying to do here but it sounds like you're
writing
at testbench in Verilog. Verilog simulators have trouble driving
"inout" pins from a "reg" in a testbench. Instead drive the "inout"
pin from your testbench with a net "wire", "tri", "wor" or a "trior"
then "assign" this net with a "reg" registered value.
Try this code out below. I've shown a "wire" net "bidir_data"
attached to the "inout" pin of the UUT module that is a 16-bit
bidirectional register.
I force tri-stated "zzzz" into the register "bidir_data_reg" which
in turn drives the "net" "bidir_data", when I expect the UUT's data
bus to be an output. I force example data "aa55" into
"bidir_data_reg", when I expect the UUT's data bus to be an input.
This approach solves multiple headaches and allows me to accurately
simulate verilog "inout" module pins.
Hope this helps,
Mark
----------------------------------------------------------
module testbench();
parameter CLK_PERIOD = 80;
// Inputs
reg mclk;
// Outputs
// Bidirs
// Nets
wire [15:0] bidir_data;
// Registers
reg [15:0] bidir_data_reg;
// Instantiate the UUT
bidir_16bit_reg UUTreg (mclk, bidir_data);
// Initialize Inputs
initial begin
mclk = 0;
bidir_data_reg = 16'hzzzz;
#20 bidir_data_reg = 16'haa55;
#80 bidir_data_reg = 16'hzzzz;
end
// Assignments
assign bidir_data = bidir_data_reg ;
// mclk Clock generator
always
begin
#(CLK_PERIOD/2) mclk = ~mclk;
end
endmodule
Article: 46186Khee, This works just fine. Austin Khee Hue wrote: > Hi All, > > Xilinx recommends LVPECL inputs to Virtex-II be terminated with a 100ohm > resistor between the LVPECL input differential pair. > > I wish to terminate my LVPECL inputs with 50ohms to VTT (where VTT = VCCO - > 2V) on each leg of the differential pair at the Virtex-II chip end. Has > anyone successfully used this LVPECL termination on Virtex-II chips ? > > Thanks. > KheeArticle: 46187
On Wed, 21 Aug 2002 13:45:03 +0100, "Alan Fitch" <alan.fitch@doulos.com> wrote: > >"Georg Heinrich" <Georg.Heinrich@eas.iis.fhg.de> wrote in message >news:3D6384B4.EBAF4EA6@eas.iis.fhg.de... >> Hi All, >> >> I have read in a roadmap from ITRS the item "tall, thin >engineer". >> >> Can someone explain me the meaning of this ? >> >I think it refers to specialisation. I.e. before a certain point, >engineers >did a bit of everything (drew layouts in pencil, built prototypes >out >of transistors, designed the system etc). Eventually everything >got >so specialised that you needed engineers who specialised in >layout i.e. had a lot of knowledge about a small area of >electronics >(tall and thin) rather than a bit of knowledge about everything >(short >and wide??). > >But who knows... > >Alan > >P.S. It reminds me of the saying > >"a salesman knows almost nothing about almost everything; an >engineer knows almost everything about almost nothing" :-) > >> It seems to be a "step" in the history of integrated circuits ?! >> >> Best Regards >> >> Georg >> >> >> The end-game here seems to be engineers who are highly skilled and can accomplish virtually nothing. When specialties get too narrow, one must depend on management to pull all the pieces together and make a real-world product work; after all, no one member of the project team understands what the others do, so only the manager knows how the end product works. Lots of luck. John (who considers himself a short, cute engineer)Article: 46188
Paul, What FPGA you learned on has nothing to do with where the opportunities will be. There are people working for me who have used Altera FPGAs before they came here. Nothing wrong with that. When you sell a part that wakes up everytime, and asks "what will I be today?" it is hard to say how the chips get used unless someone goes out and researches all of the applications (see below). To say that a front runner part like Virtex II has won XX,000 sockets implies XX,000 different applications among a lot of different customers. If you ask an ASIC designer today about what they are doing, you will find that they are a bit jealous of what we are doing: .13u, nine metal layers, power pc from IBM, multi-gigbit transceivers, all copper process, low K dielectrics, etc. etc. etc. Most ASIC designers are working with two year old technology, grinding out the standard stuff (graphics controllers, memory controllers, disc controllers) yet again, and again. And, by the way, we are now working on the next generation(s) beyond .13u... So the FPGA user engineer at our customers is in a bit of an interesting situation: they get to use technologies that are two or even three years ahead of the ASIC designer....so who is playing with the coolest toys now? I am sure the FPGA you had in school was a few years old, and hence regarded as something good to learn on, but not seriously to be thought of as something "hi-tech." But FPGAs today have become more than just "glue" and are now finding themselves at the heart of a system due to their capabilites. http://www.xilinx.com/xcell/xl30/xl30_10.pdf I wrote it over four years ago, but it has come true far sooner than I would have ever believed. http://www.xilinx.com/company/success/index.htm We go find people who use the chips, and are happy and successful. Austin Paul wrote: > In article <ajb0l6$org$1@news-int.gatech.edu>, Buddy Smith > <nullset@dookie.net> wrote: > > > I'm a (soon graduating!) student at Georgia Tech studying computer > > engineering. GT uses altera products for several classes, so I've used > > those plenty....but I've seen very little of how FPGAs are really used in > > industry. Also I've had no experience with non-altera FPGAs because I > > believe my school has some sort of deal with altera..... > > > > Can someone point me to a text, or website that contains information about > > real world applications of FPGAs? > > > > Thanks, > > > > --buddy > > From a practical standpoint, no one wants to work harder than they have > to. So, when you graduate, and someone asks you to design something, the > first thing you'll do is reuse other people's designs. If the problem > you are solving can be handled with ASICs from Motorola or IBM or AMCC > etc., you'll throw those on the board, and leave it to your software > team to make it work :-) > > However, many ASICs have most of the functionality you want, but the > interface on them is just plain wrong. Some of the designs done > by groups I've worked in, consisted of ASIC --> FPGA --> ASIC --> FPGA > and so on. The FPGA was used as a protocol translator. > > So, the simplest use for FPGAs is as "glue" logic. > > At one time, if you visited the Texas Instruments web site, you could > find just about any primitive you could ever want. As programmable logic > has advanced, TI and other logic companies have seen their sales of this > discrete logic shrink. Today, you'll find an assortment of bus > buffers/registers, but a lot of the other logic is nowhere to be found. > This is also a place where you will resort to FPGAs or CPLDs, to make > counters and decoders and the like. > > At a more ambitious level, FPGAs allow the construction of retargetable > hardware designs, where you can send a new file to a customer and > change the function of an already designed board. > > Certainly, the price of the devices can have an extreme influence on > the use of programmable logic. When a small part costs $10, you wouldn't > waste a lot of time making a decision to use such a device. But, the > top of the line >$1000 a piece devices are reserved for "price is no > object" designs. An example would be a telecom optical line card, where > the customer pays $100,000 for the hardware. If the job takes 5 or 6 > of the $1000 parts, you still make a profit. > > Things you still have to figure out - how to make logic functions that > work during powerup (as a decent size FPGA takes 1 second to initialize > after the power stabilizes). Also, you may need some JTAG logic, so > think carefully about what happens to the device that is being put in > JTAG test. > > Now, when you put an FPGA on a board - someone has to design the > innards of the device. As a new graduate, you will have to make a > career decision, as to whether you want to design boards, or whether > you want to follow the FPGA designer / ASIC designer career path. > These days, the ASIC designers still make the big bucks, and in > my view, there is much stronger demand for experienced FPGA/ASIC > designers, than there is for board designers. > > BTW - There are still some single gate logic devices available. > See http://www.onsemi.com/productSummary/0,4317,MC74VHC1G00,00.html > for an example of a single 2 input NAND gate, a device with 5 leads > on the package. These can be used for gating reset signals and the like. > > Hope that helps, > > PaulArticle: 46189
John Larkin wrote:
> Hi,
>
> we have an older product that uses Actel 1280XL-TQ176 chips, and one
> chip has a horrible, basicly-impossible-to-explain bug [1]. Since
> these critters are OTP, we may well wind up replacing the chip several
> times before we get it fixed, so we'd like to use a socket, butchered
> into the regular PCB footprint somehow.
Such a socket may give you one or two more
basicly-impossible-to-explain bugs.
> So, does anybody know of a source for such a socket? We've found the
> Yamaichi parts, which solder directly to the chip layout, but delivery
> is 10 weeks or somesuch and min order is 10 pieces at $80 each.
At those prices you could afford to have the part unsoldered
and resoldered three times by a professional board shop with a rework station.
> [1] We load a down-counter in an idle state, using the system clock;
> later we count down using a different clock. The logic looks OK, but
> one narrow range of presets loads wrong.
Consider synchronizing the design and resimulating.
-- Mike Treseler
Article: 46190Hi, I'm looking for a copy of the ERA60100 Electrically Reconfigurable Array data sheet from Plessey Semiconductors. Could someone send me it to mgg@dee.isep.ipp.pt Thanks. Manuel -- Manuel G. Gericota ----------------- Instituto Superior de Engenharia do Porto Departamento de Engenharia Electrotecnica Rua Dr. Antonio Bernardino de Almeida 4200-072 PORTO PORTUGAL Tel: (351) 22 83 40 500 Fax: (351) 22 83 21 159 E-mail: mgg@dee.isep.ipp.pt WWW: http://www.dee.isep.ipp.pt/~mgg ----------------- "Os sentimentos nao se compreendem nem se explicam" do filme "Cinema Paradiso"Article: 46191
I wanna know about the code acquisition problem in cdma and what new research is being done in this area. I would also like to get a few free papers AsifArticle: 46193
Hi, I tried a small V2P design today in Viewdraw, and it went all the way through the tools, and I pushed down to the simulation models, and they were there (though I didn't run a simulation yet)...so I believe, at least to some level, this works. There was even a symbol for the PowerPC...but I didn't explore that too much, though I think I might. I wonder if there's a simulation model for that...there was both a VHDL and a Verilog selection for the PPC... Regards, Austin "Ray Andraka" <ray@andraka.com> wrote in message news:3D61A990.77498F04@andraka.com... > It has been a while since I last used viewlogic. I dropped it when I started > using Virtex. At that time, they provided symbols, but there were no simulation > models under the virex specific parts...important things like the carry chain > components, SRL16's and block RAMs. About the same time, Xilinx indicated that > viewlogic was unwilling to do something they needed for the simulation models to > work right, and xilinx didn't see the point in keeping with schematics, > especially a 3rd party vendor. I did see the symbols on the install disk, but > I'd be surprised if there were viewlogic simulation models under all of them. Of > course, you could use the VHDL models, but then you need to edit all the > viewlogic symbols and it also requires you to have their VHDL sim with the > schematic tools. I do know that if you have a viewlogic problem with Xilinx, > you are pretty much on your own. > > Austin Franklin wrote: > > > Hi Ray, > > > > Hum. I have libraries for everything up to Virtex2...in the [Xilinx > > installation]\viewlog\data directory. Now, I can't vouch for support from > > Xilinx or not... That's on a 3. installation... I'll check with my 4. > > installation upstairs and see if it's installed there.....and...lo and > > behold...all the way to Virtex 2 PRO!!! > > > > So, does that mean it's "supported"? Now, I can't vouch that EVERYTHING is > > supported, but "some" support seems to be there, at least for the most > > recent technologies... > > > > Are you simply talking about simulation libraries, not just schematic symbol > > libraries? I haven't tried simulating...but I've simulated Virtex designs > > so far...never tried V2 or V2P... > > > > Regards, > > > > Austin > > > > "Ray Andraka" <ray@andraka.com> wrote in message > > news:3D5BB778.FF678341@andraka.com... > > > Xilinx no longer generates a viewlogic library, no will its > > > hotline help you out if you have issues with using viewlogic. > > > You can still generate an edif netlist with viewlogic, but you > > > will need to do something for the library if you plan to > > > simulate within viewlogic. Show me where to get a VL library > > > for the current Xilinx primitives if I am wrong. > > > > > > Austin Franklin wrote: > > > > > > > > Viewlogic is not really supported by Xilinx anymore... > > > > > > > > Hi Ray, > > > > > > > > Would you mind clarifying what you mean by "really" please? > > > > > > > > Regards, > > > > > > > > Austin > > > > > > -- > > > --Ray Andraka, P.E. > > > President, the Andraka Consulting Group, Inc. > > > 401/884-7930 Fax 401/884-7950 > > > email ray@andraka.com > > > http://www.andraka.com > > > > > > "They that give up essential liberty to obtain a little > > > temporary safety deserve neither liberty nor safety." > > > -Benjamin Franklin, > > > 1759 > > > > > > > > -- > --Ray Andraka, P.E. > President, the Andraka Consulting Group, Inc. > 401/884-7930 Fax 401/884-7950 > email ray@andraka.com > http://www.andraka.com > > "They that give up essential liberty to obtain a little > temporary safety deserve neither liberty nor safety." > -Benjamin Franklin, 1759 > >Article: 46194
In article <3D63AC3F.DA644BC1@xilinx.com>, Austin Lesea
<austin.lesea@xilinx.com> wrote:
> Paul,
>
> What FPGA you learned on has nothing to do with where the opportunities
will be.
>
> There are people working for me who have used Altera FPGAs before they came
> here. Nothing wrong with that. When you sell a part that wakes up everytime,
> and asks "what will I be today?" it is hard to say how the chips get
used unless
> someone goes out and researches all of the applications (see below).
>
> To say that a front runner part like Virtex II has won XX,000 sockets implies
> XX,000 different applications among a lot of different customers.
>
> If you ask an ASIC designer today about what they are doing, you will
find that
> they are a bit jealous of what we are doing: .13u, nine metal layers, power pc
> from IBM, multi-gigbit transceivers, all copper process, low K
dielectrics, etc.
> etc. etc. Most ASIC designers are working with two year old technology,
> grinding out the standard stuff (graphics controllers, memory
controllers, disc
> controllers) yet again, and again.
>
> And, by the way, we are now working on the next generation(s) beyond .13u...
>
> So the FPGA user engineer at our customers is in a bit of an interesting
> situation: they get to use technologies that are two or even three
years ahead
> of the ASIC designer....so who is playing with the coolest toys now?
>
> I am sure the FPGA you had in school was a few years old, and hence
regarded as
> something good to learn on, but not seriously to be thought of as something
> "hi-tech." But FPGAs today have become more than just "glue" and are now
> finding themselves at the heart of a system due to their capabilites.
>
> http://www.xilinx.com/xcell/xl30/xl30_10.pdf
>
> I wrote it over four years ago, but it has come true far sooner than I would
> have ever believed.
>
> http://www.xilinx.com/company/success/index.htm
>
> We go find people who use the chips, and are happy and successful.
>
> Austin
>
Austin:
I was attempting to provide some perspective as a board designer, as to what
people in the "real" world do with FPGAs. Certainly, the original poster can
tell from reading the posts in this group, as to what people are doing with
FPGAs. In my case, I've worked in an environment where they are used as glue,
and I've also worked in a startup, where an entire card was based on
nothing but FPGAs and DDR / QDR memories.
I don't think the original poster was attempting to dump on X or A. A lot of
people choose Xilinx or Altera, based on their familiarity with a particular
design flow, so the choice wasn't based on nanoseconds, it was based on a
GUI.
As a new graduate, the original poster (Buddy) will have to choose what kind
of career path to take. At one time, a board designer did designs with discrete
logic ("jelly beans"), so the board designer had to spec and design all the
logic, frequently without the aid of nifty synthesis tools. Board design now,
is all about glueing the right large ASICs together, to achieve an objective.
There isn't enough time to understand all of the operation of the devices, as
the spec sheets for a large board can total a couple thousand pages of paper.
If you are lucky, you get enough time to do the interface timing and that's it.
That is why I referred to throwing the devices on the board, and leaving it
to the software team to make it work.
If Buddy enjoys designing blocks of logic, then working first as an end user
of FPGAs gives an opportunity to become familiar with specing and designing
logic. FPGA design makes a good lead-in to ASIC design, as the learning curve
will be easier with FPGAs as a first step. No ASIC design team is going to
take a new grad with no experience, and give him or her a significant portion
of a chip to design, with all the schedule pressures inherent. A small FPGA
design, on the other hand, allows someone new to logic design to get their
feet wet, while minimizing the risk to the overall project.
As to the original question...
Can someone point me to a text, or website that contains information about
real world applications of FPGAs?
I don't think a single web site is going to do that for you. If you visited
opencores.org, for example, you would see examples of intellectual property
donated by designers, but 99% of all design is jealously guarded by
the companies that paid for it. Going to the X or A website isn't going to
help, because the IP they are selling is going to be popular, commodity stuff.
A site like fpgacpu.org gives some ideas, but would those ideas appear in
commercial products ?
The best source of ideas is probably reading this newsgroup!
As to this comment...
> I am sure the FPGA you had in school was a few years old, and hence
regarded as
> something good to learn on, but not seriously to be thought of as something
> "hi-tech." But FPGAs today have become more than just "glue" and are now
> finding themselves at the heart of a system due to their capabilites.
They may be the heart of a system to you, but if I can find an off-the-shelf
device that solves my problem, why would I mess with an FPGA ? It can take
an army of people to design systems on a chip. In my example above, where a
board was constructed of nothing but FPGAs and DDR / QDR memory, there were
two board designers and around fifteen FPGA designers. Does that sound like
a cheap way to design things ? Imagine how many units I would have to sell
to pay for the engineering!
Paul
Article: 46197
Austin Lesea wrote:
>
> Paul,
>
>
> If you ask an ASIC designer today about what they are doing, you will find that
> they are a bit jealous of what we are doing: .13u, nine metal layers, power pc
> from IBM, multi-gigbit transceivers, all copper process, low K dielectrics, etc.
> etc. etc. Most ASIC designers are working with two year old technology,
> grinding out the standard stuff (graphics controllers, memory controllers, disc
> controllers) yet again, and again.
>
By saying "two year old technology," I will guess that you mean
0.18u process technology.
While it is true that FPGA usually is the first device to use the latest
process technology, because FPGA is programmable, the interconnect
(wire) is slower than standard cell ASIC.
Therefore, a FPGA manufactured in 0.13u process technology is probably
going to be slower than a standard cell ASIC also manufactured in 0.13u
process technology.
Perhaps, comparing an FPGA manufactured in 0.13u process technology with
a standard cell ASIC manufactured in 0.18u process technology with is
fairer.
Companies that develop 3D graphics chip do also use the latest
process technology because it is a very competitive industry, and no one
wanting to be competitive is using 0.18u process technology for their
leading edge part.
3D graphics chips that use 0.18u process technology were first released
2 years ago, and are nearing end of life at this point.
Austin, have you even seen any 3D graphics chip vendors using
FPGA for production?
No, they cannot afford to use an FPGA because of FPGA's inherent density
disadvantage (FPGA achieves 1/10 of ASIC's gate density for the same
amount of die area.) and the very high price tag (> $8,000) for the
largest part.
No wonder I see almost no one using FPGA for PC related applications
(i.e., CPU, graphics chip, chipset, etc.) other than for prototyping.
> And, by the way, we are now working on the next generation(s) beyond .13u...
>
Since TSMC or UMC offer the same advanced process technology to
other fabless design firms, these firms can also take advantage of the
same technology Xilinx uses, as long as they have high enough volume to
afford the mask costs which is approaching $1 million per mask.
Kevin Brace (In general, don't respond to me directly, and respond
within the newsgroup.)
Article: 46198Hi, I have a prototyping board from Altera for testing my design. I'm new to using a prototype board and hence had some questions. The device in the prototype board is a EP20K1500E. Does anyone have views on whether I would need a logic analyzer with this board ? Do people who use prototype boards always use analyzers ? Is there an alternate way out without using analyzers ? Any recommendation on which logic analyzer should I use ? Thanks, PrashantArticle: 46199
Kolja Sulimma wrote: [snip] > > The above only applies to techniques that are required to use the > chip. So you can assume that you licensed the memory bus, but if there > is an MP3 application not for the processor you do not own an MP3 > license. > > Kolja Sulimma This is the only area where I have personal experience with this issue. I made an MP3 player in school a few years back and I used the MP3 decoder chip from MAS Electronics (I think). I looked into the licensing issues since at that time the body that owned the MP3 encoding/decoding technology was getting sensitive about the use of their technology. Anyways, to the point, MAS Electronics (or whatever the company was) paid the royalties for the MP3 decoding technology. Anyone who bought the chips were free to integrate the chips into whatever product. Now, interestingly enough, the particular MP3 decoder chip I used was controlled via I2C interface. My controller was implemented in a CPLD so I looked for but did not find any information covering legal issues of integrating master or slave I2C devices in a product. -- Davis Moore
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