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Generally said DSP will sample the data bus at a certain edge when reading, like at the rising edge of RD, so as long as your new data come to steable at that edge, you don't need to worry about those X data or those old data. But you do need take care the OE delay, if the DSP doesn't have enough hold time(recovering time) after the read, your OE delay may cause bus conflict. Peng anjanr@yahoo.com (Anjan) wrote in message news:<5a5faf7b.0208222017.a70a1e8@posting.google.com>... > Thanks. But I guess the problem is due to the fact that delay between > source and destination pad is different. To explain say the delay > between address to data is different between oe and data. And if oe > delay is smaller than address delay then it may present old data first > followed by new data. But how do I avoid this. I cannot get the same > delay for everything. Also I cann't use in a clock process owing to > the fact that the DSP timing doesn't allow this. Can you please > suggest > > Anjan >Article: 46276
I am hoping that someone has some knowledge of the Alliance software package for vlsi design. I have successfully downloaded and run it, but in running the example for the AMD2901 bit slice processor (or the other tutorials for that matter), I end up with a chip.ap and a heart.ap file. It seems that the chip.ap file contains all of the pad interconnects and the heart.ap file contains all of the standard cell interconnects. I would very much like to view the chip as placed and routed, but I can only see the outer interconnects (the contents of chip.ap), or the standard cell interconnects (the contents of heart.ap), but not the standard cells themselves. I know the software can find the cells as it routed the chip and I can view the cells one at a time, but I would like to view the entire chip at one time. I am using the graal tool that is part of Alliance for this. Perhaps there is a configuration issue with the tool, or I am using the wrong tool. Any suggestions or hints would be appreciated. -- Charles Krinke http://home.pacbell.net/cfk cfk@pacbell.netArticle: 46277
Hi, I am looking for pin description of schematic components. For example, X74_195 has pins named A, B, C, D, J, K, SL ect.. Where can i find information about function of this pins ? ThanksArticle: 46278
Here is a link I found by using google.com and searching for the key words "cdma code acquistion" : http://www.cwc.oulu.fi/home/projects/AWICS/awics_pub/2000/marcos_katz_jsac00.pdf There are about 12,000 more. Now, if you want some ideas on how to implement such things in FPGAs, comparing serial vs. parallel implementations, appropriateness of the task to do in manufacture X or A or Q's device, you might get some interesting feedback. As for me, I haven't worked on that stuff for several years (but there are many others dealing with it on a daily basis.) Jason Asif Siddiq wrote: > > I wanna know about the code acquisition problem in cdma and what new > research is being done in this area. I would also like to get a few > free papers > AsifArticle: 46279
These are TTL logic devices, originally known as 7400 logic. You can find info by a search for "TTL Logic pinouts", "74XX family" and other similar search terms. For instance, this link http://links.epanorama.net/links/components.html was obtained from google with the "TTL logic pinouts" as a search term, there were several hundred hits. Many of us keep an old copy of Texas Instruments "TTL LOGIC" book around for just such a purpose, perhaps one of your compatriots might have a copy. "BasePointer" <mfide@softhome.net> wrote in message news:ee78907.-1@WebX.sUN8CHnE... > Hi, > > I am looking for pin description of schematic components. For example, X74_195 has pins named A, B, C, D, J, K, SL ect.. Where can i find information about function of this pins ? > > ThanksArticle: 46280
Sorry the reply-to address was bogus; it should be corrected. Jason wrightjt wrote: > > Here is a link I found by using google.com and searching for the key > words "cdma code acquistion" : > > http://www.cwc.oulu.fi/home/projects/AWICS/awics_pub/2000/marcos_katz_jsac00.pdf > > There are about 12,000 more. > > Now, if you want some ideas on how to implement such things in FPGAs, > comparing serial vs. parallel implementations, appropriateness of the > task to do in manufacture X or A or Q's device, you might get some > interesting feedback. As for me, I haven't worked on that stuff for > several years (but there are many others dealing with it on a daily > basis.) > > Jason > > Asif Siddiq wrote: > > > > I wanna know about the code acquisition problem in cdma and what new > > research is being done in this area. I would also like to get a few > > free papers > > AsifArticle: 46281
Hi,
I have a system with as many as 33 spartan2e devices in it. In order to
have the startup current be acceptable I am trying to start them daisy chain
fashion. When the first unit powers up it send a delayed signal to enable
the second FPGA to power up. The second fpga, in turn, starts the third
FPGA and so forth. My first approach was to use the done signal directly
from the FPGA as the delayed link. However, it appears that either the
drive current is not high enough on this output, or the power system needs
time to recover. So I put in a counter that gives a logic one at maximum
count as an output. I used this one to halt the counter and also start the
second FPGA. Unfortunately the clock is common to all FPGAs. The input
clock is serving to partially bias the system on. If I start the clock last
then the counters will never count and enable the second unit. So I need a
cheap and dirty oscillator to run the delay counter. Does the Spartan2e
have a built-in oscilator that I can tap like the old spartanXL does?
Alternatively, can I get away with a simple RC oscilator using an input and
an output from the Spartan2e as an inverter? Note that the delay time is
not critical, even a 50% variation frequency is quite acceptable.
Thanks,
Theron Hicks
Article: 46282The data sheet states that the done signal pin may be either driven high or used open collector fashion. If it is driven, what are the output characteristics? (Drive current, output resistance, volatge levels, etc.) I would like to use this in a delayed boot-up of a second FPGA to reduce power supply requirements and I want to decide whether I should buffer if first. Thanks, Theron HicksArticle: 46283
In comp.arch.fpga Jeff Cunningham <jcc@sover.net> wrote: > Within modelsim compile virtexdummy into a library called "dummy". Use the > library mapping tools to map the name virtex to library "dummy". Now > modelsim will have something to map the library name to and will not > complain and you don't have to comment stuff in/out when going from > synthesis to simulation. > > Back when I was using Synplicity, I had to do the same thing with the > library "unisim" when synthesizing. It's safe (and useful) to synthesize unisim_vcomp.vhd - no need for tricks or the Synplify virtex library. Hamish -- Hamish Moffatt VK3SB <hamish@debian.org> <hamish@cloud.net.au>Article: 46284
"Theron Hicks" <hicksthe@egr.msu.edu> schrieb im Newsbeitrag news:ak6h7v$uhn$1@msunews.cl.msu.edu... > Hi, > I have a system with as many as 33 spartan2e devices in it. In order to > have the startup current be acceptable I am trying to start them daisy chain > fashion. When the first unit powers up it send a delayed signal to enable > the second FPGA to power up. The second fpga, in turn, starts the third > FPGA and so forth. My first approach was to use the done signal directly > from the FPGA as the delayed link. However, it appears that either the > drive current is not high enough on this output, or the power system needs > time to recover. So I put in a counter that gives a logic one at maximum > count as an output. I used this one to halt the counter and also start the > second FPGA. Unfortunately the clock is common to all FPGAs. The input > clock is serving to partially bias the system on. If I start the clock last > then the counters will never count and enable the second unit. So I need a > cheap and dirty oscillator to run the delay counter. Does the Spartan2e > have a built-in oscilator that I can tap like the old spartanXL does? > Alternatively, can I get away with a simple RC oscilator using an input and > an output from the Spartan2e as an inverter? Note that the delay time is > not critical, even a 50% variation frequency is quite acceptable. > Hello Theron, I believe you have a misunderstanding of the startup current. The startup current has nothing to do with the DONE pin or configuration of the FPGA. It is simply a high current flowing within the first few miliseconds after the power supply voltage has been applied. Chapter "Power-On Requiremnts" in http://www.xilinx.com/partinfo/ds077_3.pdf I see only one chance to reduce it, power up the FPGAs sequentially. Therefore you would need an electronic switch(Power-Mosfet) in the supply rail. That switch could be controlled from a pin of the previous powered FPGA. I have never seen this in an appnote. Why? Best Regards HelmutArticle: 46285
My Virtex-E (xcv600E) design was meeting timing with Alliance (or Foundation, presumably same P&R engine) version 3.1i, then when I upgraded to version 4.2i, the design's timing got significantly worse even though it's operating on the same EDIF netlist & same UCF file & same "effort" level (max) set in the Design Manager's " Design --> Options... " menu. Why? [ I thought it was supposed to get better! ] PS -- It's not just me .... 4 other designers in my organization are having same problem.Article: 46286
William LenihanIii <lenihan3we@earthlink.net> wrote: > My Virtex-E (xcv600E) design was meeting timing with Alliance (or > Foundation, presumably same P&R engine) version 3.1i, then when I > upgraded to version 4.2i, the design's timing got significantly > worse even though it's operating on the same EDIF netlist & same > UCF file & same "effort" level (max) set in the > Design Manager's " Design --> Options... " menu. > > Why? [ I thought it was supposed to get better! ] Two possibilities. 1. The route did get worse. Possible. 2. The speed files got more accurate, which for Virtex-E means worse, especially if you use much block RAM. Were you using all the latest service packs and speed file updates for your 3.x tools? If so you shouldn't notice much different in the speed files going to 4.2, from memory. Hamish -- Hamish Moffatt VK3SB <hamish@debian.org> <hamish@cloud.net.au>Article: 46287
Thanks but I couldn't explain my problem. I am not looking for pinouts of orginal ttl logic devices. I talk about components of ISE 4.2 Schematic (Xilinx ECS). For instance, X74_195 in Shift_Register category in Xilinx ECS has A, B, C pins don't be standard. I need description of them. Where can i find it ? ThanksArticle: 46288
hamish@cloud.net.au wrote: > William LenihanIii <lenihan3we@earthlink.net> wrote: > > My Virtex-E (xcv600E) design was meeting timing with Alliance (or > > Foundation, presumably same P&R engine) version 3.1i, then when I > > upgraded to version 4.2i, the design's timing got significantly > > worse even though it's operating on the same EDIF netlist & same > > UCF file & same "effort" level (max) set in the > > Design Manager's " Design --> Options... " menu. > > > > Why? [ I thought it was supposed to get better! ] > > Two possibilities. > > 1. The route did get worse. Possible. > Esp. in view of Ray Andraka's comments that in the change from 4.1i -> 4.2i the routing has got worse for a given placement. I think this is true of 3.xi->4.1i as well. > > 2. The speed files got more accurate, which for Virtex-E means worse, > especially if you use much block RAM. > > Were you using all the latest service packs and speed file updates for > your 3.x tools? If so you shouldn't notice much different in the speed > files going to 4.2, from memory. > To check this - speed file degradation - the OP should probably ask Xilinx for the latest 4.x speed files but in a form compatible with the 3.x P&R tools. Its been claimed on this NG that this is possible if you badger your FAE hard enough. I would say as a side note that Xilinx should really put the speed files into a format that's independent of the tool set version [simple ASCII text file ?].Article: 46289
Well, group, here is a story about the federal government essentially forbidding hospitals from increasing the size of their doctor residency programs to control the "glut" of doctors in the USofA. It seems that Medicare pays for most residency programs, which is the equivalency of the U.S. government paying for co-op engineers to work at a company for a semester or two or three. They are supposedly going to pay hospitals NOT to take in more residents. I for one didn't know that there was a glut of doctors. When I go to my doctor and ask him if he's taking more patients, he says "no, unless they are a relative of yours." Man, if engineers had the political influence that doctors have, a company wouldn't be able to order and use an FPGA unless we wrote a prescription! Engineers depend on market forces to control the number of engineers, while doctors use politics to control their numbers. The link where I got the story is below: http://www.cnn.com/HEALTH/9708/24/doctor.glut/ Now, as most of you know, there are a lot of Indian engineers in the USofA. I work with them all the time, and most of them are my friends. The doctor situation over in India is a little different. Below is a link to a story about the Indian doctors' poor working conditions and pay. It's called "there's money for everybody but doctors!" Perhaps some of you Indian engineers can comment on this story. http://www.indian-express.com/ie/daily/19991120/ile20103p.html Simon Ramirez, Consultant Synchronous Design, Inc. Oviedo, FL USAArticle: 46290
"Helmut Sennewald" <HelmutSennewald@t-online.de> wrote in message
news:ak7bon$enj$04$1@news.t-online.com...
>
> "Theron Hicks" <hicksthe@egr.msu.edu> schrieb im Newsbeitrag
> news:ak6h7v$uhn$1@msunews.cl.msu.edu...
> > Hi,
> > I have a system with as many as 33 spartan2e devices in it. In
order
> to
> > have the startup current be acceptable I am trying to start them daisy
> chain
> > fashion. When the first unit powers up it send a delayed signal to
enable
> > the second FPGA to power up. The second fpga, in turn, starts the third
> > FPGA and so forth. My first approach was to use the done signal
directly
> > from the FPGA as the delayed link. However, it appears that either the
> > drive current is not high enough on this output, or the power system
needs
> > time to recover. So I put in a counter that gives a logic one at
maximum
> > count as an output. I used this one to halt the counter and also start
> the
> > second FPGA. Unfortunately the clock is common to all FPGAs. The input
> > clock is serving to partially bias the system on. If I start the clock
> last
> > then the counters will never count and enable the second unit. So I
need
> a
> > cheap and dirty oscillator to run the delay counter. Does the Spartan2e
> > have a built-in oscilator that I can tap like the old spartanXL does?
> > Alternatively, can I get away with a simple RC oscilator using an input
> and
> > an output from the Spartan2e as an inverter? Note that the delay time
is
> > not critical, even a 50% variation frequency is quite acceptable.
> >
>
> Hello Theron,
> I believe you have a misunderstanding of the startup current.
> The startup current has nothing to do with the DONE pin or
> configuration of the FPGA. It is simply a high current flowing
> within the first few miliseconds after the power supply voltage
> has been applied. Chapter "Power-On Requiremnts" in
> http://www.xilinx.com/partinfo/ds077_3.pdf
>
> I see only one chance to reduce it, power up the FPGAs sequentially.
> Therefore you would need an electronic switch(Power-Mosfet) in the
> supply rail. That switch could be controlled from a pin of the previous
> powered FPGA. I have never seen this in an appnote. Why?
>
> Best Regards
> Helmut
>
>
>
Helmut,
That is exactly what I was trying to do, with the exception that I was
using an enable signal for the board level regulators for 1.8 and 3.3 volts.
This enable was to be driven by the "done" signal from the previous FPGA.
Unfortunately, there are two problems.
1. The done signal seems to glitch and even pull back low as the second
FPGA. I will try to drive the done signal and also buffer it with an
external gate. Alternatively, I could generate an on-board oscillator to
drive a counter to start the next FPGA in a delayed manner.
2. The off-board generated clock signals are starting with no delay.
Somehow they are being rectified and then biasing the 3.3 volt supply up to
approximately 0.8 volts. So I must start the clock generator after all the
FPGA's are running.
Thanks,
Theron
Article: 46291
"Theron Hicks" <hicksthe@egr.msu.edu> schrieb im Newsbeitrag
news:ak87q7$2frm$1@msunews.cl.msu.edu...
>
> "Helmut Sennewald" <HelmutSennewald@t-online.de> wrote in message
> news:ak7bon$enj$04$1@news.t-online.com...
> >
> > "Theron Hicks" <hicksthe@egr.msu.edu> schrieb im Newsbeitrag
> > news:ak6h7v$uhn$1@msunews.cl.msu.edu...
> > > Hi,
> > > I have a system with as many as 33 spartan2e devices in it. In
> order
> > to
> > > have the startup current be acceptable I am trying to start them daisy
> > chain
> > > fashion. When the first unit powers up it send a delayed signal to
> enable
> > > the second FPGA to power up. The second fpga, in turn, starts the
third
> > > FPGA and so forth. My first approach was to use the done signal
> directly
> > > from the FPGA as the delayed link. However, it appears that either
the
> > > drive current is not high enough on this output, or the power system
> needs
> > > time to recover. So I put in a counter that gives a logic one at
> maximum
> > > count as an output. I used this one to halt the counter and also
start
> > the
> > > second FPGA. Unfortunately the clock is common to all FPGAs. The
input
> > > clock is serving to partially bias the system on. If I start the
clock
> > last
> > > then the counters will never count and enable the second unit. So I
> need
> > a
> > > cheap and dirty oscillator to run the delay counter. Does the
Spartan2e
> > > have a built-in oscilator that I can tap like the old spartanXL does?
> > > Alternatively, can I get away with a simple RC oscilator using an
input
> > and
> > > an output from the Spartan2e as an inverter? Note that the delay time
> is
> > > not critical, even a 50% variation frequency is quite acceptable.
> > >
> >
> > Hello Theron,
> > I believe you have a misunderstanding of the startup current.
> > The startup current has nothing to do with the DONE pin or
> > configuration of the FPGA. It is simply a high current flowing
> > within the first few miliseconds after the power supply voltage
> > has been applied. Chapter "Power-On Requiremnts" in
> > http://www.xilinx.com/partinfo/ds077_3.pdf
> >
> > I see only one chance to reduce it, power up the FPGAs sequentially.
> > Therefore you would need an electronic switch(Power-Mosfet) in the
> > supply rail. That switch could be controlled from a pin of the previous
> > powered FPGA. I have never seen this in an appnote. Why?
> >
> > Best Regards
> > Helmut
> >
> >
> >
> Helmut,
> That is exactly what I was trying to do, with the exception that I was
> using an enable signal for the board level regulators for 1.8 and 3.3
volts.
> This enable was to be driven by the "done" signal from the previous FPGA.
> Unfortunately, there are two problems.
>
> 1. The done signal seems to glitch and even pull back low as the second
> FPGA. I will try to drive the done signal and also buffer it with an
> external gate. Alternatively, I could generate an on-board oscillator to
> drive a counter to start the next FPGA in a delayed manner.
>
Hello Theron,
I see an another chance to solve the glitch problem if you
have any I/O pin free. If FPGA-1 is uninitilized, it has only
its weak pullup activated. After programming, this pin of FPGA1
is activated to a high level and so drives the output to 3V.
-------------
3.3V |
FPGA-1 | |
| | |
| | | <0.4V if FPGA1 unprogrammed
'1'| \ | | 3V if activated
--| |---o--O-----o--------------> tO DC/DC power switch
| / | | of FPGA-2
| | | 470 Ohm
internal | | |
circuit | |
| ---
> 2. The off-board generated clock signals are starting with no delay.
> Somehow they are being rectified and then biasing the 3.3 volt supply up
to
> approximately 0.8 volts. So I must start the clock generator after all
the
> FPGA's are running.
I agree, the clock should be held low until all FPGAs are powered up.
All signals will be clamped by the unpowered FPGAs at an intermediate level.
How do you program the many FPGAs? Are they programmed serially
in daisy chain where D_out of the first FPGA is fed to D_in of
the second FPGA and so on or do you use a serial EEPROM for every FPGA?
Best Regards
Helmut
Article: 46292"Helmut Sennewald" <HelmutSennewald@t-online.de> wrote in message news:ak8bob$4ih$00$1@news.t-online.com... > > "Theron Hicks" <hicksthe@egr.msu.edu> schrieb im Newsbeitrag > news:ak87q7$2frm$1@msunews.cl.msu.edu... > > > > "Helmut Sennewald" <HelmutSennewald@t-online.de> wrote in message > > news:ak7bon$enj$04$1@news.t-online.com... > > > > > > "Theron Hicks" <hicksthe@egr.msu.edu> schrieb im Newsbeitrag > > > news:ak6h7v$uhn$1@msunews.cl.msu.edu... > > > > Hi, > > > > I have a system with as many as 33 spartan2e devices in it. In > > order > > > to > > > > have the startup current be acceptable I am trying to start them daisy > > > chain > > > > fashion. When the first unit powers up it send a delayed signal to > > enable > > > > the second FPGA to power up. The second fpga, in turn, starts the > third > > > > FPGA and so forth. My first approach was to use the done signal > > directly > > > > from the FPGA as the delayed link. However, it appears that either > the > > > > drive current is not high enough on this output, or the power system > > needs > > > > time to recover. So I put in a counter that gives a logic one at > > maximum > > > > count as an output. I used this one to halt the counter and also > start > > > the > > > > second FPGA. Unfortunately the clock is common to all FPGAs. The > input > > > > clock is serving to partially bias the system on. If I start the > clock > > > last > > > > then the counters will never count and enable the second unit. So I > > need > > > a > > > > cheap and dirty oscillator to run the delay counter. Does the > Spartan2e > > > > have a built-in oscilator that I can tap like the old spartanXL does? > > > > Alternatively, can I get away with a simple RC oscilator using an > input > > > and > > > > an output from the Spartan2e as an inverter? Note that the delay time > > is > > > > not critical, even a 50% variation frequency is quite acceptable. > > > > > > > > > > Hello Theron, > > > I believe you have a misunderstanding of the startup current. > > > The startup current has nothing to do with the DONE pin or > > > configuration of the FPGA. It is simply a high current flowing > > > within the first few miliseconds after the power supply voltage > > > has been applied. Chapter "Power-On Requiremnts" in > > > http://www.xilinx.com/partinfo/ds077_3.pdf > > > > > > I see only one chance to reduce it, power up the FPGAs sequentially. > > > Therefore you would need an electronic switch(Power-Mosfet) in the > > > supply rail. That switch could be controlled from a pin of the previous > > > powered FPGA. I have never seen this in an appnote. Why? > > > > > > Best Regards > > > Helmut > > > > > > > > > > > Helmut, > > That is exactly what I was trying to do, with the exception that I was > > using an enable signal for the board level regulators for 1.8 and 3.3 > volts. > > This enable was to be driven by the "done" signal from the previous FPGA. > > Unfortunately, there are two problems. > > > > 1. The done signal seems to glitch and even pull back low as the second > > FPGA. I will try to drive the done signal and also buffer it with an > > external gate. Alternatively, I could generate an on-board oscillator to > > drive a counter to start the next FPGA in a delayed manner. > > > > Hello Theron, > I see an another chance to solve the glitch problem if you > have any I/O pin free. If FPGA-1 is uninitilized, it has only > its weak pullup activated. After programming, this pin of FPGA1 > is activated to a high level and so drives the output to 3V. > > > ------------- > 3.3V | > FPGA-1 | | > | | | > | | | <0.4V if FPGA1 unprogrammed > '1'| \ | | 3V if activated > --| |---o--O-----o--------------> tO DC/DC power switch > | / | | of FPGA-2 > | | | 470 Ohm > internal | | | > circuit | | > | --- > > > > 2. The off-board generated clock signals are starting with no delay. > > Somehow they are being rectified and then biasing the 3.3 volt supply up > to > > approximately 0.8 volts. So I must start the clock generator after all > the > > FPGA's are running. > > I agree, the clock should be held low until all FPGAs are powered up. > All signals will be clamped by the unpowered FPGAs at an intermediate level. > > > How do you program the many FPGAs? Are they programmed serially > in daisy chain where D_out of the first FPGA is fed to D_in of > the second FPGA and so on or do you use a serial EEPROM for every FPGA? > > Best Regards > Helmut > In fact that is just what I tried and it does appear to solve the problem (with the exception of the clock problem I mentioned above).Article: 46293
When I couldn't find something my mother always told me to look where it's supposed to be. In this case, that's the Xilinx website. The Libraries guide is an indispensable reference when using *any* Xilinx primitives. Go to the Xilinx.com front page. Click on the large "SUPPORT" tab on the top menu bar. Just under the support tab, the "Documentation" link pops comes up. Click that link and you'll get a list of the documentation selections. Choose the "4.1i SW Manuals" link (I prefer the "HTML Collection" because a search feature is available) and choose the "Libraries Guide" from the list of reference items. All the primitives are there. Your device is found in this list: http://toolbox.xilinx.com/docsan/xilinx4/data/docs/lib/dsgnelx7424.html The Software Manuals also have very helpful information on constraints syntax in the "Constraints Guide" and - for those of you who like command-line tools - a solid source of information is the "Development System Reference Guide." Click happy. BasePointer wrote: > Thanks but I couldn't explain my problem. I am not looking for pinouts of orginal ttl logic devices. I talk about components of ISE 4.2 Schematic (Xilinx ECS). For instance, X74_195 in Shift_Register category in Xilinx ECS has A, B, C pins don't be standard. I need description of them. Where can i find it ? > Thanks >Article: 46294
Try clicking on Help->On-line documentation...->Libraries Guide->X74_42 to X74_521->X74_195. It appears to me from that page that D,C,B,A are MSB to LSB and correspond to the outputs QD..QA. In other words D->QD, C->QC, B->QB & A->QA whtn CK is a rising edge and CLR is 1 (with some modification by J & K as described in the truth table). Is this what you are looking for "BasePointer". "BasePointer" <mfide@softhome.net> wrote in message news:ee78907.1@WebX.sUN8CHnE... > Thanks but I couldn't explain my problem. I am not looking for pinouts of orginal ttl logic devices. I talk about components of ISE 4.2 Schematic (Xilinx ECS). For instance, X74_195 in Shift_Register category in Xilinx ECS has A, B, C pins don't be standard. I need description of them. Where can i find it ? > ThanksArticle: 46295
The Libraries Guide is exactly document that I look for. Thank you very much for your help.Article: 46296
Hello, > Again, since the Insight Electronics Spartan-II 200 PCI Development Kit > comes with a slower -5 part, that will probably make your life harder > when trying to reduce setup time (Tsu). some days ago i become a package from UPS-Express, i open this and i am wondered over an XC2S200-6FG456C. > Well, good luck with your PCI IP core. Thank You. > Since your target frequency is 50MHz, you will likely need to get the > setup time somewhere between 7ns (For 33MHz PCI) and 3ns (For 66MHz > PCI). For the first i begin with easy training tasks and as second with normal clocked 33MHz PCI-bus and only 4 backend-channels. If i see the Spartan-II-200 is to slow or to smal (for 11 backend-channels) then i can go to the Virtex-E with an higher speed-grade and 300k-gates. > Almost certainly, you will need to rely on Floorplanner to reduce > routing delays. This Projekt is for my privat fun and must not be easy. I will learn some things. And if my projekt in the (not so) far future ready then i am happy. Bye ErikArticle: 46297
It is both. The speed files for virtexE took a significant slow down in
several areas with the 4.x. Xilinx is not officially distributing the revised
speed files for 3.3, but like Rick said, if you badger the FAE's enough you
can shake loose the files. Personally, I think it is a sin not putting those
speedfiles for 3.3 up on the web. This of course wouldn't be an issue if 4.2
did as good a routing job as 3.3. Somewhere in the transition the router got
lazy, and even putting the new -xe=2 extra effort switch to its max setting
doesn't bring the PAR back on par with the 3.3 (revised with the latest speed
files). 4.1/2 also broke the floorplanner pretty badly.
BTW, this isn't just the virtex/virtexE with the lazy router either. I got
significantly better results on virtexII by routing a placed design under 3.3
then doing the timing analysis under 4.2 to have the same speed files compared
with doing the same design, same floorplan under 4.2. Unfortunately, that
doesn't work if there are pipelined multipliers in the design.
Rick Filipkiewicz wrote:
> hamish@cloud.net.au wrote:
>
> > William LenihanIii <lenihan3we@earthlink.net> wrote:
> > > My Virtex-E (xcv600E) design was meeting timing with Alliance (or
> > > Foundation, presumably same P&R engine) version 3.1i, then when I
> > > upgraded to version 4.2i, the design's timing got significantly
> > > worse even though it's operating on the same EDIF netlist & same
> > > UCF file & same "effort" level (max) set in the
> > > Design Manager's " Design --> Options... " menu.
> > >
> > > Why? [ I thought it was supposed to get better! ]
> >
> > Two possibilities.
> >
> > 1. The route did get worse. Possible.
> >
>
> Esp. in view of Ray Andraka's comments that in the change from 4.1i ->
> 4.2i the routing has got worse for a given placement. I think this is true
> of 3.xi->4.1i as well.
>
> >
> > 2. The speed files got more accurate, which for Virtex-E means worse,
> > especially if you use much block RAM.
> >
> > Were you using all the latest service packs and speed file updates for
> > your 3.x tools? If so you shouldn't notice much different in the speed
> > files going to 4.2, from memory.
> >
>
> To check this - speed file degradation - the OP should probably ask Xilinx
> for the latest 4.x speed files but in a form compatible with the 3.x P&R
> tools. Its been claimed on this NG that this is possible if you badger
> your FAE hard enough.
>
> I would say as a side note that Xilinx should really put the speed files
> into a format that's independent of the tool set version [simple ASCII
> text file ?].
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 46298Hi How can I connect XTAL to XCS10XL by using minimum external component ? Is there any sample available for this ? ThanksArticle: 46299
Hi all,
Do you know whether any FPGA/CPLD supports I2C bus configuration or not? Means Can I connect any I2C device like a microcontroller to the FPGA via I2C bus and The FPGA will act as a master/slave I2C device?
Sudip Saha
sudip.saha@philips.com
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