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Thank you everybody for your input. I guess the bottom line is that I needed to allow room for more pipeline stages in the Virtex II. However, this is a still a delicate balance for me because I will be severely limited by space in my design, and adding stages to the pipeline will utilize a few more registers. While this is definitely worth the trade-off in speed, I was still hoping that it would be able work well with only 2 stages if for no other reason than because the Quartus/Stratix combo seems to be able to handle it. According to Wolfgang's numbers, it seems that the Stratix is outperforming the Virtex II in multiplier speed (in a fully pipelined version I'm assuming), so I wouldn't be surprised if the 2-stage pipelined version performed better in the Stratix also. Another tidbit of info is that the Stratix 2-stage MegaWizard 14x10 multiplier was running well over 150 MHz - it was running at 180 MHz most of the time (depending on how the rest of my design was implemented). I try to will investigate this further to see how reliable my numbers are, and where the discrepencies lay.Article: 45701
"sdrg" <djd@sdfjg.zlfjv> wrote in message news:ee78334.-1@WebX.sUN8CHnE... > as we know,amplify of synplicity is a physical optimization tool,and synplify is logic synthesis tool.can i directly run place&route of xilinx after it was synthesised by amplify and not synplify? sdrg, In my experience, I ran Synplify first, then Amplify exclusively. I did not need Synplify after the first run. You may not need it at all, but I don't know that. Simon Ramirez, Consultant Synchronous Design, Inc. Oviedo, FL USAArticle: 45702
Hi group,
I have a PCI design which requires the addition of using the interrupt.
The operation is that the software will write a value to a down counter
which when it reaches zero an interrupt is generated.
Can anyone help as to explain the actual operation and possible problems
associated with the calibration of the "timer"
This delay is used in software timing so I would be interested in any
help/advice
Thanks in advance
Dave
Article: 45703Hallo Kevin, > As far as I can tell, none of the PDF files you mentioned compare the > circuit performance of a Spartan-II-6 with other Xilinx FPGA families. > Again, comparing the worst case 4-input LUT tILO performance, a Virtex-6 > and a Spartan-II-6 are both 0.6ns. (If I recall it correctly, ISE > WebPACK 4.2's Static Timing Analyzer told me that the worst case tILO is > actually 0.548ns for a Spartan-II-6.) > In some other circuit parameters, a Virtex-6 seems to be slightly faster > than a Spartan-II-6, but the difference is likely negligible since the > 4-input LUT's performance is going to be very dominant in a PCI IP > core. > One thing I am not 100% sure is the speed of the interconnect, but since > both the Virtex-6 and Spartan-II-6 are manufactured in a comparable > process technology, I will assume that the difference is also going to > be negligible. Yes, its right. Some day's ago, i have ordered the "DS-KIT-2S200-PAK-EURO" from Insight. On this Card is a "XC2S200-5FG456C" chip and i can begin with my project. For debugging (or others) are on this card two Digit 7-Segment-LED-Displays, manual switches and many more interisting toys plus VHDL-Samples . I think its a good startpoint for my project and if my PCI-Core ready and my backside-core to big for this chip i can bay a Virtex-E (XCV300E-8BG432C), finished my project and at the end sell the Insight-Kit (or use it for my next). Ciao ErikArticle: 45704
Dear Daniel
Measuring complex impedance can be done with a signal generator and a
two channel oscilloscope. The simplest way to think of it is that you are
measuring the voltage and current at the same time of a sine wave across a
DUT. The current is commonly measured in the ground leg of the circuit. The
amount by which the current lags (or leads) the voltage is essentially the
phase angle. One could take an FPGA, set it up with a couple of modest
A/D's, produce a variable frequency square wave and filter it to a sine wave
if you wish.
A few years back, I took a Fluke 97 two channel scopemeter and an ARB,
now made by Berkeley Nucleonics and built essentially a poor-mans version of
a HP4193 Vector Impedance meter using those two pieces of equipment an
LabView. I would imagine that you could get the LabView code from Berkelel's
server at http://www.berkeleynucleonics.com/smartarb/apps.htm and see how it
was done and replicate that design in an FPGA if you wish.
Charles Krinke WA6LWB
"Daniel" <Daniel.Westerheim@Lynntech.com> wrote in message
news:ee782de.1@WebX.sUN8CHnE...
> Sorry, I wasn't clear enough. I'm looking for an example or a reference
on building a system with the FPGA at the core for measuring a passive
element's impedance.
>
> Basically, i'm looking for some examples of the different ways to
implement impedance measurement.
Article: 45705Jee wrote: > > Hi, > I am using Xilinx ISE 4.2, I just found that it seemed that I have > to name the UCF file same as my top level entity name. Forexample, if my > top level entity is mysys, then ISE only look for mysys.ucf, and I can > not find where to tell ISE my UCF file name. > IS this restriction true? > > Thanks, in 4.1 it's not problem if you run on the command line, just put -uc on ngdbuild -Lasse -- // Lasse Langwadt Christensen // Aalborg, DanmarkArticle: 45706
Hello FPGA and VHDL experts, I require a little assistance. I have done some searches and read through a few texts to see if the topic is covered and can't find the information that I'm looking for. I have two counter banks which are counting away. At 1 kHz I take the counts in both of the banks, generate an interrupt and pass off the values to a CPU where the floating point division of the counts BANK A divided by BANK B occurs along with some fancy DSP filtering. I use an ISA interface for the data transfer. What I'm looking to do is move the division inside of the FPGA. Can anyone point out a couple of examples so I can learn how to do this. I'm looking for floating point division with at least 5 digits of precision in my result. Then I can perform some fancy DSP filtering inside of the FPGA. Note, the counter banks are 24 bits each. Questions: 1. Can this be done as a VHDL module or do I have to embed a CPU type core for the division? 2. Does anyone know of an app note that might cover, and provide a small example of this type of VHDl code? 3. Am I crazy to try this (ie should I just let the CPU do the work)? If my question seems rather niave I appologize, I've only been working with VHDL and FPGAs for about a year so my knowledge is somewhat limited (so go easy with the shots please!). Any help is greatly appreciated. Thanks Jason BerringerArticle: 45707
Kevin Neilson wrote: > > 100MHz. > > Worst-case margins are already built into the timing models. > > "Peter Baltazarovic" <baltazarovic@ncode.sk> wrote in message > news:aibni6$i3j$1@virtual.nextra.sk... > > Hello to everybody, > > > > I would like to know that if I want my design to be run at say 100 > MHz, > > for what speed should it be synthesized to be safe, stable and workung? I > > mean 1%, 2% above 100 MHz? > > > > Thanx for answer. > > > > Peter > > > > I'm assuming he wants to push his luck and run it above 100MHz, and would like to know how much it could be pushed and still be likely that it'll work. I've been tempted to do that, say for a prototype that with a push on the big green button, fails timing with a few percent. -Lasse -- // Lasse Langwadt Christensen // Aalborg, DanmarkArticle: 45708
Keep in mind that extenal factors such as clock jitter. While time of flight and signal fidelity issues affect the chip interface, a poor quality clock can affect both the internal and external timing. If the clock is exceedingly clean, the full 100MHz is okay. Typically the design runs better than worst case numbers in the lab environment where the temperatures and voltages are more reasonable than worst case. (snippets below) > > "Peter Baltazarovic" <baltazarovic@ncode.sk> wrote: > > > I would like to know that if I want my design to be run at say 100 MHz, > > > > for what speed should it be synthesized to be safe, stable and workung? I > > > mean 1%, 2% above 100 MHz? > Kevin Neilson wrote: > > > > 100MHz. > > > > Worst-case margins are already built into the timing models. Lasse Langwadt Christensen wrote: > I'm assuming he wants to push his luck and run it above 100MHz, and would > like to know how much it could be pushed and still be likely that it'll > work.Article: 45709
Peter Baltazarovic wrote: > > Hello to everybody, > > I would like to know that if I want my design to be run at say 100 MHz, > for what speed should it be synthesized to be safe, stable and workung? I > mean 1%, 2% above 100 MHz? If things are looking tight, it is worthwhile to also run a HW test, to make sure your are 'well clear' of 100MHz on the test bench. ( worst case is Vcc and Temp corner qualified, so a bench test should not fail at 102MHz ) The 'Rely on SW' pathway is fine in theory, but a bench reality check is the true yardstick. ( bit like Opinion Polls and Elections .. ) -jgArticle: 45710
in my project,my resource reports is:
************************************
Design Summary:
Number of errors: 0
Number of warnings: 137
Number of Slices: 33,366 out of 33,792 98%
Number of Slices containing
unrelated logic: 0 out of 33,366 0%
Number of Slice Flip Flops: 32,997 out of 67,584 48%
Total Number 4 input LUTs: 46,525 out of 67,584 68%
Number used as LUTs: 44,818
Number used as a route-thru: 1,691
Number used as Shift registers: 16
Number of bonded IOBs: 156 out of 684 22%
IOB Flip Flops: 171
Number of Block RAMs: 137 out of 144 95%
Number of GCLKs: 7 out of 16 43%
Total equivalent gate count for design: 9,605,081
Additional JTAG gate count for IOBs: 7,488
************************************
i add the constrain for my clock,and i hope it can be 83M.after p&R,it is only 50M.how should i meet my clock constrain?
Article: 45711how do i add the offset constrain in/out at inout pin?Article: 45712
Anybody ever successfully modified Vcco beyond the recommended standards ? For example using 2.7V instead of 2.5V for LVCMOS2 IOs ? Thanks, rudiArticle: 45713
after i synthesis my project by synplify,it generates the edif file.how do i simulate the synthesised edif by vcs?Article: 45714
hey sf.. You've got a pretty big device there. Study every violating nets to make sure they arn't false or multi-cycle paths. If you haven't already, download the most recent Xilinx timing patches. Its also important to constrain both synthesis and P&R timing. Some synth tools support a register 'balancing' pass. If your still not meeting timing, and you can't move to a larger/faster device, then you need to fall back on 'design for speed' changes to reduce logic levels. You can often modify your design structure to better match the fpga resources. Floor planning will reduce overall routing delays. Eric "sf" <adf@rf.xb> wrote in message news:ee78372.-1@WebX.sUN8CHnE... > in my project,my resource reports is: > ************************************ > Design Summary: > Number of errors: 0 > Number of warnings: 137 > Number of Slices: 33,366 out of 33,792 98% > Number of Slices containing > unrelated logic: 0 out of 33,366 0% > Number of Slice Flip Flops: 32,997 out of 67,584 48% > Total Number 4 input LUTs: 46,525 out of 67,584 68% > Number used as LUTs: 44,818 > Number used as a route-thru: 1,691 > Number used as Shift registers: 16 > Number of bonded IOBs: 156 out of 684 22% > IOB Flip Flops: 171 > Number of Block RAMs: 137 out of 144 95% > Number of GCLKs: 7 out of 16 43% > Total equivalent gate count for design: 9,605,081 > Additional JTAG gate count for IOBs: 7,488 > ************************************ > > i add the constrain for my clock,and i hope it can be 83M.after p&R,it is only 50M.how should i meet my clock constrain?Article: 45715
On Thu, 1 Aug 2002 19:09:13 -0700, ery <jkchv@gfij.lkfsdjb> wrote: >after i synthesis my project by synplify,it generates the edif file.how do i simulate the synthesised edif by vcs? you can also get synplify to generate mapped verilog. It is an option in the implementation results tab, optional output files section. Muzaffer Kal http://www.dspia.com ASIC/FPGA design/verification consulting specializing in DSP algorithm implementationsArticle: 45716
> Also, formal verification of hardware is much easier than of software > because hardware is simpler in its nature. The only formal verification for hardware simply tests equivalence between two representations of the same design, it does not prove any kind of correctness; don't let the vendors tell you any different! In the software world, it would be analagous to a tool that verifies that an executable does exactly what the source does, that is, the compiler does not have bugs. -StanArticle: 45717
"dudu" <dudu@dudu.com> wrote in message news:3D437F59.69044342@dudu.com... > > I have one more quesiton: > > Our company have modelsim and Tanner L-edit, > > What other tools I need for complete IC development? > > > > Which part of tools is free and which must buy? > > (Personally, I am interested to design a chip for practise, so, I do not > > need powerful tools for me). > > Well if you're designing an ASIC with just digital-logic (no analog > blocks or other 'custom IP', like a custom-layout multiplier block), > and you want to carry the design all the way through the 'backend' > process, at a minimum you need the following: > > #1) synthesis tool (example, Synopsys Design Compiler) > #2) place&route tool (example, Cadence PKS) > #3) clock-tree insertion (not sure, could be part of #1 or #2?!?) > #4) design rule-check, layout verification?!? (not sure) > > I'm not aware of any "free" development tools. The ones I list > above are all commercial, and range in cost (for 1 year license) > from $90,000 USD upward of $1 million USD. Don't let those prices scare you. Depending on the size of your design, I bet you don't need a synthesis tool at all - in fact, if you produce a good set of libraries, even very large designs don't need it. Just do your design using schematics. Use a well-planned hierarchy and do a good job of documentation. For simulation, you can buy an expensive simulator... or you can use a free one. I have had great success using both C and Pascal. You have to write some infrastructure, though. Depending on what ASIC vendor you use, they might do P&R of both logic and clocks for you. If not, if you plan well, and your design isn't huge, you can even do that yourself with some basic graphical tools. Good luck! -StanArticle: 45718
I am interfacing a virtex to a DSP. I wanted to check the timing by simulating a capacitive load to the PLD. Is there any tool which can do that. This is coz the timing analyzer doesn't consider any external devices. Also how far the timing analyzer report is accurate. AnjanArticle: 45719
I tried to implement the code below on a Xilinx Spartan2 100K, however I
get:
WARNING:NgdHelpers:334 - logical net "W29_testbram2_14_enc" has no load
WARNING:NgdHelpers:334 - logical net "W27_testbram2_14_enc" has no load
WARNING:NgdHelpers:334 - logical net "W25_testbram2_14_enc" has no load
WARNING:NgdHelpers:334 - logical net "W23_testbram2_14_enc" has no load
WARNING:NgdHelpers:334 - logical net "W21_testbram2_14_enc" has no load
WARNING:NgdHelpers:334 - logical net "W19_testbram2_14_enc" has no load
WARNING:NgdHelpers:334 - logical net "W17_testbram2_14_enc" has no load
WARNING:NgdHelpers:334 - logical net "W12_testbram2_14_enc" has no load
when synthesising in 2.1i.
The code below has no purpose other than me trying to narrow down what is
causing this. Any suggestions are appreciated, I've been chasing after this
for a good few hours now with no success. The problem goes away if I turn
the ram into flipflops, but this is totally impractical in my situation.
Regards,
Elliot.
==========================================================
// Clock definition
set clock = external ("P80");
unsigned int 32 bus_outtext;
interface bus_out () outputText(unsigned int 32 outtext = bus_outtext) with
{
pull = 1,
data = {"P206", "P205", "P204", "P203", "P202", "P201", "P200", "P199",
"P195", "P194", "P193", "P192", "P191", "P189", "P188", "P187",
"P181", "P180", "P179", "P178", "P176", "P175", "P174", "P173",
"P172", "P168", "P167", "P166", "P165", "P164", "P163", "P162"}
};
void enc () {
ram unsigned 8 ram_subst_0[4];
unsigned int 32 generatedKey;
ram_subst_0[1] = 0;
generatedKey = 0@(ram_subst_0[1]);
bus_outtext = generatedKey;
delay; //DEBUG
}
void main () {
enc ();
delay; //DEBUG
}
Article: 45720> The only formal verification for hardware simply tests > equivalence between > two representations of the same design, it does not prove any kind of > correctness; Two misconceptions here: 1) "proof of correctness" is only another version of "equivalence between two representations", with the (admittedly important) difference that one representation is a set of statements (often couched as assertions) about the design's purpose or intended behaviour, whereas the other representation is intended to represent an implementation. The kind of formal tools you're thinking about are equivalence checkers which compare two netlists for equivalence of function, or (more recently) compare a netlist against an RTL description. 2) What you say may have been true a few years ago, but I'm aware of at least two commercially available tools (and there may well be many others) that check a design against assertions describing its behaviour, using formal methods. -- Jonathan Bromley HDL Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project = Services Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 = 1AW, UK Tel: +44 (0)1425 471223 mail: = jonathan.bromley@doulos.com Fax: +44 (0)1425 471573 Web: = http://www.doulos.com This e-mail and any attachments are confidential and Doulos Ltd. = reserves all rights of privilege in respect thereof. It is intended for the use = of the addressee only. If you are not the intended recipient please delete = it from your system, any use, disclosure, or copying of this document = is unauthorised. The contents of this message may contain personal views = which are not the views of Doulos Ltd., unless specifically stated.Article: 45721
I have a idea that I can design a chip which can recive the ethenet
data from
switcher.After get the frames,I can get the payload.Then encapsulate
the payload in E1 format.Then trans them in telephone lines.In the
remote ,there is a same divice.It can recived the data and change into
ethenet frames and trans to the switcher.If the chip is duplex,the
connection between two nets is established. The scope of ethenet can
be greatly enlarged.
But I met some problems.
At first ,I want the chip surpport most switchers.And I guest
there must be a basic specification for all the swithers and a group
to maintaion it.But I don't know.If somebody has it or knows how to
download it,please tell me.
thanks very much.
second is the code speed of ethenet and E1 is too different.So I
have to design 4-8 E1 interfaces to trans data.How to schedule them is
a big problem.
And how to know a E1 interface is finished its tranmition to avoid
collision?
I want to use polling in the interfaces.Is it practical?
Last is I want to the chip duplex.But should I use one line to both
recive and send data by time div and use different lines to recive and
Transmit seperatly?
I am a graduated student in China.And I will have my postgraduated
coures in next month.I have no experiance in such project.So
They are some rudiment problems.More problems may be raised later.
If you have interesting,please discussion with me.
The experianced are greatly welcome. If you are convinet,send mail to
me directly.
My mail is yangyugang@263.sina.com
Good Luck
Article: 45722Hi Jason, Jason Berringer wrote: [...] > to do is move the division inside of the FPGA. Can anyone point out a > couple of examples so I can learn how to do this. I'm looking for floating > point division with at least 5 digits of precision in my result. In this case, maybe it would it be sufficient to multiply one operator with 2^5 (left shift) then do an integer division and divide the result by 2^5 again (right shift)? > 1. Can this be done as a VHDL module or do I have to embed a CPU type core > for the division? No, you can code a divider in an FPGA. Especially if you only need the result at 1 kHz frequencies - then you can use several clocks cycles to produce the result, which typically leads to smaller logic. > 2. Does anyone know of an app note that might cover, and provide a small > example of this type of VHDl code? Have a look at Hennessy & Patterson "Computer Architecture - a quantitative approach", they have various algorithms which should be suitable. SRT is easy to implement. Sorry I can't find a good ref on the web, right now. > 3. Am I crazy to try this (ie should I just let the CPU do the work)? I think, if it allows you to get rid of the CPU, and still fits into the FPGA, or the cost difference for the bigger FPGA is less than the CPU costs, then it's a good idea. For a past project, I designed an SRT divider with 1024 bit operands, so it should be possible to do what you want. :-) Cheers Stefan -- Stefan Doll, München, Germany http://www.stefanVHDL.comArticle: 45723
Morteza wrote: > Hi, > > It may be useful to design at the very low level: Setting programmable > switches, MUXes select lines, etc, individually. (useful for designing > compact and fast library components, for example). > > Is there any straightforward way (e.g. schematic/text editors) to do > that? > I think there are several ways to do it. You can use a graphics tool that gives you access to the wires and physical modules in the chip directly. Or you can edit the EDIF files directly too. There are also primitives that the manufacturer gives out which can give you more direct access. This is something I'm trying to learn now, I'm sure it's possible, I just don't know all the details yet! Patience, persistence, truth, Dr. mike -- Mike Rosing www.beastrider.com BeastRider, LLC SHARC debug toolsArticle: 45724
I finally got some VHDL to compile, but the synthesis uses CLB latches
instead of lut's. What I'm trying to do is hook 16 lut's together to
create a 16x16 bit matrix, and I want to eventually read out 1 row,
or 1 diagonal using the address lines to grab 1 bit from each lut.
(and this is in a Virtex-2 fpga).
My code included the following:
type matrix is array (15 downto 0) of std_logic_vector( 15 downto 0);
signal matstor: matrix;
:
variable i: integer;
:
for i in 15 downto 0 loop
row_data(i) <= matstor(row_adrs)(i);
end loop;
:
:
and row_adrs is defined to be an input port integer, and row_data is an
inout port std_logic_vector. To get the diagonal I have:
for i in 15 downto 0 loop
row_data(i) <= matstor(i)((row_adrs + i) mod 16);
end loop;
I'd like to make use of the lut's shift capability and random
memory access. I've been assuming I'd need to use primitives
to do this, but reading some threads and the help docs indicates
that's not the prefered way to do things. What is the right way
to write vhdl so the lut's are used instead of latches?
Patience, persistence, truth,
Dr. mike
--
Mike Rosing
www.beastrider.com BeastRider, LLC
SHARC debug tools
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